Describe properties that are true of each instruction in the target description file. More...

#include "llvm/MC/MCInstrDesc.h"

Collaboration diagram for llvm::MCInstrDesc:

[legend]

Public Types
using	const_opInfo_iterator = const MCOperandInfo *

Public Member Functions
int	getOperandConstraint (unsigned OpNum, MCOI::OperandConstraint Constraint) const
	Returns the value of the specified operand constraint if it is present. More...

unsigned	getOpcode () const
	Return the opcode number for this descriptor. More...

unsigned	getNumOperands () const
	Return the number of declared MachineOperands for this MachineInstruction. More...

const_opInfo_iterator	opInfo_begin () const

const_opInfo_iterator	opInfo_end () const

iterator_range< const_opInfo_iterator >	operands () const

unsigned	getNumDefs () const
	Return the number of MachineOperands that are register definitions. More...

uint64_t	getFlags () const
	Return flags of this instruction. More...

bool	isPreISelOpcode () const

bool	isVariadic () const
	Return true if this instruction can have a variable number of operands. More...

bool	hasOptionalDef () const
	Set if this instruction has an optional definition, e.g. More...

bool	isPseudo () const
	Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction. More...

bool	isReturn () const
	Return true if the instruction is a return. More...

bool	isAdd () const
	Return true if the instruction is an add instruction. More...

bool	isTrap () const
	Return true if this instruction is a trap. More...

bool	isMoveReg () const
	Return true if the instruction is a register to register move. More...

bool	isCall () const
	Return true if the instruction is a call. More...

bool	isBarrier () const
	Returns true if the specified instruction stops control flow from executing the instruction immediately following it. More...

bool	isTerminator () const
	Returns true if this instruction part of the terminator for a basic block. More...

bool	isBranch () const
	Returns true if this is a conditional, unconditional, or indirect branch. More...

bool	isIndirectBranch () const
	Return true if this is an indirect branch, such as a branch through a register. More...

bool	isConditionalBranch () const
	Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. More...

bool	isUnconditionalBranch () const
	Return true if this is a branch which always transfers control flow to some other block. More...

bool	mayAffectControlFlow (const MCInst &MI, const MCRegisterInfo &RI) const
	Return true if this is a branch or an instruction which directly writes to the program counter. More...

bool	isPredicable () const
	Return true if this instruction has a predicate operand that controls execution. More...

bool	isCompare () const
	Return true if this instruction is a comparison. More...

bool	isMoveImmediate () const
	Return true if this instruction is a move immediate (including conditional moves) instruction. More...

bool	isBitcast () const
	Return true if this instruction is a bitcast instruction. More...

bool	isSelect () const
	Return true if this is a select instruction. More...

bool	isNotDuplicable () const
	Return true if this instruction cannot be safely duplicated. More...

bool	hasDelaySlot () const
	Returns true if the specified instruction has a delay slot which must be filled by the code generator. More...

bool	canFoldAsLoad () const
	Return true for instructions that can be folded as memory operands in other instructions. More...

bool	isRegSequenceLike () const
	Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. More...

bool	isExtractSubregLike () const
	Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. More...

bool	isInsertSubregLike () const
	Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. More...

bool	isConvergent () const
	Return true if this instruction is convergent. More...

bool	variadicOpsAreDefs () const
	Return true if variadic operands of this instruction are definitions. More...

bool	isAuthenticated () const
	Return true if this instruction authenticates a pointer (e.g. More...

bool	mayLoad () const
	Return true if this instruction could possibly read memory. More...

bool	mayStore () const
	Return true if this instruction could possibly modify memory. More...

bool	mayRaiseFPException () const
	Return true if this instruction may raise a floating-point exception. More...

bool	hasUnmodeledSideEffects () const
	Return true if this instruction has side effects that are not modeled by other flags. More...

bool	isCommutable () const
	Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. More...

bool	isConvertibleTo3Addr () const
	Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. More...

bool	usesCustomInsertionHook () const
	Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. More...

bool	hasPostISelHook () const
	Return true if this instruction requires adjustment after instruction selection by calling a target hook. More...

bool	isRematerializable () const
	Returns true if this instruction is a candidate for remat. More...

bool	isAsCheapAsAMove () const
	Returns true if this instruction has the same cost (or less) than a move instruction. More...

bool	hasExtraSrcRegAllocReq () const
	Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. More...

bool	hasExtraDefRegAllocReq () const
	Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. More...

const MCPhysReg *	getImplicitUses () const
	Return a list of registers that are potentially read by any instance of this machine instruction. More...

unsigned	getNumImplicitUses () const
	Return the number of implicit uses this instruction has. More...

const MCPhysReg *	getImplicitDefs () const
	Return a list of registers that are potentially written by any instance of this machine instruction. More...

unsigned	getNumImplicitDefs () const
	Return the number of implicit defs this instruct has. More...

bool	hasImplicitUseOfPhysReg (unsigned Reg) const
	Return true if this instruction implicitly uses the specified physical register. More...

bool	hasImplicitDefOfPhysReg (unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
	Return true if this instruction implicitly defines the specified physical register. More...

unsigned	getSchedClass () const
	Return the scheduling class for this instruction. More...

unsigned	getSize () const
	Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot be known from the opcode. More...

int	findFirstPredOperandIdx () const
	Find the index of the first operand in the operand list that is used to represent the predicate. More...

bool	hasDefOfPhysReg (const MCInst &MI, unsigned Reg, const MCRegisterInfo &RI) const
	Return true if this instruction defines the specified physical register, either explicitly or implicitly. More...

Public Attributes
unsigned short	Opcode

unsigned short	NumOperands

unsigned char	NumDefs

unsigned char	Size

unsigned short	SchedClass

uint64_t	Flags

uint64_t	TSFlags

const MCPhysReg *	ImplicitUses

const MCPhysReg *	ImplicitDefs

const MCOperandInfo *	OpInfo

Detailed Description

Describe properties that are true of each instruction in the target description file.

This captures information about side effects, register use and many other things. There is one instance of this struct for each target instruction class, and the MachineInstr class points to this struct directly to describe itself.

Definition at line 195 of file MCInstrDesc.h.

Member Typedef Documentation

◆ const_opInfo_iterator

using llvm::MCInstrDesc::const_opInfo_iterator = const MCOperandInfo *

Definition at line 230 of file MCInstrDesc.h.

Member Function Documentation

◆ canFoldAsLoad()

bool llvm::MCInstrDesc::canFoldAsLoad ( ) const

inline

Return true for instructions that can be folded as memory operands in other instructions.

The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.

Definition at line 360 of file MCInstrDesc.h.

References Flags, and llvm::MCID::FoldableAsLoad.

◆ findFirstPredOperandIdx()

int llvm::MCInstrDesc::findFirstPredOperandIdx ( ) const

inline

Find the index of the first operand in the operand list that is used to represent the predicate.

It returns -1 if none is found.

Definition at line 621 of file MCInstrDesc.h.

References llvm::numbers::e, getNumOperands(), i, isPredicable(), and OpInfo.

Referenced by llvm::ARM_MC::isPredicated().

◆ getFlags()

uint64_t llvm::MCInstrDesc::getFlags ( ) const

inline

Return flags of this instruction.

Definition at line 246 of file MCInstrDesc.h.

References Flags.

Referenced by llvm::MachineInstr::hasProperty().

◆ getImplicitDefs()

const MCPhysReg* llvm::MCInstrDesc::getImplicitDefs ( ) const

inline

Return a list of registers that are potentially written by any instance of this machine instruction.

For example, on X86, many instructions implicitly set the flags register. In this case, they are marked as setting the FLAGS. Likewise, many instructions always deposit their result in a physical register. For example, the X86 divide instruction always deposits the quotient and remainder in the EAX/EDX registers. For that instruction, this will return a list containing the EAX/EDX/EFLAGS registers.

This method returns null if the instruction has no implicit defs.

Definition at line 581 of file MCInstrDesc.h.

References ImplicitDefs.

Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters(), getPhysicalRegisterVT(), HasImplicitCPSRDef(), and llvm::PPCInstrInfo::optimizeCompareInstr().

◆ getImplicitUses()

const MCPhysReg* llvm::MCInstrDesc::getImplicitUses ( ) const

inline

Return a list of registers that are potentially read by any instance of this machine instruction.

For example, on X86, the "adc" instruction adds two register operands and adds the carry bit in from the flags register. In this case, the instruction is marked as implicitly reading the flags. Likewise, the variable shift instruction on X86 is marked as implicitly reading the 'CL' register, which it always does.

This method returns null if the instruction has no implicit uses.

Definition at line 559 of file MCInstrDesc.h.

References ImplicitUses.

Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), and llvm::PPCInstrInfo::optimizeCompareInstr().

◆ getNumDefs()

unsigned llvm::MCInstrDesc::getNumDefs ( ) const

inline

Return the number of MachineOperands that are register definitions.

Register definitions always occur at the start of the machine operand list. This is the number of "outs" in the .td file, and does not include implicit defs.

Definition at line 243 of file MCInstrDesc.h.

References NumDefs.

◆ getNumImplicitDefs()

unsigned llvm::MCInstrDesc::getNumImplicitDefs ( ) const

inline

Return the number of implicit defs this instruct has.

Definition at line 584 of file MCInstrDesc.h.

References i, and ImplicitDefs.

Referenced by llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters(), llvm::MachineInstr::getNumDefs(), and stripExtraCopyOperands().

◆ getNumImplicitUses()

unsigned llvm::MCInstrDesc::getNumImplicitUses ( ) const

inline

Return the number of implicit uses this instruction has.

Definition at line 562 of file MCInstrDesc.h.

References i, and ImplicitUses.

Referenced by llvm::SIInstrInfo::expandPostRAPseudo(), stripExtraCopyOperands(), and llvm::SIInstrInfo::verifyInstruction().

◆ getNumOperands()

unsigned llvm::MCInstrDesc::getNumOperands ( ) const

inline

Return the number of declared MachineOperands for this MachineInstruction.

Note that variadic (isVariadic() returns true) instructions may have additional operands at the end of the list, and note that the machine instruction may include implicit register def/uses as well.

Definition at line 228 of file MCInstrDesc.h.

References NumOperands.

Referenced by llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::AMDGPUDisassembler::convertFMAanyK(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::PPCInstrInfo::copyPhysReg(), evaluateMemOpAddrForAddrMode3(), evaluateMemOpAddrForAddrMode5(), evaluateMemOpAddrForAddrMode5FP16(), evaluateMemOpAddrForAddrMode_i12(), evaluateMemOpAddrForAddrModeT2_i8s4(), Expand2AddrKreg(), Expand2AddrUndef(), llvm::SIInstrInfo::expandPostRAPseudo(), findFirstPredOperandIdx(), llvm::findFirstVPTPredOperandIdx(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), getCondFromBranch(), llvm::MachineInstr::getNumExplicitOperands(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::X86II::getOperandBias(), llvm::SIInstrInfo::getOpRegClass(), llvm::TargetInstrInfo::getRegClass(), llvm::SIInstrInfo::getRegClass(), getTargetMBB(), INITIALIZE_PASS(), needsExpandMemInst(), llvm::PPCInstrInfo::onlyFoldImmediate(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::HexagonMCInstrInfo::predicateInfo(), llvm::WebAssemblyInstPrinter::printInst(), llvm::FastISel::selectStackmap(), stripExtraCopyOperands(), tryAddToFoldList(), tryChangeVGPRtoSGPRinCopy(), tryToFoldACImm(), llvm::SystemZInstrInfo::verifyInstruction(), llvm::SIInstrInfo::verifyInstruction(), and llvm::mca::verifyOperands().

◆ getOpcode()

unsigned llvm::MCInstrDesc::getOpcode ( ) const

inline

Return the opcode number for this descriptor.

Definition at line 221 of file MCInstrDesc.h.

References Opcode.

Referenced by adjustDefLatency(), llvm::AVRInstrInfo::analyzeBranch(), llvm::constrainOperandRegClass(), copyPhysSubRegs(), llvm::ARM_MC::evaluateBranchTarget(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getOperandLatency(), hasRAWHazard(), llvm::HexagonShuffler::shuffle(), and llvm::SIInstrInfo::verifyInstruction().

◆ getOperandConstraint()

int llvm::MCInstrDesc::getOperandConstraint	(	unsigned	OpNum,
		MCOI::OperandConstraint	Constraint
	)		const

inline

Returns the value of the specified operand constraint if it is present.

Returns -1 if it is not present.

Definition at line 210 of file MCInstrDesc.h.

References llvm::MCOperandInfo::Constraints, NumOperands, and OpInfo.

Referenced by llvm::MachineInstr::addOperand(), llvm::X86II::getOperandBias(), llvm::MachineInstr::hasComplexRegisterTies(), isRegOrImmWithInputMods(), and printMasking().

◆ getSchedClass()

unsigned llvm::MCInstrDesc::getSchedClass ( ) const

inline

Return the scheduling class for this instruction.

The scheduling class is an index into the InstrItineraryData table. This returns zero if there is no known scheduling information for the instruction.

Definition at line 612 of file MCInstrDesc.h.

References SchedClass.

Referenced by llvm::DFAPacketizer::canReserveResources(), llvm::ResourceManager::canReserveResources(), llvm::TargetSchedModel::computeInstrLatency(), llvm::MCSchedModel::computeInstrLatency(), llvm::TargetSchedModel::computeOperandLatency(), llvm::TargetSchedModel::computeReciprocalThroughput(), llvm::ScoreboardHazardRecognizer::EmitInstruction(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::HexagonMCInstrInfo::getCVIResources(), llvm::ScoreboardHazardRecognizer::getHazardType(), llvm::TargetInstrInfo::getInstrLatency(), getItineraryLatency(), getLatency(), llvm::ARMBaseInstrInfo::getNumMicroOps(), getNumMicroOpsSwiftLdSt(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::TargetInstrInfo::getOperandLatency(), llvm::HexagonMCInstrInfo::getOtherReservedSlots(), llvm::MCSchedModel::getReciprocalThroughput(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::HexagonMCInstrInfo::getUnits(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), llvm::DFAPacketizer::reserveResources(), and llvm::ResourceManager::reserveResources().

◆ getSize()

unsigned llvm::MCInstrDesc::getSize ( ) const

inline

Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot be known from the opcode.

Definition at line 616 of file MCInstrDesc.h.

References Size.

Referenced by llvm::CSKYMCCodeEmitter::encodeInstruction(), llvm::MipsMCCodeEmitter::encodeInstruction(), llvm::MSP430MCCodeEmitter::encodeInstruction(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::AVRInstrInfo::getInstSizeInBytes(), llvm::PPCMCCodeEmitter::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), and llvm::SIInstrInfo::getInstSizeInBytes().

◆ hasDefOfPhysReg()

bool MCInstrDesc::hasDefOfPhysReg	(	const MCInst &	MI,
		unsigned	Reg,
		const MCRegisterInfo &	RI
	)		const

Return true if this instruction defines the specified physical register, either explicitly or implicitly.

Definition at line 42 of file MCInstrDesc.cpp.

References llvm::numbers::e, hasImplicitDefOfPhysReg(), i, llvm::MCRegisterInfo::isSubRegisterEq(), MI, NumDefs, NumOperands, Reg, and variadicOpsAreDefs().

Referenced by mayAffectControlFlow().

◆ hasDelaySlot()

bool llvm::MCInstrDesc::hasDelaySlot ( ) const

inline

Returns true if the specified instruction has a delay slot which must be filled by the code generator.

Definition at line 351 of file MCInstrDesc.h.

References llvm::MCID::DelaySlot, and Flags.

◆ hasExtraDefRegAllocReq()

bool llvm::MCInstrDesc::hasExtraDefRegAllocReq ( ) const

inline

Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes.

e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.

Definition at line 547 of file MCInstrDesc.h.

References llvm::MCID::ExtraDefRegAllocReq, and Flags.

◆ hasExtraSrcRegAllocReq()

bool llvm::MCInstrDesc::hasExtraSrcRegAllocReq ( ) const

inline

Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes.

e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.

Definition at line 537 of file MCInstrDesc.h.

References llvm::MCID::ExtraSrcRegAllocReq, and Flags.

◆ hasImplicitDefOfPhysReg()

bool MCInstrDesc::hasImplicitDefOfPhysReg	(	unsigned	Reg,
		const MCRegisterInfo *	MRI = `nullptr`
	)		const

Return true if this instruction implicitly defines the specified physical register.

Definition at line 33 of file MCInstrDesc.cpp.

References ImplicitDefs, MRI, and Reg.

Referenced by llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), CheckForPhysRegDependency(), and hasDefOfPhysReg().

◆ hasImplicitUseOfPhysReg()

bool llvm::MCInstrDesc::hasImplicitUseOfPhysReg ( unsigned Reg ) const

inline

Return true if this instruction implicitly uses the specified physical register.

Definition at line 595 of file MCInstrDesc.h.

References ImplicitUses, and Reg.

Referenced by llvm::ScheduleDAGInstrs::addPhysRegDataDeps().

◆ hasOptionalDef()

bool llvm::MCInstrDesc::hasOptionalDef ( ) const

inline

Set if this instruction has an optional definition, e.g.

ARM instructions which can set condition code if 's' bit is set.

Definition at line 260 of file MCInstrDesc.h.

References Flags, and llvm::MCID::HasOptionalDef.

Referenced by llvm::ARMBaseInstrInfo::FoldImmediate(), and llvm::mca::verifyOperands().

◆ hasPostISelHook()

bool llvm::MCInstrDesc::hasPostISelHook ( ) const

inline

Return true if this instruction requires adjustment after instruction selection by calling a target hook.

For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.

Definition at line 508 of file MCInstrDesc.h.

References Flags, and llvm::MCID::HasPostISelHook.

◆ hasUnmodeledSideEffects()

bool llvm::MCInstrDesc::hasUnmodeledSideEffects ( ) const

inline

Return true if this instruction has side effects that are not modeled by other flags.

This does not return true for instructions whose effects are captured by:

Their operand list and implicit definition/use list. Register use/def info is explicit for instructions.
Memory accesses. Use mayLoad/mayStore.
Calling, branching, returning: use isCall/isReturn/isBranch.

Examples of side effects would be modifying 'invisible' machine state like a control register, flushing a cache, modifying a register invisible to LLVM, etc.

Definition at line 454 of file MCInstrDesc.h.

References Flags, and llvm::MCID::UnmodeledSideEffects.

◆ isAdd()

bool llvm::MCInstrDesc::isAdd ( ) const

inline

Return true if the instruction is an add instruction.

Definition at line 270 of file MCInstrDesc.h.

References llvm::MCID::Add, and Flags.

◆ isAsCheapAsAMove()

bool llvm::MCInstrDesc::isAsCheapAsAMove ( ) const

inline

Returns true if this instruction has the same cost (or less) than a move instruction.

This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.

This method could be called by interface TargetInstrInfo::isAsCheapAsAMove for different subtargets.

Definition at line 529 of file MCInstrDesc.h.

References llvm::MCID::CheapAsAMove, and Flags.

◆ isAuthenticated()

bool llvm::MCInstrDesc::isAuthenticated ( ) const

inline

Return true if this instruction authenticates a pointer (e.g.

LDRAx/BRAx from ARMv8.3, which perform loads/branches with authentication).

An authenticated instruction may fail in an ABI-defined manner when operating on an invalid signed pointer.

Definition at line 418 of file MCInstrDesc.h.

References llvm::MCID::Authenticated, and Flags.

◆ isBarrier()

bool llvm::MCInstrDesc::isBarrier ( ) const

inline

Returns true if the specified instruction stops control flow from executing the instruction immediately following it.

Examples include unconditional branches and return instructions.

Definition at line 284 of file MCInstrDesc.h.

References llvm::MCID::Barrier, and Flags.

Referenced by isConditionalBranch(), and isUnconditionalBranch().

◆ isBitcast()

bool llvm::MCInstrDesc::isBitcast ( ) const

inline

Return true if this instruction is a bitcast instruction.

Definition at line 339 of file MCInstrDesc.h.

References llvm::MCID::Bitcast, and Flags.

◆ isBranch()

bool llvm::MCInstrDesc::isBranch ( ) const

inline

Returns true if this is a conditional, unconditional, or indirect branch.

Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::analyzeBranch method can be used to get more information.

Definition at line 298 of file MCInstrDesc.h.

References llvm::MCID::Branch, and Flags.

Referenced by llvm::PPCDispatchGroupSBHazardRecognizer::EmitInstruction(), llvm::MCInstrAnalysis::isBranch(), isConditionalBranch(), isUnconditionalBranch(), mayAffectControlFlow(), llvm::HexagonMCChecker::reportBranchErrors(), and llvm::SIInstrInfo::verifyInstruction().

◆ isCall()

bool llvm::MCInstrDesc::isCall ( ) const

inline

Return true if the instruction is a call.

Definition at line 279 of file MCInstrDesc.h.

References llvm::MCID::Call, and Flags.

Referenced by llvm::mca::computeMaxLatency(), llvm::MCInstrAnalysis::isCall(), mayAffectControlFlow(), llvm::HexagonMCChecker::reportBranchErrors(), llvm::SelectionDAGISel::runOnMachineFunction(), and llvm::ResourcePriorityQueue::SUSchedulingCost().

◆ isCommutable()

bool llvm::MCInstrDesc::isCommutable ( ) const

inline

Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.

If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.

Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.

Definition at line 472 of file MCInstrDesc.h.

References llvm::MCID::Commutable, and Flags.

Referenced by llvm::MipsInstrInfo::findCommutedOpIndices(), llvm::RISCVInstrInfo::findCommutedOpIndices(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::findCommutedOpIndices(), and llvm::TargetInstrInfo::findCommutedOpIndices().

◆ isCompare()

bool llvm::MCInstrDesc::isCompare ( ) const

inline

Return true if this instruction is a comparison.

Definition at line 332 of file MCInstrDesc.h.

References llvm::MCID::Compare, and Flags.

◆ isConditionalBranch()

bool llvm::MCInstrDesc::isConditionalBranch ( ) const

inline

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block.

The TargetInstrInfo::analyzeBranch method can be used to get more information about this branch.

Definition at line 308 of file MCInstrDesc.h.

References isBarrier(), isBranch(), and isIndirectBranch().

Referenced by llvm::MCInstrAnalysis::isConditionalBranch(), and parseCondBranch().

◆ isConvergent()

bool llvm::MCInstrDesc::isConvergent ( ) const

inline

Return true if this instruction is convergent.

Convergent instructions may not be made control-dependent on any additional values.

Definition at line 406 of file MCInstrDesc.h.

References llvm::MCID::Convergent, and Flags.

◆ isConvertibleTo3Addr()

bool llvm::MCInstrDesc::isConvertibleTo3Addr ( ) const

inline

Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed.

Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.

If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).

Definition at line 488 of file MCInstrDesc.h.

References llvm::MCID::ConvertibleTo3Addr, and Flags.

◆ isExtractSubregLike()

bool llvm::MCInstrDesc::isExtractSubregLike ( ) const

inline

Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.

E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getExtractSubregLikeInputs has to be override accordingly.

Definition at line 385 of file MCInstrDesc.h.

References llvm::MCID::ExtractSubreg, and Flags.

◆ isIndirectBranch()

bool llvm::MCInstrDesc::isIndirectBranch ( ) const

inline

Return true if this is an indirect branch, such as a branch through a register.

Definition at line 302 of file MCInstrDesc.h.

References Flags, and llvm::MCID::IndirectBranch.

Referenced by isConditionalBranch(), llvm::MCInstrAnalysis::isIndirectBranch(), isUnconditionalBranch(), and mayAffectControlFlow().

◆ isInsertSubregLike()

bool llvm::MCInstrDesc::isInsertSubregLike ( ) const

inline

Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.

E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getInsertSubregLikeInputs has to be override accordingly.

Definition at line 399 of file MCInstrDesc.h.

References Flags, and llvm::MCID::InsertSubreg.

◆ isMoveImmediate()

bool llvm::MCInstrDesc::isMoveImmediate ( ) const

inline

Return true if this instruction is a move immediate (including conditional moves) instruction.

Definition at line 336 of file MCInstrDesc.h.

References Flags, and llvm::MCID::MoveImm.

◆ isMoveReg()

bool llvm::MCInstrDesc::isMoveReg ( ) const

inline

Return true if the instruction is a register to register move.

Definition at line 276 of file MCInstrDesc.h.

References Flags, and llvm::MCID::MoveReg.

◆ isNotDuplicable()

bool llvm::MCInstrDesc::isNotDuplicable ( ) const

inline

Return true if this instruction cannot be safely duplicated.

For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.

Definition at line 347 of file MCInstrDesc.h.

References Flags, and llvm::MCID::NotDuplicable.

◆ isPredicable()

bool llvm::MCInstrDesc::isPredicable ( ) const

inline

Return true if this instruction has a predicate operand that controls execution.

It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.

Definition at line 329 of file MCInstrDesc.h.

References Flags, and llvm::MCID::Predicable.

Referenced by DecodePredicateOperand(), findFirstPredOperandIdx(), and llvm::MachineInstr::findFirstPredOperandIdx().

◆ isPreISelOpcode()

bool llvm::MCInstrDesc::isPreISelOpcode ( ) const

inline

Returns: true if this instruction is emitted before instruction selection and should be legalized/regbankselected/selected.

Definition at line 250 of file MCInstrDesc.h.

References Flags, and llvm::MCID::PreISelOpcode.

◆ isPseudo()

bool llvm::MCInstrDesc::isPseudo ( ) const

inline

Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

Definition at line 264 of file MCInstrDesc.h.

References Flags, and llvm::MCID::Pseudo.

Referenced by llvm::ResourceManager::canReserveResources(), llvm::HexagonMCInstrInfo::isCanon(), llvm::PPCInstrInfo::onlyFoldImmediate(), and llvm::ResourceManager::reserveResources().

◆ isRegSequenceLike()

bool llvm::MCInstrDesc::isRegSequenceLike ( ) const

inline

Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.

E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getRegSequenceLikeInputs has to be override accordingly.

Definition at line 372 of file MCInstrDesc.h.

References Flags, and llvm::MCID::RegSequence.

◆ isRematerializable()

bool llvm::MCInstrDesc::isRematerializable ( ) const

inline

Returns true if this instruction is a candidate for remat.

This flag is only used in TargetInstrInfo method isTriviallyRematerializable.

If this flag is set, the isReallyTriviallyReMaterializable() or isReallyTriviallyReMaterializableGeneric methods are called to verify the instruction is really rematable.

Definition at line 516 of file MCInstrDesc.h.

References Flags, and llvm::MCID::Rematerializable.

◆ isReturn()

bool llvm::MCInstrDesc::isReturn ( ) const

inline

Return true if the instruction is a return.

Definition at line 267 of file MCInstrDesc.h.

References Flags, and llvm::MCID::Return.

Referenced by llvm::MCInstrAnalysis::isReturn(), mayAffectControlFlow(), llvm::HexagonMCChecker::reportBranchErrors(), and llvm::SelectionDAGISel::runOnMachineFunction().

◆ isSelect()

bool llvm::MCInstrDesc::isSelect ( ) const

inline

Return true if this is a select instruction.

Definition at line 342 of file MCInstrDesc.h.

References Flags, and llvm::MCID::Select.

◆ isTerminator()

bool llvm::MCInstrDesc::isTerminator ( ) const

inline

Returns true if this instruction part of the terminator for a basic block.

Typically this is things like return and branch instructions.

Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.

Definition at line 292 of file MCInstrDesc.h.

References Flags, and llvm::MCID::Terminator.

Referenced by llvm::MCInstrAnalysis::isTerminator().

◆ isTrap()

bool llvm::MCInstrDesc::isTrap ( ) const

inline

Return true if this instruction is a trap.

Definition at line 273 of file MCInstrDesc.h.

References Flags, and llvm::MCID::Trap.

◆ isUnconditionalBranch()

bool llvm::MCInstrDesc::isUnconditionalBranch ( ) const

inline

Return true if this is a branch which always transfers control flow to some other block.

The TargetInstrInfo::analyzeBranch method can be used to get more information about this branch.

Definition at line 316 of file MCInstrDesc.h.

References isBarrier(), isBranch(), and isIndirectBranch().

Referenced by llvm::MCInstrAnalysis::isUnconditionalBranch().

◆ isVariadic()

bool llvm::MCInstrDesc::isVariadic ( ) const

inline

Return true if this instruction can have a variable number of operands.

In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).

Definition at line 256 of file MCInstrDesc.h.

References Flags, and llvm::MCID::Variadic.

Referenced by llvm::MachineInstr::addOperand(), llvm::MachineInstr::getNumExplicitDefs(), llvm::MachineInstr::getNumExplicitOperands(), llvm::WebAssemblyInstPrinter::printInst(), and llvm::SIInstrInfo::verifyInstruction().

◆ mayAffectControlFlow()

bool MCInstrDesc::mayAffectControlFlow	(	const MCInst &	MI,
		const MCRegisterInfo &	RI
	)		const

Return true if this is a branch or an instruction which directly writes to the program counter.

Considered 'may' affect rather than 'does' affect as things like predication are not taken into account.

Definition at line 21 of file MCInstrDesc.cpp.

References llvm::MCRegisterInfo::getProgramCounter(), hasDefOfPhysReg(), isBranch(), isCall(), isIndirectBranch(), isReturn(), and MI.

◆ mayLoad()

bool llvm::MCInstrDesc::mayLoad ( ) const

inline

Return true if this instruction could possibly read memory.

Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.

Definition at line 429 of file MCInstrDesc.h.

References Flags, and llvm::MCID::MayLoad.

Referenced by llvm::addFrameReference(), llvm::M68k::addFrameReference(), llvm::M68k::addMemOperand(), adjustAllocatableRegClass(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::HexagonShuffler::restrictStoreLoadOrder(), and llvm::SelectionDAGISel::SelectCodeCommon().

◆ mayRaiseFPException()

bool llvm::MCInstrDesc::mayRaiseFPException ( ) const

inline

Return true if this instruction may raise a floating-point exception.

Definition at line 438 of file MCInstrDesc.h.

References Flags, and llvm::MCID::MayRaiseFPException.

Referenced by llvm::SelectionDAGISel::mayRaiseFPException().

◆ mayStore()

bool llvm::MCInstrDesc::mayStore ( ) const

inline

Return true if this instruction could possibly modify memory.

Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.

Definition at line 435 of file MCInstrDesc.h.

References Flags, and llvm::MCID::MayStore.

Referenced by llvm::addFrameReference(), llvm::M68k::addFrameReference(), llvm::M68k::addMemOperand(), adjustAllocatableRegClass(), llvm::ARMBaseInstrInfo::getNumMicroOps(), and llvm::SelectionDAGISel::SelectCodeCommon().

◆ operands()

iterator_range<const_opInfo_iterator> llvm::MCInstrDesc::operands ( ) const

inline

Definition at line 235 of file MCInstrDesc.h.

References llvm::make_range(), opInfo_begin(), and opInfo_end().

Referenced by llvm::RISCVInstrInfo::verifyInstruction().

◆ opInfo_begin()

const_opInfo_iterator llvm::MCInstrDesc::opInfo_begin ( ) const

inline

Definition at line 232 of file MCInstrDesc.h.

References OpInfo.

Referenced by operands(), and llvm::LegalizerInfo::verify().

◆ opInfo_end()

const_opInfo_iterator llvm::MCInstrDesc::opInfo_end ( ) const

inline

Definition at line 233 of file MCInstrDesc.h.

References NumOperands, and OpInfo.

Referenced by operands(), and llvm::LegalizerInfo::verify().

◆ usesCustomInsertionHook()

bool llvm::MCInstrDesc::usesCustomInsertionHook ( ) const

inline

Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block.

If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.

If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.

Definition at line 500 of file MCInstrDesc.h.

References Flags, and llvm::MCID::UsesCustomInserter.

◆ variadicOpsAreDefs()

bool llvm::MCInstrDesc::variadicOpsAreDefs ( ) const

inline

Return true if variadic operands of this instruction are definitions.

Definition at line 409 of file MCInstrDesc.h.

References Flags, and llvm::MCID::VariadicOpsAreDefs.

Referenced by hasDefOfPhysReg(), llvm::WebAssemblyMCInstLower::lower(), and llvm::WebAssemblyInstPrinter::printInst().

Member Data Documentation

◆ Flags

◆ ImplicitDefs

const MCPhysReg* llvm::MCInstrDesc::ImplicitDefs

Definition at line 205 of file MCInstrDesc.h.

Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), llvm::FastISel::fastEmitInst_f(), llvm::FastISel::fastEmitInst_i(), llvm::FastISel::fastEmitInst_r(), llvm::FastISel::fastEmitInst_ri(), llvm::FastISel::fastEmitInst_rii(), llvm::FastISel::fastEmitInst_rr(), llvm::FastISel::fastEmitInst_rri(), llvm::FastISel::fastEmitInst_rrr(), getImplicitDefs(), getNumImplicitDefs(), getPhysicalRegisterVT(), hasImplicitDefOfPhysReg(), and llvm::PPCInstrInfo::optimizeCompareInstr().

◆ ImplicitUses

const MCPhysReg* llvm::MCInstrDesc::ImplicitUses

Definition at line 204 of file MCInstrDesc.h.

Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), getImplicitUses(), getNumImplicitUses(), hasImplicitUseOfPhysReg(), and llvm::PPCInstrInfo::optimizeCompareInstr().

◆ NumDefs

unsigned char llvm::MCInstrDesc::NumDefs

Definition at line 199 of file MCInstrDesc.h.

Referenced by getNumDefs(), hasDefOfPhysReg(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ NumOperands

unsigned short llvm::MCInstrDesc::NumOperands

Definition at line 198 of file MCInstrDesc.h.

Referenced by AddThumb1SBit(), findFirstVectorPredOperandIdx(), getNumOperands(), getOperandConstraint(), llvm::AMDGPU::getRegOperandSize(), hasDefOfPhysReg(), isRegOrImmWithInputMods(), llvm::AMDGPU::isSISrcFPOperand(), llvm::AMDGPU::isSISrcInlinableOperand(), llvm::AMDGPU::isSISrcOperand(), isVectorPredicable(), llvm::WebAssemblyMCInstLower::lower(), and opInfo_end().

◆ Opcode

unsigned short llvm::MCInstrDesc::Opcode

Definition at line 197 of file MCInstrDesc.h.

Referenced by llvm::BuildMI(), llvm::ScoreboardHazardRecognizer::EmitInstruction(), getOpcode(), llvm::MachineInstr::getOpcode(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getRegClass(), and llvm::MachineInstr::hasComplexRegisterTies().

◆ OpInfo

const MCOperandInfo* llvm::MCInstrDesc::OpInfo

Definition at line 206 of file MCInstrDesc.h.

Referenced by AddThumb1SBit(), llvm::TargetSchedModel::computeOperandLatency(), llvm::AMDGPUDisassembler::convertFMAanyK(), llvm::X86_MC::X86MCInstrAnalysis::evaluateBranch(), findFirstPredOperandIdx(), llvm::MachineInstr::findFirstPredOperandIdx(), findFirstVectorPredOperandIdx(), llvm::findFirstVPTPredOperandIdx(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::SIInstrInfo::getInstSizeInBytes(), getOperandConstraint(), llvm::AMDGPU::getOperandSize(), llvm::SIInstrInfo::getOpRegClass(), llvm::TargetInstrInfo::getRegClass(), llvm::SIInstrInfo::getRegClass(), llvm::PPCInstrInfo::getRegNumForOperand(), llvm::AMDGPU::getRegOperandSize(), llvm::MachineInstr::getTypeToPrint(), llvm::ARM_MC::isCPSRDefined(), llvm::SIInstrInfo::isImmOperandLegal(), isInlineConstantIfFolded(), llvm::SIInstrInfo::isOperandLegal(), llvm::HexagonMCInstrInfo::isPredRegister(), isRegOrImmWithInputMods(), llvm::AMDGPU::isSISrcFPOperand(), llvm::AMDGPU::isSISrcInlinableOperand(), llvm::AMDGPU::isSISrcOperand(), isVectorPredicable(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::WebAssemblyMCInstLower::lower(), needsExpandMemInst(), llvm::PPCInstrInfo::onlyFoldImmediate(), opInfo_begin(), opInfo_end(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::HexagonMCInstrInfo::predicateInfo(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), tryAddToFoldList(), tryToFoldACImm(), llvm::SystemZInstrInfo::verifyInstruction(), and llvm::SIInstrInfo::verifyInstruction().

◆ SchedClass

unsigned short llvm::MCInstrDesc::SchedClass

Definition at line 201 of file MCInstrDesc.h.

Referenced by getSchedClass().

◆ Size

unsigned char llvm::MCInstrDesc::Size

Definition at line 200 of file MCInstrDesc.h.

Referenced by getSize().

◆ TSFlags

uint64_t llvm::MCInstrDesc::TSFlags

Definition at line 203 of file MCInstrDesc.h.

The documentation for this class was generated from the following files:

include/llvm/MC/MCInstrDesc.h
lib/MC/MCInstrDesc.cpp

Public Types

Public Member Functions

Public Attributes

Detailed Description

Member Typedef Documentation

◆ const_opInfo_iterator

Member Function Documentation

◆ canFoldAsLoad()

◆ findFirstPredOperandIdx()

◆ getFlags()

◆ getImplicitDefs()

◆ getImplicitUses()

◆ getNumDefs()

◆ getNumImplicitDefs()

◆ getNumImplicitUses()

◆ getNumOperands()

◆ getOpcode()

◆ getOperandConstraint()

◆ getSchedClass()

◆ getSize()

◆ hasDefOfPhysReg()

◆ hasDelaySlot()

◆ hasExtraDefRegAllocReq()

◆ hasExtraSrcRegAllocReq()

◆ hasImplicitDefOfPhysReg()

◆ hasImplicitUseOfPhysReg()

◆ hasOptionalDef()

◆ hasPostISelHook()

◆ hasUnmodeledSideEffects()

◆ isAdd()

◆ isAsCheapAsAMove()

◆ isAuthenticated()

◆ isBarrier()

◆ isBitcast()

◆ isBranch()

◆ isCall()

◆ isCommutable()

◆ isCompare()

◆ isConditionalBranch()

◆ isConvergent()

◆ isConvertibleTo3Addr()

◆ isExtractSubregLike()

◆ isIndirectBranch()

◆ isInsertSubregLike()

◆ isMoveImmediate()

◆ isMoveReg()

◆ isNotDuplicable()

◆ isPredicable()

◆ isPreISelOpcode()

◆ isPseudo()

◆ isRegSequenceLike()

◆ isRematerializable()

◆ isReturn()

◆ isSelect()

◆ isTerminator()

◆ isTrap()

◆ isUnconditionalBranch()

◆ isVariadic()

◆ mayAffectControlFlow()

◆ mayLoad()

◆ mayRaiseFPException()

◆ mayStore()

◆ operands()

◆ opInfo_begin()

◆ opInfo_end()

◆ usesCustomInsertionHook()

◆ variadicOpsAreDefs()

Member Data Documentation

◆ Flags

◆ ImplicitDefs

◆ ImplicitUses

◆ NumDefs

◆ NumOperands

◆ Opcode

◆ OpInfo

◆ SchedClass

◆ Size

◆ TSFlags