15#ifndef LLVM_MC_MCREGISTERINFO_H
16#define LLVM_MC_MCREGISTERINFO_H
70 unsigned InByte = RegNo % 8;
71 unsigned Byte = RegNo / 8;
74 return (
RegSet[Byte] & (1 << InByte)) != 0;
162 unsigned NumRegUnits;
164 const int16_t *DiffLists;
167 const char *RegStrings;
168 const char *RegClassStrings;
173 unsigned NumSubRegIndices;
177 unsigned L2DwarfRegsSize;
178 unsigned EHL2DwarfRegsSize;
179 unsigned Dwarf2LRegsSize;
180 unsigned EHDwarf2LRegsSize;
198 const int16_t *List =
nullptr;
205 void init(
unsigned InitVal,
const int16_t *DiffList) {
231 template <
class SubT>
234 std::forward_iterator_tag, MCPhysReg> {
243 void init(
unsigned InitVal,
const int16_t *DiffList) {
244 Iter.
init(InitVal, DiffList);
256 End.Iter.List =
nullptr;
261 return Iter.List ==
Arg.Iter.List;
266 using mc_difflist_iterator::iterator_facade_base::operator++;
268 assert(Iter.List &&
"Cannot increment the end iterator!");
351 const MCPhysReg (*RURoots)[2],
unsigned NRU,
353 const char *Strings,
const char *ClassStrings,
354 const uint16_t *SubIndices,
unsigned NumIndices,
363 RegUnitMaskSequences = RUMS;
364 RegStrings = Strings;
365 RegClassStrings = ClassStrings;
367 RegUnitRoots = RURoots;
369 SubRegIndices = SubIndices;
370 NumSubRegIndices = NumIndices;
371 SubRegIdxRanges = SubIdxRanges;
372 RegEncodingTable = RET;
375 EHL2DwarfRegs =
nullptr;
376 EHL2DwarfRegsSize = 0;
377 L2DwarfRegs =
nullptr;
379 EHDwarf2LRegs =
nullptr;
380 EHDwarf2LRegsSize = 0;
381 Dwarf2LRegs =
nullptr;
392 EHL2DwarfRegsSize =
Size;
395 L2DwarfRegsSize =
Size;
406 EHDwarf2LRegsSize =
Size;
409 Dwarf2LRegsSize =
Size;
419 L2SEHRegs[LLVMReg] = SEHReg;
423 L2CVRegs[LLVMReg] = CVReg;
439 "Attempting to access record for invalid register number!");
477 return RegStrings +
get(RegNo).
Name;
490 return NumSubRegIndices;
508 std::optional<unsigned>
getLLVMRegNum(
unsigned RegNum,
bool isEH)
const;
540 return RegClassStrings + Class->NameIdx;
546 "Attempting to get encoding for invalid register number!");
547 return RegEncodingTable[RegNo];
591 bool IncludeSelf =
false) {
610 : SRIter(
Reg, MCRI) {
641 bool IncludeSelf =
false) {
672 static constexpr unsigned RegUnitBits = 12;
680 assert(
Reg &&
"Null register has no regunits");
684 unsigned FirstRU = RU & ((1u << RegUnitBits) - 1);
685 unsigned Offset = RU >> RegUnitBits;
708 : RUIter(
Reg, MCRI) {
710 MaskListIter = &MCRI->RegUnitMaskSequences[
Idx];
715 return std::make_pair(*RUIter, *MaskListIter);
746 assert(RegUnit < MCRI->getNumRegUnits() &&
"Invalid register unit");
747 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
748 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
785 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
790 if (!(!IncludeSelf && Reg == *
SI))
800 assert(
SI.isValid() &&
"Cannot dereference an invalid iterator.");
807 if (
SI.isValid())
return;
825 while (!IncludeSelf &&
isValid() && *
SI == Reg);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
MCRegAliasIterator enumerates all registers aliasing Reg.
MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf)
MCRegister operator*() const
MCRegUnitIterator()=default
MCRegUnitIterator - Create an iterator that traverses the register units in Reg.
MCRegUnitIterator & operator++()
MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.
MCRegUnitMaskIterator()=default
MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses the register units and their associated LaneMasks in Reg.
bool isValid() const
Returns true if this iterator is not yet at the end.
void operator++()
Moves to the next position.
std::pair< unsigned, LaneBitmask > operator*() const
Returns a (RegUnit, LaneMask) pair.
MCRegUnitRootIterator enumerates the root registers of a register unit.
MCRegUnitRootIterator()=default
unsigned operator*() const
Dereference to get the current root register.
MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI)
void operator++()
Preincrement to move to the next root register.
bool isValid() const
Check if the iterator is at the end of the list.
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getID() const
getID() - Return the register class ID number.
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
const uint16_t RegSizeInBits
unsigned getSizeInBits() const
Return the size of the physical register in bits if we are able to determine it.
const uint16_t RegSetSize
bool contains(MCRegister Reg1, MCRegister Reg2) const
contains - Return true if both registers are in this class.
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
iterator begin() const
begin/end - Return all of the registers in this class.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
const uint8_t *const RegSet
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
DiffListIterator - Base iterator class that can traverse the differentially encoded register and regu...
MCRegister operator*() const
Dereference the iterator to get the value at the current position.
void init(unsigned InitVal, const int16_t *DiffList)
Point the iterator to InitVal, decoding subsequent values from DiffList.
void operator++()
Pre-increment to move to the next position.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
DiffListIterator()=default
Create an invalid iterator. Call init() to point to something useful.
Forward iterator using DiffListIterator.
static SubT end()
Return an iterator past the last element.
const MCPhysReg & operator*() const
mc_difflist_iterator()=default
void init(unsigned InitVal, const int16_t *DiffList)
Point the iterator to InitVal, decoding subsequent values from DiffList.
bool operator==(const mc_difflist_iterator &Arg) const
mc_difflist_iterator(MCRegisterInfo::DiffListIterator Iter)
Forward iterator over all sub-registers.
mc_subreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI)
mc_subreg_iterator(MCRegisterInfo::DiffListIterator Iter)
mc_subreg_iterator()=default
Forward iterator over all super-registers.
mc_superreg_iterator()=default
mc_superreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI)
mc_superreg_iterator(MCRegisterInfo::DiffListIterator Iter)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA or if RegB == RegA.
unsigned getNumRegClasses() const
MCRegister getRARegister() const
This method should return the register where the return address can be found.
MCRegister getProgramCounter() const
Return the register which is the program counter.
regclass_iterator regclass_end() const
void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize Dwarf register to LLVM register number mapping.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
int getCodeViewRegNum(MCRegister RegNum) const
Map a target register to an equivalent CodeView register number.
iterator_range< mc_superreg_iterator > superregs_inclusive(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, including Reg.
std::optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
iterator_range< regclass_iterator > regclasses() const
regclass_iterator regclass_begin() const
const MCRegisterDesc & get(MCRegister RegNo) const
Provide a get method, equivalent to [], but more useful with a pointer to this object.
int getSEHRegNum(MCRegister RegNum) const
Map a target register to an equivalent SEH register number.
void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg)
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
const char * getRegClassName(const MCRegisterClass *Class) const
int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const
Map a target EH register number to an equivalent DWARF register number.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
iterator_range< mc_superreg_iterator > superregs(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, excluding Reg.
void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const int16_t *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET)
Initialize MCRegisterInfo, called by TableGen auto-generated routines.
iterator_range< mc_subreg_iterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
iterator_range< mc_subreg_iterator > subregs_inclusive(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, including Reg.
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize LLVM register to Dwarf register number mapping.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA or if RegB == RegA.
detail::concat_range< const MCPhysReg, iterator_range< mc_subreg_iterator >, iterator_range< mc_superreg_iterator > > sub_and_superregs_inclusive(MCRegister Reg) const
Return an iterator range over all sub- and super-registers of Reg, including Reg.
void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg)
mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
const MCRegisterDesc & operator[](MCRegister RegNo) const
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices.
MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses subregisters and their associated subregister indices.
bool isValid() const
Returns true if this iterator is not yet at the end.
void operator++()
Moves to the next position.
unsigned getSubRegIndex() const
Returns sub-register index of the current sub-register.
MCRegister getSubReg() const
Returns current sub-register.
MCSubRegIterator enumerates all sub-registers of Reg.
MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
MCSuperRegIterator enumerates all super-registers of Reg.
MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
MCSuperRegIterator()=default
Helper to store a sequence of ranges being concatenated and access them.
CRTP base class which implements the entire standard iterator facade in terms of a minimal subset of ...
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
MCRegisterDesc - This record contains information about a particular register.
uint16_t RegUnitLaneMasks
Index into list with lane mask sequences.
DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be performed with a binary se...
bool operator<(DwarfLLVMRegPair RHS) const
SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...