LLVM 17.0.0git
MCRegisterInfo.h
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1//===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes an abstract interface used to get information about a
10// target machines register file. This information is used for a variety of
11// purposed, especially register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_MC_MCREGISTERINFO_H
16#define LLVM_MC_MCREGISTERINFO_H
17
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/iterator.h"
21#include "llvm/MC/LaneBitmask.h"
22#include "llvm/MC/MCRegister.h"
23#include <cassert>
24#include <cstdint>
25#include <iterator>
26#include <utility>
27
28namespace llvm {
29
30/// MCRegisterClass - Base class of TargetRegisterClass.
32public:
33 using iterator = const MCPhysReg*;
34 using const_iterator = const MCPhysReg*;
35
37 const uint8_t *const RegSet;
41 const uint16_t ID;
43 const int8_t CopyCost;
44 const bool Allocatable;
45
46 /// getID() - Return the register class ID number.
47 ///
48 unsigned getID() const { return ID; }
49
50 /// begin/end - Return all of the registers in this class.
51 ///
52 iterator begin() const { return RegsBegin; }
53 iterator end() const { return RegsBegin + RegsSize; }
54
55 /// getNumRegs - Return the number of registers in this class.
56 ///
57 unsigned getNumRegs() const { return RegsSize; }
58
59 /// getRegister - Return the specified register in the class.
60 ///
61 unsigned getRegister(unsigned i) const {
62 assert(i < getNumRegs() && "Register number out of range!");
63 return RegsBegin[i];
64 }
65
66 /// contains - Return true if the specified register is included in this
67 /// register class. This does not include virtual registers.
68 bool contains(MCRegister Reg) const {
69 unsigned RegNo = unsigned(Reg);
70 unsigned InByte = RegNo % 8;
71 unsigned Byte = RegNo / 8;
72 if (Byte >= RegSetSize)
73 return false;
74 return (RegSet[Byte] & (1 << InByte)) != 0;
75 }
76
77 /// contains - Return true if both registers are in this class.
78 bool contains(MCRegister Reg1, MCRegister Reg2) const {
79 return contains(Reg1) && contains(Reg2);
80 }
81
82 /// Return the size of the physical register in bits if we are able to
83 /// determine it. This always returns zero for registers of targets that use
84 /// HW modes, as we need more information to determine the size of registers
85 /// in such cases. Use TargetRegisterInfo to cover them.
86 unsigned getSizeInBits() const { return RegSizeInBits; }
87
88 /// getCopyCost - Return the cost of copying a value between two registers in
89 /// this class. A negative number means the register class is very expensive
90 /// to copy e.g. status flag register classes.
91 int getCopyCost() const { return CopyCost; }
92
93 /// isAllocatable - Return true if this register class may be used to create
94 /// virtual registers.
95 bool isAllocatable() const { return Allocatable; }
96};
97
98/// MCRegisterDesc - This record contains information about a particular
99/// register. The SubRegs field is a zero terminated array of registers that
100/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
101/// of AX. The SuperRegs field is a zero terminated array of registers that are
102/// super-registers of the specific register, e.g. RAX, EAX, are
103/// super-registers of AX.
104///
106 uint32_t Name; // Printable name for the reg (for debugging)
107 uint32_t SubRegs; // Sub-register set, described above
108 uint32_t SuperRegs; // Super-register set, described above
109
110 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
111 // sub-register in SubRegs.
113
114 // RegUnits - Points to the list of register units. The low 4 bits holds the
115 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
117
118 /// Index into list with lane mask sequences. The sequence contains a lanemask
119 /// for every register unit.
121};
122
123/// MCRegisterInfo base class - We assume that the target defines a static
124/// array of MCRegisterDesc objects that represent all of the machine
125/// registers that the target has. As such, we simply have to track a pointer
126/// to this array so that we can turn register number into a register
127/// descriptor.
128///
129/// Note this class is designed to be a base class of TargetRegisterInfo, which
130/// is the interface used by codegen. However, specific targets *should never*
131/// specialize this class. MCRegisterInfo should only contain getters to access
132/// TableGen generated physical register data. It must not be extended with
133/// virtual methods.
134///
136public:
138
139 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
140 /// performed with a binary search.
142 unsigned FromReg;
143 unsigned ToReg;
144
145 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
146 };
147
148 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
149 /// index, -1 in any being invalid.
153 };
154
155private:
156 const MCRegisterDesc *Desc; // Pointer to the descriptor array
157 unsigned NumRegs; // Number of entries in the array
158 MCRegister RAReg; // Return address register
159 MCRegister PCReg; // Program counter register
160 const MCRegisterClass *Classes; // Pointer to the regclass array
161 unsigned NumClasses; // Number of entries in the array
162 unsigned NumRegUnits; // Number of regunits.
163 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
164 const MCPhysReg *DiffLists; // Pointer to the difflists array
165 const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences
166 // for register units.
167 const char *RegStrings; // Pointer to the string table.
168 const char *RegClassStrings; // Pointer to the class strings.
169 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
170 // array.
171 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
172 // bit ranges array.
173 unsigned NumSubRegIndices; // Number of subreg indices.
174 const uint16_t *RegEncodingTable; // Pointer to array of register
175 // encodings.
176
177 unsigned L2DwarfRegsSize;
178 unsigned EHL2DwarfRegsSize;
179 unsigned Dwarf2LRegsSize;
180 unsigned EHDwarf2LRegsSize;
181 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
182 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
183 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
184 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
185 DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping
186 DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping
187
188public:
189 // Forward declaration to become a friend class of DiffListIterator.
190 template <class SubT> class mc_difflist_iterator;
191
192 /// DiffListIterator - Base iterator class that can traverse the
193 /// differentially encoded register and regunit lists in DiffLists.
194 /// Don't use this class directly, use one of the specialized sub-classes
195 /// defined below.
197 uint16_t Val = 0;
198 const MCPhysReg *List = nullptr;
199
200 protected:
201 /// Create an invalid iterator. Call init() to point to something useful.
202 DiffListIterator() = default;
203
204 /// init - Point the iterator to InitVal, decoding subsequent values from
205 /// DiffList. The iterator will initially point to InitVal, sub-classes are
206 /// responsible for skipping the seed value if it is not part of the list.
207 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
208 Val = InitVal;
209 List = DiffList;
210 }
211
212 /// advance - Move to the next list position, return the applied
213 /// differential. This function does not detect the end of the list, that
214 /// is the caller's responsibility (by checking for a 0 return value).
216 assert(isValid() && "Cannot move off the end of the list.");
217 MCPhysReg D = *List++;
218 Val += D;
219 return D;
220 }
221
222 public:
223 /// isValid - returns true if this iterator is not yet at the end.
224 bool isValid() const { return List; }
225
226 /// Dereference the iterator to get the value at the current position.
227 MCRegister operator*() const { return Val; }
228
229 /// Pre-increment to move to the next position.
230 void operator++() {
231 // The end of the list is encoded as a 0 differential.
232 if (!advance())
233 List = nullptr;
234 }
235
236 template <class SubT> friend class MCRegisterInfo::mc_difflist_iterator;
237 };
238
239 /// Forward iterator using DiffListIterator.
240 template <class SubT>
242 : public iterator_facade_base<mc_difflist_iterator<SubT>,
243 std::forward_iterator_tag, MCPhysReg> {
245 /// Current value as MCPhysReg, so we can return a reference to it.
246 MCPhysReg Val;
247
248 protected:
250
251 // Allow conversion between instantiations where valid.
253 Iter.init(Reg, DiffList);
254 Val = *Iter;
255 }
256
257 public:
258 // Allow default construction to build variables, but this doesn't build
259 // a useful iterator.
261
262 /// Return an iterator past the last element.
263 static SubT end() {
264 SubT End;
265 End.Iter.List = nullptr;
266 return End;
267 }
268
270 return Iter.List == Arg.Iter.List;
271 }
272
273 const MCPhysReg &operator*() const { return Val; }
274
275 using mc_difflist_iterator::iterator_facade_base::operator++;
276 void operator++() {
277 assert(Iter.List && "Cannot increment the end iterator!");
278 ++Iter;
279 Val = *Iter;
280 }
281 };
282
283 /// Forward iterator over all sub-registers.
284 /// TODO: Replace remaining uses of MCSubRegIterator.
285 class mc_subreg_iterator : public mc_difflist_iterator<mc_subreg_iterator> {
286 public:
288 : mc_difflist_iterator(Iter) {}
291 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {}
292 };
293
294 /// Forward iterator over all super-registers.
295 /// TODO: Replace remaining uses of MCSuperRegIterator.
297 : public mc_difflist_iterator<mc_superreg_iterator> {
298 public:
300 : mc_difflist_iterator(Iter) {}
304 MCRI->DiffLists + MCRI->get(Reg).SuperRegs) {}
305 };
306
307 /// Return an iterator range over all sub-registers of \p Reg, excluding \p
308 /// Reg.
310 return make_range(std::next(mc_subreg_iterator(Reg, this)),
312 }
313
314 /// Return an iterator range over all sub-registers of \p Reg, including \p
315 /// Reg.
317 return make_range({Reg, this}, mc_subreg_iterator::end());
318 }
319
320 /// Return an iterator range over all super-registers of \p Reg, excluding \p
321 /// Reg.
323 return make_range(std::next(mc_superreg_iterator(Reg, this)),
325 }
326
327 /// Return an iterator range over all super-registers of \p Reg, including \p
328 /// Reg.
331 return make_range({Reg, this}, mc_superreg_iterator::end());
332 }
333
334 /// Return an iterator range over all sub- and super-registers of \p Reg,
335 /// including \p Reg.
339 return concat<const MCPhysReg>(subregs_inclusive(Reg), superregs(Reg));
340 }
341
342 // These iterators are allowed to sub-class DiffListIterator and access
343 // internal list pointers.
344 friend class MCSubRegIterator;
346 friend class MCSuperRegIterator;
347 friend class MCRegUnitIterator;
350
351 /// Initialize MCRegisterInfo, called by TableGen
352 /// auto-generated routines. *DO NOT USE*.
353 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
354 unsigned PC,
355 const MCRegisterClass *C, unsigned NC,
356 const MCPhysReg (*RURoots)[2],
357 unsigned NRU,
358 const MCPhysReg *DL,
359 const LaneBitmask *RUMS,
360 const char *Strings,
361 const char *ClassStrings,
362 const uint16_t *SubIndices,
363 unsigned NumIndices,
364 const SubRegCoveredBits *SubIdxRanges,
365 const uint16_t *RET) {
366 Desc = D;
367 NumRegs = NR;
368 RAReg = RA;
369 PCReg = PC;
370 Classes = C;
371 DiffLists = DL;
372 RegUnitMaskSequences = RUMS;
373 RegStrings = Strings;
374 RegClassStrings = ClassStrings;
375 NumClasses = NC;
376 RegUnitRoots = RURoots;
377 NumRegUnits = NRU;
378 SubRegIndices = SubIndices;
379 NumSubRegIndices = NumIndices;
380 SubRegIdxRanges = SubIdxRanges;
381 RegEncodingTable = RET;
382
383 // Initialize DWARF register mapping variables
384 EHL2DwarfRegs = nullptr;
385 EHL2DwarfRegsSize = 0;
386 L2DwarfRegs = nullptr;
387 L2DwarfRegsSize = 0;
388 EHDwarf2LRegs = nullptr;
389 EHDwarf2LRegsSize = 0;
390 Dwarf2LRegs = nullptr;
391 Dwarf2LRegsSize = 0;
392 }
393
394 /// Used to initialize LLVM register to Dwarf
395 /// register number mapping. Called by TableGen auto-generated routines.
396 /// *DO NOT USE*.
398 bool isEH) {
399 if (isEH) {
400 EHL2DwarfRegs = Map;
401 EHL2DwarfRegsSize = Size;
402 } else {
403 L2DwarfRegs = Map;
404 L2DwarfRegsSize = Size;
405 }
406 }
407
408 /// Used to initialize Dwarf register to LLVM
409 /// register number mapping. Called by TableGen auto-generated routines.
410 /// *DO NOT USE*.
412 bool isEH) {
413 if (isEH) {
414 EHDwarf2LRegs = Map;
415 EHDwarf2LRegsSize = Size;
416 } else {
417 Dwarf2LRegs = Map;
418 Dwarf2LRegsSize = Size;
419 }
420 }
421
422 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
423 /// number mapping. By default the SEH register number is just the same
424 /// as the LLVM register number.
425 /// FIXME: TableGen these numbers. Currently this requires target specific
426 /// initialization code.
427 void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) {
428 L2SEHRegs[LLVMReg] = SEHReg;
429 }
430
431 void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) {
432 L2CVRegs[LLVMReg] = CVReg;
433 }
434
435 /// This method should return the register where the return
436 /// address can be found.
438 return RAReg;
439 }
440
441 /// Return the register which is the program counter.
443 return PCReg;
444 }
445
447 assert(RegNo < NumRegs &&
448 "Attempting to access record for invalid register number!");
449 return Desc[RegNo];
450 }
451
452 /// Provide a get method, equivalent to [], but more useful with a
453 /// pointer to this object.
454 const MCRegisterDesc &get(MCRegister RegNo) const {
455 return operator[](RegNo);
456 }
457
458 /// Returns the physical register number of sub-register "Index"
459 /// for physical register RegNo. Return zero if the sub-register does not
460 /// exist.
461 MCRegister getSubReg(MCRegister Reg, unsigned Idx) const;
462
463 /// Return a super-register of the specified register
464 /// Reg so its sub-register of index SubIdx is Reg.
466 const MCRegisterClass *RC) const;
467
468 /// For a given register pair, return the sub-register index
469 /// if the second register is a sub-register of the first. Return zero
470 /// otherwise.
471 unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const;
472
473 /// Get the size of the bit range covered by a sub-register index.
474 /// If the index isn't continuous, return the sum of the sizes of its parts.
475 /// If the index is used to access subregisters of different sizes, return -1.
476 unsigned getSubRegIdxSize(unsigned Idx) const;
477
478 /// Get the offset of the bit range covered by a sub-register index.
479 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
480 /// access sub-registers at different offsets), return -1.
481 unsigned getSubRegIdxOffset(unsigned Idx) const;
482
483 /// Return the human-readable symbolic target-specific name for the
484 /// specified physical register.
485 const char *getName(MCRegister RegNo) const {
486 return RegStrings + get(RegNo).Name;
487 }
488
489 /// Return the number of registers this target has (useful for
490 /// sizing arrays holding per register information)
491 unsigned getNumRegs() const {
492 return NumRegs;
493 }
494
495 /// Return the number of sub-register indices
496 /// understood by the target. Index 0 is reserved for the no-op sub-register,
497 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
498 unsigned getNumSubRegIndices() const {
499 return NumSubRegIndices;
500 }
501
502 /// Return the number of (native) register units in the
503 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
504 /// can be accessed through MCRegUnitIterator defined below.
505 unsigned getNumRegUnits() const {
506 return NumRegUnits;
507 }
508
509 /// Map a target register to an equivalent dwarf register
510 /// number. Returns -1 if there is no equivalent value. The second
511 /// parameter allows targets to use different numberings for EH info and
512 /// debugging info.
513 int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
514
515 /// Map a dwarf register back to a target register. Returns std::nullopt is
516 /// there is no mapping.
517 std::optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
518
519 /// Map a target EH register number to an equivalent DWARF register
520 /// number.
521 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
522
523 /// Map a target register to an equivalent SEH register
524 /// number. Returns LLVM register number if there is no equivalent value.
525 int getSEHRegNum(MCRegister RegNum) const;
526
527 /// Map a target register to an equivalent CodeView register
528 /// number.
529 int getCodeViewRegNum(MCRegister RegNum) const;
530
531 regclass_iterator regclass_begin() const { return Classes; }
532 regclass_iterator regclass_end() const { return Classes+NumClasses; }
535 }
536
537 unsigned getNumRegClasses() const {
538 return (unsigned)(regclass_end()-regclass_begin());
539 }
540
541 /// Returns the register class associated with the enumeration
542 /// value. See class MCOperandInfo.
543 const MCRegisterClass& getRegClass(unsigned i) const {
544 assert(i < getNumRegClasses() && "Register Class ID out of range");
545 return Classes[i];
546 }
547
548 const char *getRegClassName(const MCRegisterClass *Class) const {
549 return RegClassStrings + Class->NameIdx;
550 }
551
552 /// Returns the encoding for RegNo
554 assert(RegNo < NumRegs &&
555 "Attempting to get encoding for invalid register number!");
556 return RegEncodingTable[RegNo];
557 }
558
559 /// Returns true if RegB is a sub-register of RegA.
560 bool isSubRegister(MCRegister RegA, MCRegister RegB) const {
561 return isSuperRegister(RegB, RegA);
562 }
563
564 /// Returns true if RegB is a super-register of RegA.
565 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
566
567 /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
568 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
569 return isSuperRegisterEq(RegB, RegA);
570 }
571
572 /// Returns true if RegB is a super-register of RegA or if
573 /// RegB == RegA.
574 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const {
575 return RegA == RegB || isSuperRegister(RegA, RegB);
576 }
577
578 /// Returns true if RegB is a super-register or sub-register of RegA
579 /// or if RegB == RegA.
581 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
582 }
583
584 /// Returns true if the two registers are equal or alias each other.
585 bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
586};
587
588//===----------------------------------------------------------------------===//
589// Register List Iterators
590//===----------------------------------------------------------------------===//
591
592// MCRegisterInfo provides lists of super-registers, sub-registers, and
593// aliasing registers. Use these iterator classes to traverse the lists.
594
595/// MCSubRegIterator enumerates all sub-registers of Reg.
596/// If IncludeSelf is set, Reg itself is included in the list.
598public:
600 bool IncludeSelf = false) {
601 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
602 // Initially, the iterator points to Reg itself.
603 if (!IncludeSelf)
604 ++*this;
605 }
606};
607
608/// Iterator that enumerates the sub-registers of a Reg and the associated
609/// sub-register indices.
611 MCSubRegIterator SRIter;
612 const uint16_t *SRIndex;
613
614public:
615 /// Constructs an iterator that traverses subregisters and their
616 /// associated subregister indices.
618 : SRIter(Reg, MCRI) {
619 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
620 }
621
622 /// Returns current sub-register.
624 return *SRIter;
625 }
626
627 /// Returns sub-register index of the current sub-register.
628 unsigned getSubRegIndex() const {
629 return *SRIndex;
630 }
631
632 /// Returns true if this iterator is not yet at the end.
633 bool isValid() const { return SRIter.isValid(); }
634
635 /// Moves to the next position.
636 void operator++() {
637 ++SRIter;
638 ++SRIndex;
639 }
640};
641
642/// MCSuperRegIterator enumerates all super-registers of Reg.
643/// If IncludeSelf is set, Reg itself is included in the list.
645public:
647
649 bool IncludeSelf = false) {
650 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
651 // Initially, the iterator points to Reg itself.
652 if (!IncludeSelf)
653 ++*this;
654 }
655};
656
657// Definition for isSuperRegister. Put it down here since it needs the
658// iterator defined above in addition to the MCRegisterInfo class itself.
660 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
661 if (*I == RegB)
662 return true;
663 return false;
664}
665
666//===----------------------------------------------------------------------===//
667// Register Units
668//===----------------------------------------------------------------------===//
669
670// Register units are used to compute register aliasing. Every register has at
671// least one register unit, but it can have more. Two registers overlap if and
672// only if they have a common register unit.
673//
674// A target with a complicated sub-register structure will typically have many
675// fewer register units than actual registers. MCRI::getNumRegUnits() returns
676// the number of register units in the target.
677
678// MCRegUnitIterator enumerates a list of register units for Reg. The list is
679// in ascending numerical order.
681public:
682 /// MCRegUnitIterator - Create an iterator that traverses the register units
683 /// in Reg.
684 MCRegUnitIterator() = default;
685
687 assert(Reg && "Null register has no regunits");
689 // Decode the RegUnits MCRegisterDesc field.
690 unsigned RU = MCRI->get(Reg).RegUnits;
691 unsigned Scale = RU & 15;
692 unsigned Offset = RU >> 4;
693
694 // Initialize the iterator to Reg * Scale, and the List pointer to
695 // DiffLists + Offset.
696 init(Reg * Scale, MCRI->DiffLists + Offset);
697
698 // That may not be a valid unit, we need to advance by one to get the real
699 // unit number. The first differential can be 0 which would normally
700 // terminate the list, but since we know every register has at least one
701 // unit, we can allow a 0 differential here.
702 advance();
703 }
704
707 return *this;
708 }
709};
710
711/// MCRegUnitMaskIterator enumerates a list of register units and their
712/// associated lane masks for Reg. The register units are in ascending
713/// numerical order.
715 MCRegUnitIterator RUIter;
716 const LaneBitmask *MaskListIter;
717
718public:
720
721 /// Constructs an iterator that traverses the register units and their
722 /// associated LaneMasks in Reg.
724 : RUIter(Reg, MCRI) {
726 MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
727 }
728
729 /// Returns a (RegUnit, LaneMask) pair.
730 std::pair<unsigned,LaneBitmask> operator*() const {
731 return std::make_pair(*RUIter, *MaskListIter);
732 }
733
734 /// Returns true if this iterator is not yet at the end.
735 bool isValid() const { return RUIter.isValid(); }
736
737 /// Moves to the next position.
738 void operator++() {
739 ++MaskListIter;
740 ++RUIter;
741 }
742};
743
744// Each register unit has one or two root registers. The complete set of
745// registers containing a register unit is the union of the roots and their
746// super-registers. All registers aliasing Unit can be visited like this:
747//
748// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
749// for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
750// visit(*SI);
751// }
752
753/// MCRegUnitRootIterator enumerates the root registers of a register unit.
755 uint16_t Reg0 = 0;
756 uint16_t Reg1 = 0;
757
758public:
760
761 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
762 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
763 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
764 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
765 }
766
767 /// Dereference to get the current root register.
768 unsigned operator*() const {
769 return Reg0;
770 }
771
772 /// Check if the iterator is at the end of the list.
773 bool isValid() const {
774 return Reg0;
775 }
776
777 /// Preincrement to move to the next root register.
778 void operator++() {
779 assert(isValid() && "Cannot move off the end of the list.");
780 Reg0 = Reg1;
781 Reg1 = 0;
782 }
783};
784
785/// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
786/// set, Reg itself is included in the list. This iterator does not guarantee
787/// any ordering or that entries are unique.
789private:
790 MCRegister Reg;
791 const MCRegisterInfo *MCRI;
792 bool IncludeSelf;
793
797
798public:
800 bool IncludeSelf)
801 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
802 // Initialize the iterators.
803 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
804 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
805 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
806 if (!(!IncludeSelf && Reg == *SI))
807 return;
808 }
809 }
810 }
811 }
812
813 bool isValid() const { return RI.isValid(); }
814
816 assert(SI.isValid() && "Cannot dereference an invalid iterator.");
817 return *SI;
818 }
819
820 void advance() {
821 // Assuming SI is valid.
822 ++SI;
823 if (SI.isValid()) return;
824
825 ++RRI;
826 if (RRI.isValid()) {
827 SI = MCSuperRegIterator(*RRI, MCRI, true);
828 return;
829 }
830
831 ++RI;
832 if (RI.isValid()) {
833 RRI = MCRegUnitRootIterator(*RI, MCRI);
834 SI = MCSuperRegIterator(*RRI, MCRI, true);
835 }
836 }
837
838 void operator++() {
839 assert(isValid() && "Cannot move off the end of the list.");
840 do advance();
841 while (!IncludeSelf && isValid() && *SI == Reg);
842 }
843};
844
845} // end namespace llvm
846
847#endif // LLVM_MC_MCREGISTERINFO_H
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
uint64_t Size
A common definition of LaneBitmask for use in TableGen and CodeGen.
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned Reg
const NodeList & List
Definition: RDFGraph.cpp:199
@ SI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
Value * RHS
MCRegAliasIterator enumerates all registers aliasing Reg.
MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf)
MCRegister operator*() const
MCRegUnitIterator()=default
MCRegUnitIterator - Create an iterator that traverses the register units in Reg.
MCRegUnitIterator & operator++()
MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.
MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses the register units and their associated LaneMasks in Reg.
bool isValid() const
Returns true if this iterator is not yet at the end.
void operator++()
Moves to the next position.
std::pair< unsigned, LaneBitmask > operator*() const
Returns a (RegUnit, LaneMask) pair.
MCRegUnitRootIterator enumerates the root registers of a register unit.
unsigned operator*() const
Dereference to get the current root register.
MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI)
void operator++()
Preincrement to move to the next root register.
bool isValid() const
Check if the iterator is at the end of the list.
MCRegisterClass - Base class of TargetRegisterClass.
const uint32_t NameIdx
unsigned getID() const
getID() - Return the register class ID number.
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
const uint16_t RegSizeInBits
unsigned getSizeInBits() const
Return the size of the physical register in bits if we are able to determine it.
const uint16_t RegSetSize
bool contains(MCRegister Reg1, MCRegister Reg2) const
contains - Return true if both registers are in this class.
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
iterator begin() const
begin/end - Return all of the registers in this class.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
const uint8_t *const RegSet
const iterator RegsBegin
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
iterator end() const
const uint16_t RegsSize
DiffListIterator - Base iterator class that can traverse the differentially encoded register and regu...
MCRegister operator*() const
Dereference the iterator to get the value at the current position.
MCRegister advance()
advance - Move to the next list position, return the applied differential.
void operator++()
Pre-increment to move to the next position.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void init(MCPhysReg InitVal, const MCPhysReg *DiffList)
init - Point the iterator to InitVal, decoding subsequent values from DiffList.
DiffListIterator()=default
Create an invalid iterator. Call init() to point to something useful.
Forward iterator using DiffListIterator.
static SubT end()
Return an iterator past the last element.
mc_difflist_iterator(MCRegister Reg, const MCPhysReg *DiffList)
bool operator==(const mc_difflist_iterator &Arg) const
mc_difflist_iterator(MCRegisterInfo::DiffListIterator Iter)
Forward iterator over all sub-registers.
mc_subreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI)
mc_subreg_iterator(MCRegisterInfo::DiffListIterator Iter)
Forward iterator over all super-registers.
mc_superreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI)
mc_superreg_iterator(MCRegisterInfo::DiffListIterator Iter)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA or if RegB == RegA.
unsigned getNumRegClasses() const
MCRegister getRARegister() const
This method should return the register where the return address can be found.
MCRegister getProgramCounter() const
Return the register which is the program counter.
regclass_iterator regclass_end() const
void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize Dwarf register to LLVM register number mapping.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
int getCodeViewRegNum(MCRegister RegNum) const
Map a target register to an equivalent CodeView register number.
iterator_range< mc_superreg_iterator > superregs_inclusive(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, including Reg.
std::optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
iterator_range< regclass_iterator > regclasses() const
regclass_iterator regclass_begin() const
const MCRegisterDesc & get(MCRegister RegNo) const
Provide a get method, equivalent to [], but more useful with a pointer to this object.
int getSEHRegNum(MCRegister RegNum) const
Map a target register to an equivalent SEH register number.
void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg)
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
const char * getRegClassName(const MCRegisterClass *Class) const
int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const
Map a target EH register number to an equivalent DWARF register number.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET)
Initialize MCRegisterInfo, called by TableGen auto-generated routines.
iterator_range< mc_superreg_iterator > superregs(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, excluding Reg.
iterator_range< mc_subreg_iterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
iterator_range< mc_subreg_iterator > subregs_inclusive(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, including Reg.
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize LLVM register to Dwarf register number mapping.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA or if RegB == RegA.
detail::concat_range< const MCPhysReg, iterator_range< mc_subreg_iterator >, iterator_range< mc_superreg_iterator > > sub_and_superregs_inclusive(MCRegister Reg) const
Return an iterator range over all sub- and super-registers of Reg, including Reg.
void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg)
mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
const MCRegisterDesc & operator[](MCRegister RegNo) const
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: MCRegister.h:58
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices.
MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses subregisters and their associated subregister indices.
bool isValid() const
Returns true if this iterator is not yet at the end.
void operator++()
Moves to the next position.
unsigned getSubRegIndex() const
Returns sub-register index of the current sub-register.
MCRegister getSubReg() const
Returns current sub-register.
MCSubRegIterator enumerates all sub-registers of Reg.
MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
MCSuperRegIterator enumerates all super-registers of Reg.
MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
Helper to store a sequence of ranges being concatenated and access them.
Definition: STLExtras.h:1159
CRTP base class which implements the entire standard iterator facade in terms of a minimal subset of ...
Definition: iterator.h:80
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
#define NC
Definition: regutils.h:42
MCRegisterDesc - This record contains information about a particular register.
uint16_t RegUnitLaneMasks
Index into list with lane mask sequences.
DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be performed with a binary se...
bool operator<(DwarfLLVMRegPair RHS) const
SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...