LLVM 17.0.0git
MCRegisterInfo.h
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1//===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes an abstract interface used to get information about a
10// target machines register file. This information is used for a variety of
11// purposed, especially register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_MC_MCREGISTERINFO_H
16#define LLVM_MC_MCREGISTERINFO_H
17
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/iterator.h"
21#include "llvm/MC/LaneBitmask.h"
22#include "llvm/MC/MCRegister.h"
23#include <cassert>
24#include <cstdint>
25#include <iterator>
26#include <utility>
27
28namespace llvm {
29
30/// MCRegisterClass - Base class of TargetRegisterClass.
32public:
33 using iterator = const MCPhysReg*;
34 using const_iterator = const MCPhysReg*;
35
37 const uint8_t *const RegSet;
41 const uint16_t ID;
43 const int8_t CopyCost;
44 const bool Allocatable;
45
46 /// getID() - Return the register class ID number.
47 ///
48 unsigned getID() const { return ID; }
49
50 /// begin/end - Return all of the registers in this class.
51 ///
52 iterator begin() const { return RegsBegin; }
53 iterator end() const { return RegsBegin + RegsSize; }
54
55 /// getNumRegs - Return the number of registers in this class.
56 ///
57 unsigned getNumRegs() const { return RegsSize; }
58
59 /// getRegister - Return the specified register in the class.
60 ///
61 unsigned getRegister(unsigned i) const {
62 assert(i < getNumRegs() && "Register number out of range!");
63 return RegsBegin[i];
64 }
65
66 /// contains - Return true if the specified register is included in this
67 /// register class. This does not include virtual registers.
68 bool contains(MCRegister Reg) const {
69 unsigned RegNo = unsigned(Reg);
70 unsigned InByte = RegNo % 8;
71 unsigned Byte = RegNo / 8;
72 if (Byte >= RegSetSize)
73 return false;
74 return (RegSet[Byte] & (1 << InByte)) != 0;
75 }
76
77 /// contains - Return true if both registers are in this class.
78 bool contains(MCRegister Reg1, MCRegister Reg2) const {
79 return contains(Reg1) && contains(Reg2);
80 }
81
82 /// Return the size of the physical register in bits if we are able to
83 /// determine it. This always returns zero for registers of targets that use
84 /// HW modes, as we need more information to determine the size of registers
85 /// in such cases. Use TargetRegisterInfo to cover them.
86 unsigned getSizeInBits() const { return RegSizeInBits; }
87
88 /// getCopyCost - Return the cost of copying a value between two registers in
89 /// this class. A negative number means the register class is very expensive
90 /// to copy e.g. status flag register classes.
91 int getCopyCost() const { return CopyCost; }
92
93 /// isAllocatable - Return true if this register class may be used to create
94 /// virtual registers.
95 bool isAllocatable() const { return Allocatable; }
96};
97
98/// MCRegisterDesc - This record contains information about a particular
99/// register. The SubRegs field is a zero terminated array of registers that
100/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
101/// of AX. The SuperRegs field is a zero terminated array of registers that are
102/// super-registers of the specific register, e.g. RAX, EAX, are
103/// super-registers of AX.
104///
106 uint32_t Name; // Printable name for the reg (for debugging)
107 uint32_t SubRegs; // Sub-register set, described above
108 uint32_t SuperRegs; // Super-register set, described above
109
110 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
111 // sub-register in SubRegs.
113
114 // Points to the list of register units. The low bits hold the first regunit
115 // number, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
117
118 /// Index into list with lane mask sequences. The sequence contains a lanemask
119 /// for every register unit.
121};
122
123/// MCRegisterInfo base class - We assume that the target defines a static
124/// array of MCRegisterDesc objects that represent all of the machine
125/// registers that the target has. As such, we simply have to track a pointer
126/// to this array so that we can turn register number into a register
127/// descriptor.
128///
129/// Note this class is designed to be a base class of TargetRegisterInfo, which
130/// is the interface used by codegen. However, specific targets *should never*
131/// specialize this class. MCRegisterInfo should only contain getters to access
132/// TableGen generated physical register data. It must not be extended with
133/// virtual methods.
134///
136public:
138
139 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
140 /// performed with a binary search.
142 unsigned FromReg;
143 unsigned ToReg;
144
145 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
146 };
147
148 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
149 /// index, -1 in any being invalid.
153 };
154
155private:
156 const MCRegisterDesc *Desc; // Pointer to the descriptor array
157 unsigned NumRegs; // Number of entries in the array
158 MCRegister RAReg; // Return address register
159 MCRegister PCReg; // Program counter register
160 const MCRegisterClass *Classes; // Pointer to the regclass array
161 unsigned NumClasses; // Number of entries in the array
162 unsigned NumRegUnits; // Number of regunits.
163 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
164 const int16_t *DiffLists; // Pointer to the difflists array
165 const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences
166 // for register units.
167 const char *RegStrings; // Pointer to the string table.
168 const char *RegClassStrings; // Pointer to the class strings.
169 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
170 // array.
171 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
172 // bit ranges array.
173 unsigned NumSubRegIndices; // Number of subreg indices.
174 const uint16_t *RegEncodingTable; // Pointer to array of register
175 // encodings.
176
177 unsigned L2DwarfRegsSize;
178 unsigned EHL2DwarfRegsSize;
179 unsigned Dwarf2LRegsSize;
180 unsigned EHDwarf2LRegsSize;
181 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
182 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
183 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
184 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
185 DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping
186 DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping
187
188public:
189 // Forward declaration to become a friend class of DiffListIterator.
190 template <class SubT> class mc_difflist_iterator;
191
192 /// DiffListIterator - Base iterator class that can traverse the
193 /// differentially encoded register and regunit lists in DiffLists.
194 /// Don't use this class directly, use one of the specialized sub-classes
195 /// defined below.
197 unsigned Val = 0;
198 const int16_t *List = nullptr;
199
200 protected:
201 /// Create an invalid iterator. Call init() to point to something useful.
202 DiffListIterator() = default;
203
204 /// Point the iterator to InitVal, decoding subsequent values from DiffList.
205 void init(unsigned InitVal, const int16_t *DiffList) {
206 Val = InitVal;
207 List = DiffList;
208 }
209
210 public:
211 /// isValid - returns true if this iterator is not yet at the end.
212 bool isValid() const { return List; }
213
214 /// Dereference the iterator to get the value at the current position.
215 MCRegister operator*() const { return Val; }
216
217 /// Pre-increment to move to the next position.
218 void operator++() {
219 assert(isValid() && "Cannot move off the end of the list.");
220 int16_t D = *List++;
221 Val += D;
222 // The end of the list is encoded as a 0 differential.
223 if (!D)
224 List = nullptr;
225 }
226
227 template <class SubT> friend class MCRegisterInfo::mc_difflist_iterator;
228 };
229
230 /// Forward iterator using DiffListIterator.
231 template <class SubT>
233 : public iterator_facade_base<mc_difflist_iterator<SubT>,
234 std::forward_iterator_tag, MCPhysReg> {
236 /// Current value as MCPhysReg, so we can return a reference to it.
237 MCPhysReg Val = 0;
238
239 protected:
241
242 /// Point the iterator to InitVal, decoding subsequent values from DiffList.
243 void init(unsigned InitVal, const int16_t *DiffList) {
244 Iter.init(InitVal, DiffList);
245 Val = *Iter;
246 }
247
248 public:
249 // Allow default construction to build variables, but this doesn't build
250 // a useful iterator.
252
253 /// Return an iterator past the last element.
254 static SubT end() {
255 SubT End;
256 End.Iter.List = nullptr;
257 return End;
258 }
259
261 return Iter.List == Arg.Iter.List;
262 }
263
264 const MCPhysReg &operator*() const { return Val; }
265
266 using mc_difflist_iterator::iterator_facade_base::operator++;
267 void operator++() {
268 assert(Iter.List && "Cannot increment the end iterator!");
269 ++Iter;
270 Val = *Iter;
271 }
272 };
273
274 /// Forward iterator over all sub-registers.
275 /// TODO: Replace remaining uses of MCSubRegIterator.
276 class mc_subreg_iterator : public mc_difflist_iterator<mc_subreg_iterator> {
277 public:
279 : mc_difflist_iterator(Iter) {}
281
284 init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SubRegs);
285 }
286 };
287
288 /// Forward iterator over all super-registers.
289 /// TODO: Replace remaining uses of MCSuperRegIterator.
291 : public mc_difflist_iterator<mc_superreg_iterator> {
292 public:
294 : mc_difflist_iterator(Iter) {}
296
299 init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
300 }
301 };
302
303 /// Return an iterator range over all sub-registers of \p Reg, excluding \p
304 /// Reg.
306 return make_range(std::next(mc_subreg_iterator(Reg, this)),
308 }
309
310 /// Return an iterator range over all sub-registers of \p Reg, including \p
311 /// Reg.
313 return make_range({Reg, this}, mc_subreg_iterator::end());
314 }
315
316 /// Return an iterator range over all super-registers of \p Reg, excluding \p
317 /// Reg.
319 return make_range(std::next(mc_superreg_iterator(Reg, this)),
321 }
322
323 /// Return an iterator range over all super-registers of \p Reg, including \p
324 /// Reg.
327 return make_range({Reg, this}, mc_superreg_iterator::end());
328 }
329
330 /// Return an iterator range over all sub- and super-registers of \p Reg,
331 /// including \p Reg.
335 return concat<const MCPhysReg>(subregs_inclusive(Reg), superregs(Reg));
336 }
337
338 // These iterators are allowed to sub-class DiffListIterator and access
339 // internal list pointers.
340 friend class MCSubRegIterator;
342 friend class MCSuperRegIterator;
343 friend class MCRegUnitIterator;
346
347 /// Initialize MCRegisterInfo, called by TableGen
348 /// auto-generated routines. *DO NOT USE*.
349 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
350 unsigned PC, const MCRegisterClass *C, unsigned NC,
351 const MCPhysReg (*RURoots)[2], unsigned NRU,
352 const int16_t *DL, const LaneBitmask *RUMS,
353 const char *Strings, const char *ClassStrings,
354 const uint16_t *SubIndices, unsigned NumIndices,
355 const SubRegCoveredBits *SubIdxRanges,
356 const uint16_t *RET) {
357 Desc = D;
358 NumRegs = NR;
359 RAReg = RA;
360 PCReg = PC;
361 Classes = C;
362 DiffLists = DL;
363 RegUnitMaskSequences = RUMS;
364 RegStrings = Strings;
365 RegClassStrings = ClassStrings;
366 NumClasses = NC;
367 RegUnitRoots = RURoots;
368 NumRegUnits = NRU;
369 SubRegIndices = SubIndices;
370 NumSubRegIndices = NumIndices;
371 SubRegIdxRanges = SubIdxRanges;
372 RegEncodingTable = RET;
373
374 // Initialize DWARF register mapping variables
375 EHL2DwarfRegs = nullptr;
376 EHL2DwarfRegsSize = 0;
377 L2DwarfRegs = nullptr;
378 L2DwarfRegsSize = 0;
379 EHDwarf2LRegs = nullptr;
380 EHDwarf2LRegsSize = 0;
381 Dwarf2LRegs = nullptr;
382 Dwarf2LRegsSize = 0;
383 }
384
385 /// Used to initialize LLVM register to Dwarf
386 /// register number mapping. Called by TableGen auto-generated routines.
387 /// *DO NOT USE*.
389 bool isEH) {
390 if (isEH) {
391 EHL2DwarfRegs = Map;
392 EHL2DwarfRegsSize = Size;
393 } else {
394 L2DwarfRegs = Map;
395 L2DwarfRegsSize = Size;
396 }
397 }
398
399 /// Used to initialize Dwarf register to LLVM
400 /// register number mapping. Called by TableGen auto-generated routines.
401 /// *DO NOT USE*.
403 bool isEH) {
404 if (isEH) {
405 EHDwarf2LRegs = Map;
406 EHDwarf2LRegsSize = Size;
407 } else {
408 Dwarf2LRegs = Map;
409 Dwarf2LRegsSize = Size;
410 }
411 }
412
413 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
414 /// number mapping. By default the SEH register number is just the same
415 /// as the LLVM register number.
416 /// FIXME: TableGen these numbers. Currently this requires target specific
417 /// initialization code.
418 void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) {
419 L2SEHRegs[LLVMReg] = SEHReg;
420 }
421
422 void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) {
423 L2CVRegs[LLVMReg] = CVReg;
424 }
425
426 /// This method should return the register where the return
427 /// address can be found.
429 return RAReg;
430 }
431
432 /// Return the register which is the program counter.
434 return PCReg;
435 }
436
438 assert(RegNo < NumRegs &&
439 "Attempting to access record for invalid register number!");
440 return Desc[RegNo];
441 }
442
443 /// Provide a get method, equivalent to [], but more useful with a
444 /// pointer to this object.
445 const MCRegisterDesc &get(MCRegister RegNo) const {
446 return operator[](RegNo);
447 }
448
449 /// Returns the physical register number of sub-register "Index"
450 /// for physical register RegNo. Return zero if the sub-register does not
451 /// exist.
452 MCRegister getSubReg(MCRegister Reg, unsigned Idx) const;
453
454 /// Return a super-register of the specified register
455 /// Reg so its sub-register of index SubIdx is Reg.
457 const MCRegisterClass *RC) const;
458
459 /// For a given register pair, return the sub-register index
460 /// if the second register is a sub-register of the first. Return zero
461 /// otherwise.
462 unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const;
463
464 /// Get the size of the bit range covered by a sub-register index.
465 /// If the index isn't continuous, return the sum of the sizes of its parts.
466 /// If the index is used to access subregisters of different sizes, return -1.
467 unsigned getSubRegIdxSize(unsigned Idx) const;
468
469 /// Get the offset of the bit range covered by a sub-register index.
470 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
471 /// access sub-registers at different offsets), return -1.
472 unsigned getSubRegIdxOffset(unsigned Idx) const;
473
474 /// Return the human-readable symbolic target-specific name for the
475 /// specified physical register.
476 const char *getName(MCRegister RegNo) const {
477 return RegStrings + get(RegNo).Name;
478 }
479
480 /// Return the number of registers this target has (useful for
481 /// sizing arrays holding per register information)
482 unsigned getNumRegs() const {
483 return NumRegs;
484 }
485
486 /// Return the number of sub-register indices
487 /// understood by the target. Index 0 is reserved for the no-op sub-register,
488 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
489 unsigned getNumSubRegIndices() const {
490 return NumSubRegIndices;
491 }
492
493 /// Return the number of (native) register units in the
494 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
495 /// can be accessed through MCRegUnitIterator defined below.
496 unsigned getNumRegUnits() const {
497 return NumRegUnits;
498 }
499
500 /// Map a target register to an equivalent dwarf register
501 /// number. Returns -1 if there is no equivalent value. The second
502 /// parameter allows targets to use different numberings for EH info and
503 /// debugging info.
504 int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
505
506 /// Map a dwarf register back to a target register. Returns std::nullopt is
507 /// there is no mapping.
508 std::optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
509
510 /// Map a target EH register number to an equivalent DWARF register
511 /// number.
512 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
513
514 /// Map a target register to an equivalent SEH register
515 /// number. Returns LLVM register number if there is no equivalent value.
516 int getSEHRegNum(MCRegister RegNum) const;
517
518 /// Map a target register to an equivalent CodeView register
519 /// number.
520 int getCodeViewRegNum(MCRegister RegNum) const;
521
522 regclass_iterator regclass_begin() const { return Classes; }
523 regclass_iterator regclass_end() const { return Classes+NumClasses; }
526 }
527
528 unsigned getNumRegClasses() const {
529 return (unsigned)(regclass_end()-regclass_begin());
530 }
531
532 /// Returns the register class associated with the enumeration
533 /// value. See class MCOperandInfo.
534 const MCRegisterClass& getRegClass(unsigned i) const {
535 assert(i < getNumRegClasses() && "Register Class ID out of range");
536 return Classes[i];
537 }
538
539 const char *getRegClassName(const MCRegisterClass *Class) const {
540 return RegClassStrings + Class->NameIdx;
541 }
542
543 /// Returns the encoding for RegNo
545 assert(RegNo < NumRegs &&
546 "Attempting to get encoding for invalid register number!");
547 return RegEncodingTable[RegNo];
548 }
549
550 /// Returns true if RegB is a sub-register of RegA.
551 bool isSubRegister(MCRegister RegA, MCRegister RegB) const {
552 return isSuperRegister(RegB, RegA);
553 }
554
555 /// Returns true if RegB is a super-register of RegA.
556 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
557
558 /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
559 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
560 return isSuperRegisterEq(RegB, RegA);
561 }
562
563 /// Returns true if RegB is a super-register of RegA or if
564 /// RegB == RegA.
565 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const {
566 return RegA == RegB || isSuperRegister(RegA, RegB);
567 }
568
569 /// Returns true if RegB is a super-register or sub-register of RegA
570 /// or if RegB == RegA.
572 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
573 }
574
575 /// Returns true if the two registers are equal or alias each other.
576 bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
577};
578
579//===----------------------------------------------------------------------===//
580// Register List Iterators
581//===----------------------------------------------------------------------===//
582
583// MCRegisterInfo provides lists of super-registers, sub-registers, and
584// aliasing registers. Use these iterator classes to traverse the lists.
585
586/// MCSubRegIterator enumerates all sub-registers of Reg.
587/// If IncludeSelf is set, Reg itself is included in the list.
589public:
591 bool IncludeSelf = false) {
593 init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SubRegs);
594 // Initially, the iterator points to Reg itself.
595 if (!IncludeSelf)
596 ++*this;
597 }
598};
599
600/// Iterator that enumerates the sub-registers of a Reg and the associated
601/// sub-register indices.
603 MCSubRegIterator SRIter;
604 const uint16_t *SRIndex;
605
606public:
607 /// Constructs an iterator that traverses subregisters and their
608 /// associated subregister indices.
610 : SRIter(Reg, MCRI) {
611 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
612 }
613
614 /// Returns current sub-register.
616 return *SRIter;
617 }
618
619 /// Returns sub-register index of the current sub-register.
620 unsigned getSubRegIndex() const {
621 return *SRIndex;
622 }
623
624 /// Returns true if this iterator is not yet at the end.
625 bool isValid() const { return SRIter.isValid(); }
626
627 /// Moves to the next position.
628 void operator++() {
629 ++SRIter;
630 ++SRIndex;
631 }
632};
633
634/// MCSuperRegIterator enumerates all super-registers of Reg.
635/// If IncludeSelf is set, Reg itself is included in the list.
637public:
639
641 bool IncludeSelf = false) {
643 init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
644 // Initially, the iterator points to Reg itself.
645 if (!IncludeSelf)
646 ++*this;
647 }
648};
649
650// Definition for isSuperRegister. Put it down here since it needs the
651// iterator defined above in addition to the MCRegisterInfo class itself.
653 return is_contained(superregs(RegA), RegB);
654}
655
656//===----------------------------------------------------------------------===//
657// Register Units
658//===----------------------------------------------------------------------===//
659
660// Register units are used to compute register aliasing. Every register has at
661// least one register unit, but it can have more. Two registers overlap if and
662// only if they have a common register unit.
663//
664// A target with a complicated sub-register structure will typically have many
665// fewer register units than actual registers. MCRI::getNumRegUnits() returns
666// the number of register units in the target.
667
668// MCRegUnitIterator enumerates a list of register units for Reg. The list is
669// in ascending numerical order.
671 // The value must be kept in sync with RegisterInfoEmitter.cpp.
672 static constexpr unsigned RegUnitBits = 12;
673
674public:
675 /// MCRegUnitIterator - Create an iterator that traverses the register units
676 /// in Reg.
677 MCRegUnitIterator() = default;
678
680 assert(Reg && "Null register has no regunits");
682 // Decode the RegUnits MCRegisterDesc field.
683 unsigned RU = MCRI->get(Reg).RegUnits;
684 unsigned FirstRU = RU & ((1u << RegUnitBits) - 1);
685 unsigned Offset = RU >> RegUnitBits;
686 init(FirstRU, MCRI->DiffLists + Offset);
687 }
688
691 return *this;
692 }
693};
694
695/// MCRegUnitMaskIterator enumerates a list of register units and their
696/// associated lane masks for Reg. The register units are in ascending
697/// numerical order.
699 MCRegUnitIterator RUIter;
700 const LaneBitmask *MaskListIter;
701
702public:
704
705 /// Constructs an iterator that traverses the register units and their
706 /// associated LaneMasks in Reg.
708 : RUIter(Reg, MCRI) {
710 MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
711 }
712
713 /// Returns a (RegUnit, LaneMask) pair.
714 std::pair<unsigned,LaneBitmask> operator*() const {
715 return std::make_pair(*RUIter, *MaskListIter);
716 }
717
718 /// Returns true if this iterator is not yet at the end.
719 bool isValid() const { return RUIter.isValid(); }
720
721 /// Moves to the next position.
722 void operator++() {
723 ++MaskListIter;
724 ++RUIter;
725 }
726};
727
728// Each register unit has one or two root registers. The complete set of
729// registers containing a register unit is the union of the roots and their
730// super-registers. All registers aliasing Unit can be visited like this:
731//
732// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
733// for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
734// visit(*SI);
735// }
736
737/// MCRegUnitRootIterator enumerates the root registers of a register unit.
739 uint16_t Reg0 = 0;
740 uint16_t Reg1 = 0;
741
742public:
744
745 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
746 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
747 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
748 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
749 }
750
751 /// Dereference to get the current root register.
752 unsigned operator*() const {
753 return Reg0;
754 }
755
756 /// Check if the iterator is at the end of the list.
757 bool isValid() const {
758 return Reg0;
759 }
760
761 /// Preincrement to move to the next root register.
762 void operator++() {
763 assert(isValid() && "Cannot move off the end of the list.");
764 Reg0 = Reg1;
765 Reg1 = 0;
766 }
767};
768
769/// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
770/// set, Reg itself is included in the list. This iterator does not guarantee
771/// any ordering or that entries are unique.
773private:
774 MCRegister Reg;
775 const MCRegisterInfo *MCRI;
776 bool IncludeSelf;
777
781
782public:
784 bool IncludeSelf)
785 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
786 // Initialize the iterators.
787 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
788 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
789 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
790 if (!(!IncludeSelf && Reg == *SI))
791 return;
792 }
793 }
794 }
795 }
796
797 bool isValid() const { return RI.isValid(); }
798
800 assert(SI.isValid() && "Cannot dereference an invalid iterator.");
801 return *SI;
802 }
803
804 void advance() {
805 // Assuming SI is valid.
806 ++SI;
807 if (SI.isValid()) return;
808
809 ++RRI;
810 if (RRI.isValid()) {
811 SI = MCSuperRegIterator(*RRI, MCRI, true);
812 return;
813 }
814
815 ++RI;
816 if (RI.isValid()) {
817 RRI = MCRegUnitRootIterator(*RI, MCRI);
818 SI = MCSuperRegIterator(*RRI, MCRI, true);
819 }
820 }
821
822 void operator++() {
823 assert(isValid() && "Cannot move off the end of the list.");
824 do advance();
825 while (!IncludeSelf && isValid() && *SI == Reg);
826 }
827};
828
829} // end namespace llvm
830
831#endif // LLVM_MC_MCREGISTERINFO_H
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
uint64_t Size
bool End
Definition: ELF_riscv.cpp:464
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned Reg
const NodeList & List
Definition: RDFGraph.cpp:199
@ SI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
Value * RHS
MCRegAliasIterator enumerates all registers aliasing Reg.
MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf)
MCRegister operator*() const
MCRegUnitIterator()=default
MCRegUnitIterator - Create an iterator that traverses the register units in Reg.
MCRegUnitIterator & operator++()
MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.
MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses the register units and their associated LaneMasks in Reg.
bool isValid() const
Returns true if this iterator is not yet at the end.
void operator++()
Moves to the next position.
std::pair< unsigned, LaneBitmask > operator*() const
Returns a (RegUnit, LaneMask) pair.
MCRegUnitRootIterator enumerates the root registers of a register unit.
unsigned operator*() const
Dereference to get the current root register.
MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI)
void operator++()
Preincrement to move to the next root register.
bool isValid() const
Check if the iterator is at the end of the list.
MCRegisterClass - Base class of TargetRegisterClass.
const uint32_t NameIdx
unsigned getID() const
getID() - Return the register class ID number.
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
const uint16_t RegSizeInBits
unsigned getSizeInBits() const
Return the size of the physical register in bits if we are able to determine it.
const uint16_t RegSetSize
bool contains(MCRegister Reg1, MCRegister Reg2) const
contains - Return true if both registers are in this class.
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
iterator begin() const
begin/end - Return all of the registers in this class.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
const uint8_t *const RegSet
const iterator RegsBegin
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
iterator end() const
const uint16_t RegsSize
DiffListIterator - Base iterator class that can traverse the differentially encoded register and regu...
MCRegister operator*() const
Dereference the iterator to get the value at the current position.
void init(unsigned InitVal, const int16_t *DiffList)
Point the iterator to InitVal, decoding subsequent values from DiffList.
void operator++()
Pre-increment to move to the next position.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
DiffListIterator()=default
Create an invalid iterator. Call init() to point to something useful.
Forward iterator using DiffListIterator.
static SubT end()
Return an iterator past the last element.
void init(unsigned InitVal, const int16_t *DiffList)
Point the iterator to InitVal, decoding subsequent values from DiffList.
bool operator==(const mc_difflist_iterator &Arg) const
mc_difflist_iterator(MCRegisterInfo::DiffListIterator Iter)
Forward iterator over all sub-registers.
mc_subreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI)
mc_subreg_iterator(MCRegisterInfo::DiffListIterator Iter)
Forward iterator over all super-registers.
mc_superreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI)
mc_superreg_iterator(MCRegisterInfo::DiffListIterator Iter)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA or if RegB == RegA.
unsigned getNumRegClasses() const
MCRegister getRARegister() const
This method should return the register where the return address can be found.
MCRegister getProgramCounter() const
Return the register which is the program counter.
regclass_iterator regclass_end() const
void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize Dwarf register to LLVM register number mapping.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
int getCodeViewRegNum(MCRegister RegNum) const
Map a target register to an equivalent CodeView register number.
iterator_range< mc_superreg_iterator > superregs_inclusive(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, including Reg.
std::optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
iterator_range< regclass_iterator > regclasses() const
regclass_iterator regclass_begin() const
const MCRegisterDesc & get(MCRegister RegNo) const
Provide a get method, equivalent to [], but more useful with a pointer to this object.
int getSEHRegNum(MCRegister RegNum) const
Map a target register to an equivalent SEH register number.
void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg)
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
const char * getRegClassName(const MCRegisterClass *Class) const
int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const
Map a target EH register number to an equivalent DWARF register number.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
iterator_range< mc_superreg_iterator > superregs(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, excluding Reg.
void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const int16_t *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET)
Initialize MCRegisterInfo, called by TableGen auto-generated routines.
iterator_range< mc_subreg_iterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
iterator_range< mc_subreg_iterator > subregs_inclusive(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, including Reg.
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
Used to initialize LLVM register to Dwarf register number mapping.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA or if RegB == RegA.
detail::concat_range< const MCPhysReg, iterator_range< mc_subreg_iterator >, iterator_range< mc_superreg_iterator > > sub_and_superregs_inclusive(MCRegister Reg) const
Return an iterator range over all sub- and super-registers of Reg, including Reg.
void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg)
mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
const MCRegisterDesc & operator[](MCRegister RegNo) const
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: MCRegister.h:58
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices.
MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
Constructs an iterator that traverses subregisters and their associated subregister indices.
bool isValid() const
Returns true if this iterator is not yet at the end.
void operator++()
Moves to the next position.
unsigned getSubRegIndex() const
Returns sub-register index of the current sub-register.
MCRegister getSubReg() const
Returns current sub-register.
MCSubRegIterator enumerates all sub-registers of Reg.
MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
MCSuperRegIterator enumerates all super-registers of Reg.
MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf=false)
Helper to store a sequence of ranges being concatenated and access them.
Definition: STLExtras.h:1218
CRTP base class which implements the entire standard iterator facade in terms of a minimal subset of ...
Definition: iterator.h:80
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1976
#define NC
Definition: regutils.h:42
MCRegisterDesc - This record contains information about a particular register.
uint16_t RegUnitLaneMasks
Index into list with lane mask sequences.
DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be performed with a binary se...
bool operator<(DwarfLLVMRegPair RHS) const
SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...