LLVM  13.0.0git
MCInstrDesc.h
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1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MCOperandInfo and MCInstrDesc classes, which
10 // are used to describe target instructions and their operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MC_MCINSTRDESC_H
15 #define LLVM_MC_MCINSTRDESC_H
16 
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/DataTypes.h"
19 #include <string>
20 
21 namespace llvm {
22 
23 class MCInst;
24 
25 //===----------------------------------------------------------------------===//
26 // Machine Operand Flags and Description
27 //===----------------------------------------------------------------------===//
28 
29 namespace MCOI {
30 /// Operand constraints. These are encoded in 16 bits with one of the
31 /// low-order 3 bits specifying that a constraint is present and the
32 /// corresponding high-order hex digit specifying the constraint value.
33 /// This allows for a maximum of 3 constraints.
35  TIED_TO = 0, // Must be allocated the same register as specified value.
36  EARLY_CLOBBER // If present, operand is an early clobber register.
37 };
38 
39 // Define a macro to produce each constraint value.
40 #define MCOI_TIED_TO(op) \
41  ((1 << MCOI::TIED_TO) | ((op) << (4 + MCOI::TIED_TO * 4)))
42 
43 #define MCOI_EARLY_CLOBBER \
44  (1 << MCOI::EARLY_CLOBBER)
45 
46 /// These are flags set on operands, but should be considered
47 /// private, all access should go through the MCOperandInfo accessors.
48 /// See the accessors for a description of what these are.
54 };
55 
56 /// Operands are tagged with one of the values of this enum.
63 
72 
76 
78 };
79 
80 }
81 
82 /// This holds information about one operand of a machine instruction,
83 /// indicating the register class for register operands, etc.
85 public:
86  /// This specifies the register class enumeration of the operand
87  /// if the operand is a register. If isLookupPtrRegClass is set, then this is
88  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
89  /// get a dynamic register class.
90  int16_t RegClass;
91 
92  /// These are flags from the MCOI::OperandFlags enum.
93  uint8_t Flags;
94 
95  /// Information about the type of the operand.
96  uint8_t OperandType;
97 
98  /// Operand constraints (see OperandConstraint enum).
100 
101  /// Set if this operand is a pointer value and it requires a callback
102  /// to look up its register class.
103  bool isLookupPtrRegClass() const {
104  return Flags & (1 << MCOI::LookupPtrRegClass);
105  }
106 
107  /// Set if this is one of the operands that made up of the predicate
108  /// operand that controls an isPredicable() instruction.
109  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
110 
111  /// Set if this operand is a optional def.
112  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
113 
114  /// Set if this operand is a branch target.
115  bool isBranchTarget() const { return Flags & (1 << MCOI::BranchTarget); }
116 
117  bool isGenericType() const {
120  }
121 
122  unsigned getGenericTypeIndex() const {
123  assert(isGenericType() && "non-generic types don't have an index");
125  }
126 
127  bool isGenericImm() const {
130  }
131 
132  unsigned getGenericImmIndex() const {
133  assert(isGenericImm() && "non-generic immediates don't have an index");
135  }
136 };
137 
138 //===----------------------------------------------------------------------===//
139 // Machine Instruction Flags and Description
140 //===----------------------------------------------------------------------===//
141 
142 namespace MCID {
143 /// These should be considered private to the implementation of the
144 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
145 /// not use these directly. These all correspond to bitfields in the
146 /// MCInstrDesc::Flags field.
147 enum Flag {
188 };
189 }
190 
191 /// Describe properties that are true of each instruction in the target
192 /// description file. This captures information about side effects, register
193 /// use and many other things. There is one instance of this struct for each
194 /// target instruction class, and the MachineInstr class points to this struct
195 /// directly to describe itself.
196 class MCInstrDesc {
197 public:
198  unsigned short Opcode; // The opcode number
199  unsigned short NumOperands; // Num of args (may be more if variable_ops)
200  unsigned char NumDefs; // Num of args that are definitions
201  unsigned char Size; // Number of bytes in encoding.
202  unsigned short SchedClass; // enum identifying instr sched class
203  uint64_t Flags; // Flags identifying machine instr class
204  uint64_t TSFlags; // Target Specific Flag values
205  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
206  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
207  const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
208 
209  /// Returns the value of the specified operand constraint if
210  /// it is present. Returns -1 if it is not present.
211  int getOperandConstraint(unsigned OpNum,
212  MCOI::OperandConstraint Constraint) const {
213  if (OpNum < NumOperands &&
214  (OpInfo[OpNum].Constraints & (1 << Constraint))) {
215  unsigned ValuePos = 4 + Constraint * 4;
216  return (int)(OpInfo[OpNum].Constraints >> ValuePos) & 0x0f;
217  }
218  return -1;
219  }
220 
221  /// Return the opcode number for this descriptor.
222  unsigned getOpcode() const { return Opcode; }
223 
224  /// Return the number of declared MachineOperands for this
225  /// MachineInstruction. Note that variadic (isVariadic() returns true)
226  /// instructions may have additional operands at the end of the list, and note
227  /// that the machine instruction may include implicit register def/uses as
228  /// well.
229  unsigned getNumOperands() const { return NumOperands; }
230 
232 
235 
237  return make_range(opInfo_begin(), opInfo_end());
238  }
239 
240  /// Return the number of MachineOperands that are register
241  /// definitions. Register definitions always occur at the start of the
242  /// machine operand list. This is the number of "outs" in the .td file,
243  /// and does not include implicit defs.
244  unsigned getNumDefs() const { return NumDefs; }
245 
246  /// Return flags of this instruction.
247  uint64_t getFlags() const { return Flags; }
248 
249  /// \returns true if this instruction is emitted before instruction selection
250  /// and should be legalized/regbankselected/selected.
251  bool isPreISelOpcode() const { return Flags & (1ULL << MCID::PreISelOpcode); }
252 
253  /// Return true if this instruction can have a variable number of
254  /// operands. In this case, the variable operands will be after the normal
255  /// operands but before the implicit definitions and uses (if any are
256  /// present).
257  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
258 
259  /// Set if this instruction has an optional definition, e.g.
260  /// ARM instructions which can set condition code if 's' bit is set.
261  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
262 
263  /// Return true if this is a pseudo instruction that doesn't
264  /// correspond to a real machine instruction.
265  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
266 
267  /// Return true if the instruction is a return.
268  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
269 
270  /// Return true if the instruction is an add instruction.
271  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
272 
273  /// Return true if this instruction is a trap.
274  bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
275 
276  /// Return true if the instruction is a register to register move.
277  bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
278 
279  /// Return true if the instruction is a call.
280  bool isCall() const { return Flags & (1ULL << MCID::Call); }
281 
282  /// Returns true if the specified instruction stops control flow
283  /// from executing the instruction immediately following it. Examples include
284  /// unconditional branches and return instructions.
285  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
286 
287  /// Returns true if this instruction part of the terminator for
288  /// a basic block. Typically this is things like return and branch
289  /// instructions.
290  ///
291  /// Various passes use this to insert code into the bottom of a basic block,
292  /// but before control flow occurs.
293  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
294 
295  /// Returns true if this is a conditional, unconditional, or
296  /// indirect branch. Predicates below can be used to discriminate between
297  /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
298  /// get more information.
299  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
300 
301  /// Return true if this is an indirect branch, such as a
302  /// branch through a register.
303  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
304 
305  /// Return true if this is a branch which may fall
306  /// through to the next instruction or may transfer control flow to some other
307  /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
308  /// information about this branch.
309  bool isConditionalBranch() const {
310  return isBranch() && !isBarrier() && !isIndirectBranch();
311  }
312 
313  /// Return true if this is a branch which always
314  /// transfers control flow to some other block. The
315  /// TargetInstrInfo::analyzeBranch method can be used to get more information
316  /// about this branch.
317  bool isUnconditionalBranch() const {
318  return isBranch() && isBarrier() && !isIndirectBranch();
319  }
320 
321  /// Return true if this is a branch or an instruction which directly
322  /// writes to the program counter. Considered 'may' affect rather than
323  /// 'does' affect as things like predication are not taken into account.
324  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
325 
326  /// Return true if this instruction has a predicate operand
327  /// that controls execution. It may be set to 'always', or may be set to other
328  /// values. There are various methods in TargetInstrInfo that can be used to
329  /// control and modify the predicate in this instruction.
330  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
331 
332  /// Return true if this instruction is a comparison.
333  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
334 
335  /// Return true if this instruction is a move immediate
336  /// (including conditional moves) instruction.
337  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
338 
339  /// Return true if this instruction is a bitcast instruction.
340  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
341 
342  /// Return true if this is a select instruction.
343  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
344 
345  /// Return true if this instruction cannot be safely
346  /// duplicated. For example, if the instruction has a unique labels attached
347  /// to it, duplicating it would cause multiple definition errors.
348  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
349 
350  /// Returns true if the specified instruction has a delay slot which
351  /// must be filled by the code generator.
352  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
353 
354  /// Return true for instructions that can be folded as memory operands
355  /// in other instructions. The most common use for this is instructions that
356  /// are simple loads from memory that don't modify the loaded value in any
357  /// way, but it can also be used for instructions that can be expressed as
358  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
359  /// folded when it is beneficial. This should only be set on instructions
360  /// that return a value in their only virtual register definition.
361  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
362 
363  /// Return true if this instruction behaves
364  /// the same way as the generic REG_SEQUENCE instructions.
365  /// E.g., on ARM,
366  /// dX VMOVDRR rY, rZ
367  /// is equivalent to
368  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
369  ///
370  /// Note that for the optimizers to be able to take advantage of
371  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
372  /// override accordingly.
373  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
374 
375  /// Return true if this instruction behaves
376  /// the same way as the generic EXTRACT_SUBREG instructions.
377  /// E.g., on ARM,
378  /// rX, rY VMOVRRD dZ
379  /// is equivalent to two EXTRACT_SUBREG:
380  /// rX = EXTRACT_SUBREG dZ, ssub_0
381  /// rY = EXTRACT_SUBREG dZ, ssub_1
382  ///
383  /// Note that for the optimizers to be able to take advantage of
384  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
385  /// override accordingly.
386  bool isExtractSubregLike() const {
387  return Flags & (1ULL << MCID::ExtractSubreg);
388  }
389 
390  /// Return true if this instruction behaves
391  /// the same way as the generic INSERT_SUBREG instructions.
392  /// E.g., on ARM,
393  /// dX = VSETLNi32 dY, rZ, Imm
394  /// is equivalent to a INSERT_SUBREG:
395  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
396  ///
397  /// Note that for the optimizers to be able to take advantage of
398  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
399  /// override accordingly.
400  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
401 
402 
403  /// Return true if this instruction is convergent.
404  ///
405  /// Convergent instructions may not be made control-dependent on any
406  /// additional values.
407  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
408 
409  /// Return true if variadic operands of this instruction are definitions.
410  bool variadicOpsAreDefs() const {
411  return Flags & (1ULL << MCID::VariadicOpsAreDefs);
412  }
413 
414  /// Return true if this instruction authenticates a pointer (e.g. LDRAx/BRAx
415  /// from ARMv8.3, which perform loads/branches with authentication).
416  ///
417  /// An authenticated instruction may fail in an ABI-defined manner when
418  /// operating on an invalid signed pointer.
419  bool isAuthenticated() const {
420  return Flags & (1ULL << MCID::Authenticated);
421  }
422 
423  //===--------------------------------------------------------------------===//
424  // Side Effect Analysis
425  //===--------------------------------------------------------------------===//
426 
427  /// Return true if this instruction could possibly read memory.
428  /// Instructions with this flag set are not necessarily simple load
429  /// instructions, they may load a value and modify it, for example.
430  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
431 
432  /// Return true if this instruction could possibly modify memory.
433  /// Instructions with this flag set are not necessarily simple store
434  /// instructions, they may store a modified value based on their operands, or
435  /// may not actually modify anything, for example.
436  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
437 
438  /// Return true if this instruction may raise a floating-point exception.
439  bool mayRaiseFPException() const {
440  return Flags & (1ULL << MCID::MayRaiseFPException);
441  }
442 
443  /// Return true if this instruction has side
444  /// effects that are not modeled by other flags. This does not return true
445  /// for instructions whose effects are captured by:
446  ///
447  /// 1. Their operand list and implicit definition/use list. Register use/def
448  /// info is explicit for instructions.
449  /// 2. Memory accesses. Use mayLoad/mayStore.
450  /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
451  ///
452  /// Examples of side effects would be modifying 'invisible' machine state like
453  /// a control register, flushing a cache, modifying a register invisible to
454  /// LLVM, etc.
455  bool hasUnmodeledSideEffects() const {
456  return Flags & (1ULL << MCID::UnmodeledSideEffects);
457  }
458 
459  //===--------------------------------------------------------------------===//
460  // Flags that indicate whether an instruction can be modified by a method.
461  //===--------------------------------------------------------------------===//
462 
463  /// Return true if this may be a 2- or 3-address instruction (of the
464  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
465  /// exchanged. If this flag is set, then the
466  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
467  /// instruction.
468  ///
469  /// Note that this flag may be set on instructions that are only commutable
470  /// sometimes. In these cases, the call to commuteInstruction will fail.
471  /// Also note that some instructions require non-trivial modification to
472  /// commute them.
473  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
474 
475  /// Return true if this is a 2-address instruction which can be changed
476  /// into a 3-address instruction if needed. Doing this transformation can be
477  /// profitable in the register allocator, because it means that the
478  /// instruction can use a 2-address form if possible, but degrade into a less
479  /// efficient form if the source and dest register cannot be assigned to the
480  /// same register. For example, this allows the x86 backend to turn a "shl
481  /// reg, 3" instruction into an LEA instruction, which is the same speed as
482  /// the shift but has bigger code size.
483  ///
484  /// If this returns true, then the target must implement the
485  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
486  /// is allowed to fail if the transformation isn't valid for this specific
487  /// instruction (e.g. shl reg, 4 on x86).
488  ///
489  bool isConvertibleTo3Addr() const {
490  return Flags & (1ULL << MCID::ConvertibleTo3Addr);
491  }
492 
493  /// Return true if this instruction requires custom insertion support
494  /// when the DAG scheduler is inserting it into a machine basic block. If
495  /// this is true for the instruction, it basically means that it is a pseudo
496  /// instruction used at SelectionDAG time that is expanded out into magic code
497  /// by the target when MachineInstrs are formed.
498  ///
499  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
500  /// is used to insert this into the MachineBasicBlock.
501  bool usesCustomInsertionHook() const {
502  return Flags & (1ULL << MCID::UsesCustomInserter);
503  }
504 
505  /// Return true if this instruction requires *adjustment* after
506  /// instruction selection by calling a target hook. For example, this can be
507  /// used to fill in ARM 's' optional operand depending on whether the
508  /// conditional flag register is used.
509  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
510 
511  /// Returns true if this instruction is a candidate for remat. This
512  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
513  ///
514  /// If this flag is set, the isReallyTriviallyReMaterializable()
515  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
516  /// the instruction is really rematable.
517  bool isRematerializable() const {
518  return Flags & (1ULL << MCID::Rematerializable);
519  }
520 
521  /// Returns true if this instruction has the same cost (or less) than a
522  /// move instruction. This is useful during certain types of optimizations
523  /// (e.g., remat during two-address conversion or machine licm) where we would
524  /// like to remat or hoist the instruction, but not if it costs more than
525  /// moving the instruction into the appropriate register. Note, we are not
526  /// marking copies from and to the same register class with this flag.
527  ///
528  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
529  /// for different subtargets.
530  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
531 
532  /// Returns true if this instruction source operands have special
533  /// register allocation requirements that are not captured by the operand
534  /// register classes. e.g. ARM::STRD's two source registers must be an even /
535  /// odd pair, ARM::STM registers have to be in ascending order. Post-register
536  /// allocation passes should not attempt to change allocations for sources of
537  /// instructions with this flag.
538  bool hasExtraSrcRegAllocReq() const {
539  return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
540  }
541 
542  /// Returns true if this instruction def operands have special register
543  /// allocation requirements that are not captured by the operand register
544  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
545  /// ARM::LDM registers have to be in ascending order. Post-register
546  /// allocation passes should not attempt to change allocations for definitions
547  /// of instructions with this flag.
548  bool hasExtraDefRegAllocReq() const {
549  return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
550  }
551 
552  /// Return a list of registers that are potentially read by any
553  /// instance of this machine instruction. For example, on X86, the "adc"
554  /// instruction adds two register operands and adds the carry bit in from the
555  /// flags register. In this case, the instruction is marked as implicitly
556  /// reading the flags. Likewise, the variable shift instruction on X86 is
557  /// marked as implicitly reading the 'CL' register, which it always does.
558  ///
559  /// This method returns null if the instruction has no implicit uses.
560  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
561 
562  /// Return the number of implicit uses this instruction has.
563  unsigned getNumImplicitUses() const {
564  if (!ImplicitUses)
565  return 0;
566  unsigned i = 0;
567  for (; ImplicitUses[i]; ++i) /*empty*/
568  ;
569  return i;
570  }
571 
572  /// Return a list of registers that are potentially written by any
573  /// instance of this machine instruction. For example, on X86, many
574  /// instructions implicitly set the flags register. In this case, they are
575  /// marked as setting the FLAGS. Likewise, many instructions always deposit
576  /// their result in a physical register. For example, the X86 divide
577  /// instruction always deposits the quotient and remainder in the EAX/EDX
578  /// registers. For that instruction, this will return a list containing the
579  /// EAX/EDX/EFLAGS registers.
580  ///
581  /// This method returns null if the instruction has no implicit defs.
582  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
583 
584  /// Return the number of implicit defs this instruct has.
585  unsigned getNumImplicitDefs() const {
586  if (!ImplicitDefs)
587  return 0;
588  unsigned i = 0;
589  for (; ImplicitDefs[i]; ++i) /*empty*/
590  ;
591  return i;
592  }
593 
594  /// Return true if this instruction implicitly
595  /// uses the specified physical register.
596  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
597  if (const MCPhysReg *ImpUses = ImplicitUses)
598  for (; *ImpUses; ++ImpUses)
599  if (*ImpUses == Reg)
600  return true;
601  return false;
602  }
603 
604  /// Return true if this instruction implicitly
605  /// defines the specified physical register.
606  bool hasImplicitDefOfPhysReg(unsigned Reg,
607  const MCRegisterInfo *MRI = nullptr) const;
608 
609  /// Return the scheduling class for this instruction. The
610  /// scheduling class is an index into the InstrItineraryData table. This
611  /// returns zero if there is no known scheduling information for the
612  /// instruction.
613  unsigned getSchedClass() const { return SchedClass; }
614 
615  /// Return the number of bytes in the encoding of this instruction,
616  /// or zero if the encoding size cannot be known from the opcode.
617  unsigned getSize() const { return Size; }
618 
619  /// Find the index of the first operand in the
620  /// operand list that is used to represent the predicate. It returns -1 if
621  /// none is found.
623  if (isPredicable()) {
624  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
625  if (OpInfo[i].isPredicate())
626  return i;
627  }
628  return -1;
629  }
630 
631  /// Return true if this instruction defines the specified physical
632  /// register, either explicitly or implicitly.
633  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
634  const MCRegisterInfo &RI) const;
635 };
636 
637 } // end namespace llvm
638 
639 #endif
i
i
Definition: README.txt:29
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:244
llvm::MCID::EHScopeReturn
@ EHScopeReturn
Definition: MCInstrDesc.h:153
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:222
llvm::MCID::Compare
@ Compare
Definition: MCInstrDesc.h:159
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::MCID::UnmodeledSideEffects
@ UnmodeledSideEffects
Definition: MCInstrDesc.h:171
llvm::MCID::DelaySlot
@ DelaySlot
Definition: MCInstrDesc.h:164
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCInstrDesc::isConvergent
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:407
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::MCOI::OPERAND_FIRST_GENERIC_IMM
@ OPERAND_FIRST_GENERIC_IMM
Definition: MCInstrDesc.h:73
llvm::MCInstrDesc::Flags
uint64_t Flags
Definition: MCInstrDesc.h:203
llvm::MCOI::OPERAND_GENERIC_0
@ OPERAND_GENERIC_0
Definition: MCInstrDesc.h:65
llvm::MCID::Authenticated
@ Authenticated
Definition: MCInstrDesc.h:187
llvm::MCInstrDesc::isPreISelOpcode
bool isPreISelOpcode() const
Definition: MCInstrDesc.h:251
llvm::MCInstrDesc::hasExtraDefRegAllocReq
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MCInstrDesc.h:548
llvm::MCInstrDesc::isBranch
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:299
llvm::MCInstrDesc::isAsCheapAsAMove
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MCInstrDesc.h:530
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:59
llvm::MCID::FoldableAsLoad
@ FoldableAsLoad
Definition: MCInstrDesc.h:165
llvm::MCInstrDesc::isPseudo
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MCInstrDesc.h:265
llvm::MCInstrDesc::opInfo_end
const_opInfo_iterator opInfo_end() const
Definition: MCInstrDesc.h:234
llvm::MCOI::OPERAND_MEMORY
@ OPERAND_MEMORY
Definition: MCInstrDesc.h:61
llvm::MCID::NotDuplicable
@ NotDuplicable
Definition: MCInstrDesc.h:170
llvm::MCInstrDesc::getSchedClass
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:613
llvm::MCID::Commutable
@ Commutable
Definition: MCInstrDesc.h:172
llvm::MCInstrDesc::isBitcast
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
Definition: MCInstrDesc.h:340
llvm::MCInstrDesc::Size
unsigned char Size
Definition: MCInstrDesc.h:201
llvm::MCOI::LookupPtrRegClass
@ LookupPtrRegClass
Definition: MCInstrDesc.h:50
llvm::MCInstrDesc::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MCInstrDesc.h:622
llvm::MCID::Convergent
@ Convergent
Definition: MCInstrDesc.h:183
llvm::MCOI::OPERAND_GENERIC_4
@ OPERAND_GENERIC_4
Definition: MCInstrDesc.h:69
llvm::MCOI::OPERAND_GENERIC_1
@ OPERAND_GENERIC_1
Definition: MCInstrDesc.h:66
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:183
llvm::MCInstrDesc::isIndirectBranch
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:303
llvm::MCOperandInfo::Constraints
uint16_t Constraints
Operand constraints (see OperandConstraint enum).
Definition: MCInstrDesc.h:99
llvm::MCOperandInfo::isLookupPtrRegClass
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class.
Definition: MCInstrDesc.h:103
llvm::MCOI::OPERAND_LAST_GENERIC_IMM
@ OPERAND_LAST_GENERIC_IMM
Definition: MCInstrDesc.h:75
llvm::MCInstrDesc::isPredicable
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:330
llvm::MCOI::OPERAND_LAST_GENERIC
@ OPERAND_LAST_GENERIC
Definition: MCInstrDesc.h:71
llvm::MCInstrDesc::hasPostISelHook
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:509
llvm::MCInstrDesc::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
Definition: MCInstrDesc.h:455
llvm::MCInstrDesc::NumDefs
unsigned char NumDefs
Definition: MCInstrDesc.h:200
llvm::MCOI::OPERAND_GENERIC_3
@ OPERAND_GENERIC_3
Definition: MCInstrDesc.h:68
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::MCInstrDesc::isRematerializable
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:517
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:204
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:617
llvm::MCOI::OPERAND_FIRST_GENERIC
@ OPERAND_FIRST_GENERIC
Definition: MCInstrDesc.h:64
llvm::MCInstrDesc::isMoveImmediate
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition: MCInstrDesc.h:337
llvm::MCInstrDesc::ImplicitUses
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:205
llvm::MCOI::OperandFlags
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:49
llvm::MCInstrDesc::hasExtraSrcRegAllocReq
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MCInstrDesc.h:538
llvm::MCInstrDesc::isTrap
bool isTrap() const
Return true if this instruction is a trap.
Definition: MCInstrDesc.h:274
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:563
llvm::MCID::Predicable
@ Predicable
Definition: MCInstrDesc.h:169
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:582
llvm::MCInstrDesc::isTerminator
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:293
llvm::MCID::Return
@ Return
Definition: MCInstrDesc.h:152
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
llvm::MCOI::OPERAND_GENERIC_IMM_0
@ OPERAND_GENERIC_IMM_0
Definition: MCInstrDesc.h:74
llvm::MCInstrDesc::isMoveReg
bool isMoveReg() const
Return true if the instruction is a register to register move.
Definition: MCInstrDesc.h:277
llvm::MCInstrDesc::isCommutable
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MCInstrDesc.h:473
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:585
llvm::MCInstrDesc::isBarrier
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:285
llvm::MCOI::BranchTarget
@ BranchTarget
Definition: MCInstrDesc.h:53
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:198
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:62
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:154
llvm::MCInstrDesc::isAuthenticated
bool isAuthenticated() const
Return true if this instruction authenticates a pointer (e.g.
Definition: MCInstrDesc.h:419
llvm::MCID::RegSequence
@ RegSequence
Definition: MCInstrDesc.h:180
llvm::MCID::VariadicOpsAreDefs
@ VariadicOpsAreDefs
Definition: MCInstrDesc.h:186
llvm::MCInstrDesc::usesCustomInsertionHook
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MCInstrDesc.h:501
llvm::MCID::MayStore
@ MayStore
Definition: MCInstrDesc.h:167
llvm::MCInstrDesc::hasImplicitDefOfPhysReg
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
Definition: MCInstrDesc.cpp:33
llvm::MCID::MayLoad
@ MayLoad
Definition: MCInstrDesc.h:166
llvm::MCID::MayRaiseFPException
@ MayRaiseFPException
Definition: MCInstrDesc.h:168
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:112
llvm::MCOperandInfo::isPredicate
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:109
llvm::MCID::Trap
@ Trap
Definition: MCInstrDesc.h:185
llvm::MCID::ExtraSrcRegAllocReq
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:178
llvm::MCInstrDesc::mayLoad
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:430
llvm::MCID::Pseudo
@ Pseudo
Definition: MCInstrDesc.h:151
llvm::MCInstrDesc::isNotDuplicable
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
Definition: MCInstrDesc.h:348
llvm::MCInstrDesc::NumOperands
unsigned short NumOperands
Definition: MCInstrDesc.h:199
llvm::MCInstrDesc::isAdd
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:271
llvm::MCID::IndirectBranch
@ IndirectBranch
Definition: MCInstrDesc.h:158
llvm::MCOI::EARLY_CLOBBER
@ EARLY_CLOBBER
Definition: MCInstrDesc.h:36
llvm::MCOperandInfo::getGenericImmIndex
unsigned getGenericImmIndex() const
Definition: MCInstrDesc.h:132
llvm::MCID::Barrier
@ Barrier
Definition: MCInstrDesc.h:155
llvm::MCInstrDesc::isCall
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:280
llvm::MCOperandInfo::isGenericType
bool isGenericType() const
Definition: MCInstrDesc.h:117
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::MCInstrDesc::isInsertSubregLike
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
Definition: MCInstrDesc.h:400
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:60
llvm::MCInstrDesc::isExtractSubregLike
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
Definition: MCInstrDesc.h:386
MCRegisterInfo.h
llvm::MCOI::OperandType
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:57
llvm::MCID::Rematerializable
@ Rematerializable
Definition: MCInstrDesc.h:176
llvm::MCID::Bitcast
@ Bitcast
Definition: MCInstrDesc.h:162
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCID::CheapAsAMove
@ CheapAsAMove
Definition: MCInstrDesc.h:177
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:207
llvm::MCOperandInfo::isBranchTarget
bool isBranchTarget() const
Set if this operand is a branch target.
Definition: MCInstrDesc.h:115
llvm::MCOI::OPERAND_GENERIC_5
@ OPERAND_GENERIC_5
Definition: MCInstrDesc.h:70
llvm::MCOperandInfo::isGenericImm
bool isGenericImm() const
Definition: MCInstrDesc.h:127
llvm::MCInstrDesc::mayStore
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:436
llvm::MCOI::OperandConstraint
OperandConstraint
Operand constraints.
Definition: MCInstrDesc.h:34
llvm::MCID::HasPostISelHook
@ HasPostISelHook
Definition: MCInstrDesc.h:175
llvm::MCInstrDesc::getFlags
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:247
llvm::MCID::UsesCustomInserter
@ UsesCustomInserter
Definition: MCInstrDesc.h:174
llvm::MCInstrDesc::isConvertibleTo3Addr
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MCInstrDesc.h:489
llvm::MCID::MoveImm
@ MoveImm
Definition: MCInstrDesc.h:160
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:410
llvm::MCInstrDesc::hasDefOfPhysReg
bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, const MCRegisterInfo &RI) const
Return true if this instruction defines the specified physical register, either explicitly or implici...
Definition: MCInstrDesc.cpp:42
llvm::MCInstrDesc::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction may raise a floating-point exception.
Definition: MCInstrDesc.h:439
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCInstrDesc::isCompare
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:333
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MCID::Variadic
@ Variadic
Definition: MCInstrDesc.h:149
llvm::MCID::ExtractSubreg
@ ExtractSubreg
Definition: MCInstrDesc.h:181
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:163
llvm::MCOI::OPERAND_GENERIC_2
@ OPERAND_GENERIC_2
Definition: MCInstrDesc.h:67
llvm::MCOperandInfo::getGenericTypeIndex
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:122
llvm::MCInstrDesc::mayAffectControlFlow
bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const
Return true if this is a branch or an instruction which directly writes to the program counter.
Definition: MCInstrDesc.cpp:21
uint16_t
llvm::MCInstrDesc::hasImplicitUseOfPhysReg
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
Definition: MCInstrDesc.h:596
llvm::MCInstrDesc::hasOptionalDef
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:261
llvm::MCID::Branch
@ Branch
Definition: MCInstrDesc.h:157
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:257
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:184
llvm::MCID::MoveReg
@ MoveReg
Definition: MCInstrDesc.h:161
llvm::MCInstrDesc::opInfo_begin
const_opInfo_iterator opInfo_begin() const
Definition: MCInstrDesc.h:233
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:77
llvm::MCOI::OptionalDef
@ OptionalDef
Definition: MCInstrDesc.h:52
llvm::MCInstrDesc::isRegSequenceLike
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MCInstrDesc.h:373
llvm::MCID::HasOptionalDef
@ HasOptionalDef
Definition: MCInstrDesc.h:150
llvm::MCInstrDesc::isUnconditionalBranch
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MCInstrDesc.h:317
llvm::MCInstrDesc::SchedClass
unsigned short SchedClass
Definition: MCInstrDesc.h:202
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::MCID::PreISelOpcode
@ PreISelOpcode
Definition: MCInstrDesc.h:148
llvm::MCOI::OPERAND_UNKNOWN
@ OPERAND_UNKNOWN
Definition: MCInstrDesc.h:58
llvm::MCInstrDesc::canFoldAsLoad
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MCInstrDesc.h:361
DataTypes.h
llvm::MCID::ConvertibleTo3Addr
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:173
llvm::MCInstrDesc::isReturn
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:268
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::MCID::ExtraDefRegAllocReq
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:179
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:211
llvm::MCOI::Predicate
@ Predicate
Definition: MCInstrDesc.h:51
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:229
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:156
llvm::MCID::InsertSubreg
@ InsertSubreg
Definition: MCInstrDesc.h:182
llvm::MCInstrDesc::operands
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:236
llvm::MCInstrDesc::isConditionalBranch
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:309
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:560
llvm::MCInstrDesc::hasDelaySlot
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MCInstrDesc.h:352
llvm::MCOperandInfo::Flags
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
Definition: MCInstrDesc.h:93
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:206
llvm::MCInstrDesc::isSelect
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:343