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14 #ifndef LLVM_MC_MCINSTRDESC_H
15 #define LLVM_MC_MCINSTRDESC_H
40 #define MCOI_TIED_TO(op) \
41 ((1 << MCOI::TIED_TO) | ((op) << (4 + MCOI::TIED_TO * 4)))
43 #define MCOI_EARLY_CLOBBER \
44 (1 << MCOI::EARLY_CLOBBER)
215 (
OpInfo[OpNum].Constraints & (1 << Constraint))) {
216 unsigned ValuePos = 4 + Constraint * 4;
603 for (; *ImpUses; ++ImpUses)
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
unsigned getOpcode() const
Return the opcode number for this descriptor.
This is an optimization pass for GlobalISel generic memory operations.
bool isConvergent() const
Return true if this instruction is convergent.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
@ OPERAND_FIRST_GENERIC_IMM
bool isPreISelOpcode() const
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
const_opInfo_iterator opInfo_end() const
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Reg
All possible values of the reg field in the ModR/M byte.
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Instances of this class represent a single low-level machine instruction.
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
uint16_t Constraints
Operand constraints (see OperandConstraint enum).
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class.
@ OPERAND_LAST_GENERIC_IMM
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
This holds information about one operand of a machine instruction, indicating the register class for ...
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction.
const MCPhysReg * ImplicitUses
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
bool isTrap() const
Return true if this instruction is a trap.
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
bool isMetaInstruction() const
Return true if this is a meta instruction that doesn't produce any output in the form of executable i...
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Describe properties that are true of each instruction in the target description file.
bool isMoveReg() const
Return true if the instruction is a register to register move.
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
bool isAuthenticated() const
Return true if this instruction authenticates a pointer (e.g.
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
bool isOptionalDef() const
Set if this operand is a optional def.
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
bool mayLoad() const
Return true if this instruction could possibly read memory.
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
unsigned short NumOperands
bool isAdd() const
Return true if the instruction is an add instruction.
unsigned getGenericImmIndex() const
bool isCall() const
Return true if the instruction is a call.
bool isGenericType() const
uint8_t OperandType
Information about the type of the operand.
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
OperandType
Operands are tagged with one of the values of this enum.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCOperandInfo * OpInfo
bool isBranchTarget() const
Set if this operand is a branch target.
bool isGenericImm() const
bool mayStore() const
Return true if this instruction could possibly modify memory.
OperandConstraint
Operand constraints.
uint64_t getFlags() const
Return flags of this instruction.
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, const MCRegisterInfo &RI) const
Return true if this instruction defines the specified physical register, either explicitly or implici...
bool mayRaiseFPException() const
Return true if this instruction may raise a floating-point exception.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isCompare() const
Return true if this instruction is a comparison.
unsigned const MachineRegisterInfo * MRI
unsigned getGenericTypeIndex() const
bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const
Return true if this is a branch or an instruction which directly writes to the program counter.
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
const_opInfo_iterator opInfo_begin() const
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block.
unsigned short SchedClass
A range adaptor for a pair of iterators.
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
bool isReturn() const
Return true if the instruction is a return.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
iterator_range< const_opInfo_iterator > operands() const
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
const MCPhysReg * ImplicitDefs
bool isSelect() const
Return true if this is a select instruction.