LLVM  14.0.0git
MCInstrDesc.h
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1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MCOperandInfo and MCInstrDesc classes, which
10 // are used to describe target instructions and their operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MC_MCINSTRDESC_H
15 #define LLVM_MC_MCINSTRDESC_H
16 
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/DataTypes.h"
19 
20 namespace llvm {
21 
22 class MCInst;
23 
24 //===----------------------------------------------------------------------===//
25 // Machine Operand Flags and Description
26 //===----------------------------------------------------------------------===//
27 
28 namespace MCOI {
29 /// Operand constraints. These are encoded in 16 bits with one of the
30 /// low-order 3 bits specifying that a constraint is present and the
31 /// corresponding high-order hex digit specifying the constraint value.
32 /// This allows for a maximum of 3 constraints.
34  TIED_TO = 0, // Must be allocated the same register as specified value.
35  EARLY_CLOBBER // If present, operand is an early clobber register.
36 };
37 
38 // Define a macro to produce each constraint value.
39 #define MCOI_TIED_TO(op) \
40  ((1 << MCOI::TIED_TO) | ((op) << (4 + MCOI::TIED_TO * 4)))
41 
42 #define MCOI_EARLY_CLOBBER \
43  (1 << MCOI::EARLY_CLOBBER)
44 
45 /// These are flags set on operands, but should be considered
46 /// private, all access should go through the MCOperandInfo accessors.
47 /// See the accessors for a description of what these are.
53 };
54 
55 /// Operands are tagged with one of the values of this enum.
62 
71 
75 
77 };
78 
79 } // namespace MCOI
80 
81 /// This holds information about one operand of a machine instruction,
82 /// indicating the register class for register operands, etc.
84 public:
85  /// This specifies the register class enumeration of the operand
86  /// if the operand is a register. If isLookupPtrRegClass is set, then this is
87  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
88  /// get a dynamic register class.
89  int16_t RegClass;
90 
91  /// These are flags from the MCOI::OperandFlags enum.
92  uint8_t Flags;
93 
94  /// Information about the type of the operand.
95  uint8_t OperandType;
96 
97  /// Operand constraints (see OperandConstraint enum).
99 
100  /// Set if this operand is a pointer value and it requires a callback
101  /// to look up its register class.
102  bool isLookupPtrRegClass() const {
103  return Flags & (1 << MCOI::LookupPtrRegClass);
104  }
105 
106  /// Set if this is one of the operands that made up of the predicate
107  /// operand that controls an isPredicable() instruction.
108  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
109 
110  /// Set if this operand is a optional def.
111  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
112 
113  /// Set if this operand is a branch target.
114  bool isBranchTarget() const { return Flags & (1 << MCOI::BranchTarget); }
115 
116  bool isGenericType() const {
119  }
120 
121  unsigned getGenericTypeIndex() const {
122  assert(isGenericType() && "non-generic types don't have an index");
124  }
125 
126  bool isGenericImm() const {
129  }
130 
131  unsigned getGenericImmIndex() const {
132  assert(isGenericImm() && "non-generic immediates don't have an index");
134  }
135 };
136 
137 //===----------------------------------------------------------------------===//
138 // Machine Instruction Flags and Description
139 //===----------------------------------------------------------------------===//
140 
141 namespace MCID {
142 /// These should be considered private to the implementation of the
143 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
144 /// not use these directly. These all correspond to bitfields in the
145 /// MCInstrDesc::Flags field.
146 enum Flag {
187 };
188 } // namespace MCID
189 
190 /// Describe properties that are true of each instruction in the target
191 /// description file. This captures information about side effects, register
192 /// use and many other things. There is one instance of this struct for each
193 /// target instruction class, and the MachineInstr class points to this struct
194 /// directly to describe itself.
195 class MCInstrDesc {
196 public:
197  unsigned short Opcode; // The opcode number
198  unsigned short NumOperands; // Num of args (may be more if variable_ops)
199  unsigned char NumDefs; // Num of args that are definitions
200  unsigned char Size; // Number of bytes in encoding.
201  unsigned short SchedClass; // enum identifying instr sched class
202  uint64_t Flags; // Flags identifying machine instr class
203  uint64_t TSFlags; // Target Specific Flag values
204  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
205  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
206  const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
207 
208  /// Returns the value of the specified operand constraint if
209  /// it is present. Returns -1 if it is not present.
210  int getOperandConstraint(unsigned OpNum,
211  MCOI::OperandConstraint Constraint) const {
212  if (OpNum < NumOperands &&
213  (OpInfo[OpNum].Constraints & (1 << Constraint))) {
214  unsigned ValuePos = 4 + Constraint * 4;
215  return (int)(OpInfo[OpNum].Constraints >> ValuePos) & 0x0f;
216  }
217  return -1;
218  }
219 
220  /// Return the opcode number for this descriptor.
221  unsigned getOpcode() const { return Opcode; }
222 
223  /// Return the number of declared MachineOperands for this
224  /// MachineInstruction. Note that variadic (isVariadic() returns true)
225  /// instructions may have additional operands at the end of the list, and note
226  /// that the machine instruction may include implicit register def/uses as
227  /// well.
228  unsigned getNumOperands() const { return NumOperands; }
229 
231 
234 
236  return make_range(opInfo_begin(), opInfo_end());
237  }
238 
239  /// Return the number of MachineOperands that are register
240  /// definitions. Register definitions always occur at the start of the
241  /// machine operand list. This is the number of "outs" in the .td file,
242  /// and does not include implicit defs.
243  unsigned getNumDefs() const { return NumDefs; }
244 
245  /// Return flags of this instruction.
246  uint64_t getFlags() const { return Flags; }
247 
248  /// \returns true if this instruction is emitted before instruction selection
249  /// and should be legalized/regbankselected/selected.
250  bool isPreISelOpcode() const { return Flags & (1ULL << MCID::PreISelOpcode); }
251 
252  /// Return true if this instruction can have a variable number of
253  /// operands. In this case, the variable operands will be after the normal
254  /// operands but before the implicit definitions and uses (if any are
255  /// present).
256  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
257 
258  /// Set if this instruction has an optional definition, e.g.
259  /// ARM instructions which can set condition code if 's' bit is set.
260  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
261 
262  /// Return true if this is a pseudo instruction that doesn't
263  /// correspond to a real machine instruction.
264  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
265 
266  /// Return true if the instruction is a return.
267  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
268 
269  /// Return true if the instruction is an add instruction.
270  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
271 
272  /// Return true if this instruction is a trap.
273  bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
274 
275  /// Return true if the instruction is a register to register move.
276  bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
277 
278  /// Return true if the instruction is a call.
279  bool isCall() const { return Flags & (1ULL << MCID::Call); }
280 
281  /// Returns true if the specified instruction stops control flow
282  /// from executing the instruction immediately following it. Examples include
283  /// unconditional branches and return instructions.
284  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
285 
286  /// Returns true if this instruction part of the terminator for
287  /// a basic block. Typically this is things like return and branch
288  /// instructions.
289  ///
290  /// Various passes use this to insert code into the bottom of a basic block,
291  /// but before control flow occurs.
292  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
293 
294  /// Returns true if this is a conditional, unconditional, or
295  /// indirect branch. Predicates below can be used to discriminate between
296  /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
297  /// get more information.
298  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
299 
300  /// Return true if this is an indirect branch, such as a
301  /// branch through a register.
302  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
303 
304  /// Return true if this is a branch which may fall
305  /// through to the next instruction or may transfer control flow to some other
306  /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
307  /// information about this branch.
308  bool isConditionalBranch() const {
309  return isBranch() && !isBarrier() && !isIndirectBranch();
310  }
311 
312  /// Return true if this is a branch which always
313  /// transfers control flow to some other block. The
314  /// TargetInstrInfo::analyzeBranch method can be used to get more information
315  /// about this branch.
316  bool isUnconditionalBranch() const {
317  return isBranch() && isBarrier() && !isIndirectBranch();
318  }
319 
320  /// Return true if this is a branch or an instruction which directly
321  /// writes to the program counter. Considered 'may' affect rather than
322  /// 'does' affect as things like predication are not taken into account.
323  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
324 
325  /// Return true if this instruction has a predicate operand
326  /// that controls execution. It may be set to 'always', or may be set to other
327  /// values. There are various methods in TargetInstrInfo that can be used to
328  /// control and modify the predicate in this instruction.
329  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
330 
331  /// Return true if this instruction is a comparison.
332  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
333 
334  /// Return true if this instruction is a move immediate
335  /// (including conditional moves) instruction.
336  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
337 
338  /// Return true if this instruction is a bitcast instruction.
339  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
340 
341  /// Return true if this is a select instruction.
342  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
343 
344  /// Return true if this instruction cannot be safely
345  /// duplicated. For example, if the instruction has a unique labels attached
346  /// to it, duplicating it would cause multiple definition errors.
347  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
348 
349  /// Returns true if the specified instruction has a delay slot which
350  /// must be filled by the code generator.
351  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
352 
353  /// Return true for instructions that can be folded as memory operands
354  /// in other instructions. The most common use for this is instructions that
355  /// are simple loads from memory that don't modify the loaded value in any
356  /// way, but it can also be used for instructions that can be expressed as
357  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
358  /// folded when it is beneficial. This should only be set on instructions
359  /// that return a value in their only virtual register definition.
360  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
361 
362  /// Return true if this instruction behaves
363  /// the same way as the generic REG_SEQUENCE instructions.
364  /// E.g., on ARM,
365  /// dX VMOVDRR rY, rZ
366  /// is equivalent to
367  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
368  ///
369  /// Note that for the optimizers to be able to take advantage of
370  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
371  /// override accordingly.
372  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
373 
374  /// Return true if this instruction behaves
375  /// the same way as the generic EXTRACT_SUBREG instructions.
376  /// E.g., on ARM,
377  /// rX, rY VMOVRRD dZ
378  /// is equivalent to two EXTRACT_SUBREG:
379  /// rX = EXTRACT_SUBREG dZ, ssub_0
380  /// rY = EXTRACT_SUBREG dZ, ssub_1
381  ///
382  /// Note that for the optimizers to be able to take advantage of
383  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
384  /// override accordingly.
385  bool isExtractSubregLike() const {
386  return Flags & (1ULL << MCID::ExtractSubreg);
387  }
388 
389  /// Return true if this instruction behaves
390  /// the same way as the generic INSERT_SUBREG instructions.
391  /// E.g., on ARM,
392  /// dX = VSETLNi32 dY, rZ, Imm
393  /// is equivalent to a INSERT_SUBREG:
394  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
395  ///
396  /// Note that for the optimizers to be able to take advantage of
397  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
398  /// override accordingly.
399  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
400 
401 
402  /// Return true if this instruction is convergent.
403  ///
404  /// Convergent instructions may not be made control-dependent on any
405  /// additional values.
406  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
407 
408  /// Return true if variadic operands of this instruction are definitions.
409  bool variadicOpsAreDefs() const {
410  return Flags & (1ULL << MCID::VariadicOpsAreDefs);
411  }
412 
413  /// Return true if this instruction authenticates a pointer (e.g. LDRAx/BRAx
414  /// from ARMv8.3, which perform loads/branches with authentication).
415  ///
416  /// An authenticated instruction may fail in an ABI-defined manner when
417  /// operating on an invalid signed pointer.
418  bool isAuthenticated() const {
419  return Flags & (1ULL << MCID::Authenticated);
420  }
421 
422  //===--------------------------------------------------------------------===//
423  // Side Effect Analysis
424  //===--------------------------------------------------------------------===//
425 
426  /// Return true if this instruction could possibly read memory.
427  /// Instructions with this flag set are not necessarily simple load
428  /// instructions, they may load a value and modify it, for example.
429  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
430 
431  /// Return true if this instruction could possibly modify memory.
432  /// Instructions with this flag set are not necessarily simple store
433  /// instructions, they may store a modified value based on their operands, or
434  /// may not actually modify anything, for example.
435  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
436 
437  /// Return true if this instruction may raise a floating-point exception.
438  bool mayRaiseFPException() const {
439  return Flags & (1ULL << MCID::MayRaiseFPException);
440  }
441 
442  /// Return true if this instruction has side
443  /// effects that are not modeled by other flags. This does not return true
444  /// for instructions whose effects are captured by:
445  ///
446  /// 1. Their operand list and implicit definition/use list. Register use/def
447  /// info is explicit for instructions.
448  /// 2. Memory accesses. Use mayLoad/mayStore.
449  /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
450  ///
451  /// Examples of side effects would be modifying 'invisible' machine state like
452  /// a control register, flushing a cache, modifying a register invisible to
453  /// LLVM, etc.
454  bool hasUnmodeledSideEffects() const {
455  return Flags & (1ULL << MCID::UnmodeledSideEffects);
456  }
457 
458  //===--------------------------------------------------------------------===//
459  // Flags that indicate whether an instruction can be modified by a method.
460  //===--------------------------------------------------------------------===//
461 
462  /// Return true if this may be a 2- or 3-address instruction (of the
463  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
464  /// exchanged. If this flag is set, then the
465  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
466  /// instruction.
467  ///
468  /// Note that this flag may be set on instructions that are only commutable
469  /// sometimes. In these cases, the call to commuteInstruction will fail.
470  /// Also note that some instructions require non-trivial modification to
471  /// commute them.
472  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
473 
474  /// Return true if this is a 2-address instruction which can be changed
475  /// into a 3-address instruction if needed. Doing this transformation can be
476  /// profitable in the register allocator, because it means that the
477  /// instruction can use a 2-address form if possible, but degrade into a less
478  /// efficient form if the source and dest register cannot be assigned to the
479  /// same register. For example, this allows the x86 backend to turn a "shl
480  /// reg, 3" instruction into an LEA instruction, which is the same speed as
481  /// the shift but has bigger code size.
482  ///
483  /// If this returns true, then the target must implement the
484  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
485  /// is allowed to fail if the transformation isn't valid for this specific
486  /// instruction (e.g. shl reg, 4 on x86).
487  ///
488  bool isConvertibleTo3Addr() const {
489  return Flags & (1ULL << MCID::ConvertibleTo3Addr);
490  }
491 
492  /// Return true if this instruction requires custom insertion support
493  /// when the DAG scheduler is inserting it into a machine basic block. If
494  /// this is true for the instruction, it basically means that it is a pseudo
495  /// instruction used at SelectionDAG time that is expanded out into magic code
496  /// by the target when MachineInstrs are formed.
497  ///
498  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
499  /// is used to insert this into the MachineBasicBlock.
500  bool usesCustomInsertionHook() const {
501  return Flags & (1ULL << MCID::UsesCustomInserter);
502  }
503 
504  /// Return true if this instruction requires *adjustment* after
505  /// instruction selection by calling a target hook. For example, this can be
506  /// used to fill in ARM 's' optional operand depending on whether the
507  /// conditional flag register is used.
508  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
509 
510  /// Returns true if this instruction is a candidate for remat. This
511  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
512  ///
513  /// If this flag is set, the isReallyTriviallyReMaterializable()
514  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
515  /// the instruction is really rematable.
516  bool isRematerializable() const {
517  return Flags & (1ULL << MCID::Rematerializable);
518  }
519 
520  /// Returns true if this instruction has the same cost (or less) than a
521  /// move instruction. This is useful during certain types of optimizations
522  /// (e.g., remat during two-address conversion or machine licm) where we would
523  /// like to remat or hoist the instruction, but not if it costs more than
524  /// moving the instruction into the appropriate register. Note, we are not
525  /// marking copies from and to the same register class with this flag.
526  ///
527  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
528  /// for different subtargets.
529  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
530 
531  /// Returns true if this instruction source operands have special
532  /// register allocation requirements that are not captured by the operand
533  /// register classes. e.g. ARM::STRD's two source registers must be an even /
534  /// odd pair, ARM::STM registers have to be in ascending order. Post-register
535  /// allocation passes should not attempt to change allocations for sources of
536  /// instructions with this flag.
537  bool hasExtraSrcRegAllocReq() const {
538  return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
539  }
540 
541  /// Returns true if this instruction def operands have special register
542  /// allocation requirements that are not captured by the operand register
543  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
544  /// ARM::LDM registers have to be in ascending order. Post-register
545  /// allocation passes should not attempt to change allocations for definitions
546  /// of instructions with this flag.
547  bool hasExtraDefRegAllocReq() const {
548  return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
549  }
550 
551  /// Return a list of registers that are potentially read by any
552  /// instance of this machine instruction. For example, on X86, the "adc"
553  /// instruction adds two register operands and adds the carry bit in from the
554  /// flags register. In this case, the instruction is marked as implicitly
555  /// reading the flags. Likewise, the variable shift instruction on X86 is
556  /// marked as implicitly reading the 'CL' register, which it always does.
557  ///
558  /// This method returns null if the instruction has no implicit uses.
559  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
560 
561  /// Return the number of implicit uses this instruction has.
562  unsigned getNumImplicitUses() const {
563  if (!ImplicitUses)
564  return 0;
565  unsigned i = 0;
566  for (; ImplicitUses[i]; ++i) /*empty*/
567  ;
568  return i;
569  }
570 
571  /// Return a list of registers that are potentially written by any
572  /// instance of this machine instruction. For example, on X86, many
573  /// instructions implicitly set the flags register. In this case, they are
574  /// marked as setting the FLAGS. Likewise, many instructions always deposit
575  /// their result in a physical register. For example, the X86 divide
576  /// instruction always deposits the quotient and remainder in the EAX/EDX
577  /// registers. For that instruction, this will return a list containing the
578  /// EAX/EDX/EFLAGS registers.
579  ///
580  /// This method returns null if the instruction has no implicit defs.
581  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
582 
583  /// Return the number of implicit defs this instruct has.
584  unsigned getNumImplicitDefs() const {
585  if (!ImplicitDefs)
586  return 0;
587  unsigned i = 0;
588  for (; ImplicitDefs[i]; ++i) /*empty*/
589  ;
590  return i;
591  }
592 
593  /// Return true if this instruction implicitly
594  /// uses the specified physical register.
595  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
596  if (const MCPhysReg *ImpUses = ImplicitUses)
597  for (; *ImpUses; ++ImpUses)
598  if (*ImpUses == Reg)
599  return true;
600  return false;
601  }
602 
603  /// Return true if this instruction implicitly
604  /// defines the specified physical register.
605  bool hasImplicitDefOfPhysReg(unsigned Reg,
606  const MCRegisterInfo *MRI = nullptr) const;
607 
608  /// Return the scheduling class for this instruction. The
609  /// scheduling class is an index into the InstrItineraryData table. This
610  /// returns zero if there is no known scheduling information for the
611  /// instruction.
612  unsigned getSchedClass() const { return SchedClass; }
613 
614  /// Return the number of bytes in the encoding of this instruction,
615  /// or zero if the encoding size cannot be known from the opcode.
616  unsigned getSize() const { return Size; }
617 
618  /// Find the index of the first operand in the
619  /// operand list that is used to represent the predicate. It returns -1 if
620  /// none is found.
622  if (isPredicable()) {
623  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
624  if (OpInfo[i].isPredicate())
625  return i;
626  }
627  return -1;
628  }
629 
630  /// Return true if this instruction defines the specified physical
631  /// register, either explicitly or implicitly.
632  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
633  const MCRegisterInfo &RI) const;
634 };
635 
636 } // end namespace llvm
637 
638 #endif
i
i
Definition: README.txt:29
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
llvm::MCID::EHScopeReturn
@ EHScopeReturn
Definition: MCInstrDesc.h:152
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:221
llvm::MCID::Compare
@ Compare
Definition: MCInstrDesc.h:158
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MCID::UnmodeledSideEffects
@ UnmodeledSideEffects
Definition: MCInstrDesc.h:170
llvm::MCID::DelaySlot
@ DelaySlot
Definition: MCInstrDesc.h:163
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCInstrDesc::isConvergent
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:406
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::MCOI::OPERAND_FIRST_GENERIC_IMM
@ OPERAND_FIRST_GENERIC_IMM
Definition: MCInstrDesc.h:72
llvm::MCInstrDesc::Flags
uint64_t Flags
Definition: MCInstrDesc.h:202
llvm::MCOI::OPERAND_GENERIC_0
@ OPERAND_GENERIC_0
Definition: MCInstrDesc.h:64
llvm::MCID::Authenticated
@ Authenticated
Definition: MCInstrDesc.h:186
llvm::MCInstrDesc::isPreISelOpcode
bool isPreISelOpcode() const
Definition: MCInstrDesc.h:250
llvm::MCInstrDesc::hasExtraDefRegAllocReq
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MCInstrDesc.h:547
llvm::MCInstrDesc::isBranch
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:298
llvm::MCInstrDesc::isAsCheapAsAMove
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MCInstrDesc.h:529
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:58
llvm::MCID::FoldableAsLoad
@ FoldableAsLoad
Definition: MCInstrDesc.h:164
llvm::MCInstrDesc::isPseudo
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MCInstrDesc.h:264
llvm::MCInstrDesc::opInfo_end
const_opInfo_iterator opInfo_end() const
Definition: MCInstrDesc.h:233
llvm::MCOI::OPERAND_MEMORY
@ OPERAND_MEMORY
Definition: MCInstrDesc.h:60
llvm::MCID::NotDuplicable
@ NotDuplicable
Definition: MCInstrDesc.h:169
llvm::MCInstrDesc::getSchedClass
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:612
llvm::MCID::Commutable
@ Commutable
Definition: MCInstrDesc.h:171
llvm::MCInstrDesc::isBitcast
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
Definition: MCInstrDesc.h:339
llvm::MCInstrDesc::Size
unsigned char Size
Definition: MCInstrDesc.h:200
llvm::MCOI::LookupPtrRegClass
@ LookupPtrRegClass
Definition: MCInstrDesc.h:49
llvm::MCInstrDesc::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MCInstrDesc.h:621
llvm::MCID::Convergent
@ Convergent
Definition: MCInstrDesc.h:182
llvm::MCOI::OPERAND_GENERIC_4
@ OPERAND_GENERIC_4
Definition: MCInstrDesc.h:68
llvm::MCOI::OPERAND_GENERIC_1
@ OPERAND_GENERIC_1
Definition: MCInstrDesc.h:65
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInstrDesc::isIndirectBranch
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:302
llvm::MCOperandInfo::Constraints
uint16_t Constraints
Operand constraints (see OperandConstraint enum).
Definition: MCInstrDesc.h:98
llvm::MCOperandInfo::isLookupPtrRegClass
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class.
Definition: MCInstrDesc.h:102
llvm::MCOI::OPERAND_LAST_GENERIC_IMM
@ OPERAND_LAST_GENERIC_IMM
Definition: MCInstrDesc.h:74
llvm::MCInstrDesc::isPredicable
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:329
llvm::MCOI::OPERAND_LAST_GENERIC
@ OPERAND_LAST_GENERIC
Definition: MCInstrDesc.h:70
llvm::MCInstrDesc::hasPostISelHook
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:508
llvm::MCInstrDesc::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
Definition: MCInstrDesc.h:454
llvm::MCInstrDesc::NumDefs
unsigned char NumDefs
Definition: MCInstrDesc.h:199
llvm::MCOI::OPERAND_GENERIC_3
@ OPERAND_GENERIC_3
Definition: MCInstrDesc.h:67
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:83
llvm::MCInstrDesc::isRematerializable
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:516
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:616
llvm::MCOI::OPERAND_FIRST_GENERIC
@ OPERAND_FIRST_GENERIC
Definition: MCInstrDesc.h:63
llvm::MCInstrDesc::isMoveImmediate
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition: MCInstrDesc.h:336
llvm::MCInstrDesc::ImplicitUses
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:204
llvm::MCOI::OperandFlags
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:48
llvm::MCInstrDesc::hasExtraSrcRegAllocReq
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MCInstrDesc.h:537
llvm::MCInstrDesc::isTrap
bool isTrap() const
Return true if this instruction is a trap.
Definition: MCInstrDesc.h:273
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:562
llvm::MCID::Predicable
@ Predicable
Definition: MCInstrDesc.h:168
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:581
llvm::MCInstrDesc::isTerminator
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:292
llvm::MCID::Return
@ Return
Definition: MCInstrDesc.h:151
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MCOI::OPERAND_GENERIC_IMM_0
@ OPERAND_GENERIC_IMM_0
Definition: MCInstrDesc.h:73
llvm::MCInstrDesc::isMoveReg
bool isMoveReg() const
Return true if the instruction is a register to register move.
Definition: MCInstrDesc.h:276
llvm::MCInstrDesc::isCommutable
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MCInstrDesc.h:472
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:584
llvm::MCInstrDesc::isBarrier
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:284
llvm::MCOI::BranchTarget
@ BranchTarget
Definition: MCInstrDesc.h:52
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:197
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:61
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:89
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::MCInstrDesc::isAuthenticated
bool isAuthenticated() const
Return true if this instruction authenticates a pointer (e.g.
Definition: MCInstrDesc.h:418
llvm::MCID::RegSequence
@ RegSequence
Definition: MCInstrDesc.h:179
llvm::MCID::VariadicOpsAreDefs
@ VariadicOpsAreDefs
Definition: MCInstrDesc.h:185
llvm::MCInstrDesc::usesCustomInsertionHook
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MCInstrDesc.h:500
llvm::MCID::MayStore
@ MayStore
Definition: MCInstrDesc.h:166
llvm::MCInstrDesc::hasImplicitDefOfPhysReg
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
Definition: MCInstrDesc.cpp:33
llvm::MCID::MayLoad
@ MayLoad
Definition: MCInstrDesc.h:165
llvm::MCID::MayRaiseFPException
@ MayRaiseFPException
Definition: MCInstrDesc.h:167
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:111
llvm::MCOperandInfo::isPredicate
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:108
llvm::MCID::Trap
@ Trap
Definition: MCInstrDesc.h:184
llvm::MCID::ExtraSrcRegAllocReq
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:177
llvm::MCInstrDesc::mayLoad
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:429
llvm::MCID::Pseudo
@ Pseudo
Definition: MCInstrDesc.h:150
llvm::MCInstrDesc::isNotDuplicable
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
Definition: MCInstrDesc.h:347
llvm::MCInstrDesc::NumOperands
unsigned short NumOperands
Definition: MCInstrDesc.h:198
llvm::MCInstrDesc::isAdd
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:270
llvm::MCID::IndirectBranch
@ IndirectBranch
Definition: MCInstrDesc.h:157
llvm::MCOI::EARLY_CLOBBER
@ EARLY_CLOBBER
Definition: MCInstrDesc.h:35
uint64_t
llvm::MCOperandInfo::getGenericImmIndex
unsigned getGenericImmIndex() const
Definition: MCInstrDesc.h:131
llvm::MCID::Barrier
@ Barrier
Definition: MCInstrDesc.h:154
llvm::MCInstrDesc::isCall
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:279
llvm::MCOperandInfo::isGenericType
bool isGenericType() const
Definition: MCInstrDesc.h:116
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::MCInstrDesc::isInsertSubregLike
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
Definition: MCInstrDesc.h:399
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:59
llvm::MCInstrDesc::isExtractSubregLike
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
Definition: MCInstrDesc.h:385
MCRegisterInfo.h
llvm::MCOI::OperandType
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:56
llvm::MCID::Rematerializable
@ Rematerializable
Definition: MCInstrDesc.h:175
llvm::MCID::Bitcast
@ Bitcast
Definition: MCInstrDesc.h:161
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCID::CheapAsAMove
@ CheapAsAMove
Definition: MCInstrDesc.h:176
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::MCOperandInfo::isBranchTarget
bool isBranchTarget() const
Set if this operand is a branch target.
Definition: MCInstrDesc.h:114
llvm::MCOI::OPERAND_GENERIC_5
@ OPERAND_GENERIC_5
Definition: MCInstrDesc.h:69
llvm::MCOperandInfo::isGenericImm
bool isGenericImm() const
Definition: MCInstrDesc.h:126
llvm::MCInstrDesc::mayStore
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:435
llvm::MCOI::OperandConstraint
OperandConstraint
Operand constraints.
Definition: MCInstrDesc.h:33
llvm::MCID::HasPostISelHook
@ HasPostISelHook
Definition: MCInstrDesc.h:174
llvm::MCInstrDesc::getFlags
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:246
llvm::MCID::UsesCustomInserter
@ UsesCustomInserter
Definition: MCInstrDesc.h:173
llvm::MCInstrDesc::isConvertibleTo3Addr
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MCInstrDesc.h:488
llvm::MCID::MoveImm
@ MoveImm
Definition: MCInstrDesc.h:159
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:409
llvm::MCInstrDesc::hasDefOfPhysReg
bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, const MCRegisterInfo &RI) const
Return true if this instruction defines the specified physical register, either explicitly or implici...
Definition: MCInstrDesc.cpp:42
llvm::MCInstrDesc::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction may raise a floating-point exception.
Definition: MCInstrDesc.h:438
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCInstrDesc::isCompare
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:332
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MCID::Variadic
@ Variadic
Definition: MCInstrDesc.h:148
llvm::MCID::ExtractSubreg
@ ExtractSubreg
Definition: MCInstrDesc.h:180
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::MCOI::OPERAND_GENERIC_2
@ OPERAND_GENERIC_2
Definition: MCInstrDesc.h:66
llvm::MCOperandInfo::getGenericTypeIndex
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:121
llvm::MCInstrDesc::mayAffectControlFlow
bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const
Return true if this is a branch or an instruction which directly writes to the program counter.
Definition: MCInstrDesc.cpp:21
uint16_t
llvm::MCInstrDesc::hasImplicitUseOfPhysReg
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
Definition: MCInstrDesc.h:595
llvm::MCInstrDesc::hasOptionalDef
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:260
llvm::MCID::Branch
@ Branch
Definition: MCInstrDesc.h:156
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:256
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::MCID::MoveReg
@ MoveReg
Definition: MCInstrDesc.h:160
llvm::MCInstrDesc::opInfo_begin
const_opInfo_iterator opInfo_begin() const
Definition: MCInstrDesc.h:232
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:76
llvm::MCOI::OptionalDef
@ OptionalDef
Definition: MCInstrDesc.h:51
llvm::MCInstrDesc::isRegSequenceLike
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MCInstrDesc.h:372
llvm::MCID::HasOptionalDef
@ HasOptionalDef
Definition: MCInstrDesc.h:149
llvm::MCInstrDesc::isUnconditionalBranch
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MCInstrDesc.h:316
llvm::MCInstrDesc::SchedClass
unsigned short SchedClass
Definition: MCInstrDesc.h:201
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::MCID::PreISelOpcode
@ PreISelOpcode
Definition: MCInstrDesc.h:147
llvm::MCOI::OPERAND_UNKNOWN
@ OPERAND_UNKNOWN
Definition: MCInstrDesc.h:57
llvm::MCInstrDesc::canFoldAsLoad
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MCInstrDesc.h:360
DataTypes.h
llvm::MCID::ConvertibleTo3Addr
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:172
llvm::MCInstrDesc::isReturn
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:267
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:34
llvm::MCID::ExtraDefRegAllocReq
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:178
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:210
llvm::MCOI::Predicate
@ Predicate
Definition: MCInstrDesc.h:50
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:155
llvm::MCID::InsertSubreg
@ InsertSubreg
Definition: MCInstrDesc.h:181
llvm::MCInstrDesc::operands
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:235
llvm::MCInstrDesc::isConditionalBranch
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:308
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:559
llvm::MCInstrDesc::hasDelaySlot
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MCInstrDesc.h:351
llvm::MCOperandInfo::Flags
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
Definition: MCInstrDesc.h:92
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:205
llvm::MCInstrDesc::isSelect
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:342