LLVM  16.0.0git
MCInstrDesc.h
Go to the documentation of this file.
1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MCOperandInfo and MCInstrDesc classes, which
10 // are used to describe target instructions and their operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MC_MCINSTRDESC_H
15 #define LLVM_MC_MCINSTRDESC_H
16 
18 #include "llvm/MC/MCRegister.h"
19 
20 namespace llvm {
21 class MCRegisterInfo;
22 
23 class MCInst;
24 
25 //===----------------------------------------------------------------------===//
26 // Machine Operand Flags and Description
27 //===----------------------------------------------------------------------===//
28 
29 namespace MCOI {
30 /// Operand constraints. These are encoded in 16 bits with one of the
31 /// low-order 3 bits specifying that a constraint is present and the
32 /// corresponding high-order hex digit specifying the constraint value.
33 /// This allows for a maximum of 3 constraints.
35  TIED_TO = 0, // Must be allocated the same register as specified value.
36  EARLY_CLOBBER // If present, operand is an early clobber register.
37 };
38 
39 // Define a macro to produce each constraint value.
40 #define MCOI_TIED_TO(op) \
41  ((1 << MCOI::TIED_TO) | ((op) << (4 + MCOI::TIED_TO * 4)))
42 
43 #define MCOI_EARLY_CLOBBER \
44  (1 << MCOI::EARLY_CLOBBER)
45 
46 /// These are flags set on operands, but should be considered
47 /// private, all access should go through the MCOperandInfo accessors.
48 /// See the accessors for a description of what these are.
54 };
55 
56 /// Operands are tagged with one of the values of this enum.
63 
72 
76 
78 };
79 
80 } // namespace MCOI
81 
82 /// This holds information about one operand of a machine instruction,
83 /// indicating the register class for register operands, etc.
85 public:
86  /// This specifies the register class enumeration of the operand
87  /// if the operand is a register. If isLookupPtrRegClass is set, then this is
88  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
89  /// get a dynamic register class.
90  int16_t RegClass;
91 
92  /// These are flags from the MCOI::OperandFlags enum.
93  uint8_t Flags;
94 
95  /// Information about the type of the operand.
96  uint8_t OperandType;
97 
98  /// Operand constraints (see OperandConstraint enum).
100 
101  /// Set if this operand is a pointer value and it requires a callback
102  /// to look up its register class.
103  bool isLookupPtrRegClass() const {
104  return Flags & (1 << MCOI::LookupPtrRegClass);
105  }
106 
107  /// Set if this is one of the operands that made up of the predicate
108  /// operand that controls an isPredicable() instruction.
109  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
110 
111  /// Set if this operand is a optional def.
112  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
113 
114  /// Set if this operand is a branch target.
115  bool isBranchTarget() const { return Flags & (1 << MCOI::BranchTarget); }
116 
117  bool isGenericType() const {
120  }
121 
122  unsigned getGenericTypeIndex() const {
123  assert(isGenericType() && "non-generic types don't have an index");
125  }
126 
127  bool isGenericImm() const {
130  }
131 
132  unsigned getGenericImmIndex() const {
133  assert(isGenericImm() && "non-generic immediates don't have an index");
135  }
136 };
137 
138 //===----------------------------------------------------------------------===//
139 // Machine Instruction Flags and Description
140 //===----------------------------------------------------------------------===//
141 
142 namespace MCID {
143 /// These should be considered private to the implementation of the
144 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
145 /// not use these directly. These all correspond to bitfields in the
146 /// MCInstrDesc::Flags field.
147 enum Flag {
189 };
190 } // namespace MCID
191 
192 /// Describe properties that are true of each instruction in the target
193 /// description file. This captures information about side effects, register
194 /// use and many other things. There is one instance of this struct for each
195 /// target instruction class, and the MachineInstr class points to this struct
196 /// directly to describe itself.
197 class MCInstrDesc {
198 public:
199  unsigned short Opcode; // The opcode number
200  unsigned short NumOperands; // Num of args (may be more if variable_ops)
201  unsigned char NumDefs; // Num of args that are definitions
202  unsigned char Size; // Number of bytes in encoding.
203  unsigned short SchedClass; // enum identifying instr sched class
204  uint64_t Flags; // Flags identifying machine instr class
205  uint64_t TSFlags; // Target Specific Flag values
206  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
207  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
208  const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
209 
210  /// Returns the value of the specified operand constraint if
211  /// it is present. Returns -1 if it is not present.
212  int getOperandConstraint(unsigned OpNum,
213  MCOI::OperandConstraint Constraint) const {
214  if (OpNum < NumOperands &&
215  (OpInfo[OpNum].Constraints & (1 << Constraint))) {
216  unsigned ValuePos = 4 + Constraint * 4;
217  return (int)(OpInfo[OpNum].Constraints >> ValuePos) & 0x0f;
218  }
219  return -1;
220  }
221 
222  /// Return the opcode number for this descriptor.
223  unsigned getOpcode() const { return Opcode; }
224 
225  /// Return the number of declared MachineOperands for this
226  /// MachineInstruction. Note that variadic (isVariadic() returns true)
227  /// instructions may have additional operands at the end of the list, and note
228  /// that the machine instruction may include implicit register def/uses as
229  /// well.
230  unsigned getNumOperands() const { return NumOperands; }
231 
233 
236 
238  return make_range(opInfo_begin(), opInfo_end());
239  }
240 
241  /// Return the number of MachineOperands that are register
242  /// definitions. Register definitions always occur at the start of the
243  /// machine operand list. This is the number of "outs" in the .td file,
244  /// and does not include implicit defs.
245  unsigned getNumDefs() const { return NumDefs; }
246 
247  /// Return flags of this instruction.
248  uint64_t getFlags() const { return Flags; }
249 
250  /// \returns true if this instruction is emitted before instruction selection
251  /// and should be legalized/regbankselected/selected.
252  bool isPreISelOpcode() const { return Flags & (1ULL << MCID::PreISelOpcode); }
253 
254  /// Return true if this instruction can have a variable number of
255  /// operands. In this case, the variable operands will be after the normal
256  /// operands but before the implicit definitions and uses (if any are
257  /// present).
258  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
259 
260  /// Set if this instruction has an optional definition, e.g.
261  /// ARM instructions which can set condition code if 's' bit is set.
262  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
263 
264  /// Return true if this is a pseudo instruction that doesn't
265  /// correspond to a real machine instruction.
266  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
267 
268  /// Return true if this is a meta instruction that doesn't
269  /// produce any output in the form of executable instructions.
270  bool isMetaInstruction() const { return Flags & (1ULL << MCID::Meta); }
271 
272  /// Return true if the instruction is a return.
273  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
274 
275  /// Return true if the instruction is an add instruction.
276  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
277 
278  /// Return true if this instruction is a trap.
279  bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
280 
281  /// Return true if the instruction is a register to register move.
282  bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
283 
284  /// Return true if the instruction is a call.
285  bool isCall() const { return Flags & (1ULL << MCID::Call); }
286 
287  /// Returns true if the specified instruction stops control flow
288  /// from executing the instruction immediately following it. Examples include
289  /// unconditional branches and return instructions.
290  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
291 
292  /// Returns true if this instruction part of the terminator for
293  /// a basic block. Typically this is things like return and branch
294  /// instructions.
295  ///
296  /// Various passes use this to insert code into the bottom of a basic block,
297  /// but before control flow occurs.
298  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
299 
300  /// Returns true if this is a conditional, unconditional, or
301  /// indirect branch. Predicates below can be used to discriminate between
302  /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
303  /// get more information.
304  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
305 
306  /// Return true if this is an indirect branch, such as a
307  /// branch through a register.
308  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
309 
310  /// Return true if this is a branch which may fall
311  /// through to the next instruction or may transfer control flow to some other
312  /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
313  /// information about this branch.
314  bool isConditionalBranch() const {
315  return isBranch() && !isBarrier() && !isIndirectBranch();
316  }
317 
318  /// Return true if this is a branch which always
319  /// transfers control flow to some other block. The
320  /// TargetInstrInfo::analyzeBranch method can be used to get more information
321  /// about this branch.
322  bool isUnconditionalBranch() const {
323  return isBranch() && isBarrier() && !isIndirectBranch();
324  }
325 
326  /// Return true if this is a branch or an instruction which directly
327  /// writes to the program counter. Considered 'may' affect rather than
328  /// 'does' affect as things like predication are not taken into account.
329  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
330 
331  /// Return true if this instruction has a predicate operand
332  /// that controls execution. It may be set to 'always', or may be set to other
333  /// values. There are various methods in TargetInstrInfo that can be used to
334  /// control and modify the predicate in this instruction.
335  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
336 
337  /// Return true if this instruction is a comparison.
338  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
339 
340  /// Return true if this instruction is a move immediate
341  /// (including conditional moves) instruction.
342  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
343 
344  /// Return true if this instruction is a bitcast instruction.
345  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
346 
347  /// Return true if this is a select instruction.
348  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
349 
350  /// Return true if this instruction cannot be safely
351  /// duplicated. For example, if the instruction has a unique labels attached
352  /// to it, duplicating it would cause multiple definition errors.
353  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
354 
355  /// Returns true if the specified instruction has a delay slot which
356  /// must be filled by the code generator.
357  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
358 
359  /// Return true for instructions that can be folded as memory operands
360  /// in other instructions. The most common use for this is instructions that
361  /// are simple loads from memory that don't modify the loaded value in any
362  /// way, but it can also be used for instructions that can be expressed as
363  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
364  /// folded when it is beneficial. This should only be set on instructions
365  /// that return a value in their only virtual register definition.
366  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
367 
368  /// Return true if this instruction behaves
369  /// the same way as the generic REG_SEQUENCE instructions.
370  /// E.g., on ARM,
371  /// dX VMOVDRR rY, rZ
372  /// is equivalent to
373  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
374  ///
375  /// Note that for the optimizers to be able to take advantage of
376  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
377  /// override accordingly.
378  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
379 
380  /// Return true if this instruction behaves
381  /// the same way as the generic EXTRACT_SUBREG instructions.
382  /// E.g., on ARM,
383  /// rX, rY VMOVRRD dZ
384  /// is equivalent to two EXTRACT_SUBREG:
385  /// rX = EXTRACT_SUBREG dZ, ssub_0
386  /// rY = EXTRACT_SUBREG dZ, ssub_1
387  ///
388  /// Note that for the optimizers to be able to take advantage of
389  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
390  /// override accordingly.
391  bool isExtractSubregLike() const {
392  return Flags & (1ULL << MCID::ExtractSubreg);
393  }
394 
395  /// Return true if this instruction behaves
396  /// the same way as the generic INSERT_SUBREG instructions.
397  /// E.g., on ARM,
398  /// dX = VSETLNi32 dY, rZ, Imm
399  /// is equivalent to a INSERT_SUBREG:
400  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
401  ///
402  /// Note that for the optimizers to be able to take advantage of
403  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
404  /// override accordingly.
405  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
406 
407 
408  /// Return true if this instruction is convergent.
409  ///
410  /// Convergent instructions may not be made control-dependent on any
411  /// additional values.
412  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
413 
414  /// Return true if variadic operands of this instruction are definitions.
415  bool variadicOpsAreDefs() const {
416  return Flags & (1ULL << MCID::VariadicOpsAreDefs);
417  }
418 
419  /// Return true if this instruction authenticates a pointer (e.g. LDRAx/BRAx
420  /// from ARMv8.3, which perform loads/branches with authentication).
421  ///
422  /// An authenticated instruction may fail in an ABI-defined manner when
423  /// operating on an invalid signed pointer.
424  bool isAuthenticated() const {
425  return Flags & (1ULL << MCID::Authenticated);
426  }
427 
428  //===--------------------------------------------------------------------===//
429  // Side Effect Analysis
430  //===--------------------------------------------------------------------===//
431 
432  /// Return true if this instruction could possibly read memory.
433  /// Instructions with this flag set are not necessarily simple load
434  /// instructions, they may load a value and modify it, for example.
435  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
436 
437  /// Return true if this instruction could possibly modify memory.
438  /// Instructions with this flag set are not necessarily simple store
439  /// instructions, they may store a modified value based on their operands, or
440  /// may not actually modify anything, for example.
441  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
442 
443  /// Return true if this instruction may raise a floating-point exception.
444  bool mayRaiseFPException() const {
445  return Flags & (1ULL << MCID::MayRaiseFPException);
446  }
447 
448  /// Return true if this instruction has side
449  /// effects that are not modeled by other flags. This does not return true
450  /// for instructions whose effects are captured by:
451  ///
452  /// 1. Their operand list and implicit definition/use list. Register use/def
453  /// info is explicit for instructions.
454  /// 2. Memory accesses. Use mayLoad/mayStore.
455  /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
456  ///
457  /// Examples of side effects would be modifying 'invisible' machine state like
458  /// a control register, flushing a cache, modifying a register invisible to
459  /// LLVM, etc.
460  bool hasUnmodeledSideEffects() const {
461  return Flags & (1ULL << MCID::UnmodeledSideEffects);
462  }
463 
464  //===--------------------------------------------------------------------===//
465  // Flags that indicate whether an instruction can be modified by a method.
466  //===--------------------------------------------------------------------===//
467 
468  /// Return true if this may be a 2- or 3-address instruction (of the
469  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
470  /// exchanged. If this flag is set, then the
471  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
472  /// instruction.
473  ///
474  /// Note that this flag may be set on instructions that are only commutable
475  /// sometimes. In these cases, the call to commuteInstruction will fail.
476  /// Also note that some instructions require non-trivial modification to
477  /// commute them.
478  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
479 
480  /// Return true if this is a 2-address instruction which can be changed
481  /// into a 3-address instruction if needed. Doing this transformation can be
482  /// profitable in the register allocator, because it means that the
483  /// instruction can use a 2-address form if possible, but degrade into a less
484  /// efficient form if the source and dest register cannot be assigned to the
485  /// same register. For example, this allows the x86 backend to turn a "shl
486  /// reg, 3" instruction into an LEA instruction, which is the same speed as
487  /// the shift but has bigger code size.
488  ///
489  /// If this returns true, then the target must implement the
490  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
491  /// is allowed to fail if the transformation isn't valid for this specific
492  /// instruction (e.g. shl reg, 4 on x86).
493  ///
494  bool isConvertibleTo3Addr() const {
495  return Flags & (1ULL << MCID::ConvertibleTo3Addr);
496  }
497 
498  /// Return true if this instruction requires custom insertion support
499  /// when the DAG scheduler is inserting it into a machine basic block. If
500  /// this is true for the instruction, it basically means that it is a pseudo
501  /// instruction used at SelectionDAG time that is expanded out into magic code
502  /// by the target when MachineInstrs are formed.
503  ///
504  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
505  /// is used to insert this into the MachineBasicBlock.
506  bool usesCustomInsertionHook() const {
507  return Flags & (1ULL << MCID::UsesCustomInserter);
508  }
509 
510  /// Return true if this instruction requires *adjustment* after
511  /// instruction selection by calling a target hook. For example, this can be
512  /// used to fill in ARM 's' optional operand depending on whether the
513  /// conditional flag register is used.
514  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
515 
516  /// Returns true if this instruction is a candidate for remat. This
517  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
518  ///
519  /// If this flag is set, the isReallyTriviallyReMaterializable()
520  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
521  /// the instruction is really rematable.
522  bool isRematerializable() const {
523  return Flags & (1ULL << MCID::Rematerializable);
524  }
525 
526  /// Returns true if this instruction has the same cost (or less) than a
527  /// move instruction. This is useful during certain types of optimizations
528  /// (e.g., remat during two-address conversion or machine licm) where we would
529  /// like to remat or hoist the instruction, but not if it costs more than
530  /// moving the instruction into the appropriate register. Note, we are not
531  /// marking copies from and to the same register class with this flag.
532  ///
533  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
534  /// for different subtargets.
535  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
536 
537  /// Returns true if this instruction source operands have special
538  /// register allocation requirements that are not captured by the operand
539  /// register classes. e.g. ARM::STRD's two source registers must be an even /
540  /// odd pair, ARM::STM registers have to be in ascending order. Post-register
541  /// allocation passes should not attempt to change allocations for sources of
542  /// instructions with this flag.
543  bool hasExtraSrcRegAllocReq() const {
544  return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
545  }
546 
547  /// Returns true if this instruction def operands have special register
548  /// allocation requirements that are not captured by the operand register
549  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
550  /// ARM::LDM registers have to be in ascending order. Post-register
551  /// allocation passes should not attempt to change allocations for definitions
552  /// of instructions with this flag.
553  bool hasExtraDefRegAllocReq() const {
554  return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
555  }
556 
557  /// Return a list of registers that are potentially read by any
558  /// instance of this machine instruction. For example, on X86, the "adc"
559  /// instruction adds two register operands and adds the carry bit in from the
560  /// flags register. In this case, the instruction is marked as implicitly
561  /// reading the flags. Likewise, the variable shift instruction on X86 is
562  /// marked as implicitly reading the 'CL' register, which it always does.
563  ///
564  /// This method returns null if the instruction has no implicit uses.
565  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
566 
567  /// Return the number of implicit uses this instruction has.
568  unsigned getNumImplicitUses() const {
569  if (!ImplicitUses)
570  return 0;
571  unsigned i = 0;
572  for (; ImplicitUses[i]; ++i) /*empty*/
573  ;
574  return i;
575  }
576 
577  /// Return a list of registers that are potentially written by any
578  /// instance of this machine instruction. For example, on X86, many
579  /// instructions implicitly set the flags register. In this case, they are
580  /// marked as setting the FLAGS. Likewise, many instructions always deposit
581  /// their result in a physical register. For example, the X86 divide
582  /// instruction always deposits the quotient and remainder in the EAX/EDX
583  /// registers. For that instruction, this will return a list containing the
584  /// EAX/EDX/EFLAGS registers.
585  ///
586  /// This method returns null if the instruction has no implicit defs.
587  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
588 
589  /// Return the number of implicit defs this instruct has.
590  unsigned getNumImplicitDefs() const {
591  if (!ImplicitDefs)
592  return 0;
593  unsigned i = 0;
594  for (; ImplicitDefs[i]; ++i) /*empty*/
595  ;
596  return i;
597  }
598 
599  /// Return true if this instruction implicitly
600  /// uses the specified physical register.
601  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
602  if (const MCPhysReg *ImpUses = ImplicitUses)
603  for (; *ImpUses; ++ImpUses)
604  if (*ImpUses == Reg)
605  return true;
606  return false;
607  }
608 
609  /// Return true if this instruction implicitly
610  /// defines the specified physical register.
611  bool hasImplicitDefOfPhysReg(unsigned Reg,
612  const MCRegisterInfo *MRI = nullptr) const;
613 
614  /// Return the scheduling class for this instruction. The
615  /// scheduling class is an index into the InstrItineraryData table. This
616  /// returns zero if there is no known scheduling information for the
617  /// instruction.
618  unsigned getSchedClass() const { return SchedClass; }
619 
620  /// Return the number of bytes in the encoding of this instruction,
621  /// or zero if the encoding size cannot be known from the opcode.
622  unsigned getSize() const { return Size; }
623 
624  /// Find the index of the first operand in the
625  /// operand list that is used to represent the predicate. It returns -1 if
626  /// none is found.
628  if (isPredicable()) {
629  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
630  if (OpInfo[i].isPredicate())
631  return i;
632  }
633  return -1;
634  }
635 
636  /// Return true if this instruction defines the specified physical
637  /// register, either explicitly or implicitly.
638  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
639  const MCRegisterInfo &RI) const;
640 };
641 
642 } // end namespace llvm
643 
644 #endif
i
i
Definition: README.txt:29
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::MCID::EHScopeReturn
@ EHScopeReturn
Definition: MCInstrDesc.h:154
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:223
llvm::MCID::Compare
@ Compare
Definition: MCInstrDesc.h:160
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MCID::UnmodeledSideEffects
@ UnmodeledSideEffects
Definition: MCInstrDesc.h:172
llvm::MCID::DelaySlot
@ DelaySlot
Definition: MCInstrDesc.h:165
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MCInstrDesc::isConvergent
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:412
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::MCOI::OPERAND_FIRST_GENERIC_IMM
@ OPERAND_FIRST_GENERIC_IMM
Definition: MCInstrDesc.h:73
llvm::MCInstrDesc::Flags
uint64_t Flags
Definition: MCInstrDesc.h:204
llvm::MCOI::OPERAND_GENERIC_0
@ OPERAND_GENERIC_0
Definition: MCInstrDesc.h:65
llvm::MCID::Authenticated
@ Authenticated
Definition: MCInstrDesc.h:188
llvm::MCInstrDesc::isPreISelOpcode
bool isPreISelOpcode() const
Definition: MCInstrDesc.h:252
llvm::MCInstrDesc::hasExtraDefRegAllocReq
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MCInstrDesc.h:553
llvm::MCInstrDesc::isBranch
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:304
llvm::MCInstrDesc::isAsCheapAsAMove
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MCInstrDesc.h:535
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:59
llvm::MCID::FoldableAsLoad
@ FoldableAsLoad
Definition: MCInstrDesc.h:166
llvm::MCInstrDesc::isPseudo
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MCInstrDesc.h:266
llvm::MCInstrDesc::opInfo_end
const_opInfo_iterator opInfo_end() const
Definition: MCInstrDesc.h:235
llvm::MCOI::OPERAND_MEMORY
@ OPERAND_MEMORY
Definition: MCInstrDesc.h:61
llvm::MCID::NotDuplicable
@ NotDuplicable
Definition: MCInstrDesc.h:171
llvm::MCInstrDesc::getSchedClass
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:618
llvm::MCID::Commutable
@ Commutable
Definition: MCInstrDesc.h:173
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MCInstrDesc::isBitcast
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
Definition: MCInstrDesc.h:345
llvm::MCInstrDesc::Size
unsigned char Size
Definition: MCInstrDesc.h:202
llvm::MCOI::LookupPtrRegClass
@ LookupPtrRegClass
Definition: MCInstrDesc.h:50
llvm::MCInstrDesc::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MCInstrDesc.h:627
llvm::MCID::Convergent
@ Convergent
Definition: MCInstrDesc.h:184
llvm::MCOI::OPERAND_GENERIC_4
@ OPERAND_GENERIC_4
Definition: MCInstrDesc.h:69
llvm::MCOI::OPERAND_GENERIC_1
@ OPERAND_GENERIC_1
Definition: MCInstrDesc.h:66
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInstrDesc::isIndirectBranch
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:308
llvm::MCOperandInfo::Constraints
uint16_t Constraints
Operand constraints (see OperandConstraint enum).
Definition: MCInstrDesc.h:99
llvm::MCOperandInfo::isLookupPtrRegClass
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class.
Definition: MCInstrDesc.h:103
llvm::MCOI::OPERAND_LAST_GENERIC_IMM
@ OPERAND_LAST_GENERIC_IMM
Definition: MCInstrDesc.h:75
llvm::MCInstrDesc::isPredicable
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:335
llvm::MCOI::OPERAND_LAST_GENERIC
@ OPERAND_LAST_GENERIC
Definition: MCInstrDesc.h:71
llvm::MCInstrDesc::hasPostISelHook
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:514
llvm::MCInstrDesc::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
Definition: MCInstrDesc.h:460
llvm::MCInstrDesc::NumDefs
unsigned char NumDefs
Definition: MCInstrDesc.h:201
llvm::MCOI::OPERAND_GENERIC_3
@ OPERAND_GENERIC_3
Definition: MCInstrDesc.h:68
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::MCInstrDesc::isRematerializable
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:522
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:622
llvm::MCOI::OPERAND_FIRST_GENERIC
@ OPERAND_FIRST_GENERIC
Definition: MCInstrDesc.h:64
llvm::MCInstrDesc::isMoveImmediate
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition: MCInstrDesc.h:342
llvm::MCInstrDesc::ImplicitUses
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:206
llvm::MCOI::OperandFlags
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:49
llvm::MCInstrDesc::hasExtraSrcRegAllocReq
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MCInstrDesc.h:543
llvm::MCInstrDesc::isTrap
bool isTrap() const
Return true if this instruction is a trap.
Definition: MCInstrDesc.h:279
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:568
llvm::MCInstrDesc::isMetaInstruction
bool isMetaInstruction() const
Return true if this is a meta instruction that doesn't produce any output in the form of executable i...
Definition: MCInstrDesc.h:270
llvm::MCID::Predicable
@ Predicable
Definition: MCInstrDesc.h:170
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:587
llvm::MCInstrDesc::isTerminator
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:298
llvm::MCID::Return
@ Return
Definition: MCInstrDesc.h:153
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MCOI::OPERAND_GENERIC_IMM_0
@ OPERAND_GENERIC_IMM_0
Definition: MCInstrDesc.h:74
llvm::MCInstrDesc::isMoveReg
bool isMoveReg() const
Return true if the instruction is a register to register move.
Definition: MCInstrDesc.h:282
llvm::MCInstrDesc::isCommutable
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MCInstrDesc.h:478
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:590
llvm::MCInstrDesc::isBarrier
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:290
llvm::MCOI::BranchTarget
@ BranchTarget
Definition: MCInstrDesc.h:53
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:199
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:62
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:155
llvm::MCInstrDesc::isAuthenticated
bool isAuthenticated() const
Return true if this instruction authenticates a pointer (e.g.
Definition: MCInstrDesc.h:424
llvm::MCID::RegSequence
@ RegSequence
Definition: MCInstrDesc.h:181
llvm::MCID::VariadicOpsAreDefs
@ VariadicOpsAreDefs
Definition: MCInstrDesc.h:187
llvm::MCInstrDesc::usesCustomInsertionHook
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MCInstrDesc.h:506
llvm::MCID::MayStore
@ MayStore
Definition: MCInstrDesc.h:168
MCRegister.h
llvm::MCInstrDesc::hasImplicitDefOfPhysReg
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
Definition: MCInstrDesc.cpp:32
llvm::MCID::MayLoad
@ MayLoad
Definition: MCInstrDesc.h:167
llvm::MCID::MayRaiseFPException
@ MayRaiseFPException
Definition: MCInstrDesc.h:169
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:112
llvm::MCOperandInfo::isPredicate
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:109
llvm::MCID::Trap
@ Trap
Definition: MCInstrDesc.h:186
llvm::MCID::ExtraSrcRegAllocReq
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:179
llvm::MCInstrDesc::mayLoad
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:435
llvm::MCID::Pseudo
@ Pseudo
Definition: MCInstrDesc.h:151
llvm::MCInstrDesc::isNotDuplicable
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
Definition: MCInstrDesc.h:353
llvm::MCInstrDesc::NumOperands
unsigned short NumOperands
Definition: MCInstrDesc.h:200
llvm::MCInstrDesc::isAdd
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:276
llvm::MCID::IndirectBranch
@ IndirectBranch
Definition: MCInstrDesc.h:159
llvm::MCOI::EARLY_CLOBBER
@ EARLY_CLOBBER
Definition: MCInstrDesc.h:36
uint64_t
llvm::MCOperandInfo::getGenericImmIndex
unsigned getGenericImmIndex() const
Definition: MCInstrDesc.h:132
llvm::MCID::Barrier
@ Barrier
Definition: MCInstrDesc.h:156
llvm::MCInstrDesc::isCall
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:285
llvm::MCOperandInfo::isGenericType
bool isGenericType() const
Definition: MCInstrDesc.h:117
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:54
llvm::MCInstrDesc::isInsertSubregLike
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
Definition: MCInstrDesc.h:405
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:60
llvm::MCInstrDesc::isExtractSubregLike
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
Definition: MCInstrDesc.h:391
llvm::MCOI::OperandType
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:57
llvm::MCID::Rematerializable
@ Rematerializable
Definition: MCInstrDesc.h:177
llvm::MCID::Bitcast
@ Bitcast
Definition: MCInstrDesc.h:163
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCID::CheapAsAMove
@ CheapAsAMove
Definition: MCInstrDesc.h:178
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
iterator_range.h
llvm::MCOperandInfo::isBranchTarget
bool isBranchTarget() const
Set if this operand is a branch target.
Definition: MCInstrDesc.h:115
llvm::MCOI::OPERAND_GENERIC_5
@ OPERAND_GENERIC_5
Definition: MCInstrDesc.h:70
llvm::MCOperandInfo::isGenericImm
bool isGenericImm() const
Definition: MCInstrDesc.h:127
llvm::MCInstrDesc::mayStore
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:441
llvm::MCOI::OperandConstraint
OperandConstraint
Operand constraints.
Definition: MCInstrDesc.h:34
llvm::MCID::HasPostISelHook
@ HasPostISelHook
Definition: MCInstrDesc.h:176
llvm::MCInstrDesc::getFlags
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:248
llvm::MCID::UsesCustomInserter
@ UsesCustomInserter
Definition: MCInstrDesc.h:175
llvm::MCInstrDesc::isConvertibleTo3Addr
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MCInstrDesc.h:494
llvm::MCID::MoveImm
@ MoveImm
Definition: MCInstrDesc.h:161
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:415
llvm::MCInstrDesc::hasDefOfPhysReg
bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, const MCRegisterInfo &RI) const
Return true if this instruction defines the specified physical register, either explicitly or implici...
Definition: MCInstrDesc.cpp:41
llvm::MCInstrDesc::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction may raise a floating-point exception.
Definition: MCInstrDesc.h:444
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCInstrDesc::isCompare
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:338
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MCID::Variadic
@ Variadic
Definition: MCInstrDesc.h:149
llvm::MCID::ExtractSubreg
@ ExtractSubreg
Definition: MCInstrDesc.h:182
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:164
llvm::MCOI::OPERAND_GENERIC_2
@ OPERAND_GENERIC_2
Definition: MCInstrDesc.h:67
llvm::MCOperandInfo::getGenericTypeIndex
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:122
llvm::MCInstrDesc::mayAffectControlFlow
bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const
Return true if this is a branch or an instruction which directly writes to the program counter.
Definition: MCInstrDesc.cpp:20
uint16_t
llvm::MCInstrDesc::hasImplicitUseOfPhysReg
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
Definition: MCInstrDesc.h:601
llvm::MCInstrDesc::hasOptionalDef
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:262
llvm::MCID::Branch
@ Branch
Definition: MCInstrDesc.h:158
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:258
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:185
llvm::MCID::MoveReg
@ MoveReg
Definition: MCInstrDesc.h:162
llvm::MCInstrDesc::opInfo_begin
const_opInfo_iterator opInfo_begin() const
Definition: MCInstrDesc.h:234
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:77
llvm::MCOI::OptionalDef
@ OptionalDef
Definition: MCInstrDesc.h:52
llvm::MCInstrDesc::isRegSequenceLike
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MCInstrDesc.h:378
llvm::MCID::HasOptionalDef
@ HasOptionalDef
Definition: MCInstrDesc.h:150
llvm::MCInstrDesc::isUnconditionalBranch
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MCInstrDesc.h:322
llvm::MCInstrDesc::SchedClass
unsigned short SchedClass
Definition: MCInstrDesc.h:203
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::MCID::PreISelOpcode
@ PreISelOpcode
Definition: MCInstrDesc.h:148
llvm::MCOI::OPERAND_UNKNOWN
@ OPERAND_UNKNOWN
Definition: MCInstrDesc.h:58
llvm::MCInstrDesc::canFoldAsLoad
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MCInstrDesc.h:366
llvm::MCID::Meta
@ Meta
Definition: MCInstrDesc.h:152
llvm::MCID::ConvertibleTo3Addr
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:174
llvm::MCInstrDesc::isReturn
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:273
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::MCID::ExtraDefRegAllocReq
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:180
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:212
llvm::MCOI::Predicate
@ Predicate
Definition: MCInstrDesc.h:51
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:157
llvm::MCID::InsertSubreg
@ InsertSubreg
Definition: MCInstrDesc.h:183
llvm::MCInstrDesc::operands
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:237
llvm::MCInstrDesc::isConditionalBranch
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:314
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:565
llvm::MCInstrDesc::hasDelaySlot
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MCInstrDesc.h:357
llvm::MCOperandInfo::Flags
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
Definition: MCInstrDesc.h:93
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:207
llvm::MCInstrDesc::isSelect
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:348