LLVM  16.0.0git
IRTranslator.cpp
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1 //===- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator ---*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the IRTranslator class.
10 //===----------------------------------------------------------------------===//
11 
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/ScopeExit.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/Analysis/Loads.h"
24 #include "llvm/CodeGen/Analysis.h"
49 #include "llvm/IR/BasicBlock.h"
50 #include "llvm/IR/CFG.h"
51 #include "llvm/IR/Constant.h"
52 #include "llvm/IR/Constants.h"
53 #include "llvm/IR/DataLayout.h"
54 #include "llvm/IR/DerivedTypes.h"
55 #include "llvm/IR/DiagnosticInfo.h"
56 #include "llvm/IR/Function.h"
58 #include "llvm/IR/InlineAsm.h"
59 #include "llvm/IR/InstrTypes.h"
60 #include "llvm/IR/Instructions.h"
61 #include "llvm/IR/IntrinsicInst.h"
62 #include "llvm/IR/Intrinsics.h"
63 #include "llvm/IR/LLVMContext.h"
64 #include "llvm/IR/Metadata.h"
65 #include "llvm/IR/PatternMatch.h"
66 #include "llvm/IR/Statepoint.h"
67 #include "llvm/IR/Type.h"
68 #include "llvm/IR/User.h"
69 #include "llvm/IR/Value.h"
70 #include "llvm/InitializePasses.h"
71 #include "llvm/MC/MCContext.h"
72 #include "llvm/Pass.h"
73 #include "llvm/Support/Casting.h"
74 #include "llvm/Support/CodeGen.h"
75 #include "llvm/Support/Debug.h"
83 #include <algorithm>
84 #include <cassert>
85 #include <cstdint>
86 #include <iterator>
87 #include <string>
88 #include <utility>
89 #include <vector>
90 
91 #define DEBUG_TYPE "irtranslator"
92 
93 using namespace llvm;
94 
95 static cl::opt<bool>
96  EnableCSEInIRTranslator("enable-cse-in-irtranslator",
97  cl::desc("Should enable CSE in irtranslator"),
98  cl::Optional, cl::init(false));
99 char IRTranslator::ID = 0;
100 
101 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
102  false, false)
110 
112  const TargetPassConfig &TPC,
115  MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
116 
117  // Print the function name explicitly if we don't have a debug location (which
118  // makes the diagnostic less useful) or if we're going to emit a raw error.
119  if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
120  R << (" (in function: " + MF.getName() + ")").str();
121 
122  if (TPC.isGlobalISelAbortEnabled())
123  report_fatal_error(Twine(R.getMsg()));
124  else
125  ORE.emit(R);
126 }
127 
129  : MachineFunctionPass(ID), OptLevel(optlevel) {}
130 
131 #ifndef NDEBUG
132 namespace {
133 /// Verify that every instruction created has the same DILocation as the
134 /// instruction being translated.
135 class DILocationVerifier : public GISelChangeObserver {
136  const Instruction *CurrInst = nullptr;
137 
138 public:
139  DILocationVerifier() = default;
140  ~DILocationVerifier() = default;
141 
142  const Instruction *getCurrentInst() const { return CurrInst; }
143  void setCurrentInst(const Instruction *Inst) { CurrInst = Inst; }
144 
145  void erasingInstr(MachineInstr &MI) override {}
146  void changingInstr(MachineInstr &MI) override {}
147  void changedInstr(MachineInstr &MI) override {}
148 
149  void createdInstr(MachineInstr &MI) override {
150  assert(getCurrentInst() && "Inserted instruction without a current MI");
151 
152  // Only print the check message if we're actually checking it.
153 #ifndef NDEBUG
154  LLVM_DEBUG(dbgs() << "Checking DILocation from " << *CurrInst
155  << " was copied to " << MI);
156 #endif
157  // We allow insts in the entry block to have no debug loc because
158  // they could have originated from constants, and we don't want a jumpy
159  // debug experience.
160  assert((CurrInst->getDebugLoc() == MI.getDebugLoc() ||
161  (MI.getParent()->isEntryBlock() && !MI.getDebugLoc())) &&
162  "Line info was not transferred to all instructions");
163  }
164 };
165 } // namespace
166 #endif // ifndef NDEBUG
167 
168 
174  if (OptLevel != CodeGenOpt::None) {
177  }
182 }
183 
185 IRTranslator::allocateVRegs(const Value &Val) {
186  auto VRegsIt = VMap.findVRegs(Val);
187  if (VRegsIt != VMap.vregs_end())
188  return *VRegsIt->second;
189  auto *Regs = VMap.getVRegs(Val);
190  auto *Offsets = VMap.getOffsets(Val);
191  SmallVector<LLT, 4> SplitTys;
192  computeValueLLTs(*DL, *Val.getType(), SplitTys,
193  Offsets->empty() ? Offsets : nullptr);
194  for (unsigned i = 0; i < SplitTys.size(); ++i)
195  Regs->push_back(0);
196  return *Regs;
197 }
198 
199 ArrayRef<Register> IRTranslator::getOrCreateVRegs(const Value &Val) {
200  auto VRegsIt = VMap.findVRegs(Val);
201  if (VRegsIt != VMap.vregs_end())
202  return *VRegsIt->second;
203 
204  if (Val.getType()->isVoidTy())
205  return *VMap.getVRegs(Val);
206 
207  // Create entry for this type.
208  auto *VRegs = VMap.getVRegs(Val);
209  auto *Offsets = VMap.getOffsets(Val);
210 
211  assert(Val.getType()->isSized() &&
212  "Don't know how to create an empty vreg");
213 
214  SmallVector<LLT, 4> SplitTys;
215  computeValueLLTs(*DL, *Val.getType(), SplitTys,
216  Offsets->empty() ? Offsets : nullptr);
217 
218  if (!isa<Constant>(Val)) {
219  for (auto Ty : SplitTys)
220  VRegs->push_back(MRI->createGenericVirtualRegister(Ty));
221  return *VRegs;
222  }
223 
224  if (Val.getType()->isAggregateType()) {
225  // UndefValue, ConstantAggregateZero
226  auto &C = cast<Constant>(Val);
227  unsigned Idx = 0;
228  while (auto Elt = C.getAggregateElement(Idx++)) {
229  auto EltRegs = getOrCreateVRegs(*Elt);
230  llvm::copy(EltRegs, std::back_inserter(*VRegs));
231  }
232  } else {
233  assert(SplitTys.size() == 1 && "unexpectedly split LLT");
234  VRegs->push_back(MRI->createGenericVirtualRegister(SplitTys[0]));
235  bool Success = translate(cast<Constant>(Val), VRegs->front());
236  if (!Success) {
237  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
238  MF->getFunction().getSubprogram(),
239  &MF->getFunction().getEntryBlock());
240  R << "unable to translate constant: " << ore::NV("Type", Val.getType());
241  reportTranslationError(*MF, *TPC, *ORE, R);
242  return *VRegs;
243  }
244  }
245 
246  return *VRegs;
247 }
248 
249 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
250  auto MapEntry = FrameIndices.find(&AI);
251  if (MapEntry != FrameIndices.end())
252  return MapEntry->second;
253 
254  uint64_t ElementSize = DL->getTypeAllocSize(AI.getAllocatedType());
255  uint64_t Size =
256  ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
257 
258  // Always allocate at least one byte.
259  Size = std::max<uint64_t>(Size, 1u);
260 
261  int &FI = FrameIndices[&AI];
262  FI = MF->getFrameInfo().CreateStackObject(Size, AI.getAlign(), false, &AI);
263  return FI;
264 }
265 
266 Align IRTranslator::getMemOpAlign(const Instruction &I) {
267  if (const StoreInst *SI = dyn_cast<StoreInst>(&I))
268  return SI->getAlign();
269  if (const LoadInst *LI = dyn_cast<LoadInst>(&I))
270  return LI->getAlign();
271  if (const AtomicCmpXchgInst *AI = dyn_cast<AtomicCmpXchgInst>(&I))
272  return AI->getAlign();
273  if (const AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(&I))
274  return AI->getAlign();
275 
276  OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
277  R << "unable to translate memop: " << ore::NV("Opcode", &I);
278  reportTranslationError(*MF, *TPC, *ORE, R);
279  return Align(1);
280 }
281 
282 MachineBasicBlock &IRTranslator::getMBB(const BasicBlock &BB) {
283  MachineBasicBlock *&MBB = BBToMBB[&BB];
284  assert(MBB && "BasicBlock was not encountered before");
285  return *MBB;
286 }
287 
288 void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
289  assert(NewPred && "new predecessor must be a real MachineBasicBlock");
290  MachinePreds[Edge].push_back(NewPred);
291 }
292 
293 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
294  MachineIRBuilder &MIRBuilder) {
295  // Get or create a virtual register for each value.
296  // Unless the value is a Constant => loadimm cst?
297  // or inline constant each time?
298  // Creation of a virtual register needs to have a size.
299  Register Op0 = getOrCreateVReg(*U.getOperand(0));
300  Register Op1 = getOrCreateVReg(*U.getOperand(1));
301  Register Res = getOrCreateVReg(U);
302  uint16_t Flags = 0;
303  if (isa<Instruction>(U)) {
304  const Instruction &I = cast<Instruction>(U);
306  }
307 
308  MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags);
309  return true;
310 }
311 
312 bool IRTranslator::translateUnaryOp(unsigned Opcode, const User &U,
313  MachineIRBuilder &MIRBuilder) {
314  Register Op0 = getOrCreateVReg(*U.getOperand(0));
315  Register Res = getOrCreateVReg(U);
316  uint16_t Flags = 0;
317  if (isa<Instruction>(U)) {
318  const Instruction &I = cast<Instruction>(U);
320  }
321  MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags);
322  return true;
323 }
324 
325 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
326  return translateUnaryOp(TargetOpcode::G_FNEG, U, MIRBuilder);
327 }
328 
329 bool IRTranslator::translateCompare(const User &U,
330  MachineIRBuilder &MIRBuilder) {
331  auto *CI = dyn_cast<CmpInst>(&U);
332  Register Op0 = getOrCreateVReg(*U.getOperand(0));
333  Register Op1 = getOrCreateVReg(*U.getOperand(1));
334  Register Res = getOrCreateVReg(U);
335  CmpInst::Predicate Pred =
336  CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
337  cast<ConstantExpr>(U).getPredicate());
338  if (CmpInst::isIntPredicate(Pred))
339  MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
340  else if (Pred == CmpInst::FCMP_FALSE)
341  MIRBuilder.buildCopy(
342  Res, getOrCreateVReg(*Constant::getNullValue(U.getType())));
343  else if (Pred == CmpInst::FCMP_TRUE)
344  MIRBuilder.buildCopy(
345  Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType())));
346  else {
347  uint16_t Flags = 0;
348  if (CI)
350  MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, Flags);
351  }
352 
353  return true;
354 }
355 
356 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
357  const ReturnInst &RI = cast<ReturnInst>(U);
358  const Value *Ret = RI.getReturnValue();
359  if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
360  Ret = nullptr;
361 
362  ArrayRef<Register> VRegs;
363  if (Ret)
364  VRegs = getOrCreateVRegs(*Ret);
365 
366  Register SwiftErrorVReg = 0;
367  if (CLI->supportSwiftError() && SwiftError.getFunctionArg()) {
368  SwiftErrorVReg = SwiftError.getOrCreateVRegUseAt(
369  &RI, &MIRBuilder.getMBB(), SwiftError.getFunctionArg());
370  }
371 
372  // The target may mess up with the insertion point, but
373  // this is not important as a return is the last instruction
374  // of the block anyway.
375  return CLI->lowerReturn(MIRBuilder, Ret, VRegs, FuncInfo, SwiftErrorVReg);
376 }
377 
378 void IRTranslator::emitBranchForMergedCondition(
380  MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB,
381  BranchProbability TProb, BranchProbability FProb, bool InvertCond) {
382  // If the leaf of the tree is a comparison, merge the condition into
383  // the caseblock.
384  if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
385  CmpInst::Predicate Condition;
386  if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
387  Condition = InvertCond ? IC->getInversePredicate() : IC->getPredicate();
388  } else {
389  const FCmpInst *FC = cast<FCmpInst>(Cond);
390  Condition = InvertCond ? FC->getInversePredicate() : FC->getPredicate();
391  }
392 
393  SwitchCG::CaseBlock CB(Condition, false, BOp->getOperand(0),
394  BOp->getOperand(1), nullptr, TBB, FBB, CurBB,
395  CurBuilder->getDebugLoc(), TProb, FProb);
396  SL->SwitchCases.push_back(CB);
397  return;
398  }
399 
400  // Create a CaseBlock record representing this branch.
403  Pred, false, Cond, ConstantInt::getTrue(MF->getFunction().getContext()),
404  nullptr, TBB, FBB, CurBB, CurBuilder->getDebugLoc(), TProb, FProb);
405  SL->SwitchCases.push_back(CB);
406 }
407 
408 static bool isValInBlock(const Value *V, const BasicBlock *BB) {
409  if (const Instruction *I = dyn_cast<Instruction>(V))
410  return I->getParent() == BB;
411  return true;
412 }
413 
414 void IRTranslator::findMergedConditions(
416  MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB,
418  BranchProbability FProb, bool InvertCond) {
419  using namespace PatternMatch;
420  assert((Opc == Instruction::And || Opc == Instruction::Or) &&
421  "Expected Opc to be AND/OR");
422  // Skip over not part of the tree and remember to invert op and operands at
423  // next level.
424  Value *NotCond;
425  if (match(Cond, m_OneUse(m_Not(m_Value(NotCond)))) &&
426  isValInBlock(NotCond, CurBB->getBasicBlock())) {
427  findMergedConditions(NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb,
428  !InvertCond);
429  return;
430  }
431 
432  const Instruction *BOp = dyn_cast<Instruction>(Cond);
433  const Value *BOpOp0, *BOpOp1;
434  // Compute the effective opcode for Cond, taking into account whether it needs
435  // to be inverted, e.g.
436  // and (not (or A, B)), C
437  // gets lowered as
438  // and (and (not A, not B), C)
440  if (BOp) {
441  BOpc = match(BOp, m_LogicalAnd(m_Value(BOpOp0), m_Value(BOpOp1)))
442  ? Instruction::And
443  : (match(BOp, m_LogicalOr(m_Value(BOpOp0), m_Value(BOpOp1)))
444  ? Instruction::Or
446  if (InvertCond) {
447  if (BOpc == Instruction::And)
448  BOpc = Instruction::Or;
449  else if (BOpc == Instruction::Or)
450  BOpc = Instruction::And;
451  }
452  }
453 
454  // If this node is not part of the or/and tree, emit it as a branch.
455  // Note that all nodes in the tree should have same opcode.
456  bool BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->hasOneUse();
457  if (!BOpIsInOrAndTree || BOp->getParent() != CurBB->getBasicBlock() ||
458  !isValInBlock(BOpOp0, CurBB->getBasicBlock()) ||
459  !isValInBlock(BOpOp1, CurBB->getBasicBlock())) {
460  emitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB, TProb, FProb,
461  InvertCond);
462  return;
463  }
464 
465  // Create TmpBB after CurBB.
466  MachineFunction::iterator BBI(CurBB);
467  MachineBasicBlock *TmpBB =
468  MF->CreateMachineBasicBlock(CurBB->getBasicBlock());
469  CurBB->getParent()->insert(++BBI, TmpBB);
470 
471  if (Opc == Instruction::Or) {
472  // Codegen X | Y as:
473  // BB1:
474  // jmp_if_X TBB
475  // jmp TmpBB
476  // TmpBB:
477  // jmp_if_Y TBB
478  // jmp FBB
479  //
480 
481  // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
482  // The requirement is that
483  // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
484  // = TrueProb for original BB.
485  // Assuming the original probabilities are A and B, one choice is to set
486  // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
487  // A/(1+B) and 2B/(1+B). This choice assumes that
488  // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
489  // Another choice is to assume TrueProb for BB1 equals to TrueProb for
490  // TmpBB, but the math is more complicated.
491 
492  auto NewTrueProb = TProb / 2;
493  auto NewFalseProb = TProb / 2 + FProb;
494  // Emit the LHS condition.
495  findMergedConditions(BOpOp0, TBB, TmpBB, CurBB, SwitchBB, Opc, NewTrueProb,
496  NewFalseProb, InvertCond);
497 
498  // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
499  SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
500  BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
501  // Emit the RHS condition into TmpBB.
502  findMergedConditions(BOpOp1, TBB, FBB, TmpBB, SwitchBB, Opc, Probs[0],
503  Probs[1], InvertCond);
504  } else {
505  assert(Opc == Instruction::And && "Unknown merge op!");
506  // Codegen X & Y as:
507  // BB1:
508  // jmp_if_X TmpBB
509  // jmp FBB
510  // TmpBB:
511  // jmp_if_Y TBB
512  // jmp FBB
513  //
514  // This requires creation of TmpBB after CurBB.
515 
516  // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
517  // The requirement is that
518  // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
519  // = FalseProb for original BB.
520  // Assuming the original probabilities are A and B, one choice is to set
521  // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
522  // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
523  // TrueProb for BB1 * FalseProb for TmpBB.
524 
525  auto NewTrueProb = TProb + FProb / 2;
526  auto NewFalseProb = FProb / 2;
527  // Emit the LHS condition.
528  findMergedConditions(BOpOp0, TmpBB, FBB, CurBB, SwitchBB, Opc, NewTrueProb,
529  NewFalseProb, InvertCond);
530 
531  // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
532  SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
533  BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
534  // Emit the RHS condition into TmpBB.
535  findMergedConditions(BOpOp1, TBB, FBB, TmpBB, SwitchBB, Opc, Probs[0],
536  Probs[1], InvertCond);
537  }
538 }
539 
540 bool IRTranslator::shouldEmitAsBranches(
541  const std::vector<SwitchCG::CaseBlock> &Cases) {
542  // For multiple cases, it's better to emit as branches.
543  if (Cases.size() != 2)
544  return true;
545 
546  // If this is two comparisons of the same values or'd or and'd together, they
547  // will get folded into a single comparison, so don't emit two blocks.
548  if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
549  Cases[0].CmpRHS == Cases[1].CmpRHS) ||
550  (Cases[0].CmpRHS == Cases[1].CmpLHS &&
551  Cases[0].CmpLHS == Cases[1].CmpRHS)) {
552  return false;
553  }
554 
555  // Handle: (X != null) | (Y != null) --> (X|Y) != 0
556  // Handle: (X == null) & (Y == null) --> (X|Y) == 0
557  if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
558  Cases[0].PredInfo.Pred == Cases[1].PredInfo.Pred &&
559  isa<Constant>(Cases[0].CmpRHS) &&
560  cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
561  if (Cases[0].PredInfo.Pred == CmpInst::ICMP_EQ &&
562  Cases[0].TrueBB == Cases[1].ThisBB)
563  return false;
564  if (Cases[0].PredInfo.Pred == CmpInst::ICMP_NE &&
565  Cases[0].FalseBB == Cases[1].ThisBB)
566  return false;
567  }
568 
569  return true;
570 }
571 
572 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
573  const BranchInst &BrInst = cast<BranchInst>(U);
574  auto &CurMBB = MIRBuilder.getMBB();
575  auto *Succ0MBB = &getMBB(*BrInst.getSuccessor(0));
576 
577  if (BrInst.isUnconditional()) {
578  // If the unconditional target is the layout successor, fallthrough.
579  if (OptLevel == CodeGenOpt::None || !CurMBB.isLayoutSuccessor(Succ0MBB))
580  MIRBuilder.buildBr(*Succ0MBB);
581 
582  // Link successors.
583  for (const BasicBlock *Succ : successors(&BrInst))
584  CurMBB.addSuccessor(&getMBB(*Succ));
585  return true;
586  }
587 
588  // If this condition is one of the special cases we handle, do special stuff
589  // now.
590  const Value *CondVal = BrInst.getCondition();
591  MachineBasicBlock *Succ1MBB = &getMBB(*BrInst.getSuccessor(1));
592 
593  const auto &TLI = *MF->getSubtarget().getTargetLowering();
594 
595  // If this is a series of conditions that are or'd or and'd together, emit
596  // this as a sequence of branches instead of setcc's with and/or operations.
597  // As long as jumps are not expensive (exceptions for multi-use logic ops,
598  // unpredictable branches, and vector extracts because those jumps are likely
599  // expensive for any target), this should improve performance.
600  // For example, instead of something like:
601  // cmp A, B
602  // C = seteq
603  // cmp D, E
604  // F = setle
605  // or C, F
606  // jnz foo
607  // Emit:
608  // cmp A, B
609  // je foo
610  // cmp D, E
611  // jle foo
612  using namespace PatternMatch;
613  const Instruction *CondI = dyn_cast<Instruction>(CondVal);
614  if (!TLI.isJumpExpensive() && CondI && CondI->hasOneUse() &&
615  !BrInst.hasMetadata(LLVMContext::MD_unpredictable)) {
617  Value *Vec;
618  const Value *BOp0, *BOp1;
619  if (match(CondI, m_LogicalAnd(m_Value(BOp0), m_Value(BOp1))))
620  Opcode = Instruction::And;
621  else if (match(CondI, m_LogicalOr(m_Value(BOp0), m_Value(BOp1))))
622  Opcode = Instruction::Or;
623 
624  if (Opcode && !(match(BOp0, m_ExtractElt(m_Value(Vec), m_Value())) &&
625  match(BOp1, m_ExtractElt(m_Specific(Vec), m_Value())))) {
626  findMergedConditions(CondI, Succ0MBB, Succ1MBB, &CurMBB, &CurMBB, Opcode,
627  getEdgeProbability(&CurMBB, Succ0MBB),
628  getEdgeProbability(&CurMBB, Succ1MBB),
629  /*InvertCond=*/false);
630  assert(SL->SwitchCases[0].ThisBB == &CurMBB && "Unexpected lowering!");
631 
632  // Allow some cases to be rejected.
633  if (shouldEmitAsBranches(SL->SwitchCases)) {
634  // Emit the branch for this block.
635  emitSwitchCase(SL->SwitchCases[0], &CurMBB, *CurBuilder);
636  SL->SwitchCases.erase(SL->SwitchCases.begin());
637  return true;
638  }
639 
640  // Okay, we decided not to do this, remove any inserted MBB's and clear
641  // SwitchCases.
642  for (unsigned I = 1, E = SL->SwitchCases.size(); I != E; ++I)
643  MF->erase(SL->SwitchCases[I].ThisBB);
644 
645  SL->SwitchCases.clear();
646  }
647  }
648 
649  // Create a CaseBlock record representing this branch.
650  SwitchCG::CaseBlock CB(CmpInst::ICMP_EQ, false, CondVal,
651  ConstantInt::getTrue(MF->getFunction().getContext()),
652  nullptr, Succ0MBB, Succ1MBB, &CurMBB,
653  CurBuilder->getDebugLoc());
654 
655  // Use emitSwitchCase to actually insert the fast branch sequence for this
656  // cond branch.
657  emitSwitchCase(CB, &CurMBB, *CurBuilder);
658  return true;
659 }
660 
661 void IRTranslator::addSuccessorWithProb(MachineBasicBlock *Src,
662  MachineBasicBlock *Dst,
663  BranchProbability Prob) {
664  if (!FuncInfo.BPI) {
665  Src->addSuccessorWithoutProb(Dst);
666  return;
667  }
668  if (Prob.isUnknown())
669  Prob = getEdgeProbability(Src, Dst);
670  Src->addSuccessor(Dst, Prob);
671 }
672 
674 IRTranslator::getEdgeProbability(const MachineBasicBlock *Src,
675  const MachineBasicBlock *Dst) const {
676  const BasicBlock *SrcBB = Src->getBasicBlock();
677  const BasicBlock *DstBB = Dst->getBasicBlock();
678  if (!FuncInfo.BPI) {
679  // If BPI is not available, set the default probability as 1 / N, where N is
680  // the number of successors.
681  auto SuccSize = std::max<uint32_t>(succ_size(SrcBB), 1);
682  return BranchProbability(1, SuccSize);
683  }
684  return FuncInfo.BPI->getEdgeProbability(SrcBB, DstBB);
685 }
686 
687 bool IRTranslator::translateSwitch(const User &U, MachineIRBuilder &MIB) {
688  using namespace SwitchCG;
689  // Extract cases from the switch.
690  const SwitchInst &SI = cast<SwitchInst>(U);
691  BranchProbabilityInfo *BPI = FuncInfo.BPI;
692  CaseClusterVector Clusters;
693  Clusters.reserve(SI.getNumCases());
694  for (const auto &I : SI.cases()) {
695  MachineBasicBlock *Succ = &getMBB(*I.getCaseSuccessor());
696  assert(Succ && "Could not find successor mbb in mapping");
697  const ConstantInt *CaseVal = I.getCaseValue();
698  BranchProbability Prob =
699  BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex())
700  : BranchProbability(1, SI.getNumCases() + 1);
701  Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob));
702  }
703 
704  MachineBasicBlock *DefaultMBB = &getMBB(*SI.getDefaultDest());
705 
706  // Cluster adjacent cases with the same destination. We do this at all
707  // optimization levels because it's cheap to do and will make codegen faster
708  // if there are many clusters.
709  sortAndRangeify(Clusters);
710 
711  MachineBasicBlock *SwitchMBB = &getMBB(*SI.getParent());
712 
713  // If there is only the default destination, jump there directly.
714  if (Clusters.empty()) {
715  SwitchMBB->addSuccessor(DefaultMBB);
716  if (DefaultMBB != SwitchMBB->getNextNode())
717  MIB.buildBr(*DefaultMBB);
718  return true;
719  }
720 
721  SL->findJumpTables(Clusters, &SI, DefaultMBB, nullptr, nullptr);
722  SL->findBitTestClusters(Clusters, &SI);
723 
724  LLVM_DEBUG({
725  dbgs() << "Case clusters: ";
726  for (const CaseCluster &C : Clusters) {
727  if (C.Kind == CC_JumpTable)
728  dbgs() << "JT:";
729  if (C.Kind == CC_BitTests)
730  dbgs() << "BT:";
731 
732  C.Low->getValue().print(dbgs(), true);
733  if (C.Low != C.High) {
734  dbgs() << '-';
735  C.High->getValue().print(dbgs(), true);
736  }
737  dbgs() << ' ';
738  }
739  dbgs() << '\n';
740  });
741 
742  assert(!Clusters.empty());
743  SwitchWorkList WorkList;
744  CaseClusterIt First = Clusters.begin();
745  CaseClusterIt Last = Clusters.end() - 1;
746  auto DefaultProb = getEdgeProbability(SwitchMBB, DefaultMBB);
747  WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultProb});
748 
749  // FIXME: At the moment we don't do any splitting optimizations here like
750  // SelectionDAG does, so this worklist only has one entry.
751  while (!WorkList.empty()) {
752  SwitchWorkListItem W = WorkList.pop_back_val();
753  if (!lowerSwitchWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB, MIB))
754  return false;
755  }
756  return true;
757 }
758 
759 void IRTranslator::emitJumpTable(SwitchCG::JumpTable &JT,
761  // Emit the code for the jump table
762  assert(JT.Reg != -1U && "Should lower JT Header first!");
763  MachineIRBuilder MIB(*MBB->getParent());
764  MIB.setMBB(*MBB);
765  MIB.setDebugLoc(CurBuilder->getDebugLoc());
766 
767  Type *PtrIRTy = Type::getInt8PtrTy(MF->getFunction().getContext());
768  const LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
769 
770  auto Table = MIB.buildJumpTable(PtrTy, JT.JTI);
771  MIB.buildBrJT(Table.getReg(0), JT.JTI, JT.Reg);
772 }
773 
774 bool IRTranslator::emitJumpTableHeader(SwitchCG::JumpTable &JT,
776  MachineBasicBlock *HeaderBB) {
777  MachineIRBuilder MIB(*HeaderBB->getParent());
778  MIB.setMBB(*HeaderBB);
779  MIB.setDebugLoc(CurBuilder->getDebugLoc());
780 
781  const Value &SValue = *JTH.SValue;
782  // Subtract the lowest switch case value from the value being switched on.
783  const LLT SwitchTy = getLLTForType(*SValue.getType(), *DL);
784  Register SwitchOpReg = getOrCreateVReg(SValue);
785  auto FirstCst = MIB.buildConstant(SwitchTy, JTH.First);
786  auto Sub = MIB.buildSub({SwitchTy}, SwitchOpReg, FirstCst);
787 
788  // This value may be smaller or larger than the target's pointer type, and
789  // therefore require extension or truncating.
790  Type *PtrIRTy = SValue.getType()->getPointerTo();
791  const LLT PtrScalarTy = LLT::scalar(DL->getTypeSizeInBits(PtrIRTy));
792  Sub = MIB.buildZExtOrTrunc(PtrScalarTy, Sub);
793 
794  JT.Reg = Sub.getReg(0);
795 
796  if (JTH.FallthroughUnreachable) {
797  if (JT.MBB != HeaderBB->getNextNode())
798  MIB.buildBr(*JT.MBB);
799  return true;
800  }
801 
802  // Emit the range check for the jump table, and branch to the default block
803  // for the switch statement if the value being switched on exceeds the
804  // largest case in the switch.
805  auto Cst = getOrCreateVReg(
806  *ConstantInt::get(SValue.getType(), JTH.Last - JTH.First));
807  Cst = MIB.buildZExtOrTrunc(PtrScalarTy, Cst).getReg(0);
808  auto Cmp = MIB.buildICmp(CmpInst::ICMP_UGT, LLT::scalar(1), Sub, Cst);
809 
810  auto BrCond = MIB.buildBrCond(Cmp.getReg(0), *JT.Default);
811 
812  // Avoid emitting unnecessary branches to the next block.
813  if (JT.MBB != HeaderBB->getNextNode())
814  BrCond = MIB.buildBr(*JT.MBB);
815  return true;
816 }
817 
818 void IRTranslator::emitSwitchCase(SwitchCG::CaseBlock &CB,
819  MachineBasicBlock *SwitchBB,
820  MachineIRBuilder &MIB) {
821  Register CondLHS = getOrCreateVReg(*CB.CmpLHS);
822  Register Cond;
823  DebugLoc OldDbgLoc = MIB.getDebugLoc();
824  MIB.setDebugLoc(CB.DbgLoc);
825  MIB.setMBB(*CB.ThisBB);
826 
827  if (CB.PredInfo.NoCmp) {
828  // Branch or fall through to TrueBB.
829  addSuccessorWithProb(CB.ThisBB, CB.TrueBB, CB.TrueProb);
830  addMachineCFGPred({SwitchBB->getBasicBlock(), CB.TrueBB->getBasicBlock()},
831  CB.ThisBB);
833  if (CB.TrueBB != CB.ThisBB->getNextNode())
834  MIB.buildBr(*CB.TrueBB);
835  MIB.setDebugLoc(OldDbgLoc);
836  return;
837  }
838 
839  const LLT i1Ty = LLT::scalar(1);
840  // Build the compare.
841  if (!CB.CmpMHS) {
842  const auto *CI = dyn_cast<ConstantInt>(CB.CmpRHS);
843  // For conditional branch lowering, we might try to do something silly like
844  // emit an G_ICMP to compare an existing G_ICMP i1 result with true. If so,
845  // just re-use the existing condition vreg.
846  if (MRI->getType(CondLHS).getSizeInBits() == 1 && CI &&
847  CI->getZExtValue() == 1 && CB.PredInfo.Pred == CmpInst::ICMP_EQ) {
848  Cond = CondLHS;
849  } else {
850  Register CondRHS = getOrCreateVReg(*CB.CmpRHS);
852  Cond =
853  MIB.buildFCmp(CB.PredInfo.Pred, i1Ty, CondLHS, CondRHS).getReg(0);
854  else
855  Cond =
856  MIB.buildICmp(CB.PredInfo.Pred, i1Ty, CondLHS, CondRHS).getReg(0);
857  }
858  } else {
860  "Can only handle SLE ranges");
861 
862  const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
863  const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
864 
865  Register CmpOpReg = getOrCreateVReg(*CB.CmpMHS);
866  if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
867  Register CondRHS = getOrCreateVReg(*CB.CmpRHS);
868  Cond =
869  MIB.buildICmp(CmpInst::ICMP_SLE, i1Ty, CmpOpReg, CondRHS).getReg(0);
870  } else {
871  const LLT CmpTy = MRI->getType(CmpOpReg);
872  auto Sub = MIB.buildSub({CmpTy}, CmpOpReg, CondLHS);
873  auto Diff = MIB.buildConstant(CmpTy, High - Low);
874  Cond = MIB.buildICmp(CmpInst::ICMP_ULE, i1Ty, Sub, Diff).getReg(0);
875  }
876  }
877 
878  // Update successor info
879  addSuccessorWithProb(CB.ThisBB, CB.TrueBB, CB.TrueProb);
880 
881  addMachineCFGPred({SwitchBB->getBasicBlock(), CB.TrueBB->getBasicBlock()},
882  CB.ThisBB);
883 
884  // TrueBB and FalseBB are always different unless the incoming IR is
885  // degenerate. This only happens when running llc on weird IR.
886  if (CB.TrueBB != CB.FalseBB)
887  addSuccessorWithProb(CB.ThisBB, CB.FalseBB, CB.FalseProb);
889 
890  addMachineCFGPred({SwitchBB->getBasicBlock(), CB.FalseBB->getBasicBlock()},
891  CB.ThisBB);
892 
893  MIB.buildBrCond(Cond, *CB.TrueBB);
894  MIB.buildBr(*CB.FalseBB);
895  MIB.setDebugLoc(OldDbgLoc);
896 }
897 
898 bool IRTranslator::lowerJumpTableWorkItem(SwitchCG::SwitchWorkListItem W,
899  MachineBasicBlock *SwitchMBB,
900  MachineBasicBlock *CurMBB,
901  MachineBasicBlock *DefaultMBB,
902  MachineIRBuilder &MIB,
904  BranchProbability UnhandledProbs,
906  MachineBasicBlock *Fallthrough,
907  bool FallthroughUnreachable) {
908  using namespace SwitchCG;
909  MachineFunction *CurMF = SwitchMBB->getParent();
910  // FIXME: Optimize away range check based on pivot comparisons.
911  JumpTableHeader *JTH = &SL->JTCases[I->JTCasesIndex].first;
912  SwitchCG::JumpTable *JT = &SL->JTCases[I->JTCasesIndex].second;
913  BranchProbability DefaultProb = W.DefaultProb;
914 
915  // The jump block hasn't been inserted yet; insert it here.
916  MachineBasicBlock *JumpMBB = JT->MBB;
917  CurMF->insert(BBI, JumpMBB);
918 
919  // Since the jump table block is separate from the switch block, we need
920  // to keep track of it as a machine predecessor to the default block,
921  // otherwise we lose the phi edges.
922  addMachineCFGPred({SwitchMBB->getBasicBlock(), DefaultMBB->getBasicBlock()},
923  CurMBB);
924  addMachineCFGPred({SwitchMBB->getBasicBlock(), DefaultMBB->getBasicBlock()},
925  JumpMBB);
926 
927  auto JumpProb = I->Prob;
928  auto FallthroughProb = UnhandledProbs;
929 
930  // If the default statement is a target of the jump table, we evenly
931  // distribute the default probability to successors of CurMBB. Also
932  // update the probability on the edge from JumpMBB to Fallthrough.
934  SE = JumpMBB->succ_end();
935  SI != SE; ++SI) {
936  if (*SI == DefaultMBB) {
937  JumpProb += DefaultProb / 2;
938  FallthroughProb -= DefaultProb / 2;
939  JumpMBB->setSuccProbability(SI, DefaultProb / 2);
940  JumpMBB->normalizeSuccProbs();
941  } else {
942  // Also record edges from the jump table block to it's successors.
943  addMachineCFGPred({SwitchMBB->getBasicBlock(), (*SI)->getBasicBlock()},
944  JumpMBB);
945  }
946  }
947 
948  if (FallthroughUnreachable)
949  JTH->FallthroughUnreachable = true;
950 
951  if (!JTH->FallthroughUnreachable)
952  addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
953  addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
954  CurMBB->normalizeSuccProbs();
955 
956  // The jump table header will be inserted in our current block, do the
957  // range check, and fall through to our fallthrough block.
958  JTH->HeaderBB = CurMBB;
959  JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
960 
961  // If we're in the right place, emit the jump table header right now.
962  if (CurMBB == SwitchMBB) {
963  if (!emitJumpTableHeader(*JT, *JTH, CurMBB))
964  return false;
965  JTH->Emitted = true;
966  }
967  return true;
968 }
969 bool IRTranslator::lowerSwitchRangeWorkItem(SwitchCG::CaseClusterIt I,
970  Value *Cond,
971  MachineBasicBlock *Fallthrough,
972  bool FallthroughUnreachable,
973  BranchProbability UnhandledProbs,
974  MachineBasicBlock *CurMBB,
975  MachineIRBuilder &MIB,
976  MachineBasicBlock *SwitchMBB) {
977  using namespace SwitchCG;
978  const Value *RHS, *LHS, *MHS;
979  CmpInst::Predicate Pred;
980  if (I->Low == I->High) {
981  // Check Cond == I->Low.
982  Pred = CmpInst::ICMP_EQ;
983  LHS = Cond;
984  RHS = I->Low;
985  MHS = nullptr;
986  } else {
987  // Check I->Low <= Cond <= I->High.
988  Pred = CmpInst::ICMP_SLE;
989  LHS = I->Low;
990  MHS = Cond;
991  RHS = I->High;
992  }
993 
994  // If Fallthrough is unreachable, fold away the comparison.
995  // The false probability is the sum of all unhandled cases.
996  CaseBlock CB(Pred, FallthroughUnreachable, LHS, RHS, MHS, I->MBB, Fallthrough,
997  CurMBB, MIB.getDebugLoc(), I->Prob, UnhandledProbs);
998 
999  emitSwitchCase(CB, SwitchMBB, MIB);
1000  return true;
1001 }
1002 
1003 void IRTranslator::emitBitTestHeader(SwitchCG::BitTestBlock &B,
1004  MachineBasicBlock *SwitchBB) {
1005  MachineIRBuilder &MIB = *CurBuilder;
1006  MIB.setMBB(*SwitchBB);
1007 
1008  // Subtract the minimum value.
1009  Register SwitchOpReg = getOrCreateVReg(*B.SValue);
1010 
1011  LLT SwitchOpTy = MRI->getType(SwitchOpReg);
1012  Register MinValReg = MIB.buildConstant(SwitchOpTy, B.First).getReg(0);
1013  auto RangeSub = MIB.buildSub(SwitchOpTy, SwitchOpReg, MinValReg);
1014 
1015  Type *PtrIRTy = Type::getInt8PtrTy(MF->getFunction().getContext());
1016  const LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
1017 
1018  LLT MaskTy = SwitchOpTy;
1019  if (MaskTy.getSizeInBits() > PtrTy.getSizeInBits() ||
1020  !isPowerOf2_32(MaskTy.getSizeInBits()))
1021  MaskTy = LLT::scalar(PtrTy.getSizeInBits());
1022  else {
1023  // Ensure that the type will fit the mask value.
1024  for (unsigned I = 0, E = B.Cases.size(); I != E; ++I) {
1025  if (!isUIntN(SwitchOpTy.getSizeInBits(), B.Cases[I].Mask)) {
1026  // Switch table case range are encoded into series of masks.
1027  // Just use pointer type, it's guaranteed to fit.
1028  MaskTy = LLT::scalar(PtrTy.getSizeInBits());
1029  break;
1030  }
1031  }
1032  }
1033  Register SubReg = RangeSub.getReg(0);
1034  if (SwitchOpTy != MaskTy)
1035  SubReg = MIB.buildZExtOrTrunc(MaskTy, SubReg).getReg(0);
1036 
1037  B.RegVT = getMVTForLLT(MaskTy);
1038  B.Reg = SubReg;
1039 
1040  MachineBasicBlock *MBB = B.Cases[0].ThisBB;
1041 
1042  if (!B.FallthroughUnreachable)
1043  addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
1044  addSuccessorWithProb(SwitchBB, MBB, B.Prob);
1045 
1046  SwitchBB->normalizeSuccProbs();
1047 
1048  if (!B.FallthroughUnreachable) {
1049  // Conditional branch to the default block.
1050  auto RangeCst = MIB.buildConstant(SwitchOpTy, B.Range);
1051  auto RangeCmp = MIB.buildICmp(CmpInst::Predicate::ICMP_UGT, LLT::scalar(1),
1052  RangeSub, RangeCst);
1053  MIB.buildBrCond(RangeCmp, *B.Default);
1054  }
1055 
1056  // Avoid emitting unnecessary branches to the next block.
1057  if (MBB != SwitchBB->getNextNode())
1058  MIB.buildBr(*MBB);
1059 }
1060 
1061 void IRTranslator::emitBitTestCase(SwitchCG::BitTestBlock &BB,
1062  MachineBasicBlock *NextMBB,
1063  BranchProbability BranchProbToNext,
1065  MachineBasicBlock *SwitchBB) {
1066  MachineIRBuilder &MIB = *CurBuilder;
1067  MIB.setMBB(*SwitchBB);
1068 
1069  LLT SwitchTy = getLLTForMVT(BB.RegVT);
1070  Register Cmp;
1071  unsigned PopCount = countPopulation(B.Mask);
1072  if (PopCount == 1) {
1073  // Testing for a single bit; just compare the shift count with what it
1074  // would need to be to shift a 1 bit in that position.
1075  auto MaskTrailingZeros =
1076  MIB.buildConstant(SwitchTy, countTrailingZeros(B.Mask));
1077  Cmp =
1078  MIB.buildICmp(ICmpInst::ICMP_EQ, LLT::scalar(1), Reg, MaskTrailingZeros)
1079  .getReg(0);
1080  } else if (PopCount == BB.Range) {
1081  // There is only one zero bit in the range, test for it directly.
1082  auto MaskTrailingOnes =
1083  MIB.buildConstant(SwitchTy, countTrailingOnes(B.Mask));
1084  Cmp = MIB.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), Reg, MaskTrailingOnes)
1085  .getReg(0);
1086  } else {
1087  // Make desired shift.
1088  auto CstOne = MIB.buildConstant(SwitchTy, 1);
1089  auto SwitchVal = MIB.buildShl(SwitchTy, CstOne, Reg);
1090 
1091  // Emit bit tests and jumps.
1092  auto CstMask = MIB.buildConstant(SwitchTy, B.Mask);
1093  auto AndOp = MIB.buildAnd(SwitchTy, SwitchVal, CstMask);
1094  auto CstZero = MIB.buildConstant(SwitchTy, 0);
1095  Cmp = MIB.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), AndOp, CstZero)
1096  .getReg(0);
1097  }
1098 
1099  // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
1100  addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
1101  // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
1102  addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
1103  // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
1104  // one as they are relative probabilities (and thus work more like weights),
1105  // and hence we need to normalize them to let the sum of them become one.
1106  SwitchBB->normalizeSuccProbs();
1107 
1108  // Record the fact that the IR edge from the header to the bit test target
1109  // will go through our new block. Neeeded for PHIs to have nodes added.
1110  addMachineCFGPred({BB.Parent->getBasicBlock(), B.TargetBB->getBasicBlock()},
1111  SwitchBB);
1112 
1113  MIB.buildBrCond(Cmp, *B.TargetBB);
1114 
1115  // Avoid emitting unnecessary branches to the next block.
1116  if (NextMBB != SwitchBB->getNextNode())
1117  MIB.buildBr(*NextMBB);
1118 }
1119 
1120 bool IRTranslator::lowerBitTestWorkItem(
1122  MachineBasicBlock *CurMBB, MachineBasicBlock *DefaultMBB,
1124  BranchProbability DefaultProb, BranchProbability UnhandledProbs,
1126  bool FallthroughUnreachable) {
1127  using namespace SwitchCG;
1128  MachineFunction *CurMF = SwitchMBB->getParent();
1129  // FIXME: Optimize away range check based on pivot comparisons.
1130  BitTestBlock *BTB = &SL->BitTestCases[I->BTCasesIndex];
1131  // The bit test blocks haven't been inserted yet; insert them here.
1132  for (BitTestCase &BTC : BTB->Cases)
1133  CurMF->insert(BBI, BTC.ThisBB);
1134 
1135  // Fill in fields of the BitTestBlock.
1136  BTB->Parent = CurMBB;
1137  BTB->Default = Fallthrough;
1138 
1139  BTB->DefaultProb = UnhandledProbs;
1140  // If the cases in bit test don't form a contiguous range, we evenly
1141  // distribute the probability on the edge to Fallthrough to two
1142  // successors of CurMBB.
1143  if (!BTB->ContiguousRange) {
1144  BTB->Prob += DefaultProb / 2;
1145  BTB->DefaultProb -= DefaultProb / 2;
1146  }
1147 
1148  if (FallthroughUnreachable)
1149  BTB->FallthroughUnreachable = true;
1150 
1151  // If we're in the right place, emit the bit test header right now.
1152  if (CurMBB == SwitchMBB) {
1153  emitBitTestHeader(*BTB, SwitchMBB);
1154  BTB->Emitted = true;
1155  }
1156  return true;
1157 }
1158 
1159 bool IRTranslator::lowerSwitchWorkItem(SwitchCG::SwitchWorkListItem W,
1160  Value *Cond,
1161  MachineBasicBlock *SwitchMBB,
1162  MachineBasicBlock *DefaultMBB,
1163  MachineIRBuilder &MIB) {
1164  using namespace SwitchCG;
1165  MachineFunction *CurMF = FuncInfo.MF;
1166  MachineBasicBlock *NextMBB = nullptr;
1167  MachineFunction::iterator BBI(W.MBB);
1168  if (++BBI != FuncInfo.MF->end())
1169  NextMBB = &*BBI;
1170 
1171  if (EnableOpts) {
1172  // Here, we order cases by probability so the most likely case will be
1173  // checked first. However, two clusters can have the same probability in
1174  // which case their relative ordering is non-deterministic. So we use Low
1175  // as a tie-breaker as clusters are guaranteed to never overlap.
1176  llvm::sort(W.FirstCluster, W.LastCluster + 1,
1177  [](const CaseCluster &a, const CaseCluster &b) {
1178  return a.Prob != b.Prob
1179  ? a.Prob > b.Prob
1180  : a.Low->getValue().slt(b.Low->getValue());
1181  });
1182 
1183  // Rearrange the case blocks so that the last one falls through if possible
1184  // without changing the order of probabilities.
1185  for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster;) {
1186  --I;
1187  if (I->Prob > W.LastCluster->Prob)
1188  break;
1189  if (I->Kind == CC_Range && I->MBB == NextMBB) {
1190  std::swap(*I, *W.LastCluster);
1191  break;
1192  }
1193  }
1194  }
1195 
1196  // Compute total probability.
1197  BranchProbability DefaultProb = W.DefaultProb;
1198  BranchProbability UnhandledProbs = DefaultProb;
1199  for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
1200  UnhandledProbs += I->Prob;
1201 
1202  MachineBasicBlock *CurMBB = W.MBB;
1203  for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
1204  bool FallthroughUnreachable = false;
1205  MachineBasicBlock *Fallthrough;
1206  if (I == W.LastCluster) {
1207  // For the last cluster, fall through to the default destination.
1208  Fallthrough = DefaultMBB;
1209  FallthroughUnreachable = isa<UnreachableInst>(
1210  DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg());
1211  } else {
1212  Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
1213  CurMF->insert(BBI, Fallthrough);
1214  }
1215  UnhandledProbs -= I->Prob;
1216 
1217  switch (I->Kind) {
1218  case CC_BitTests: {
1219  if (!lowerBitTestWorkItem(W, SwitchMBB, CurMBB, DefaultMBB, MIB, BBI,
1220  DefaultProb, UnhandledProbs, I, Fallthrough,
1221  FallthroughUnreachable)) {
1222  LLVM_DEBUG(dbgs() << "Failed to lower bit test for switch");
1223  return false;
1224  }
1225  break;
1226  }
1227 
1228  case CC_JumpTable: {
1229  if (!lowerJumpTableWorkItem(W, SwitchMBB, CurMBB, DefaultMBB, MIB, BBI,
1230  UnhandledProbs, I, Fallthrough,
1231  FallthroughUnreachable)) {
1232  LLVM_DEBUG(dbgs() << "Failed to lower jump table");
1233  return false;
1234  }
1235  break;
1236  }
1237  case CC_Range: {
1238  if (!lowerSwitchRangeWorkItem(I, Cond, Fallthrough,
1239  FallthroughUnreachable, UnhandledProbs,
1240  CurMBB, MIB, SwitchMBB)) {
1241  LLVM_DEBUG(dbgs() << "Failed to lower switch range");
1242  return false;
1243  }
1244  break;
1245  }
1246  }
1247  CurMBB = Fallthrough;
1248  }
1249 
1250  return true;
1251 }
1252 
1253 bool IRTranslator::translateIndirectBr(const User &U,
1254  MachineIRBuilder &MIRBuilder) {
1255  const IndirectBrInst &BrInst = cast<IndirectBrInst>(U);
1256 
1257  const Register Tgt = getOrCreateVReg(*BrInst.getAddress());
1258  MIRBuilder.buildBrIndirect(Tgt);
1259 
1260  // Link successors.
1261  SmallPtrSet<const BasicBlock *, 32> AddedSuccessors;
1262  MachineBasicBlock &CurBB = MIRBuilder.getMBB();
1263  for (const BasicBlock *Succ : successors(&BrInst)) {
1264  // It's legal for indirectbr instructions to have duplicate blocks in the
1265  // destination list. We don't allow this in MIR. Skip anything that's
1266  // already a successor.
1267  if (!AddedSuccessors.insert(Succ).second)
1268  continue;
1269  CurBB.addSuccessor(&getMBB(*Succ));
1270  }
1271 
1272  return true;
1273 }
1274 
1275 static bool isSwiftError(const Value *V) {
1276  if (auto Arg = dyn_cast<Argument>(V))
1277  return Arg->hasSwiftErrorAttr();
1278  if (auto AI = dyn_cast<AllocaInst>(V))
1279  return AI->isSwiftError();
1280  return false;
1281 }
1282 
1283 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
1284  const LoadInst &LI = cast<LoadInst>(U);
1285 
1286  unsigned StoreSize = DL->getTypeStoreSize(LI.getType());
1287  if (StoreSize == 0)
1288  return true;
1289 
1290  ArrayRef<Register> Regs = getOrCreateVRegs(LI);
1291  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(LI);
1292  Register Base = getOrCreateVReg(*LI.getPointerOperand());
1293  AAMDNodes AAInfo = LI.getAAMetadata();
1294 
1295  const Value *Ptr = LI.getPointerOperand();
1296  Type *OffsetIRTy = DL->getIntPtrType(Ptr->getType());
1297  LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
1298 
1299  if (CLI->supportSwiftError() && isSwiftError(Ptr)) {
1300  assert(Regs.size() == 1 && "swifterror should be single pointer");
1301  Register VReg =
1302  SwiftError.getOrCreateVRegUseAt(&LI, &MIRBuilder.getMBB(), Ptr);
1303  MIRBuilder.buildCopy(Regs[0], VReg);
1304  return true;
1305  }
1306 
1307  auto &TLI = *MF->getSubtarget().getTargetLowering();
1308  MachineMemOperand::Flags Flags = TLI.getLoadMemOperandFlags(LI, *DL);
1309  if (AA && !(Flags & MachineMemOperand::MOInvariant)) {
1310  if (AA->pointsToConstantMemory(
1311  MemoryLocation(Ptr, LocationSize::precise(StoreSize), AAInfo))) {
1313  }
1314  }
1315 
1316  if (!(Flags & MachineMemOperand::MODereferenceable)) {
1318  *DL, &LI, AC, nullptr, LibInfo))
1320  }
1321 
1322  const MDNode *Ranges =
1323  Regs.size() == 1 ? LI.getMetadata(LLVMContext::MD_range) : nullptr;
1324  for (unsigned i = 0; i < Regs.size(); ++i) {
1325  Register Addr;
1326  MIRBuilder.materializePtrAdd(Addr, Base, OffsetTy, Offsets[i] / 8);
1327 
1329  Align BaseAlign = getMemOpAlign(LI);
1330  auto MMO = MF->getMachineMemOperand(
1331  Ptr, Flags, MRI->getType(Regs[i]),
1332  commonAlignment(BaseAlign, Offsets[i] / 8), AAInfo, Ranges,
1333  LI.getSyncScopeID(), LI.getOrdering());
1334  MIRBuilder.buildLoad(Regs[i], Addr, *MMO);
1335  }
1336 
1337  return true;
1338 }
1339 
1340 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
1341  const StoreInst &SI = cast<StoreInst>(U);
1342  if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
1343  return true;
1344 
1345  ArrayRef<Register> Vals = getOrCreateVRegs(*SI.getValueOperand());
1346  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*SI.getValueOperand());
1347  Register Base = getOrCreateVReg(*SI.getPointerOperand());
1348 
1349  Type *OffsetIRTy = DL->getIntPtrType(SI.getPointerOperandType());
1350  LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
1351 
1352  if (CLI->supportSwiftError() && isSwiftError(SI.getPointerOperand())) {
1353  assert(Vals.size() == 1 && "swifterror should be single pointer");
1354 
1355  Register VReg = SwiftError.getOrCreateVRegDefAt(&SI, &MIRBuilder.getMBB(),
1356  SI.getPointerOperand());
1357  MIRBuilder.buildCopy(VReg, Vals[0]);
1358  return true;
1359  }
1360 
1361  auto &TLI = *MF->getSubtarget().getTargetLowering();
1363 
1364  for (unsigned i = 0; i < Vals.size(); ++i) {
1365  Register Addr;
1366  MIRBuilder.materializePtrAdd(Addr, Base, OffsetTy, Offsets[i] / 8);
1367 
1368  MachinePointerInfo Ptr(SI.getPointerOperand(), Offsets[i] / 8);
1369  Align BaseAlign = getMemOpAlign(SI);
1370  auto MMO = MF->getMachineMemOperand(
1371  Ptr, Flags, MRI->getType(Vals[i]),
1372  commonAlignment(BaseAlign, Offsets[i] / 8), SI.getAAMetadata(), nullptr,
1373  SI.getSyncScopeID(), SI.getOrdering());
1374  MIRBuilder.buildStore(Vals[i], Addr, *MMO);
1375  }
1376  return true;
1377 }
1378 
1379 static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL) {
1380  const Value *Src = U.getOperand(0);
1382 
1383  // getIndexedOffsetInType is designed for GEPs, so the first index is the
1384  // usual array element rather than looking into the actual aggregate.
1385  SmallVector<Value *, 1> Indices;
1386  Indices.push_back(ConstantInt::get(Int32Ty, 0));
1387 
1388  if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
1389  for (auto Idx : EVI->indices())
1390  Indices.push_back(ConstantInt::get(Int32Ty, Idx));
1391  } else if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
1392  for (auto Idx : IVI->indices())
1393  Indices.push_back(ConstantInt::get(Int32Ty, Idx));
1394  } else {
1395  for (unsigned i = 1; i < U.getNumOperands(); ++i)
1396  Indices.push_back(U.getOperand(i));
1397  }
1398 
1399  return 8 * static_cast<uint64_t>(
1400  DL.getIndexedOffsetInType(Src->getType(), Indices));
1401 }
1402 
1403 bool IRTranslator::translateExtractValue(const User &U,
1404  MachineIRBuilder &MIRBuilder) {
1405  const Value *Src = U.getOperand(0);
1407  ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src);
1408  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*Src);
1409  unsigned Idx = llvm::lower_bound(Offsets, Offset) - Offsets.begin();
1410  auto &DstRegs = allocateVRegs(U);
1411 
1412  for (unsigned i = 0; i < DstRegs.size(); ++i)
1413  DstRegs[i] = SrcRegs[Idx++];
1414 
1415  return true;
1416 }
1417 
1418 bool IRTranslator::translateInsertValue(const User &U,
1419  MachineIRBuilder &MIRBuilder) {
1420  const Value *Src = U.getOperand(0);
1422  auto &DstRegs = allocateVRegs(U);
1423  ArrayRef<uint64_t> DstOffsets = *VMap.getOffsets(U);
1424  ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src);
1425  ArrayRef<Register> InsertedRegs = getOrCreateVRegs(*U.getOperand(1));
1426  auto *InsertedIt = InsertedRegs.begin();
1427 
1428  for (unsigned i = 0; i < DstRegs.size(); ++i) {
1429  if (DstOffsets[i] >= Offset && InsertedIt != InsertedRegs.end())
1430  DstRegs[i] = *InsertedIt++;
1431  else
1432  DstRegs[i] = SrcRegs[i];
1433  }
1434 
1435  return true;
1436 }
1437 
1438 bool IRTranslator::translateSelect(const User &U,
1439  MachineIRBuilder &MIRBuilder) {
1440  Register Tst = getOrCreateVReg(*U.getOperand(0));
1441  ArrayRef<Register> ResRegs = getOrCreateVRegs(U);
1442  ArrayRef<Register> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
1443  ArrayRef<Register> Op1Regs = getOrCreateVRegs(*U.getOperand(2));
1444 
1445  uint16_t Flags = 0;
1446  if (const SelectInst *SI = dyn_cast<SelectInst>(&U))
1448 
1449  for (unsigned i = 0; i < ResRegs.size(); ++i) {
1450  MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags);
1451  }
1452 
1453  return true;
1454 }
1455 
1456 bool IRTranslator::translateCopy(const User &U, const Value &V,
1457  MachineIRBuilder &MIRBuilder) {
1458  Register Src = getOrCreateVReg(V);
1459  auto &Regs = *VMap.getVRegs(U);
1460  if (Regs.empty()) {
1461  Regs.push_back(Src);
1462  VMap.getOffsets(U)->push_back(0);
1463  } else {
1464  // If we already assigned a vreg for this instruction, we can't change that.
1465  // Emit a copy to satisfy the users we already emitted.
1466  MIRBuilder.buildCopy(Regs[0], Src);
1467  }
1468  return true;
1469 }
1470 
1471 bool IRTranslator::translateBitCast(const User &U,
1472  MachineIRBuilder &MIRBuilder) {
1473  // If we're bitcasting to the source type, we can reuse the source vreg.
1474  if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
1475  getLLTForType(*U.getType(), *DL))
1476  return translateCopy(U, *U.getOperand(0), MIRBuilder);
1477 
1478  return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
1479 }
1480 
1481 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
1482  MachineIRBuilder &MIRBuilder) {
1483  Register Op = getOrCreateVReg(*U.getOperand(0));
1484  Register Res = getOrCreateVReg(U);
1485  MIRBuilder.buildInstr(Opcode, {Res}, {Op});
1486  return true;
1487 }
1488 
1489 bool IRTranslator::translateGetElementPtr(const User &U,
1490  MachineIRBuilder &MIRBuilder) {
1491  Value &Op0 = *U.getOperand(0);
1492  Register BaseReg = getOrCreateVReg(Op0);
1493  Type *PtrIRTy = Op0.getType();
1494  LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
1495  Type *OffsetIRTy = DL->getIntPtrType(PtrIRTy);
1496  LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
1497 
1498  // Normalize Vector GEP - all scalar operands should be converted to the
1499  // splat vector.
1500  unsigned VectorWidth = 0;
1501 
1502  // True if we should use a splat vector; using VectorWidth alone is not
1503  // sufficient.
1504  bool WantSplatVector = false;
1505  if (auto *VT = dyn_cast<VectorType>(U.getType())) {
1506  VectorWidth = cast<FixedVectorType>(VT)->getNumElements();
1507  // We don't produce 1 x N vectors; those are treated as scalars.
1508  WantSplatVector = VectorWidth > 1;
1509  }
1510 
1511  // We might need to splat the base pointer into a vector if the offsets
1512  // are vectors.
1513  if (WantSplatVector && !PtrTy.isVector()) {
1514  BaseReg =
1515  MIRBuilder
1516  .buildSplatVector(LLT::fixed_vector(VectorWidth, PtrTy), BaseReg)
1517  .getReg(0);
1518  PtrIRTy = FixedVectorType::get(PtrIRTy, VectorWidth);
1519  PtrTy = getLLTForType(*PtrIRTy, *DL);
1520  OffsetIRTy = DL->getIntPtrType(PtrIRTy);
1521  OffsetTy = getLLTForType(*OffsetIRTy, *DL);
1522  }
1523 
1524  int64_t Offset = 0;
1525  for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
1526  GTI != E; ++GTI) {
1527  const Value *Idx = GTI.getOperand();
1528  if (StructType *StTy = GTI.getStructTypeOrNull()) {
1529  unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
1531  continue;
1532  } else {
1533  uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
1534 
1535  // If this is a scalar constant or a splat vector of constants,
1536  // handle it quickly.
1537  if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
1538  Offset += ElementSize * CI->getSExtValue();
1539  continue;
1540  }
1541 
1542  if (Offset != 0) {
1543  auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
1544  BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, OffsetMIB.getReg(0))
1545  .getReg(0);
1546  Offset = 0;
1547  }
1548 
1549  Register IdxReg = getOrCreateVReg(*Idx);
1550  LLT IdxTy = MRI->getType(IdxReg);
1551  if (IdxTy != OffsetTy) {
1552  if (!IdxTy.isVector() && WantSplatVector) {
1553  IdxReg = MIRBuilder.buildSplatVector(
1554  OffsetTy.changeElementType(IdxTy), IdxReg).getReg(0);
1555  }
1556 
1557  IdxReg = MIRBuilder.buildSExtOrTrunc(OffsetTy, IdxReg).getReg(0);
1558  }
1559 
1560  // N = N + Idx * ElementSize;
1561  // Avoid doing it for ElementSize of 1.
1562  Register GepOffsetReg;
1563  if (ElementSize != 1) {
1564  auto ElementSizeMIB = MIRBuilder.buildConstant(
1565  getLLTForType(*OffsetIRTy, *DL), ElementSize);
1566  GepOffsetReg =
1567  MIRBuilder.buildMul(OffsetTy, IdxReg, ElementSizeMIB).getReg(0);
1568  } else
1569  GepOffsetReg = IdxReg;
1570 
1571  BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0);
1572  }
1573  }
1574 
1575  if (Offset != 0) {
1576  auto OffsetMIB =
1577  MIRBuilder.buildConstant(OffsetTy, Offset);
1578  MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0));
1579  return true;
1580  }
1581 
1582  MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
1583  return true;
1584 }
1585 
1586 bool IRTranslator::translateMemFunc(const CallInst &CI,
1587  MachineIRBuilder &MIRBuilder,
1588  unsigned Opcode) {
1589  const Value *SrcPtr = CI.getArgOperand(1);
1590  // If the source is undef, then just emit a nop.
1591  if (isa<UndefValue>(SrcPtr))
1592  return true;
1593 
1594  SmallVector<Register, 3> SrcRegs;
1595 
1596  unsigned MinPtrSize = UINT_MAX;
1597  for (auto AI = CI.arg_begin(), AE = CI.arg_end(); std::next(AI) != AE; ++AI) {
1598  Register SrcReg = getOrCreateVReg(**AI);
1599  LLT SrcTy = MRI->getType(SrcReg);
1600  if (SrcTy.isPointer())
1601  MinPtrSize = std::min<unsigned>(SrcTy.getSizeInBits(), MinPtrSize);
1602  SrcRegs.push_back(SrcReg);
1603  }
1604 
1605  LLT SizeTy = LLT::scalar(MinPtrSize);
1606 
1607  // The size operand should be the minimum of the pointer sizes.
1608  Register &SizeOpReg = SrcRegs[SrcRegs.size() - 1];
1609  if (MRI->getType(SizeOpReg) != SizeTy)
1610  SizeOpReg = MIRBuilder.buildZExtOrTrunc(SizeTy, SizeOpReg).getReg(0);
1611 
1612  auto ICall = MIRBuilder.buildInstr(Opcode);
1613  for (Register SrcReg : SrcRegs)
1614  ICall.addUse(SrcReg);
1615 
1616  Align DstAlign;
1617  Align SrcAlign;
1618  unsigned IsVol =
1619  cast<ConstantInt>(CI.getArgOperand(CI.arg_size() - 1))->getZExtValue();
1620 
1621  ConstantInt *CopySize = nullptr;
1622 
1623  if (auto *MCI = dyn_cast<MemCpyInst>(&CI)) {
1624  DstAlign = MCI->getDestAlign().valueOrOne();
1625  SrcAlign = MCI->getSourceAlign().valueOrOne();
1626  CopySize = dyn_cast<ConstantInt>(MCI->getArgOperand(2));
1627  } else if (auto *MCI = dyn_cast<MemCpyInlineInst>(&CI)) {
1628  DstAlign = MCI->getDestAlign().valueOrOne();
1629  SrcAlign = MCI->getSourceAlign().valueOrOne();
1630  CopySize = dyn_cast<ConstantInt>(MCI->getArgOperand(2));
1631  } else if (auto *MMI = dyn_cast<MemMoveInst>(&CI)) {
1632  DstAlign = MMI->getDestAlign().valueOrOne();
1633  SrcAlign = MMI->getSourceAlign().valueOrOne();
1634  CopySize = dyn_cast<ConstantInt>(MMI->getArgOperand(2));
1635  } else {
1636  auto *MSI = cast<MemSetInst>(&CI);
1637  DstAlign = MSI->getDestAlign().valueOrOne();
1638  }
1639 
1640  if (Opcode != TargetOpcode::G_MEMCPY_INLINE) {
1641  // We need to propagate the tail call flag from the IR inst as an argument.
1642  // Otherwise, we have to pessimize and assume later that we cannot tail call
1643  // any memory intrinsics.
1644  ICall.addImm(CI.isTailCall() ? 1 : 0);
1645  }
1646 
1647  // Create mem operands to store the alignment and volatile info.
1650  if (IsVol) {
1651  LoadFlags |= MachineMemOperand::MOVolatile;
1652  StoreFlags |= MachineMemOperand::MOVolatile;
1653  }
1654 
1655  AAMDNodes AAInfo = CI.getAAMetadata();
1656  if (AA && CopySize &&
1657  AA->pointsToConstantMemory(MemoryLocation(
1658  SrcPtr, LocationSize::precise(CopySize->getZExtValue()), AAInfo))) {
1659  LoadFlags |= MachineMemOperand::MOInvariant;
1660 
1661  // FIXME: pointsToConstantMemory probably does not imply dereferenceable,
1662  // but the previous usage implied it did. Probably should check
1663  // isDereferenceableAndAlignedPointer.
1665  }
1666 
1667  ICall.addMemOperand(
1669  StoreFlags, 1, DstAlign, AAInfo));
1670  if (Opcode != TargetOpcode::G_MEMSET)
1671  ICall.addMemOperand(MF->getMachineMemOperand(
1672  MachinePointerInfo(SrcPtr), LoadFlags, 1, SrcAlign, AAInfo));
1673 
1674  return true;
1675 }
1676 
1677 void IRTranslator::getStackGuard(Register DstReg,
1678  MachineIRBuilder &MIRBuilder) {
1680  MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
1681  auto MIB =
1682  MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {});
1683 
1684  auto &TLI = *MF->getSubtarget().getTargetLowering();
1685  Value *Global = TLI.getSDagStackGuard(*MF->getFunction().getParent());
1686  if (!Global)
1687  return;
1688 
1689  unsigned AddrSpace = Global->getType()->getPointerAddressSpace();
1690  LLT PtrTy = LLT::pointer(AddrSpace, DL->getPointerSizeInBits(AddrSpace));
1691 
1692  MachinePointerInfo MPInfo(Global);
1696  MPInfo, Flags, PtrTy, DL->getPointerABIAlignment(AddrSpace));
1697  MIB.setMemRefs({MemRef});
1698 }
1699 
1700 bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
1701  MachineIRBuilder &MIRBuilder) {
1702  ArrayRef<Register> ResRegs = getOrCreateVRegs(CI);
1703  MIRBuilder.buildInstr(
1704  Op, {ResRegs[0], ResRegs[1]},
1705  {getOrCreateVReg(*CI.getOperand(0)), getOrCreateVReg(*CI.getOperand(1))});
1706 
1707  return true;
1708 }
1709 
1710 bool IRTranslator::translateFixedPointIntrinsic(unsigned Op, const CallInst &CI,
1711  MachineIRBuilder &MIRBuilder) {
1712  Register Dst = getOrCreateVReg(CI);
1713  Register Src0 = getOrCreateVReg(*CI.getOperand(0));
1714  Register Src1 = getOrCreateVReg(*CI.getOperand(1));
1715  uint64_t Scale = cast<ConstantInt>(CI.getOperand(2))->getZExtValue();
1716  MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale });
1717  return true;
1718 }
1719 
1720 unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
1721  switch (ID) {
1722  default:
1723  break;
1724  case Intrinsic::bswap:
1725  return TargetOpcode::G_BSWAP;
1726  case Intrinsic::bitreverse:
1727  return TargetOpcode::G_BITREVERSE;
1728  case Intrinsic::fshl:
1729  return TargetOpcode::G_FSHL;
1730  case Intrinsic::fshr:
1731  return TargetOpcode::G_FSHR;
1732  case Intrinsic::ceil:
1733  return TargetOpcode::G_FCEIL;
1734  case Intrinsic::cos:
1735  return TargetOpcode::G_FCOS;
1736  case Intrinsic::ctpop:
1737  return TargetOpcode::G_CTPOP;
1738  case Intrinsic::exp:
1739  return TargetOpcode::G_FEXP;
1740  case Intrinsic::exp2:
1741  return TargetOpcode::G_FEXP2;
1742  case Intrinsic::fabs:
1743  return TargetOpcode::G_FABS;
1744  case Intrinsic::copysign:
1745  return TargetOpcode::G_FCOPYSIGN;
1746  case Intrinsic::minnum:
1747  return TargetOpcode::G_FMINNUM;
1748  case Intrinsic::maxnum:
1749  return TargetOpcode::G_FMAXNUM;
1750  case Intrinsic::minimum:
1751  return TargetOpcode::G_FMINIMUM;
1752  case Intrinsic::maximum:
1753  return TargetOpcode::G_FMAXIMUM;
1754  case Intrinsic::canonicalize:
1755  return TargetOpcode::G_FCANONICALIZE;
1756  case Intrinsic::floor:
1757  return TargetOpcode::G_FFLOOR;
1758  case Intrinsic::fma:
1759  return TargetOpcode::G_FMA;
1760  case Intrinsic::log:
1761  return TargetOpcode::G_FLOG;
1762  case Intrinsic::log2:
1763  return TargetOpcode::G_FLOG2;
1764  case Intrinsic::log10:
1765  return TargetOpcode::G_FLOG10;
1766  case Intrinsic::nearbyint:
1767  return TargetOpcode::G_FNEARBYINT;
1768  case Intrinsic::pow:
1769  return TargetOpcode::G_FPOW;
1770  case Intrinsic::powi:
1771  return TargetOpcode::G_FPOWI;
1772  case Intrinsic::rint:
1773  return TargetOpcode::G_FRINT;
1774  case Intrinsic::round:
1775  return TargetOpcode::G_INTRINSIC_ROUND;
1776  case Intrinsic::roundeven:
1777  return TargetOpcode::G_INTRINSIC_ROUNDEVEN;
1778  case Intrinsic::sin:
1779  return TargetOpcode::G_FSIN;
1780  case Intrinsic::sqrt:
1781  return TargetOpcode::G_FSQRT;
1782  case Intrinsic::trunc:
1783  return TargetOpcode::G_INTRINSIC_TRUNC;
1784  case Intrinsic::readcyclecounter:
1785  return TargetOpcode::G_READCYCLECOUNTER;
1786  case Intrinsic::ptrmask:
1787  return TargetOpcode::G_PTRMASK;
1788  case Intrinsic::lrint:
1789  return TargetOpcode::G_INTRINSIC_LRINT;
1790  // FADD/FMUL require checking the FMF, so are handled elsewhere.
1791  case Intrinsic::vector_reduce_fmin:
1792  return TargetOpcode::G_VECREDUCE_FMIN;
1793  case Intrinsic::vector_reduce_fmax:
1794  return TargetOpcode::G_VECREDUCE_FMAX;
1795  case Intrinsic::vector_reduce_add:
1796  return TargetOpcode::G_VECREDUCE_ADD;
1797  case Intrinsic::vector_reduce_mul:
1798  return TargetOpcode::G_VECREDUCE_MUL;
1799  case Intrinsic::vector_reduce_and:
1800  return TargetOpcode::G_VECREDUCE_AND;
1801  case Intrinsic::vector_reduce_or:
1802  return TargetOpcode::G_VECREDUCE_OR;
1803  case Intrinsic::vector_reduce_xor:
1804  return TargetOpcode::G_VECREDUCE_XOR;
1805  case Intrinsic::vector_reduce_smax:
1806  return TargetOpcode::G_VECREDUCE_SMAX;
1807  case Intrinsic::vector_reduce_smin:
1808  return TargetOpcode::G_VECREDUCE_SMIN;
1809  case Intrinsic::vector_reduce_umax:
1810  return TargetOpcode::G_VECREDUCE_UMAX;
1811  case Intrinsic::vector_reduce_umin:
1812  return TargetOpcode::G_VECREDUCE_UMIN;
1813  case Intrinsic::lround:
1814  return TargetOpcode::G_LROUND;
1815  case Intrinsic::llround:
1816  return TargetOpcode::G_LLROUND;
1817  }
1818  return Intrinsic::not_intrinsic;
1819 }
1820 
1821 bool IRTranslator::translateSimpleIntrinsic(const CallInst &CI,
1822  Intrinsic::ID ID,
1823  MachineIRBuilder &MIRBuilder) {
1824 
1825  unsigned Op = getSimpleIntrinsicOpcode(ID);
1826 
1827  // Is this a simple intrinsic?
1829  return false;
1830 
1831  // Yes. Let's translate it.
1833  for (const auto &Arg : CI.args())
1834  VRegs.push_back(getOrCreateVReg(*Arg));
1835 
1836  MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs,
1838  return true;
1839 }
1840 
1841 // TODO: Include ConstainedOps.def when all strict instructions are defined.
1843  switch (ID) {
1844  case Intrinsic::experimental_constrained_fadd:
1845  return TargetOpcode::G_STRICT_FADD;
1846  case Intrinsic::experimental_constrained_fsub:
1847  return TargetOpcode::G_STRICT_FSUB;
1848  case Intrinsic::experimental_constrained_fmul:
1849  return TargetOpcode::G_STRICT_FMUL;
1850  case Intrinsic::experimental_constrained_fdiv:
1851  return TargetOpcode::G_STRICT_FDIV;
1852  case Intrinsic::experimental_constrained_frem:
1853  return TargetOpcode::G_STRICT_FREM;
1854  case Intrinsic::experimental_constrained_fma:
1855  return TargetOpcode::G_STRICT_FMA;
1856  case Intrinsic::experimental_constrained_sqrt:
1857  return TargetOpcode::G_STRICT_FSQRT;
1858  default:
1859  return 0;
1860  }
1861 }
1862 
1863 bool IRTranslator::translateConstrainedFPIntrinsic(
1864  const ConstrainedFPIntrinsic &FPI, MachineIRBuilder &MIRBuilder) {
1866 
1867  unsigned Opcode = getConstrainedOpcode(FPI.getIntrinsicID());
1868  if (!Opcode)
1869  return false;
1870 
1871  unsigned Flags = MachineInstr::copyFlagsFromInstruction(FPI);
1873  Flags |= MachineInstr::NoFPExcept;
1874 
1876  VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(0)));
1877  if (!FPI.isUnaryOp())
1878  VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(1)));
1879  if (FPI.isTernaryOp())
1880  VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(2)));
1881 
1882  MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags);
1883  return true;
1884 }
1885 
1886 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
1887  MachineIRBuilder &MIRBuilder) {
1888  if (auto *MI = dyn_cast<AnyMemIntrinsic>(&CI)) {
1889  if (ORE->enabled()) {
1890  if (MemoryOpRemark::canHandle(MI, *LibInfo)) {
1891  MemoryOpRemark R(*ORE, "gisel-irtranslator-memsize", *DL, *LibInfo);
1892  R.visit(MI);
1893  }
1894  }
1895  }
1896 
1897  // If this is a simple intrinsic (that is, we just need to add a def of
1898  // a vreg, and uses for each arg operand, then translate it.
1899  if (translateSimpleIntrinsic(CI, ID, MIRBuilder))
1900  return true;
1901 
1902  switch (ID) {
1903  default:
1904  break;
1905  case Intrinsic::lifetime_start:
1906  case Intrinsic::lifetime_end: {
1907  // No stack colouring in O0, discard region information.
1908  if (MF->getTarget().getOptLevel() == CodeGenOpt::None)
1909  return true;
1910 
1911  unsigned Op = ID == Intrinsic::lifetime_start ? TargetOpcode::LIFETIME_START
1913 
1914  // Get the underlying objects for the location passed on the lifetime
1915  // marker.
1917  getUnderlyingObjects(CI.getArgOperand(1), Allocas);
1918 
1919  // Iterate over each underlying object, creating lifetime markers for each
1920  // static alloca. Quit if we find a non-static alloca.
1921  for (const Value *V : Allocas) {
1922  const AllocaInst *AI = dyn_cast<AllocaInst>(V);
1923  if (!AI)
1924  continue;
1925 
1926  if (!AI->isStaticAlloca())
1927  return true;
1928 
1929  MIRBuilder.buildInstr(Op).addFrameIndex(getOrCreateFrameIndex(*AI));
1930  }
1931  return true;
1932  }
1933  case Intrinsic::dbg_declare: {
1934  const DbgDeclareInst &DI = cast<DbgDeclareInst>(CI);
1935  assert(DI.getVariable() && "Missing variable");
1936 
1937  const Value *Address = DI.getAddress();
1938  if (!Address || isa<UndefValue>(Address)) {
1939  LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
1940  return true;
1941  }
1942 
1944  MIRBuilder.getDebugLoc()) &&
1945  "Expected inlined-at fields to agree");
1946  auto AI = dyn_cast<AllocaInst>(Address);
1947  if (AI && AI->isStaticAlloca()) {
1948  // Static allocas are tracked at the MF level, no need for DBG_VALUE
1949  // instructions (in fact, they get ignored if they *do* exist).
1951  getOrCreateFrameIndex(*AI), DI.getDebugLoc());
1952  } else {
1953  // A dbg.declare describes the address of a source variable, so lower it
1954  // into an indirect DBG_VALUE.
1955  MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address),
1956  DI.getVariable(), DI.getExpression());
1957  }
1958  return true;
1959  }
1960  case Intrinsic::dbg_label: {
1961  const DbgLabelInst &DI = cast<DbgLabelInst>(CI);
1962  assert(DI.getLabel() && "Missing label");
1963 
1965  MIRBuilder.getDebugLoc()) &&
1966  "Expected inlined-at fields to agree");
1967 
1968  MIRBuilder.buildDbgLabel(DI.getLabel());
1969  return true;
1970  }
1971  case Intrinsic::vaend:
1972  // No target I know of cares about va_end. Certainly no in-tree target
1973  // does. Simplest intrinsic ever!
1974  return true;
1975  case Intrinsic::vastart: {
1976  auto &TLI = *MF->getSubtarget().getTargetLowering();
1977  Value *Ptr = CI.getArgOperand(0);
1978  unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
1979 
1980  // FIXME: Get alignment
1981  MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)})
1984  ListSize, Align(1)));
1985  return true;
1986  }
1987  case Intrinsic::dbg_value: {
1988  // This form of DBG_VALUE is target-independent.
1989  const DbgValueInst &DI = cast<DbgValueInst>(CI);
1990  const Value *V = DI.getValue();
1992  MIRBuilder.getDebugLoc()) &&
1993  "Expected inlined-at fields to agree");
1994  if (!V || DI.hasArgList()) {
1995  // DI cannot produce a valid DBG_VALUE, so produce an undef DBG_VALUE to
1996  // terminate any prior location.
1997  MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression());
1998  } else if (const auto *CI = dyn_cast<Constant>(V)) {
1999  MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
2000  } else {
2001  for (Register Reg : getOrCreateVRegs(*V)) {
2002  // FIXME: This does not handle register-indirect values at offset 0. The
2003  // direct/indirect thing shouldn't really be handled by something as
2004  // implicit as reg+noreg vs reg+imm in the first place, but it seems
2005  // pretty baked in right now.
2006  MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
2007  }
2008  }
2009  return true;
2010  }
2011  case Intrinsic::uadd_with_overflow:
2012  return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder);
2013  case Intrinsic::sadd_with_overflow:
2014  return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
2015  case Intrinsic::usub_with_overflow:
2016  return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder);
2017  case Intrinsic::ssub_with_overflow:
2018  return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
2019  case Intrinsic::umul_with_overflow:
2020  return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
2021  case Intrinsic::smul_with_overflow:
2022  return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
2023  case Intrinsic::uadd_sat:
2024  return translateBinaryOp(TargetOpcode::G_UADDSAT, CI, MIRBuilder);
2025  case Intrinsic::sadd_sat:
2026  return translateBinaryOp(TargetOpcode::G_SADDSAT, CI, MIRBuilder);
2027  case Intrinsic::usub_sat:
2028  return translateBinaryOp(TargetOpcode::G_USUBSAT, CI, MIRBuilder);
2029  case Intrinsic::ssub_sat:
2030  return translateBinaryOp(TargetOpcode::G_SSUBSAT, CI, MIRBuilder);
2031  case Intrinsic::ushl_sat:
2032  return translateBinaryOp(TargetOpcode::G_USHLSAT, CI, MIRBuilder);
2033  case Intrinsic::sshl_sat:
2034  return translateBinaryOp(TargetOpcode::G_SSHLSAT, CI, MIRBuilder);
2035  case Intrinsic::umin:
2036  return translateBinaryOp(TargetOpcode::G_UMIN, CI, MIRBuilder);
2037  case Intrinsic::umax:
2038  return translateBinaryOp(TargetOpcode::G_UMAX, CI, MIRBuilder);
2039  case Intrinsic::smin:
2040  return translateBinaryOp(TargetOpcode::G_SMIN, CI, MIRBuilder);
2041  case Intrinsic::smax:
2042  return translateBinaryOp(TargetOpcode::G_SMAX, CI, MIRBuilder);
2043  case Intrinsic::abs:
2044  // TODO: Preserve "int min is poison" arg in GMIR?
2045  return translateUnaryOp(TargetOpcode::G_ABS, CI, MIRBuilder);
2046  case Intrinsic::smul_fix:
2047  return translateFixedPointIntrinsic(TargetOpcode::G_SMULFIX, CI, MIRBuilder);
2048  case Intrinsic::umul_fix:
2049  return translateFixedPointIntrinsic(TargetOpcode::G_UMULFIX, CI, MIRBuilder);
2050  case Intrinsic::smul_fix_sat:
2051  return translateFixedPointIntrinsic(TargetOpcode::G_SMULFIXSAT, CI, MIRBuilder);
2052  case Intrinsic::umul_fix_sat:
2053  return translateFixedPointIntrinsic(TargetOpcode::G_UMULFIXSAT, CI, MIRBuilder);
2054  case Intrinsic::sdiv_fix:
2055  return translateFixedPointIntrinsic(TargetOpcode::G_SDIVFIX, CI, MIRBuilder);
2056  case Intrinsic::udiv_fix:
2057  return translateFixedPointIntrinsic(TargetOpcode::G_UDIVFIX, CI, MIRBuilder);
2058  case Intrinsic::sdiv_fix_sat:
2059  return translateFixedPointIntrinsic(TargetOpcode::G_SDIVFIXSAT, CI, MIRBuilder);
2060  case Intrinsic::udiv_fix_sat:
2061  return translateFixedPointIntrinsic(TargetOpcode::G_UDIVFIXSAT, CI, MIRBuilder);
2062  case Intrinsic::fmuladd: {
2063  const TargetMachine &TM = MF->getTarget();
2064  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
2065  Register Dst = getOrCreateVReg(CI);
2066  Register Op0 = getOrCreateVReg(*CI.getArgOperand(0));
2067  Register Op1 = getOrCreateVReg(*CI.getArgOperand(1));
2068  Register Op2 = getOrCreateVReg(*CI.getArgOperand(2));
2069  if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
2071  TLI.getValueType(*DL, CI.getType()))) {
2072  // TODO: Revisit this to see if we should move this part of the
2073  // lowering to the combiner.
2074  MIRBuilder.buildFMA(Dst, Op0, Op1, Op2,
2076  } else {
2077  LLT Ty = getLLTForType(*CI.getType(), *DL);
2078  auto FMul = MIRBuilder.buildFMul(
2079  Ty, Op0, Op1, MachineInstr::copyFlagsFromInstruction(CI));
2080  MIRBuilder.buildFAdd(Dst, FMul, Op2,
2082  }
2083  return true;
2084  }
2085  case Intrinsic::convert_from_fp16:
2086  // FIXME: This intrinsic should probably be removed from the IR.
2087  MIRBuilder.buildFPExt(getOrCreateVReg(CI),
2088  getOrCreateVReg(*CI.getArgOperand(0)),
2090  return true;
2091  case Intrinsic::convert_to_fp16:
2092  // FIXME: This intrinsic should probably be removed from the IR.
2093  MIRBuilder.buildFPTrunc(getOrCreateVReg(CI),
2094  getOrCreateVReg(*CI.getArgOperand(0)),
2096  return true;
2097  case Intrinsic::memcpy_inline:
2098  return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMCPY_INLINE);
2099  case Intrinsic::memcpy:
2100  return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMCPY);
2101  case Intrinsic::memmove:
2102  return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMMOVE);
2103  case Intrinsic::memset:
2104  return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMSET);
2105  case Intrinsic::eh_typeid_for: {
2107  Register Reg = getOrCreateVReg(CI);
2108  unsigned TypeID = MF->getTypeIDFor(GV);
2109  MIRBuilder.buildConstant(Reg, TypeID);
2110  return true;
2111  }
2112  case Intrinsic::objectsize:
2113  llvm_unreachable("llvm.objectsize.* should have been lowered already");
2114 
2115  case Intrinsic::is_constant:
2116  llvm_unreachable("llvm.is.constant.* should have been lowered already");
2117 
2118  case Intrinsic::stackguard:
2119  getStackGuard(getOrCreateVReg(CI), MIRBuilder);
2120  return true;
2121  case Intrinsic::stackprotector: {
2122  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
2123  LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
2124  Register GuardVal;
2125  if (TLI.useLoadStackGuardNode()) {
2126  GuardVal = MRI->createGenericVirtualRegister(PtrTy);
2127  getStackGuard(GuardVal, MIRBuilder);
2128  } else
2129  GuardVal = getOrCreateVReg(*CI.getArgOperand(0)); // The guard's value.
2130 
2131  AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
2132  int FI = getOrCreateFrameIndex(*Slot);
2134 
2135  MIRBuilder.buildStore(
2136  GuardVal, getOrCreateVReg(*Slot),
2140  PtrTy, Align(8)));
2141  return true;
2142  }
2143  case Intrinsic::stacksave: {
2144  // Save the stack pointer to the location provided by the intrinsic.
2145  Register Reg = getOrCreateVReg(CI);
2149 
2150  // If the target doesn't specify a stack pointer, then fall back.
2151  if (!StackPtr)
2152  return false;
2153 
2154  MIRBuilder.buildCopy(Reg, StackPtr);
2155  return true;
2156  }
2157  case Intrinsic::stackrestore: {
2158  // Restore the stack pointer from the location provided by the intrinsic.
2159  Register Reg = getOrCreateVReg(*CI.getArgOperand(0));
2163 
2164  // If the target doesn't specify a stack pointer, then fall back.
2165  if (!StackPtr)
2166  return false;
2167 
2168  MIRBuilder.buildCopy(StackPtr, Reg);
2169  return true;
2170  }
2171  case Intrinsic::cttz:
2172  case Intrinsic::ctlz: {
2173  ConstantInt *Cst = cast<ConstantInt>(CI.getArgOperand(1));
2174  bool isTrailing = ID == Intrinsic::cttz;
2175  unsigned Opcode = isTrailing
2176  ? Cst->isZero() ? TargetOpcode::G_CTTZ
2177  : TargetOpcode::G_CTTZ_ZERO_UNDEF
2178  : Cst->isZero() ? TargetOpcode::G_CTLZ
2179  : TargetOpcode::G_CTLZ_ZERO_UNDEF;
2180  MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)},
2181  {getOrCreateVReg(*CI.getArgOperand(0))});
2182  return true;
2183  }
2184  case Intrinsic::invariant_start: {
2185  LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
2187  MIRBuilder.buildUndef(Undef);
2188  return true;
2189  }
2190  case Intrinsic::invariant_end:
2191  return true;
2192  case Intrinsic::expect:
2193  case Intrinsic::annotation:
2194  case Intrinsic::ptr_annotation:
2195  case Intrinsic::launder_invariant_group:
2196  case Intrinsic::strip_invariant_group: {
2197  // Drop the intrinsic, but forward the value.
2198  MIRBuilder.buildCopy(getOrCreateVReg(CI),
2199  getOrCreateVReg(*CI.getArgOperand(0)));
2200  return true;
2201  }
2202  case Intrinsic::assume:
2203  case Intrinsic::experimental_noalias_scope_decl:
2204  case Intrinsic::var_annotation:
2205  case Intrinsic::sideeffect:
2206  // Discard annotate attributes, assumptions, and artificial side-effects.
2207  return true;
2208  case Intrinsic::read_volatile_register:
2209  case Intrinsic::read_register: {
2210  Value *Arg = CI.getArgOperand(0);
2211  MIRBuilder
2212  .buildInstr(TargetOpcode::G_READ_REGISTER, {getOrCreateVReg(CI)}, {})
2213  .addMetadata(cast<MDNode>(cast<MetadataAsValue>(Arg)->getMetadata()));
2214  return true;
2215  }
2216  case Intrinsic::write_register: {
2217  Value *Arg = CI.getArgOperand(0);
2218  MIRBuilder.buildInstr(TargetOpcode::G_WRITE_REGISTER)
2219  .addMetadata(cast<MDNode>(cast<MetadataAsValue>(Arg)->getMetadata()))
2220  .addUse(getOrCreateVReg(*CI.getArgOperand(1)));
2221  return true;
2222  }
2223  case Intrinsic::localescape: {
2224  MachineBasicBlock &EntryMBB = MF->front();
2226 
2227  // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
2228  // is the same on all targets.
2229  for (unsigned Idx = 0, E = CI.arg_size(); Idx < E; ++Idx) {
2230  Value *Arg = CI.getArgOperand(Idx)->stripPointerCasts();
2231  if (isa<ConstantPointerNull>(Arg))
2232  continue; // Skip null pointers. They represent a hole in index space.
2233 
2234  int FI = getOrCreateFrameIndex(*cast<AllocaInst>(Arg));
2235  MCSymbol *FrameAllocSym =
2236  MF->getMMI().getContext().getOrCreateFrameAllocSymbol(EscapedName,
2237  Idx);
2238 
2239  // This should be inserted at the start of the entry block.
2240  auto LocalEscape =
2241  MIRBuilder.buildInstrNoInsert(TargetOpcode::LOCAL_ESCAPE)
2242  .addSym(FrameAllocSym)
2243  .addFrameIndex(FI);
2244 
2245  EntryMBB.insert(EntryMBB.begin(), LocalEscape);
2246  }
2247 
2248  return true;
2249  }
2250  case Intrinsic::vector_reduce_fadd:
2251  case Intrinsic::vector_reduce_fmul: {
2252  // Need to check for the reassoc flag to decide whether we want a
2253  // sequential reduction opcode or not.
2254  Register Dst = getOrCreateVReg(CI);
2255  Register ScalarSrc = getOrCreateVReg(*CI.getArgOperand(0));
2256  Register VecSrc = getOrCreateVReg(*CI.getArgOperand(1));
2257  unsigned Opc = 0;
2258  if (!CI.hasAllowReassoc()) {
2259  // The sequential ordering case.
2260  Opc = ID == Intrinsic::vector_reduce_fadd
2261  ? TargetOpcode::G_VECREDUCE_SEQ_FADD
2262  : TargetOpcode::G_VECREDUCE_SEQ_FMUL;
2263  MIRBuilder.buildInstr(Opc, {Dst}, {ScalarSrc, VecSrc},
2265  return true;
2266  }
2267  // We split the operation into a separate G_FADD/G_FMUL + the reduce,
2268  // since the associativity doesn't matter.
2269  unsigned ScalarOpc;
2270  if (ID == Intrinsic::vector_reduce_fadd) {
2271  Opc = TargetOpcode::G_VECREDUCE_FADD;
2272  ScalarOpc = TargetOpcode::G_FADD;
2273  } else {
2274  Opc = TargetOpcode::G_VECREDUCE_FMUL;
2275  ScalarOpc = TargetOpcode::G_FMUL;
2276  }
2277  LLT DstTy = MRI->getType(Dst);
2278  auto Rdx = MIRBuilder.buildInstr(
2279  Opc, {DstTy}, {VecSrc}, MachineInstr::copyFlagsFromInstruction(CI));
2280  MIRBuilder.buildInstr(ScalarOpc, {Dst}, {ScalarSrc, Rdx},
2282 
2283  return true;
2284  }
2285  case Intrinsic::trap:
2286  case Intrinsic::debugtrap:
2287  case Intrinsic::ubsantrap: {
2288  StringRef TrapFuncName =
2289  CI.getAttributes().getFnAttr("trap-func-name").getValueAsString();
2290  if (TrapFuncName.empty())
2291  break; // Use the default handling.
2293  if (ID == Intrinsic::ubsantrap) {
2294  Info.OrigArgs.push_back({getOrCreateVRegs(*CI.getArgOperand(0)),
2295  CI.getArgOperand(0)->getType(), 0});
2296  }
2297  Info.Callee = MachineOperand::CreateES(TrapFuncName.data());
2298  Info.CB = &CI;
2299  Info.OrigRet = {Register(), Type::getVoidTy(CI.getContext()), 0};
2300  return CLI->lowerCall(MIRBuilder, Info);
2301  }
2302  case Intrinsic::fptrunc_round: {
2303  unsigned Flags = MachineInstr::copyFlagsFromInstruction(CI);
2304 
2305  // Convert the metadata argument to a constant integer
2306  Metadata *MD = cast<MetadataAsValue>(CI.getArgOperand(1))->getMetadata();
2307  Optional<RoundingMode> RoundMode =
2308  convertStrToRoundingMode(cast<MDString>(MD)->getString());
2309 
2310  // Add the Rounding mode as an integer
2311  MIRBuilder
2312  .buildInstr(TargetOpcode::G_INTRINSIC_FPTRUNC_ROUND,
2313  {getOrCreateVReg(CI)},
2314  {getOrCreateVReg(*CI.getArgOperand(0))}, Flags)
2315  .addImm((int)*RoundMode);
2316 
2317  return true;
2318  }
2319 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \
2320  case Intrinsic::INTRINSIC:
2321 #include "llvm/IR/ConstrainedOps.def"
2322  return translateConstrainedFPIntrinsic(cast<ConstrainedFPIntrinsic>(CI),
2323  MIRBuilder);
2324 
2325  }
2326  return false;
2327 }
2328 
2329 bool IRTranslator::translateInlineAsm(const CallBase &CB,
2330  MachineIRBuilder &MIRBuilder) {
2331 
2333 
2334  if (!ALI) {
2335  LLVM_DEBUG(
2336  dbgs() << "Inline asm lowering is not supported for this target yet\n");
2337  return false;
2338  }
2339 
2340  return ALI->lowerInlineAsm(
2341  MIRBuilder, CB, [&](const Value &Val) { return getOrCreateVRegs(Val); });
2342 }
2343 
2344 bool IRTranslator::translateCallBase(const CallBase &CB,
2345  MachineIRBuilder &MIRBuilder) {
2346  ArrayRef<Register> Res = getOrCreateVRegs(CB);
2347 
2349  Register SwiftInVReg = 0;
2350  Register SwiftErrorVReg = 0;
2351  for (const auto &Arg : CB.args()) {
2352  if (CLI->supportSwiftError() && isSwiftError(Arg)) {
2353  assert(SwiftInVReg == 0 && "Expected only one swift error argument");
2354  LLT Ty = getLLTForType(*Arg->getType(), *DL);
2355  SwiftInVReg = MRI->createGenericVirtualRegister(Ty);
2356  MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt(
2357  &CB, &MIRBuilder.getMBB(), Arg));
2358  Args.emplace_back(makeArrayRef(SwiftInVReg));
2359  SwiftErrorVReg =
2360  SwiftError.getOrCreateVRegDefAt(&CB, &MIRBuilder.getMBB(), Arg);
2361  continue;
2362  }
2363  Args.push_back(getOrCreateVRegs(*Arg));
2364  }
2365 
2366  if (auto *CI = dyn_cast<CallInst>(&CB)) {
2367  if (ORE->enabled()) {
2368  if (MemoryOpRemark::canHandle(CI, *LibInfo)) {
2369  MemoryOpRemark R(*ORE, "gisel-irtranslator-memsize", *DL, *LibInfo);
2370  R.visit(CI);
2371  }
2372  }
2373  }
2374 
2375  // We don't set HasCalls on MFI here yet because call lowering may decide to
2376  // optimize into tail calls. Instead, we defer that to selection where a final
2377  // scan is done to check if any instructions are calls.
2378  bool Success =
2379  CLI->lowerCall(MIRBuilder, CB, Res, Args, SwiftErrorVReg,
2380  [&]() { return getOrCreateVReg(*CB.getCalledOperand()); });
2381 
2382  // Check if we just inserted a tail call.
2383  if (Success) {
2384  assert(!HasTailCall && "Can't tail call return twice from block?");
2385  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
2386  HasTailCall = TII->isTailCall(*std::prev(MIRBuilder.getInsertPt()));
2387  }
2388 
2389  return Success;
2390 }
2391 
2392 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
2393  const CallInst &CI = cast<CallInst>(U);
2394  auto TII = MF->getTarget().getIntrinsicInfo();
2395  const Function *F = CI.getCalledFunction();
2396 
2397  // FIXME: support Windows dllimport function calls.
2398  if (F && (F->hasDLLImportStorageClass() ||
2399  (MF->getTarget().getTargetTriple().isOSWindows() &&
2400  F->hasExternalWeakLinkage())))
2401  return false;
2402 
2403  // FIXME: support control flow guard targets.
2405  return false;
2406 
2407  // FIXME: support statepoints and related.
2408  if (isa<GCStatepointInst, GCRelocateInst, GCResultInst>(U))
2409  return false;
2410 
2411  if (CI.isInlineAsm())
2412  return translateInlineAsm(CI, MIRBuilder);
2413 
2414  diagnoseDontCall(CI);
2415 
2417  if (F && F->isIntrinsic()) {
2418  ID = F->getIntrinsicID();
2419  if (TII && ID == Intrinsic::not_intrinsic)
2420  ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
2421  }
2422 
2423  if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic)
2424  return translateCallBase(CI, MIRBuilder);
2425 
2426  assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
2427 
2428  if (translateKnownIntrinsic(CI, ID, MIRBuilder))
2429  return true;
2430 
2431  ArrayRef<Register> ResultRegs;
2432  if (!CI.getType()->isVoidTy())
2433  ResultRegs = getOrCreateVRegs(CI);
2434 
2435  // Ignore the callsite attributes. Backend code is most likely not expecting
2436  // an intrinsic to sometimes have side effects and sometimes not.
2437  MachineInstrBuilder MIB =
2438  MIRBuilder.buildIntrinsic(ID, ResultRegs, !F->doesNotAccessMemory());
2439  if (isa<FPMathOperator>(CI))
2440  MIB->copyIRFlags(CI);
2441 
2442  for (const auto &Arg : enumerate(CI.args())) {
2443  // If this is required to be an immediate, don't materialize it in a
2444  // register.
2445  if (CI.paramHasAttr(Arg.index(), Attribute::ImmArg)) {
2446  if (ConstantInt *CI = dyn_cast<ConstantInt>(Arg.value())) {
2447  // imm arguments are more convenient than cimm (and realistically
2448  // probably sufficient), so use them.
2449  assert(CI->getBitWidth() <= 64 &&
2450  "large intrinsic immediates not handled");
2451  MIB.addImm(CI->getSExtValue());
2452  } else {
2453  MIB.addFPImm(cast<ConstantFP>(Arg.value()));
2454  }
2455  } else if (auto *MDVal = dyn_cast<MetadataAsValue>(Arg.value())) {
2456  auto *MD = MDVal->getMetadata();
2457  auto *MDN = dyn_cast<MDNode>(MD);
2458  if (!MDN) {
2459  if (auto *ConstMD = dyn_cast<ConstantAsMetadata>(MD))
2460  MDN = MDNode::get(MF->getFunction().getContext(), ConstMD);
2461  else // This was probably an MDString.
2462  return false;
2463  }
2464  MIB.addMetadata(MDN);
2465  } else {
2466  ArrayRef<Register> VRegs = getOrCreateVRegs(*Arg.value());
2467  if (VRegs.size() > 1)
2468  return false;
2469  MIB.addUse(VRegs[0]);
2470  }
2471  }
2472 
2473  // Add a MachineMemOperand if it is a target mem intrinsic.
2474  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
2475  TargetLowering::IntrinsicInfo Info;
2476  // TODO: Add a GlobalISel version of getTgtMemIntrinsic.
2477  if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) {
2478  Align Alignment = Info.align.value_or(
2479  DL->getABITypeAlign(Info.memVT.getTypeForEVT(F->getContext())));
2480  LLT MemTy = Info.memVT.isSimple()
2481  ? getLLTForMVT(Info.memVT.getSimpleVT())
2482  : LLT::scalar(Info.memVT.getStoreSizeInBits());
2484  Info.flags, MemTy, Alignment));
2485  }
2486 
2487  return true;
2488 }
2489 
2490 bool IRTranslator::findUnwindDestinations(
2491  const BasicBlock *EHPadBB,
2492  BranchProbability Prob,
2493  SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
2494  &UnwindDests) {
2495  EHPersonality Personality = classifyEHPersonality(
2496  EHPadBB->getParent()->getFunction().getPersonalityFn());
2497  bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
2498  bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
2499  bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX;
2500  bool IsSEH = isAsynchronousEHPersonality(Personality);
2501 
2502  if (IsWasmCXX) {
2503  // Ignore this for now.
2504  return false;
2505  }
2506 
2507  while (EHPadBB) {
2508  const Instruction *Pad = EHPadBB->getFirstNonPHI();
2509  BasicBlock *NewEHPadBB = nullptr;
2510  if (isa<LandingPadInst>(Pad)) {
2511  // Stop on landingpads. They are not funclets.
2512  UnwindDests.emplace_back(&getMBB(*EHPadBB), Prob);
2513  break;
2514  }
2515  if (isa<CleanupPadInst>(Pad)) {
2516  // Stop on cleanup pads. Cleanups are always funclet entries for all known
2517  // personalities.
2518  UnwindDests.emplace_back(&getMBB(*EHPadBB), Prob);
2519  UnwindDests.back().first->setIsEHScopeEntry();
2520  UnwindDests.back().first->setIsEHFuncletEntry();
2521  break;
2522  }
2523  if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
2524  // Add the catchpad handlers to the possible destinations.
2525  for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
2526  UnwindDests.emplace_back(&getMBB(*CatchPadBB), Prob);
2527  // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
2528  if (IsMSVCCXX || IsCoreCLR)
2529  UnwindDests.back().first->setIsEHFuncletEntry();
2530  if (!IsSEH)
2531  UnwindDests.back().first->setIsEHScopeEntry();
2532  }
2533  NewEHPadBB = CatchSwitch->getUnwindDest();
2534  } else {
2535  continue;
2536  }
2537 
2538  BranchProbabilityInfo *BPI = FuncInfo.BPI;
2539  if (BPI && NewEHPadBB)
2540  Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
2541  EHPadBB = NewEHPadBB;
2542  }
2543  return true;
2544 }
2545 
2546 bool IRTranslator::translateInvoke(const User &U,
2547  MachineIRBuilder &MIRBuilder) {
2548  const InvokeInst &I = cast<InvokeInst>(U);
2549  MCContext &Context = MF->getContext();
2550 
2551  const BasicBlock *ReturnBB = I.getSuccessor(0);
2552  const BasicBlock *EHPadBB = I.getSuccessor(1);
2553 
2554  const Function *Fn = I.getCalledFunction();
2555 
2556  // FIXME: support invoking patchpoint and statepoint intrinsics.
2557  if (Fn && Fn->isIntrinsic())
2558  return false;
2559 
2560  // FIXME: support whatever these are.
2561  if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
2562  return false;
2563 
2564  // FIXME: support control flow guard targets.
2565  if (I.countOperandBundlesOfType(LLVMContext::OB_cfguardtarget))
2566  return false;
2567 
2568  // FIXME: support Windows exception handling.
2569  if (!isa<LandingPadInst>(EHPadBB->getFirstNonPHI()))
2570  return false;
2571 
2572  bool LowerInlineAsm = I.isInlineAsm();
2573  bool NeedEHLabel = true;
2574  // If it can't throw then use a fast-path without emitting EH labels.
2575  if (LowerInlineAsm)
2576  NeedEHLabel = (cast<InlineAsm>(I.getCalledOperand()))->canThrow();
2577 
2578  // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
2579  // the region covered by the try.
2580  MCSymbol *BeginSymbol = nullptr;
2581  if (NeedEHLabel) {
2582  BeginSymbol = Context.createTempSymbol();
2583  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
2584  }
2585 
2586  if (LowerInlineAsm) {
2587  if (!translateInlineAsm(I, MIRBuilder))
2588  return false;
2589  } else if (!translateCallBase(I, MIRBuilder))
2590  return false;
2591 
2592  MCSymbol *EndSymbol = nullptr;
2593  if (NeedEHLabel) {
2594  EndSymbol = Context.createTempSymbol();
2595  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
2596  }
2597 
2599  BranchProbabilityInfo *BPI = FuncInfo.BPI;
2600  MachineBasicBlock *InvokeMBB = &MIRBuilder.getMBB();
2601  BranchProbability EHPadBBProb =
2602  BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
2604 
2605  if (!findUnwindDestinations(EHPadBB, EHPadBBProb, UnwindDests))
2606  return false;
2607 
2608  MachineBasicBlock &EHPadMBB = getMBB(*EHPadBB),
2609  &ReturnMBB = getMBB(*ReturnBB);
2610  // Update successor info.
2611  addSuccessorWithProb(InvokeMBB, &ReturnMBB);
2612  for (auto &UnwindDest : UnwindDests) {
2613  UnwindDest.first->setIsEHPad();
2614  addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
2615  }
2616  InvokeMBB->normalizeSuccProbs();
2617 
2618  if (NeedEHLabel) {
2619  assert(BeginSymbol && "Expected a begin symbol!");
2620  assert(EndSymbol && "Expected an end symbol!");
2621  MF->addInvoke(&EHPadMBB, BeginSymbol, EndSymbol);
2622  }
2623 
2624  MIRBuilder.buildBr(ReturnMBB);
2625  return true;
2626 }
2627 
2628 bool IRTranslator::translateCallBr(const User &U,
2629  MachineIRBuilder &MIRBuilder) {
2630  // FIXME: Implement this.
2631  return false;
2632 }
2633 
2634 bool IRTranslator::translateLandingPad(const User &U,
2635  MachineIRBuilder &MIRBuilder) {
2636  const LandingPadInst &LP = cast<LandingPadInst>(U);
2637 
2638  MachineBasicBlock &MBB = MIRBuilder.getMBB();
2639 
2640  MBB.setIsEHPad();
2641 
2642  // If there aren't registers to copy the values into (e.g., during SjLj
2643  // exceptions), then don't bother.
2644  auto &TLI = *MF->getSubtarget().getTargetLowering();
2645  const Constant *PersonalityFn = MF->getFunction().getPersonalityFn();
2646  if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2647  TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2648  return true;
2649 
2650  // If landingpad's return type is token type, we don't create DAG nodes
2651  // for its exception pointer and selector value. The extraction of exception
2652  // pointer or selector value from token type landingpads is not currently
2653  // supported.
2654  if (LP.getType()->isTokenTy())
2655  return true;
2656 
2657  // Add a label to mark the beginning of the landing pad. Deletion of the
2658  // landing pad can thus be detected via the MachineModuleInfo.
2660  .addSym(MF->addLandingPad(&MBB));
2661 
2662  // If the unwinder does not preserve all registers, ensure that the
2663  // function marks the clobbered registers as used.
2665  if (auto *RegMask = TRI.getCustomEHPadPreservedMask(*MF))
2666  MF->getRegInfo().addPhysRegsUsedFromRegMask(RegMask);
2667 
2668  LLT Ty = getLLTForType(*LP.getType(), *DL);
2670  MIRBuilder.buildUndef(Undef);
2671 
2672  SmallVector<LLT, 2> Tys;
2673  for (Type *Ty : cast<StructType>(LP.getType())->elements())
2674  Tys.push_back(getLLTForType(*Ty, *DL));
2675  assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
2676 
2677  // Mark exception register as live in.
2678  Register ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
2679  if (!ExceptionReg)
2680  return false;
2681 
2682  MBB.addLiveIn(ExceptionReg);
2683  ArrayRef<Register> ResRegs = getOrCreateVRegs(LP);
2684  MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
2685 
2686  Register SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
2687  if (!SelectorReg)
2688  return false;
2689 
2690  MBB.addLiveIn(SelectorReg);
2691  Register PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
2692  MIRBuilder.buildCopy(PtrVReg, SelectorReg);
2693  MIRBuilder.buildCast(ResRegs[1], PtrVReg);
2694 
2695  return true;
2696 }
2697 
2698 bool IRTranslator::translateAlloca(const User &U,
2699  MachineIRBuilder &MIRBuilder) {
2700  auto &AI = cast<AllocaInst>(U);
2701 
2702  if (AI.isSwiftError())
2703  return true;
2704 
2705  if (AI.isStaticAlloca()) {
2706  Register Res = getOrCreateVReg(AI);
2707  int FI = getOrCreateFrameIndex(AI);
2708  MIRBuilder.buildFrameIndex(Res, FI);
2709  return true;
2710  }
2711 
2712  // FIXME: support stack probing for Windows.
2713  if (MF->getTarget().getTargetTriple().isOSWindows())
2714  return false;
2715 
2716  // Now we're in the harder dynamic case.
2717  Register NumElts = getOrCreateVReg(*AI.getArraySize());
2718  Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
2719  LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
2720  if (MRI->getType(NumElts) != IntPtrTy) {
2721  Register ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
2722  MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
2723  NumElts = ExtElts;
2724  }
2725 
2726  Type *Ty = AI.getAllocatedType();
2727 
2728  Register AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
2729  Register TySize =
2730  getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, DL->getTypeAllocSize(Ty)));
2731  MIRBuilder.buildMul(AllocSize, NumElts, TySize);
2732 
2733  // Round the size of the allocation up to the stack alignment size
2734  // by add SA-1 to the size. This doesn't overflow because we're computing
2735  // an address inside an alloca.
2737  auto SAMinusOne = MIRBuilder.buildConstant(IntPtrTy, StackAlign.value() - 1);
2738  auto AllocAdd = MIRBuilder.buildAdd(IntPtrTy, AllocSize, SAMinusOne,
2740  auto AlignCst =
2741  MIRBuilder.buildConstant(IntPtrTy, ~(uint64_t)(StackAlign.value() - 1));
2742  auto AlignedAlloc = MIRBuilder.buildAnd(IntPtrTy, AllocAdd, AlignCst);
2743 
2744  Align Alignment = std::max(AI.getAlign(), DL->getPrefTypeAlign(Ty));
2745  if (Alignment <= StackAlign)
2746  Alignment = Align(1);
2747  MIRBuilder.buildDynStackAlloc(getOrCreateVReg(AI), AlignedAlloc, Alignment);
2748 
2749  MF->getFrameInfo().CreateVariableSizedObject(Alignment, &AI);
2751  return true;
2752 }
2753 
2754 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
2755  // FIXME: We may need more info about the type. Because of how LLT works,
2756  // we're completely discarding the i64/double distinction here (amongst
2757  // others). Fortunately the ABIs I know of where that matters don't use va_arg
2758  // anyway but that's not guaranteed.
2759  MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)},
2760  {getOrCreateVReg(*U.getOperand(0)),
2761  DL->getABITypeAlign(U.getType()).value()});
2762  return true;
2763 }
2764 
2765 bool IRTranslator::translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
2766  if (!MF->getTarget().Options.TrapUnreachable)
2767  return true;
2768 
2769  auto &UI = cast<UnreachableInst>(U);
2770  // We may be able to ignore unreachable behind a noreturn call.
2772  const BasicBlock &BB = *UI.getParent();
2773  if (&UI != &BB.front()) {
2775  std::prev(BasicBlock::const_iterator(UI));
2776  if (const CallInst *Call = dyn_cast<CallInst>(&*PredI)) {
2777  if (Call->doesNotReturn())
2778  return true;
2779  }
2780  }
2781  }
2782 
2783  MIRBuilder.buildIntrinsic(Intrinsic::trap, ArrayRef<Register>(), true);
2784  return true;
2785 }
2786 
2787 bool IRTranslator::translateInsertElement(const User &U,
2788  MachineIRBuilder &MIRBuilder) {
2789  // If it is a <1 x Ty> vector, use the scalar as it is
2790  // not a legal vector type in LLT.
2791  if (cast<FixedVectorType>(U.getType())->getNumElements() == 1)
2792  return translateCopy(U, *U.getOperand(1), MIRBuilder);
2793 
2794  Register Res = getOrCreateVReg(U);
2795  Register Val = getOrCreateVReg(*U.getOperand(0));
2796  Register Elt = getOrCreateVReg(*U.getOperand(1));
2797  Register Idx = getOrCreateVReg(*U.getOperand(2));
2798  MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
2799  return true;
2800 }
2801 
2802 bool IRTranslator::translateExtractElement(const User &U,
2803  MachineIRBuilder &MIRBuilder) {
2804  // If it is a <1 x Ty> vector, use the scalar as it is
2805  // not a legal vector type in LLT.
2806  if (cast<FixedVectorType>(U.getOperand(0)->getType())->getNumElements() == 1)
2807  return translateCopy(U, *U.getOperand(0), MIRBuilder);
2808 
2809  Register Res = getOrCreateVReg(U);
2810  Register Val = getOrCreateVReg(*U.getOperand(0));
2811  const auto &TLI = *MF->getSubtarget().getTargetLowering();
2812  unsigned PreferredVecIdxWidth = TLI.getVectorIdxTy(*DL).getSizeInBits();
2813  Register Idx;
2814  if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(1))) {
2815  if (CI->getBitWidth() != PreferredVecIdxWidth) {
2816  APInt NewIdx = CI->getValue().sextOrTrunc(PreferredVecIdxWidth);
2817  auto *NewIdxCI = ConstantInt::get(CI->getContext(), NewIdx);
2818  Idx = getOrCreateVReg(*NewIdxCI);
2819  }
2820  }
2821  if (!Idx)
2822  Idx = getOrCreateVReg(*U.getOperand(1));
2823  if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) {
2824  const LLT VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
2825  Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx).getReg(0);
2826  }
2827  MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
2828  return true;
2829 }
2830 
2831 bool IRTranslator::translateShuffleVector(const User &U,
2832  MachineIRBuilder &MIRBuilder) {
2834  if (auto *SVI = dyn_cast<ShuffleVectorInst>(&U))
2835  Mask = SVI->getShuffleMask();
2836  else
2837  Mask = cast<ConstantExpr>(U).getShuffleMask();
2838  ArrayRef<int> MaskAlloc = MF->allocateShuffleMask(Mask);
2839  MIRBuilder
2840  .buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {getOrCreateVReg(U)},
2841  {getOrCreateVReg(*U.getOperand(0)),
2842  getOrCreateVReg(*U.getOperand(1))})
2843  .addShuffleMask(MaskAlloc);
2844  return true;
2845 }
2846 
2847 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
2848  const PHINode &PI = cast<PHINode>(U);
2849 
2851  for (auto Reg : getOrCreateVRegs(PI)) {
2852  auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {});
2853  Insts.push_back(MIB.getInstr());
2854  }
2855 
2856  PendingPHIs.emplace_back(&PI, std::move(Insts));
2857  return true;
2858 }
2859 
2860 bool IRTranslator::translateAtomicCmpXchg(const User &U,
2861  MachineIRBuilder &MIRBuilder) {
2862  const AtomicCmpXchgInst &I = cast<AtomicCmpXchgInst>(U);
2863 
2864  auto &TLI = *MF->getSubtarget().getTargetLowering();
2865  auto Flags = TLI.getAtomicMemOperandFlags(I, *DL);
2866 
2867  auto Res = getOrCreateVRegs(I);
2868  Register OldValRes = Res[0];
2869  Register SuccessRes = Res[1];
2870  Register Addr = getOrCreateVReg(*I.getPointerOperand());
2871  Register Cmp = getOrCreateVReg(*I.getCompareOperand());
2872  Register NewVal = getOrCreateVReg(*I.getNewValOperand());
2873 
2874  MIRBuilder.buildAtomicCmpXchgWithSuccess(
2875  OldValRes, SuccessRes, Addr, Cmp, NewVal,
2876  *MF->getMachineMemOperand(
2877  MachinePointerInfo(I.getPointerOperand()), Flags, MRI->getType(Cmp),
2878  getMemOpAlign(I), I.getAAMetadata(), nullptr, I.getSyncScopeID(),
2879  I.getSuccessOrdering(), I.getFailureOrdering()));
2880  return true;
2881 }
2882 
2883 bool IRTranslator::translateAtomicRMW(const User &U,
2884  MachineIRBuilder &MIRBuilder) {
2885  const AtomicRMWInst &I = cast<AtomicRMWInst>(U);
2886  auto &TLI = *MF->getSubtarget().getTargetLowering();
2887  auto Flags = TLI.getAtomicMemOperandFlags(I, *DL);
2888 
2889  Register Res = getOrCreateVReg(I);
2890  Register Addr = getOrCreateVReg(*I.getPointerOperand());
2891  Register Val = getOrCreateVReg(*I.getValOperand());
2892 
2893  unsigned Opcode = 0;
2894  switch (I.getOperation()) {
2895  default:
2896  return false;
2897  case AtomicRMWInst::Xchg:
2898  Opcode = TargetOpcode::G_ATOMICRMW_XCHG;
2899  break;
2900  case AtomicRMWInst::Add:
2901  Opcode = TargetOpcode::G_ATOMICRMW_ADD;
2902  break;
2903  case AtomicRMWInst::Sub:
2904  Opcode = TargetOpcode::G_ATOMICRMW_SUB;
2905  break;
2906  case AtomicRMWInst::And:
2907  Opcode = TargetOpcode::G_ATOMICRMW_AND;
2908  break;
2909  case AtomicRMWInst::Nand:
2910  Opcode = TargetOpcode::G_ATOMICRMW_NAND;
2911  break;
2912  case AtomicRMWInst::Or:
2913  Opcode = TargetOpcode::G_ATOMICRMW_OR;
2914  break;
2915  case AtomicRMWInst::Xor:
2916  Opcode = TargetOpcode::G_ATOMICRMW_XOR;
2917  break;
2918  case AtomicRMWInst::Max:
2919  Opcode = TargetOpcode::G_ATOMICRMW_MAX;
2920  break;
2921  case AtomicRMWInst::Min:
2922  Opcode = TargetOpcode::G_ATOMICRMW_MIN;
2923  break;
2924  case AtomicRMWInst::UMax:
2925  Opcode = TargetOpcode::G_ATOMICRMW_UMAX;
2926  break;
2927  case AtomicRMWInst::UMin:
2928  Opcode = TargetOpcode::G_ATOMICRMW_UMIN;
2929  break;
2930  case AtomicRMWInst::FAdd:
2931  Opcode = TargetOpcode::G_ATOMICRMW_FADD;
2932  break;
2933  case AtomicRMWInst::FSub:
2934  Opcode = TargetOpcode::G_ATOMICRMW_FSUB;
2935  break;
2936  case AtomicRMWInst::FMax:
2937  Opcode = TargetOpcode::G_ATOMICRMW_FMAX;
2938  break;
2939  case AtomicRMWInst::FMin:
2940  Opcode = TargetOpcode::G_ATOMICRMW_FMIN;
2941  break;
2942  }
2943 
2944  MIRBuilder.buildAtomicRMW(
2945  Opcode, Res, Addr, Val,
2946  *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
2947  Flags, MRI->getType(Val), getMemOpAlign(I),
2948  I.getAAMetadata(), nullptr, I.getSyncScopeID(),
2949  I.getOrdering()));
2950  return true;
2951 }
2952 
2953 bool IRTranslator::translateFence(const User &U,
2954  MachineIRBuilder &MIRBuilder) {
2955  const FenceInst &Fence = cast<FenceInst>(U);
2956  MIRBuilder.buildFence(static_cast<unsigned>(Fence.getOrdering()),
2957  Fence.getSyncScopeID());
2958  return true;
2959 }
2960 
2961 bool IRTranslator::translateFreeze(const User &U,
2962  MachineIRBuilder &MIRBuilder) {
2963  const ArrayRef<Register> DstRegs = getOrCreateVRegs(U);
2964  const ArrayRef<Register> SrcRegs = getOrCreateVRegs(*U.getOperand(0));
2965 
2966  assert(DstRegs.size() == SrcRegs.size() &&
2967  "Freeze with different source and destination type?");
2968 
2969  for (unsigned I = 0; I < DstRegs.size(); ++I) {
2970  MIRBuilder.buildFreeze(DstRegs[I], SrcRegs[I]);
2971  }
2972 
2973  return true;
2974 }
2975 
2976 void IRTranslator::finishPendingPhis() {
2977 #ifndef NDEBUG
2978  DILocationVerifier Verifier;
2979  GISelObserverWrapper WrapperObserver(&Verifier);
2980  RAIIDelegateInstaller DelInstall(*MF, &WrapperObserver);
2981 #endif // ifndef NDEBUG
2982  for (auto &Phi : PendingPHIs) {
2983  const PHINode *PI = Phi.first;
2984  ArrayRef<MachineInstr *> ComponentPHIs = Phi.second;
2985  MachineBasicBlock *PhiMBB = ComponentPHIs[0]->getParent();
2986  EntryBuilder->setDebugLoc(PI->getDebugLoc());
2987 #ifndef NDEBUG
2988  Verifier.setCurrentInst(PI);
2989 #endif // ifndef NDEBUG
2990 
2992  for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
2993  auto IRPred = PI->getIncomingBlock(i);
2994  ArrayRef<Register> ValRegs = getOrCreateVRegs(*PI->getIncomingValue(i));
2995  for (auto *Pred : getMachinePredBBs({IRPred, PI->getParent()})) {
2996  if (SeenPreds.count(Pred) || !PhiMBB->isPredecessor(Pred))
2997  continue;
2998  SeenPreds.insert(Pred);
2999  for (unsigned j = 0; j < ValRegs.size(); ++j) {
3000  MachineInstrBuilder MIB(*MF, ComponentPHIs[j]);
3001  MIB.addUse(ValRegs[j]);
3002  MIB.addMBB(Pred);
3003  }
3004  }
3005  }
3006  }
3007 }
3008 
3009 bool IRTranslator::translate(const Instruction &Inst) {
3010  CurBuilder->setDebugLoc(Inst.getDebugLoc());
3011  CurBuilder->setPCSections(Inst.getMetadata(LLVMContext::MD_pcsections));
3012 
3013  auto &TLI = *MF->getSubtarget().getTargetLowering();
3014  if (TLI.fallBackToDAGISel(Inst))
3015  return false;
3016 
3017  switch (Inst.getOpcode()) {
3018 #define HANDLE_INST(NUM, OPCODE, CLASS) \
3019  case Instruction::OPCODE: \
3020  return translate##OPCODE(Inst, *CurBuilder.get());
3021 #include "llvm/IR/Instruction.def"
3022  default:
3023  return false;
3024  }
3025 }
3026 
3027 bool IRTranslator::translate(const Constant &C, Register Reg) {
3028  // We only emit constants into the entry block from here. To prevent jumpy
3029  // debug behaviour remove debug line.
3030  if (auto CurrInstDL = CurBuilder->getDL())
3031  EntryBuilder->setDebugLoc(DebugLoc());
3032 
3033  if (auto CI = dyn_cast<ConstantInt>(&C))
3034  EntryBuilder->buildConstant(Reg, *CI);
3035  else if (auto CF = dyn_cast<ConstantFP>(&C))
3036  EntryBuilder->buildFConstant(Reg, *CF);
3037  else if (isa<UndefValue>(C))
3038  EntryBuilder->buildUndef(Reg);
3039  else if (isa<ConstantPointerNull>(C))
3040  EntryBuilder->buildConstant(Reg, 0);
3041  else if (auto GV = dyn_cast<GlobalValue>(&C))
3042  EntryBuilder->buildGlobalValue(Reg, GV);
3043  else if (auto CAZ = dyn_cast<ConstantAggregateZero>(&C)) {
3044  if (!isa<FixedVectorType>(CAZ->getType()))
3045  return false;
3046  // Return the scalar if it is a <1 x Ty> vector.
3047  unsigned NumElts = CAZ->getElementCount().getFixedValue();
3048  if (NumElts == 1)
3049  return translateCopy(C, *CAZ->getElementValue(0u), *EntryBuilder);
3051  for (unsigned I = 0; I < NumElts; ++I) {
3052  Constant &Elt = *CAZ->getElementValue(I);
3053  Ops.push_back(getOrCreateVReg(Elt));
3054  }
3055  EntryBuilder->buildBuildVector(Reg, Ops);
3056  } else if (auto CV = dyn_cast<ConstantDataVector>(&C)) {
3057  // Return the scalar if it is a <1 x Ty> vector.
3058  if (CV->getNumElements() == 1)
3059  return translateCopy(C, *CV->getElementAsConstant(0), *EntryBuilder);
3061  for (unsigned i = 0; i < CV->getNumElements(); ++i) {
3062  Constant &Elt = *CV->getElementAsConstant(i);
3063  Ops.push_back(getOrCreateVReg(Elt));
3064  }
3065  EntryBuilder->buildBuildVector(Reg, Ops);
3066  } else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
3067  switch(CE->getOpcode()) {
3068 #define HANDLE_INST(NUM, OPCODE, CLASS) \
3069  case Instruction::OPCODE: \
3070  return translate##OPCODE(*CE, *EntryBuilder.get());
3071 #include "llvm/IR/Instruction.def"
3072  default:
3073  return false;
3074  }
3075  } else if (auto CV = dyn_cast<ConstantVector>(&C)) {
3076  if (CV->getNumOperands() == 1)
3077  return translateCopy(C, *CV->getOperand(0), *EntryBuilder);
3079  for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
3080  Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
3081  }
3082  EntryBuilder->buildBuildVector(Reg, Ops);
3083  } else if (auto *BA = dyn_cast<BlockAddress>(&C)) {
3084  EntryBuilder->buildBlockAddress(Reg, BA);
3085  } else
3086  return false;
3087 
3088  return true;
3089 }
3090 
3091 bool IRTranslator::finalizeBasicBlock(const BasicBlock &BB,
3093  for (auto &BTB : SL->BitTestCases) {
3094  // Emit header first, if it wasn't already emitted.
3095  if (!BTB.Emitted)
3096  emitBitTestHeader(BTB, BTB.Parent);
3097 
3098  BranchProbability UnhandledProb = BTB.Prob;
3099  for (unsigned j = 0, ej = BTB.Cases.size(); j != ej; ++j) {
3100  UnhandledProb -= BTB.Cases[j].ExtraProb;
3101  // Set the current basic block to the mbb we wish to insert the code into
3102  MachineBasicBlock *MBB = BTB.Cases[j].ThisBB;
3103  // If all cases cover a contiguous range, it is not necessary to jump to
3104  // the default block after the last bit test fails. This is because the
3105  // range check during bit test header creation has guaranteed that every
3106  // case here doesn't go outside the range. In this case, there is no need
3107  // to perform the last bit test, as it will always be true. Instead, make
3108  // the second-to-last bit-test fall through to the target of the last bit
3109  // test, and delete the last bit test.
3110 
3111  MachineBasicBlock *NextMBB;
3112  if ((BTB.ContiguousRange || BTB.FallthroughUnreachable) && j + 2 == ej) {
3113  // Second-to-last bit-test with contiguous range: fall through to the
3114  // target of the final bit test.
3115  NextMBB = BTB.Cases[j + 1].TargetBB;
3116  } else if (j + 1 == ej) {
3117  // For the last bit test, fall through to Default.
3118  NextMBB = BTB.Default;
3119  } else {
3120  // Otherwise, fall through to the next bit test.
3121  NextMBB = BTB.Cases[j + 1].ThisBB;
3122  }
3123 
3124  emitBitTestCase(BTB, NextMBB, UnhandledProb, BTB.Reg, BTB.Cases[j], MBB);
3125 
3126  if ((BTB.ContiguousRange || BTB.FallthroughUnreachable) && j + 2 == ej) {
3127  // We need to record the replacement phi edge here that normally
3128  // happens in emitBitTestCase before we delete the case, otherwise the
3129  // phi edge will be lost.
3130  addMachineCFGPred({BTB.Parent->getBasicBlock(),
3131  BTB.Cases[ej - 1].TargetBB->getBasicBlock()},
3132  MBB);
3133  // Since we're not going to use the final bit test, remove it.
3134  BTB.Cases.pop_back();
3135  break;
3136  }
3137  }
3138  // This is "default" BB. We have two jumps to it. From "header" BB and from
3139  // last "case" BB, unless the latter was skipped.
3140  CFGEdge HeaderToDefaultEdge = {BTB.Parent->getBasicBlock(),
3141  BTB.Default->getBasicBlock()};
3142  addMachineCFGPred(HeaderToDefaultEdge, BTB.Parent);
3143  if (!BTB.ContiguousRange) {
3144  addMachineCFGPred(HeaderToDefaultEdge, BTB.Cases.back().ThisBB);
3145  }
3146  }
3147  SL->BitTestCases.clear();
3148 
3149  for (auto &JTCase : SL->JTCases) {
3150  // Emit header first, if it wasn't already emitted.
3151  if (!JTCase.first.Emitted)
3152  emitJumpTableHeader(JTCase.second, JTCase.first, JTCase.first.HeaderBB);
3153 
3154  emitJumpTable(JTCase.second, JTCase.second.MBB);
3155  }
3156  SL->JTCases.clear();
3157 
3158  for (auto &SwCase : SL->SwitchCases)
3159  emitSwitchCase(SwCase, &CurBuilder->getMBB(), *CurBuilder);
3160  SL->SwitchCases.clear();
3161 
3162  // Check if we need to generate stack-protector guard checks.
3163  StackProtector &SP = getAnalysis<StackProtector>();
3164  if (SP.shouldEmitSDCheck(BB)) {
3165  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
3166  bool FunctionBasedInstrumentation =
3168  SPDescriptor.initialize(&BB, &MBB, FunctionBasedInstrumentation);
3169  }
3170  // Handle stack protector.
3171  if (SPDescriptor.shouldEmitFunctionBasedCheckStackProtector()) {
3172  LLVM_DEBUG(dbgs() << "Unimplemented stack protector case\n");
3173  return false;
3174  } else if (SPDescriptor.shouldEmitStackProtector()) {
3175  MachineBasicBlock *ParentMBB = SPDescriptor.getParentMBB();
3176  MachineBasicBlock *SuccessMBB = SPDescriptor.getSuccessMBB();
3177 
3178  // Find the split point to split the parent mbb. At the same time copy all
3179  // physical registers used in the tail of parent mbb into virtual registers
3180  // before the split point and back into physical registers after the split
3181  // point. This prevents us needing to deal with Live-ins and many other
3182  // register allocation issues caused by us splitting the parent mbb. The
3183  // register allocator will clean up said virtual copies later on.
3185  ParentMBB, *MF->getSubtarget().getInstrInfo());
3186 
3187  // Splice the terminator of ParentMBB into SuccessMBB.
3188  SuccessMBB->splice(SuccessMBB->end(), ParentMBB, SplitPoint,
3189  ParentMBB->end());
3190 
3191  // Add compare/jump on neq/jump to the parent BB.
3192  if (!emitSPDescriptorParent(SPDescriptor, ParentMBB))
3193  return false;
3194 
3195  // CodeGen Failure MBB if we have not codegened it yet.
3196  MachineBasicBlock *FailureMBB = SPDescriptor.getFailureMBB();
3197  if (FailureMBB->empty()) {
3198  if (!emitSPDescriptorFailure(SPDescriptor, FailureMBB))
3199  return false;
3200  }
3201 
3202  // Clear the Per-BB State.
3203  SPDescriptor.resetPerBBState();
3204  }
3205  return true;
3206 }
3207 
3208 bool IRTranslator::emitSPDescriptorParent(StackProtectorDescriptor &SPD,
3209  MachineBasicBlock *ParentBB) {
3210  CurBuilder->setInsertPt(*ParentBB, ParentBB->end());
3211  // First create the loads to the guard/stack slot for the comparison.
3212  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
3213  Type *PtrIRTy = Type::getInt8PtrTy(MF->getFunction().getContext());
3214  const LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
3215  LLT PtrMemTy = getLLTForMVT(TLI.getPointerMemTy(*DL));
3216 
3217  MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
3218  int FI = MFI.getStackProtectorIndex();
3219 
3220  Register Guard;
3221  Register StackSlotPtr = CurBuilder->buildFrameIndex(PtrTy, FI).getReg(0);
3222  const Module &M = *ParentBB->getParent()->getFunction().getParent();
3223  Align Align = DL->getPrefTypeAlign(Type::getInt8PtrTy(M.getContext()));
3224 
3225  // Generate code to load the content of the guard slot.
3226  Register GuardVal =
3227  CurBuilder
3228  ->buildLoad(PtrMemTy, StackSlotPtr,
3231  .getReg(0);
3232 
3233  if (TLI.useStackGuardXorFP()) {
3234  LLVM_DEBUG(dbgs() << "Stack protector xor'ing with FP not yet implemented");
3235  return false;
3236  }
3237 
3238  // Retrieve guard check function, nullptr if instrumentation is inlined.
3239  if (const Function *GuardCheckFn = TLI.getSSPStackGuardCheck(M)) {
3240  // This path is currently untestable on GlobalISel, since the only platform
3241  // that needs this seems to be Windows, and we fall back on that currently.
3242  // The code still lives here in case that changes.
3243  // Silence warning about unused variable until the code below that uses
3244  // 'GuardCheckFn' is enabled.
3245  (void)GuardCheckFn;
3246  return false;
3247 #if 0
3248  // The target provides a guard check function to validate the guard value.
3249  // Generate a call to that function with the content of the guard slot as
3250  // argument.
3251  FunctionType *FnTy = GuardCheckFn->getFunctionType();
3252  assert(FnTy->getNumParams() == 1 && "Invalid function signature");
3253  ISD::ArgFlagsTy Flags;
3254  if (GuardCheckFn->hasAttribute(1, Attribute::AttrKind::InReg))
3255  Flags.setInReg();
3256  CallLowering::ArgInfo GuardArgInfo(
3257  {GuardVal, FnTy->getParamType(0), {Flags}});
3258 
3260  Info.OrigArgs.push_back(GuardArgInfo);
3261  Info.CallConv = GuardCheckFn->getCallingConv();
3262  Info.Callee = MachineOperand::CreateGA(GuardCheckFn, 0);
3263  Info.OrigRet = {Register(), FnTy->getReturnType()};
3264  if (!CLI->lowerCall(MIRBuilder, Info)) {
3265  LLVM_DEBUG(dbgs() << "Failed to lower call to stack protector check\n");
3266  return false;
3267  }
3268  return true;
3269 #endif
3270  }
3271 
3272  // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD.
3273  // Otherwise, emit a volatile load to retrieve the stack guard value.
3274  if (TLI.useLoadStackGuardNode()) {
3275  Guard =
3277  getStackGuard(Guard, *CurBuilder);
3278  } else {
3279  // TODO: test using android subtarget when we support @llvm.thread.pointer.
3280  const Value *IRGuard = TLI.getSDagStackGuard(M);
3281  Register GuardPtr = getOrCreateVReg(*IRGuard);
3282 
3283  Guard = CurBuilder
3284  ->buildLoad(PtrMemTy, GuardPtr,
3288  .getReg(0);
3289  }
3290 
3291  // Perform the comparison.
3292  auto Cmp =
3293  CurBuilder->buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), Guard, GuardVal);
3294  // If the guard/stackslot do not equal, branch to failure MBB.
3295  CurBuilder->buildBrCond(Cmp, *SPD.getFailureMBB());
3296  // Otherwise branch to success MBB.
3297  CurBuilder->buildBr(*SPD.getSuccessMBB());
3298  return true;
3299 }
3300 
3301 bool IRTranslator::emitSPDescriptorFailure(StackProtectorDescriptor &SPD,
3302  MachineBasicBlock *FailureBB) {
3303  CurBuilder->setInsertPt(*FailureBB, FailureBB->end());
3304  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
3305 
3306  const RTLIB::Libcall Libcall = RTLIB::STACKPROTECTOR_CHECK_FAIL;
3307  const char *Name = TLI.getLibcallName(Libcall);
3308 
3310  Info.CallConv = TLI.getLibcallCallingConv(Libcall);
3312  Info.OrigRet = {Register(), Type::getVoidTy(MF->getFunction().getContext()),
3313  0};
3314  if (!CLI->lowerCall(*CurBuilder, Info)) {
3315  LLVM_DEBUG(dbgs() << "Failed to lower call to stack protector fail\n");
3316  return false;
3317  }
3318 
3319  // On PS4/PS5, the "return address" must still be within the calling
3320  // function, even if it's at the very end, so emit an explicit TRAP here.
3321  // WebAssembly needs an unreachable instruction after a non-returning call,
3322  // because the function return type can be different from __stack_chk_fail's
3323  // return type (void).
3324  const TargetMachine &TM = MF->getTarget();
3325  if (TM.getTargetTriple().isPS() || TM.getTargetTriple().isWasm()) {
3326  LLVM_DEBUG(dbgs() << "Unhandled trap emission for stack protector fail\n");
3327  return false;
3328  }
3329  return true;
3330 }
3331 
3332 void IRTranslator::finalizeFunction() {
3333  // Release the memory used by the different maps we
3334  // needed during the translation.
3335  PendingPHIs.clear();
3336  VMap.reset();
3337  FrameIndices.clear();
3338  MachinePreds.clear();
3339  // MachineIRBuilder::DebugLoc can outlive the DILocation it holds. Clear it
3340  // to avoid accessing free’d memory (in runOnMachineFunction) and to avoid
3341  // destroying it twice (in ~IRTranslator() and ~LLVMContext())
3342  EntryBuilder.reset();
3343  CurBuilder.reset();
3344  FuncInfo.clear();
3345  SPDescriptor.resetPerFunctionState();
3346 }
3347 
3348 /// Returns true if a BasicBlock \p BB within a variadic function contains a
3349 /// variadic musttail call.
3350 static bool checkForMustTailInVarArgFn(bool IsVarArg, const BasicBlock &BB) {
3351  if (!IsVarArg)
3352  return false;
3353 
3354  // Walk the block backwards, because tail calls usually only appear at the end
3355  // of a block.
3356  return llvm::any_of(llvm::reverse(BB), [](const Instruction &I) {
3357  const auto *CI = dyn_cast<CallInst>(&I);
3358  return CI && CI->isMustTailCall();
3359  });
3360 }
3361 
3363  MF = &CurMF;
3364  const Function &F = MF->getFunction();
3366  getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
3367  // Set the CSEConfig and run the analysis.
3368  GISelCSEInfo *CSEInfo = nullptr;
3369  TPC = &getAnalysis<TargetPassConfig>();
3370  bool EnableCSE = EnableCSEInIRTranslator.getNumOccurrences()
3372  : TPC->isGISelCSEEnabled();
3373 
3374  if (EnableCSE) {
3375  EntryBuilder = std::make_unique<CSEMIRBuilder>(CurMF);
3376  CSEInfo = &Wrapper.get(TPC->getCSEConfig());
3377  EntryBuilder->setCSEInfo(CSEInfo);
3378  CurBuilder = std::make_unique<CSEMIRBuilder>(CurMF);
3379  CurBuilder->setCSEInfo(CSEInfo);
3380  } else {
3381  EntryBuilder = std::make_unique<MachineIRBuilder>();
3382  CurBuilder = std::make_unique<MachineIRBuilder>();
3383  }
3384  CLI = MF->getSubtarget().getCallLowering();
3385  CurBuilder->setMF(*MF);
3386  EntryBuilder->setMF(*MF);
3387  MRI = &MF->getRegInfo();
3388  DL = &F.getParent()->getDataLayout();
3389  ORE = std::make_unique<OptimizationRemarkEmitter>(&F);
3390  const TargetMachine &TM = MF->getTarget();
3391  TM.resetTargetOptions(F);
3392  EnableOpts = OptLevel != CodeGenOpt::None && !skipFunction(F);
3393  FuncInfo.MF = MF;
3394  if (EnableOpts) {
3395  AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
3396  FuncInfo.BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
3397  } else {
3398  AA = nullptr;
3399  FuncInfo.BPI = nullptr;
3400  }
3401 
3402  AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(
3403  MF->getFunction());
3404  LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
3405  FuncInfo.CanLowerReturn = CLI->checkReturnTypeForCallConv(*MF);
3406 
3407  const auto &TLI = *MF->getSubtarget().getTargetLowering();
3408 
3409  SL = std::make_unique<GISelSwitchLowering>(this, FuncInfo);
3410  SL->init(TLI, TM, *DL);
3411 
3412 
3413 
3414  assert(PendingPHIs.empty() && "stale PHIs");
3415 
3416  // Targets which want to use big endian can enable it using
3417  // enableBigEndian()
3418  if (!DL->isLittleEndian() && !CLI->enableBigEndian()) {
3419  // Currently we don't properly handle big endian code.
3420  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
3421  F.getSubprogram(), &F.getEntryBlock());
3422  R << "unable to translate in big endian mode";
3423  reportTranslationError(*MF, *TPC, *ORE, R);
3424  }
3425 
3426  // Release the per-function state when we return, whether we succeeded or not.
3427  auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
3428 
3429  // Setup a separate basic-block for the arguments and constants
3430  MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
3431  MF->push_back(EntryBB);
3432  EntryBuilder->setMBB(*EntryBB);
3433 
3434  DebugLoc DbgLoc = F.getEntryBlock().getFirstNonPHI()->getDebugLoc();
3435  SwiftError.setFunction(CurMF);
3436  SwiftError.createEntriesInEntryBlock(DbgLoc);
3437 
3438  bool IsVarArg = F.isVarArg();
3439  bool HasMustTailInVarArgFn = false;
3440 
3441  // Create all blocks, in IR order, to preserve the layout.
3442  for (const BasicBlock &BB: F) {
3443  auto *&MBB = BBToMBB[&BB];
3444 
3445  MBB = MF->CreateMachineBasicBlock(&BB);
3446  MF->push_back(MBB);
3447 
3448  if (BB.hasAddressTaken())
3449  MBB->setAddressTakenIRBlock(const_cast<BasicBlock *>(&BB));
3450 
3451  if (!HasMustTailInVarArgFn)
3452  HasMustTailInVarArgFn = checkForMustTailInVarArgFn(IsVarArg, BB);
3453  }
3454 
3455  MF->getFrameInfo().setHasMustTailInVarArgFunc(HasMustTailInVarArgFn);
3456 
3457  // Make our arguments/constants entry block fallthrough to the IR entry block.
3458  EntryBB->addSuccessor(&getMBB(F.front()));
3459 
3460  if (CLI->fallBackToDAGISel(*MF)) {
3461  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
3462  F.getSubprogram(), &F.getEntryBlock());
3463  R << "unable to lower function: " << ore::NV("Prototype", F.getType());
3464  reportTranslationError(*MF, *TPC, *ORE, R);
3465  return false;
3466  }
3467 
3468  // Lower the actual args into this basic block.
3469  SmallVector<ArrayRef<Register>, 8> VRegArgs;
3470  for (const Argument &Arg: F.args()) {
3471  if (DL->getTypeStoreSize(Arg.getType()).isZero())
3472  continue; // Don't handle zero sized types.
3473  ArrayRef<Register> VRegs = getOrCreateVRegs(Arg);
3474  VRegArgs.push_back(VRegs);
3475 
3476  if (Arg.hasSwiftErrorAttr()) {
3477  assert(VRegs.size() == 1 && "Too many vregs for Swift error");
3478  SwiftError.setCurrentVReg(EntryBB, SwiftError.getFunctionArg(), VRegs[0]);
3479  }
3480  }
3481 
3482  if (!CLI->lowerFormalArguments(*EntryBuilder, F, VRegArgs, FuncInfo)) {
3483  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
3484  F.getSubprogram(), &F.getEntryBlock());
3485  R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
3486  reportTranslationError(*MF, *TPC, *ORE, R);
3487  return false;
3488  }
3489 
3490  // Need to visit defs before uses when translating instructions.
3491  GISelObserverWrapper WrapperObserver;
3492  if (EnableCSE && CSEInfo)
3493  WrapperObserver.addObserver(CSEInfo);
3494  {
3496 #ifndef NDEBUG
3497  DILocationVerifier Verifier;
3498  WrapperObserver.addObserver(&Verifier);
3499 #endif // ifndef NDEBUG
3500  RAIIDelegateInstaller DelInstall(*MF, &WrapperObserver);
3501  RAIIMFObserverInstaller ObsInstall(*MF, WrapperObserver);
3502  for (const BasicBlock *BB : RPOT) {
3503  MachineBasicBlock &MBB = getMBB(*BB);
3504  // Set the insertion point of all the following translations to
3505  // the end of this basic block.
3506  CurBuilder->setMBB(MBB);
3507  HasTailCall = false;
3508  for (const Instruction &Inst : *BB) {
3509  // If we translated a tail call in the last step, then we know
3510  // everything after the call is either a return, or something that is
3511  // handled by the call itself. (E.g. a lifetime marker or assume
3512  // intrinsic.) In this case, we should stop translating the block and
3513  // move on.
3514  if (HasTailCall)
3515  break;
3516 #ifndef NDEBUG
3517  Verifier.setCurrentInst(&Inst);
3518 #endif // ifndef NDEBUG
3519  if (translate(Inst))
3520  continue;
3521 
3522  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
3523  Inst.getDebugLoc(), BB);
3524  R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
3525 
3526  if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
3527  std::string InstStrStorage;
3528  raw_string_ostream InstStr(InstStrStorage);
3529  InstStr << Inst;
3530 
3531  R << ": '" << InstStr.str() << "'";
3532  }
3533 
3534  reportTranslationError(*MF, *TPC, *ORE, R);
3535  return false;
3536  }
3537 
3538  if (!finalizeBasicBlock(*BB, MBB)) {
3539  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
3540  BB->getTerminator()->getDebugLoc(), BB);
3541  R << "unable to translate basic block";
3542  reportTranslationError(*MF, *TPC, *ORE, R);
3543  return false;
3544  }
3545  }
3546 #ifndef NDEBUG
3547  WrapperObserver.removeObserver(&Verifier);
3548 #endif
3549  }
3550 
3551  finishPendingPhis();
3552 
3553  SwiftError.propagateVRegs();
3554 
3555  // Merge the argument lowering and constants block with its single
3556  // successor, the LLVM-IR entry block. We want the basic block to
3557  // be maximal.
3558  assert(EntryBB->succ_size() == 1 &&
3559  "Custom BB used for lowering should have only one successor");
3560  // Get the successor of the current entry block.
3561  MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
3562  assert(NewEntryBB.pred_size() == 1 &&
3563  "LLVM-IR entry block has a predecessor!?");
3564  // Move all the instruction from the current entry block to the
3565  // new entry block.
3566  NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
3567  EntryBB->end());
3568 
3569  // Update the live-in information for the new entry block.
3570  for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
3571  NewEntryBB.addLiveIn(LiveIn);
3572  NewEntryBB.sortUniqueLiveIns();
3573 
3574  // Get rid of the now empty basic block.
3575  EntryBB->removeSuccessor(&NewEntryBB);
3576  MF->remove(EntryBB);
3577  MF->deleteMachineBasicBlock(EntryBB);
3578 
3579  assert(&MF->front() == &NewEntryBB &&
3580  "New entry wasn't next in the list of basic block!");
3581 
3582  // Initialize stack protector information.
3583  StackProtector &SP = getAnalysis<StackProtector>();
3585 
3586  return false;
3587 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
llvm::EHPersonality::MSVC_CXX
@ MSVC_CXX
i
i
Definition: README.txt:29
llvm::HexagonInstrInfo::isTailCall
bool isTailCall(const MachineInstr &MI) const override
Definition: HexagonInstrInfo.cpp:2644
llvm::MachineFunction::remove
void remove(iterator MBBI)
Definition: MachineFunction.h:885
llvm::isAsynchronousEHPersonality
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
Definition: EHPersonalities.h:49
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:182
Int32Ty
IntegerType * Int32Ty
Definition: NVVMIntrRange.cpp:67
llvm::DbgVariableIntrinsic::getExpression
DIExpression * getExpression() const
Definition: IntrinsicInst.h:262
llvm::TargetLoweringBase::getPointerMemTy
virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
Definition: TargetLowering.h:360
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:354
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
AssumptionCache.h
llvm::MachineIRBuilder::buildInsertVectorElement
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
Definition: MachineIRBuilder.cpp:797
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
StackProtector.h
llvm::Type::isSized
bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:269
llvm::OptimizationRemarkMissed
Diagnostic information for missed-optimization remarks.
Definition: DiagnosticInfo.h:735
llvm::Function::isIntrinsic
bool isIntrinsic() const
isIntrinsic - Returns true if the function's name starts with "llvm.".
Definition: Function.h:210
llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
Definition: TargetLowering.h:1819
LowLevelType.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::SwitchCG::sortAndRangeify
void sortAndRangeify(CaseClusterVector &Clusters)
Sort Clusters and merge adjacent cases.
Definition: SwitchLoweringUtils.cpp:464
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::DbgDeclareInst::getAddress
Value * getAddress() const
Definition: IntrinsicInst.h:315
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MachineIRBuilder::buildFMul
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1541
llvm::MachineIRBuilder::buildAtomicRMW
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:860
llvm::MachineIRBuilder::setDebugLoc
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
Definition: MachineIRBuilder.h:365
llvm::CmpInst::ICMP_EQ
@ ICMP_EQ
equal
Definition: InstrTypes.h:740
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:141
llvm::ReturnInst
Return a value (possibly void), from a function.
Definition: Instructions.h:3052
TargetFrameLowering.h
llvm::MachineIRBuilder::buildICmp
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
Definition: MachineIRBuilder.cpp:771
llvm::MemoryOpRemark
Definition: MemoryOpRemark.h:34
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:434
llvm::GISelCSEAnalysisWrapperPass
The actual analysis pass wrapper.
Definition: CSEInfo.h:220
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:209
llvm::generic_gep_type_iterator
Definition: GetElementPtrTypeIterator.h:31
llvm::RecurKind::FMul
@ FMul
Product of floats.
Metadata.h
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1225
llvm::Type::getInt8PtrTy
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:291
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::MachineModuleInfo::getContext
const MCContext & getContext() const
Definition: MachineModuleInfo.h:143
llvm::AllocaInst::getAlign
Align getAlign() const
Return the alignment of the memory that is being allocated by the instruction.
Definition: Instructions.h:122
CallLowering.h
llvm::BasicBlock::getParent
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:104
llvm::InlineAsmLowering
Definition: InlineAsmLowering.h:28
IntrinsicInst.h
ceil
We have fiadd patterns now but the followings have the same cost and complexity We need a way to specify the later is more profitable def def The FP stackifier should handle simple permutates to reduce number of shuffle e g ceil
Definition: README-FPStack.txt:54
llvm::GlobalValue::dropLLVMManglingEscape
static StringRef dropLLVMManglingEscape(StringRef Name)
If the given string begins with the GlobalValue name mangling escape character '\1',...
Definition: GlobalValue.h:554
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
Loads.h
llvm::SwitchCG::CaseBlock
This structure is used to communicate between SelectionDAGBuilder and SDISel for the code generation ...
Definition: SwitchLoweringUtils.h:109
llvm::SwitchCG::CaseBlock::DbgLoc
DebugLoc DbgLoc
Definition: SwitchLoweringUtils.h:138
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::Function
Definition: Function.h:60
llvm::SwitchCG::SwitchWorkList
SmallVector< SwitchWorkListItem, 4 > SwitchWorkList
Definition: SwitchLoweringUtils.h:247
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition: MachineFunction.h:608
llvm::lower_bound
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1727
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1224
llvm::MachineInstr::copyFlagsFromInstruction
static uint16_t copyFlagsFromInstruction(const Instruction &I)
Definition: MachineInstr.cpp:532
Pass.h
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:53
llvm::BlockFrequencyInfoWrapperPass
Legacy analysis pass which computes BlockFrequencyInfo.
Definition: BlockFrequencyInfo.h:138
llvm::AtomicRMWInst::Xor
@ Xor
*p = old ^ v
Definition: Instructions.h:741
llvm::StackProtector::copyToMachineFrameInfo
void copyToMachineFrameInfo(MachineFrameInfo &MFI) const
Definition: StackProtector.cpp:599
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:673
llvm::M68k::addMemOperand
static const MachineInstrBuilder & addMemOperand(const MachineInstrBuilder &MIB, int FI, int Offset=0)
Definition: M68kInstrBuilder.h:76
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:628
minimum
Should compile r2 movcc movcs str strb mov lr r1 movcs movcc mov lr r1 str mov mov cmp r1 movlo r2 str bx lr r0 mov mov cmp r0 movhs r2 mov r1 bx lr Some of the NEON intrinsics may be appropriate for more general either as target independent intrinsics or perhaps elsewhere in the ARM backend Some of them may also be lowered to target independent and perhaps some new SDNodes could be added For minimum
Definition: README.txt:489
GetElementPtrTypeIterator.h
llvm::MachineIRBuilder::buildSplatVector
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
Definition: MachineIRBuilder.cpp:664
High
uint64_t High
Definition: NVVMIntrRange.cpp:61
llvm::ReturnInst::getReturnValue
Value * getReturnValue() const
Convenience accessor. Returns null if there is no return value.
Definition: Instructions.h:3097
llvm::AllocaInst::getType
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:101
llvm::ilist_node_with_parent::getNextNode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1181
Wrapper
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
Definition: AMDGPUAliasAnalysis.cpp:31
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:266
InlineAsm.h
llvm::LandingPadInst
The landingpad instruction holds all of the information necessary to generate correct exception handl...
Definition: Instructions.h:2951
llvm::StackProtectorDescriptor::getSuccessMBB
MachineBasicBlock * getSuccessMBB()
Definition: CodeGenCommonISel.h:169
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::enumerate
detail::enumerator< R > enumerate(R &&TheRange)
Given an input range, returns a new range whose values are are pair (A,B) such that A is the 0-based ...
Definition: STLExtras.h:2068
llvm::SwitchCG::JumpTableHeader::FallthroughUnreachable
bool FallthroughUnreachable
Definition: SwitchLoweringUtils.h:186
llvm::CallBase::isInlineAsm
bool isInlineAsm() const
Check if this call is an inline asm statement.
Definition: InstrTypes.h:1464
llvm::DataLayout::getTypeStoreSize
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Definition: DataLayout.h:474
llvm::FunctionPass::skipFunction
bool skipFunction(const Function &F) const
Optional passes call this function to check whether the pass should be skipped.
Definition: Pass.cpp:173
llvm::Function::getSubprogram
DISubprogram * getSubprogram() const
Get the attached subprogram.
Definition: Metadata.cpp:1583
llvm::InlineAsmLowering::lowerInlineAsm
bool lowerInlineAsm(MachineIRBuilder &MIRBuilder, const CallBase &CB, std::function< ArrayRef< Register >(const Value &Val)> GetOrCreateVRegs) const
Lower the given inline asm call instruction GetOrCreateVRegs is a callback to materialize a register ...
Definition: InlineAsmLowering.cpp:269
llvm::GISelCSEInfo
The CSE Analysis object.
Definition: CSEInfo.h:69
ErrorHandling.h
llvm::Function::getEntryBlock
const BasicBlock & getEntryBlock() const
Definition: Function.h:710
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::IRTranslator::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: IRTranslator.cpp:3362
llvm::SwiftErrorValueTracking::createEntriesInEntryBlock
bool createEntriesInEntryBlock(DebugLoc DbgLoc)
Create initial definitions of swifterror values in the entry block of the current function.
Definition: SwiftErrorValueTracking.cpp:115
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::SwiftErrorValueTracking::propagateVRegs
void propagateVRegs()
Propagate assigned swifterror vregs through a function, synthesizing PHI nodes when needed to maintai...
Definition: SwiftErrorValueTracking.cpp:147
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1033
llvm::CmpInst::ICMP_NE
@ ICMP_NE
not equal
Definition: InstrTypes.h:741
R600_InstFlag::FC
@ FC
Definition: R600Defines.h:32
llvm::TargetLoweringBase::getTgtMemIntrinsic
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: TargetLowering.h:1065
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::MachineBasicBlock::setSuccProbability
void setSuccProbability(succ_iterator I, BranchProbability Prob)
Set successor probability of a given iterator.
Definition: MachineBasicBlock.cpp:1466
llvm::MachineIRBuilder::buildZExtOrTrunc
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:532
ValueTracking.h
llvm::SwitchCG::CC_JumpTable
@ CC_JumpTable
A cluster of cases suitable for jump table lowering.
Definition: SwitchLoweringUtils.h:36
OptimizationRemarkEmitter.h
llvm::TargetLoweringBase::getLibcallName
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
Definition: TargetLowering.h:3112
MachineBasicBlock.h
llvm::SwitchCG::SwitchWorkListItem
Definition: SwitchLoweringUtils.h:239
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::DataLayout::getStructLayout
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
Definition: DataLayout.cpp:678
llvm::GISelObserverWrapper::removeObserver
void removeObserver(GISelChangeObserver *O)
Definition: GISelChangeObserver.h:78
reportTranslationError
IRTranslator LLVM IR static false void reportTranslationError(MachineFunction &MF, const TargetPassConfig &TPC, OptimizationRemarkEmitter &ORE, OptimizationRemarkMissed &R)
Definition: IRTranslator.cpp:111
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:652
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:320
llvm::MachineIRBuilder::buildDbgLabel
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
Definition: MachineIRBuilder.cpp:125
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
llvm::BranchProbability::getZero
static BranchProbability getZero()
Definition: BranchProbability.h:49
llvm::diagnoseDontCall
void diagnoseDontCall(const CallInst &CI)
Definition: DiagnosticInfo.cpp:410
TargetInstrInfo.h
llvm::CallBase::getAttributes
AttributeList getAttributes() const
Return the parameter attributes for this call.
Definition: InstrTypes.h:1474
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::TargetOptions::TrapUnreachable
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:280
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:142
llvm::TargetLoweringBase::getExceptionPointerRegister
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: TargetLowering.h:1826
llvm::MachineIRBuilder::buildFPTrunc
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPTRUNC Op.
Definition: MachineIRBuilder.cpp:765
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:872
llvm::copy
OutputIt copy(R &&Range, OutputIt Out)
Definition: STLExtras.h:1641
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::CallLowering::supportSwiftError
virtual bool supportSwiftError() const
Definition: CallLowering.h:441
llvm::SwitchCG::CaseClusterIt
CaseClusterVector::iterator CaseClusterIt
Definition: SwitchLoweringUtils.h:87
llvm::DbgVariableIntrinsic::getVariable
DILocalVariable * getVariable() const
Definition: IntrinsicInst.h:258
llvm::Optional
Definition: APInt.h:33
llvm::FenceInst
An instruction for ordering other memory operations.
Definition: Instructions.h:433
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::ore::NV
DiagnosticInfoOptimizationBase::Argument NV
Definition: OptimizationRemarkEmitter.h:136
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:880
llvm::TargetLoweringBase::getVectorIdxTy
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
Definition: TargetLowering.h:407
llvm::successors
auto successors(MachineBasicBlock *BB)
Definition: MachineSSAContext.h:29
llvm::CmpInst::ICMP_SLE
@ ICMP_SLE
signed less or equal
Definition: InstrTypes.h:749
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::FunctionType::getNumParams
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:39
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::Intrinsic::not_intrinsic
@ not_intrinsic
Definition: Intrinsics.h:45
MachineIRBuilder.h
STLExtras.h
llvm::CallBase::arg_begin
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1316
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::LoadInst::getPointerOperand
Value * getPointerOperand()
Definition: Instructions.h:261
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:458
llvm::SwitchCG::JumpTableHeader::Last
APInt Last
Definition: SwitchLoweringUtils.h:182
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:123
llvm::MachineFrameInfo::CreateVariableSizedObject
int CreateVariableSizedObject(Align Alignment, const AllocaInst *Alloca)
Notify the MachineFrameInfo object that a variable sized object has been created.
Definition: MachineFrameInfo.cpp:74
llvm::RAIIMFObserverInstaller
A simple RAII based Observer installer.
Definition: GISelChangeObserver.h:120
llvm::MachineIRBuilder::buildFence
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
Definition: MachineIRBuilder.cpp:982
llvm::LoadInst::getAlign
Align getAlign() const
Return the alignment of the access that is being performed.
Definition: Instructions.h:217
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineIRBuilder::buildDynStackAlloc
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
Definition: MachineIRBuilder.cpp:134
llvm::FunctionLoweringInfo::CanLowerReturn
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
Definition: FunctionLoweringInfo.h:62
llvm::Type::getInt32Ty
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:239
llvm::AtomicRMWInst::FMin
@ FMin
*p = minnum(old, v) minnum matches the behavior of llvm.minnum.
Definition: Instructions.h:763
llvm::MachineIRBuilder::getDebugLoc
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
Definition: MachineIRBuilder.h:368
llvm::SwitchCG::CaseBlock::CmpMHS
const Value * CmpMHS
Definition: SwitchLoweringUtils.h:127
llvm::APIntOps::umin
const APInt & umin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be unsigned.
Definition: APInt.h:2137
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:167
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::MDNode::get
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1400
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:293
llvm::commonAlignment
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:213
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetPassConfig::isGISelCSEEnabled
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
Definition: TargetPassConfig.cpp:1572
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:265
MachineRegisterInfo.h
llvm::MachineOperand::CreateES
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
Definition: MachineOperand.h:867
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
llvm::gep_type_end
gep_type_iterator gep_type_end(const User *GEP)
Definition: GetElementPtrTypeIterator.h:130
floor
We have fiadd patterns now but the followings have the same cost and complexity We need a way to specify the later is more profitable def def The FP stackifier should handle simple permutates to reduce number of shuffle e g floor
Definition: README-FPStack.txt:54
llvm::DILabel::isValidLocationForIntrinsic
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this label.
Definition: DebugInfoMetadata.h:3204
AliasAnalysis.h
llvm::getLLTForType
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
Definition: LowLevelType.cpp:20
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
CSEInfo.h
llvm::classifyEHPersonality
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Definition: EHPersonalities.cpp:22
llvm::LLT::fixed_vector
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:74
EnableCSEInIRTranslator
static cl::opt< bool > EnableCSEInIRTranslator("enable-cse-in-irtranslator", cl::desc("Should enable CSE in irtranslator"), cl::Optional, cl::init(false))
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:762
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineBasicBlock::pred_size
unsigned pred_size() const
Definition: MachineBasicBlock.h:365
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
TargetLowering.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::AllocaInst::isStaticAlloca
bool isStaticAlloca() const
Return true if this alloca is in the entry block of the function and is a constant size.
Definition: Instructions.cpp:1417
llvm::Instruction::getOpcode
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:164
llvm::FenceInst::getSyncScopeID
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this fence instruction.
Definition: Instructions.h:469
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:865
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::RAIIDelegateInstaller
A simple RAII based Delegate installer.
Definition: GISelChangeObserver.h:108
llvm::MachineIRBuilder::buildAtomicCmpXchgWithSuccess
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
Definition: MachineIRBuilder.cpp:808
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
TargetMachine.h
llvm::SwitchCG::CaseBlock::FalseBB
MachineBasicBlock * FalseBB
Definition: SwitchLoweringUtils.h:130
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MachineIRBuilder::buildExtractVectorElement
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Definition: MachineIRBuilder.cpp:803
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:904
InlineAsmLowering.h
llvm::CmpInst::isFPPredicate
bool isFPPredicate() const
Definition: InstrTypes.h:826
Constants.h
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::CallLowering::checkReturnTypeForCallConv
bool checkReturnTypeForCallConv(MachineFunction &MF) const
Toplevel function to check the return type based on the target calling convention.
Definition: CallLowering.cpp:953
llvm::MachineIRBuilder::buildShl
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1571
llvm::PHINode::getIncomingValue
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
Definition: Instructions.h:2795
llvm::DbgValueInst
This represents the llvm.dbg.value instruction.
Definition: IntrinsicInst.h:352
llvm::AllocaInst::getAllocatedType
Type * getAllocatedType() const
Return the type that is being allocated by the instruction.
Definition: Instructions.h:115
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:333
llvm::BranchProbabilityInfoWrapperPass
Legacy analysis pass which computes BranchProbabilityInfo.
Definition: BranchProbabilityInfo.h:438
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineBasicBlock::succ_end
succ_iterator succ_end()
Definition: MachineBasicBlock.h:371
llvm::User
Definition: User.h:44
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:62
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
Intrinsics.h
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::ConstrainedFPIntrinsic
This is the common base class for constrained floating point intrinsics.
Definition: IntrinsicInst.h:513
llvm::CmpInst::ICMP_ULE
@ ICMP_ULE
unsigned less or equal
Definition: InstrTypes.h:745
llvm::getLLTForMVT
LLT getLLTForMVT(MVT Ty)
Get a rough equivalent of an LLT for a given MVT.
Definition: LowLevelType.cpp:64
llvm::StackProtectorDescriptor
Encapsulates all of the information needed to generate a stack protector check, and signals to isel w...
Definition: CodeGenCommonISel.h:114
round
static uint64_t round(uint64_t Acc, uint64_t Input)
Definition: xxhash.cpp:56
InstrTypes.h
llvm::CallBase::getCalledFunction
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
Definition: InstrTypes.h:1396
llvm::TargetMachine::getIntrinsicInfo
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
Definition: TargetMachine.h:212
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3446
llvm::CallLowering::lowerFormalArguments
virtual bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: CallLowering.h:538
MCContext.h
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::CallLowering::lowerReturn
virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
Definition: CallLowering.h:506
llvm::FCmpInst
This instruction compares its operands according to the predicate given to the constructor.
Definition: Instructions.h:1360
llvm::BranchProbabilityInfo
Analysis providing branch probability information.
Definition: BranchProbabilityInfo.h:113
llvm::StackProtector
Definition: StackProtector.h:36
canThrow
static bool canThrow(const Value *V)
Definition: WebAssemblyLowerEmscriptenEHSjLj.cpp:394
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
b
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Definition: README.txt:418
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::MachineIRBuilder::buildFCmp
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_FCMP PredOp0, Op1.
Definition: MachineIRBuilder.cpp:778
false
Definition: StackSlotColoring.cpp:141
CSEMIRBuilder.h
llvm::succ_size
unsigned succ_size(MachineBasicBlock *BB)
Definition: MachineSSAContext.h:31
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineFunction::deleteMachineBasicBlock
void deleteMachineBasicBlock(MachineBasicBlock *MBB)
DeleteMachineBasicBlock - Delete the given MachineBasicBlock.
Definition: MachineFunction.cpp:445
llvm::MachineFunction::getTypeIDFor
unsigned getTypeIDFor(const GlobalValue *TI)
Return the type id for the specified typeinfo. This is function wide.
Definition: MachineFunction.cpp:866
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::isUIntN
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:422
llvm::Constant::getAllOnesValue
static Constant * getAllOnesValue(Type *Ty)
Definition: Constants.cpp:395
llvm::Type::isTokenTy
bool isTokenTy() const
Return true if this is 'token'.
Definition: Type.h:193
llvm::MachineBasicBlock::RegisterMaskPair
Pair of physical register and lane mask.
Definition: MachineBasicBlock.h:100
llvm::Instruction
Definition: Instruction.h:42
llvm::SwiftErrorValueTracking::getOrCreateVRegUseAt
Register getOrCreateVRegUseAt(const Instruction *, const MachineBasicBlock *, const Value *)
Get or create the swifterror value virtual register for a use of a swifterror by an instruction.
Definition: SwiftErrorValueTracking.cpp:65
llvm::DataLayout::getABITypeAlign
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:829
llvm::SwitchCG::CaseBlock::PredInfoPair::NoCmp
bool NoCmp
Definition: SwitchLoweringUtils.h:114
llvm::AllocaInst::getArraySize
const Value * getArraySize() const
Get the number of elements allocated.
Definition: Instructions.h:97
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::AtomicRMWInst::Nand
@ Nand
*p = ~(old & v)
Definition: Instructions.h:737
llvm::TargetLoweringBase::getSDagStackGuard
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: TargetLoweringBase.cpp:1977
SwitchLoweringUtils.h
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:402
llvm::ThreadPriority::Low
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
llvm::LocationSize::precise
static LocationSize precise(uint64_t Value)
Definition: MemoryLocation.h:101
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:879
llvm::DILocalVariable::isValidLocationForIntrinsic
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Definition: DebugInfoMetadata.h:3137
llvm::StringRef::data
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:131
llvm::FunctionLoweringInfo::BPI
BranchProbabilityInfo * BPI
Definition: FunctionLoweringInfo.h:58
llvm::MachineIRBuilder::buildAnd
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
Definition: MachineIRBuilder.h:1600
IR
Statically lint checks LLVM IR
Definition: Lint.cpp:746
llvm::Instruction::getAAMetadata
AAMDNodes getAAMetadata() const
Returns the AA metadata for this instruction.
Definition: Metadata.cpp:1462
llvm::DbgVariableIntrinsic::hasArgList
bool hasArgList() const
Definition: IntrinsicInst.h:232
llvm::SwitchCG::CaseBlock::FalseProb
BranchProbability FalseProb
Definition: SwitchLoweringUtils.h:141
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
getOffsetFromIndices
static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL)
Definition: IRTranslator.cpp:1379
llvm::ISD::ArgFlagsTy::setInReg
void setInReg()
Definition: TargetCallingConv.h:80
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
PatternMatch.h
llvm::BasicBlock::getFirstNonPHI
const Instruction * getFirstNonPHI() const
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Definition: BasicBlock.cpp:209
llvm::MachineIRBuilder::buildIndirectDbgValue
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
Definition: MachineIRBuilder.cpp:63
llvm::AtomicRMWInst::FMax
@ FMax
*p = maxnum(old, v) maxnum matches the behavior of llvm.maxnum.
Definition: Instructions.h:759
llvm::FixedVectorType::get
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:684
llvm::CallInst::isTailCall
bool isTailCall() const
Definition: Instructions.h:1668
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:155
llvm::Metadata
Root of the metadata hierarchy.
Definition: Metadata.h:62
llvm::MachineIRBuilder::buildBrCond
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
Definition: MachineIRBuilder.cpp:370
llvm::AtomicRMWInst::Xchg
@ Xchg
*p = v
Definition: Instructions.h:729
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
llvm::PHINode::getNumIncomingValues
unsigned getNumIncomingValues() const
Return the number of incoming edges.
Definition: Instructions.h:2791
llvm::AtomicRMWInst::Add
@ Add
*p = old + v
Definition: Instructions.h:731
llvm::EHPersonality::Wasm_CXX
@ Wasm_CXX
llvm::LoadInst::getSyncScopeID
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this load instruction.
Definition: Instructions.h:236
Statepoint.h
llvm::MachineFunction::addInvoke
void addInvoke(MachineBasicBlock *LandingPad, MCSymbol *BeginLabel, MCSymbol *EndLabel)
Provide the begin and end labels of an invoke style call and associate it with a try landing pad bloc...
Definition: MachineFunction.cpp:741
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:110
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::SwitchCG::JumpTableHeader::First
APInt First
Definition: SwitchLoweringUtils.h:181
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineIRBuilder::buildBrIndirect
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
Definition: MachineIRBuilder.cpp:272
LowLevelTypeImpl.h
llvm::Instruction::getMetadata
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:271
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
CFG.h
llvm::maxnum
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
Definition: APFloat.h:1307
llvm::AllocaInst::isSwiftError
bool isSwiftError() const
Return true if this alloca is used as a swifterror argument to a call.
Definition: Instructions.h:147
llvm::BranchInst::getCondition
Value * getCondition() const
Definition: Instructions.h:3215
llvm::PatternMatch::m_ExtractElt
TwoOps_match< Val_t, Idx_t, Instruction::ExtractElement > m_ExtractElt(const Val_t &Val, const Idx_t &Idx)
Matches ExtractElementInst.
Definition: PatternMatch.h:1492
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:791
llvm::CmpInst::FCMP_FALSE
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:721
llvm::InvokeInst
Invoke instruction.
Definition: Instructions.h:3811
llvm::CmpInst
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:709
llvm::sort
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1538
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:49
llvm::MachineInstr::copyIRFlags
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
Definition: MachineInstr.cpp:570
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::MachineIRBuilder::buildBr
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
Definition: MachineIRBuilder.cpp:268
llvm::DataLayout::getPrefTypeAlign
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Definition: DataLayout.cpp:838
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:607
llvm::StackProtectorDescriptor::resetPerBBState
void resetPerBBState()
Reset state that changes when we handle different basic blocks.
Definition: CodeGenCommonISel.h:152
llvm::MachineBasicBlock::succ_iterator
std::vector< MachineBasicBlock * >::iterator succ_iterator
Definition: MachineBasicBlock.h:343
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
Verifier
verify safepoint Safepoint IR Verifier
Definition: SafepointIRVerifier.cpp:251
llvm::AtomicRMWInst::UMin
@ UMin
*p = old <unsigned v ? old : v
Definition: Instructions.h:749
BasicBlock.h
llvm::cl::opt< bool >
llvm::MachineFunction::push_back
void push_back(MachineBasicBlock *MBB)
Definition: MachineFunction.h:870
llvm::StackProtectorDescriptor::getFailureMBB
MachineBasicBlock * getFailureMBB()
Definition: CodeGenCommonISel.h:170
llvm::MachineIRBuilder::buildFAdd
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FADD Op0, Op1.
Definition: MachineIRBuilder.h:1674
llvm::MachineFrameInfo::setHasMustTailInVarArgFunc
void setHasMustTailInVarArgFunc(bool B)
Definition: MachineFrameInfo.h:627
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:298
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::pdb::PDB_ColorItem::Address
@ Address
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:501
llvm::MachineIRBuilder::buildBrJT
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
Definition: MachineIRBuilder.cpp:277
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:165
llvm::getUnderlyingObjects
void getUnderlyingObjects(const Value *V, SmallVectorImpl< const Value * > &Objects, LoopInfo *LI=nullptr, unsigned MaxLookup=6)
This method is similar to getUnderlyingObject except that it can look through phi and select instruct...
Definition: ValueTracking.cpp:4532
llvm::MachineBasicBlock::setAddressTakenIRBlock
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
Definition: MachineBasicBlock.h:251
llvm::MachineIRBuilder::buildSExtOrTrunc
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:527
BranchProbabilityInfo.h
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:221
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::StackProtectorDescriptor::shouldEmitStackProtector
bool shouldEmitStackProtector() const
Returns true if all fields of the stack protector descriptor are initialized implying that we should/...
Definition: CodeGenCommonISel.h:120
llvm::AtomicRMWInst::Sub
@ Sub
*p = old - v
Definition: Instructions.h:733
llvm::CallBase::countOperandBundlesOfType
unsigned countOperandBundlesOfType(StringRef Name) const
Return the number of operand bundles with the tag Name attached to this instruction.
Definition: InstrTypes.h:2003
llvm::ICmpInst
This instruction compares its operands according to the predicate given to the constructor.
Definition: Instructions.h:1186
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::TargetLibraryInfoWrapperPass
Definition: TargetLibraryInfo.h:468
uint64_t
RuntimeLibcalls.h
llvm::PatternMatch::m_LogicalOr
LogicalOp_match< LHS, RHS, Instruction::Or > m_LogicalOr(const LHS &L, const RHS &R)
Matches L || R either in the form of L | R or L ? true : R.
Definition: PatternMatch.h:2555
llvm::SwitchCG::CaseBlock::PredInfo
struct PredInfoPair PredInfo
Definition: SwitchLoweringUtils.h:121
llvm::ExtractTypeInfo
GlobalValue * ExtractTypeInfo(Value *V)
ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
Definition: Analysis.cpp:165
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:644
llvm::DbgDeclareInst
This represents the llvm.dbg.declare instruction.
Definition: IntrinsicInst.h:313
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
llvm::DbgLabelInst
This represents the llvm.dbg.label instruction.
Definition: IntrinsicInst.h:375
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::SwitchCG::CaseBlock::TrueProb
BranchProbability TrueProb
Definition: SwitchLoweringUtils.h:141
llvm::MachineBasicBlock::setIsEHPad
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
Definition: MachineBasicBlock.h:580
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::DbgLabelInst::getLabel
DILabel * getLabel() const
Definition: IntrinsicInst.h:377
llvm::MachineIRBuilder::buildMul
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
Definition: MachineIRBuilder.h:1516
llvm::MachineIRBuilder::getInsertPt
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
Definition: MachineIRBuilder.h:310
llvm::DataLayout::isLittleEndian
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:244
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MachineIRBuilder::buildPtrAdd
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
Definition: MachineIRBuilder.cpp:190
llvm::TargetLoweringBase::getAtomicMemOperandFlags
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2247
llvm::TargetOptions::NoTrapAfterNoreturn
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
Definition: TargetOptions.h:284
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::FunctionType::getParamType
Type * getParamType(unsigned i) const
Parameter type accessors.
Definition: DerivedTypes.h:135
Analysis.h
llvm::AtomicRMWInst::Min
@ Min
*p = old <signed v ? old : v
Definition: Instructions.h:745
llvm::countTrailingOnes
unsigned countTrailingOnes(T Value, ZeroBehavior ZB=ZB_Width)
Count the number of ones from the least significant bit to the first zero bit.
Definition: MathExtras.h:491
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:439
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
llvm::SwitchCG::CaseBlock::CmpRHS
const Value * CmpRHS
Definition: SwitchLoweringUtils.h:127
llvm::AtomicRMWInst::Or
@ Or
*p = old | v
Definition: Instructions.h:739
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:439
llvm::TargetLoweringBase::isFMAFasterThanFMulAndFAdd
virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: TargetLowering.h:2939
TargetPassConfig.h
MemoryOpRemark.h
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::MachineIRBuilder::buildSelect
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
Definition: MachineIRBuilder.cpp:787
llvm::SwitchCG::CaseBlock::ThisBB
MachineBasicBlock * ThisBB
Definition: SwitchLoweringUtils.h:133
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
llvm::BranchProbability::isUnknown
bool isUnknown() const
Definition: BranchProbability.h:47
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
maximum
Should compile r2 movcc movcs str strb mov lr r1 movcs movcc mov lr r1 str mov mov cmp r1 movlo r2 str bx lr r0 mov mov cmp r0 movhs r2 mov r1 bx lr Some of the NEON intrinsics may be appropriate for more general either as target independent intrinsics or perhaps elsewhere in the ARM backend Some of them may also be lowered to target independent and perhaps some new SDNodes could be added For maximum
Definition: README.txt:489
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MachineIRBuilder::buildConstDbgValue
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
Definition: MachineIRBuilder.cpp:90
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:120
llvm::Instruction::hasMetadata
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
Definition: Instruction.h:253
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:890
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:296
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:369
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::DataLayout::getPointerABIAlignment
Align getPointerABIAlignment(unsigned AS) const
Layout pointer alignment.
Definition: DataLayout.cpp:700
memcpy
<%struct.s * > cast struct s *S to sbyte *< sbyte * > sbyte uint cast struct s *agg result to sbyte *< sbyte * > sbyte uint cast struct s *memtmp to sbyte *< sbyte * > sbyte uint ret void llc ends up issuing two memcpy or custom lower memcpy(of small size) to be ldmia/stmia. I think option 2 is better but the current register allocator cannot allocate a chunk of registers at a time. A feasible temporary solution is to use specific physical registers at the lowering time for small(<
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::IndexedInstrProf::HashT::Last
@ Last
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::TargetLoweringBase::getStoreMemOperandFlags
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2231
llvm::FenceInst::getOrdering
AtomicOrdering getOrdering() const
Returns the ordering constraint of this fence instruction.
Definition: Instructions.h:458
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::SelectInst
This class represents the LLVM 'select' instruction.
Definition: Instructions.h:1737
llvm::SwitchCG::JumpTableHeader
Definition: SwitchLoweringUtils.h:180
llvm::Type::isVoidTy
bool isVoidTy() const
Return true if this is 'void'.
Definition: Type.h:139
MachineModuleInfo.h
llvm::WinEH::EncodingType::CE
@ CE
Windows NT (Windows on ARM)
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:186
llvm::SwiftErrorValueTracking::setFunction
void setFunction(MachineFunction &MF)
Initialize data structures for specified new function.
Definition: SwiftErrorValueTracking.cpp:79
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
llvm::MachineIRBuilder::buildFMA
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
Build and insert Res = G_FMA Op0, Op1, Op2.
Definition: MachineIRBuilder.h:1695
llvm::SwitchCG::CC_Range
@ CC_Range
A cluster of adjacent case labels with the same destination, or just one case.
Definition: SwitchLoweringUtils.h:34
llvm::MCContext::getOrCreateFrameAllocSymbol
MCSymbol * getOrCreateFrameAllocSymbol(StringRef FuncName, unsigned Idx)
Gets a symbol that will be defined to the final stack offset of a local variable after codegen.
Definition: MCContext.cpp:220
llvm::EHPersonality::CoreCLR
@ CoreCLR
llvm::CallBase::arg_end
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1322
llvm::Function::getFunction
const Function & getFunction() const
Definition: Function.h:135
llvm::BranchInst::isUnconditional
bool isUnconditional() const
Definition: Instructions.h:3212
llvm::TargetLoweringBase::useStackGuardXorFP
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
Definition: TargetLowering.h:1883
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::BranchProbabilityInfo::getEdgeProbability
BranchProbability getEdgeProbability(const BasicBlock *Src, unsigned IndexInSuccessors) const
Get an edge's probability, relative to other out-edges of the Src.
Definition: BranchProbabilityInfo.cpp:1100
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::TargetSubtargetInfo::getCallLowering
virtual const CallLowering * getCallLowering() const
Definition: TargetSubtargetInfo.h:101
llvm::CmpInst::isIntPredicate
bool isIntPredicate() const
Definition: InstrTypes.h:827
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:383
llvm::APIntOps::smin
const APInt & smin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be signed.
Definition: APInt.h:2127
llvm::AssumptionCacheTracker
An immutable pass that tracks lazily created AssumptionCache objects.
Definition: AssumptionCache.h:202
llvm::CallLowering::enableBigEndian
virtual bool enableBigEndian() const
For targets which want to use big-endian can enable it with enableBigEndian() hook.
Definition: CallLowering.h:586
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ConstrainedFPIntrinsic::getExceptionBehavior
Optional< fp::ExceptionBehavior > getExceptionBehavior() const
Definition: IntrinsicInst.cpp:245
llvm::StackProtector::shouldEmitSDCheck
bool shouldEmitSDCheck(const BasicBlock &BB) const
Definition: StackProtector.cpp:595
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1597
llvm::MachineOperand::CreateGA
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:859
DataLayout.h
llvm::MachineFunction::allocateShuffleMask
ArrayRef< int > allocateShuffleMask(ArrayRef< int > Mask)
Definition: MachineFunction.cpp:555
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:213
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:152
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1009
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI", false, false) INITIALIZE_PASS_END(IRTranslator
llvm::SwiftErrorValueTracking::getOrCreateVRegDefAt
Register getOrCreateVRegDefAt(const Instruction *, const MachineBasicBlock *, const Value *)
Get or create the swifterror value virtual register for a def of a swifterror by an instruction.
Definition: SwiftErrorValueTracking.cpp:50
llvm::SwitchCG::CaseClusterVector
std::vector< CaseCluster > CaseClusterVector
Definition: SwitchLoweringUtils.h:86
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::convertStrToRoundingMode
Optional< RoundingMode > convertStrToRoundingMode(StringRef)
Returns a valid RoundingMode enumerator when given a string that is valid as input in constrained int...
Definition: FPEnv.cpp:23
llvm::ConstantInt::isZero
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:194
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:288
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
llvm::MachineIRBuilder::buildFPExt
MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPEXT Op.
Definition: MachineIRBuilder.h:660
llvm::MemoryOpRemark::canHandle
static bool canHandle(const Instruction *I, const TargetLibraryInfo &TLI)
Definition: MemoryOpRemark.cpp:25
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::Value::getContext
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:994
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
IRTranslator.h
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
isSwiftError
static bool isSwiftError(const Value *V)
Definition: IRTranslator.cpp:1275
trunc
We have fiadd patterns now but the followings have the same cost and complexity We need a way to specify the later is more profitable def def The FP stackifier should handle simple permutates to reduce number of shuffle e g trunc
Definition: README-FPStack.txt:63
llvm::CallInst::isMustTailCall
bool isMustTailCall() const
Definition: Instructions.h:1673
llvm::SwitchCG::BitTestCase
Definition: SwitchLoweringUtils.h:195
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::LoadInst::getOrdering
AtomicOrdering getOrdering() const
Returns the ordering constraint of this load instruction.
Definition: Instructions.h:226
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::EHPersonality
EHPersonality
Definition: EHPersonalities.h:21
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:138
llvm::CallBase::paramHasAttr
bool paramHasAttr(unsigned ArgNo, Attribute::AttrKind Kind) const
Determine whether the argument or parameter has the given attribute.
Definition: Instructions.cpp:342
llvm::SwitchCG::BitTestBlock
Definition: SwitchLoweringUtils.h:208
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::StackProtectorDescriptor::resetPerFunctionState
void resetPerFunctionState()
Reset state that only changes when we switch functions.
Definition: CodeGenCommonISel.h:166
llvm::LLT::changeElementType
LLT changeElementType(LLT NewEltTy) const
If this type is a vector, return a vector with the same number of elements but the new element type.
Definition: LowLevelTypeImpl.h:173
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:715
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
llvm::Value::stripPointerCasts
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:685
llvm::MachineIRBuilder::materializePtrAdd
Optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
Definition: MachineIRBuilder.cpp:201
llvm::MachineIRBuilder::buildJumpTable
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
Definition: MachineIRBuilder.cpp:167
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::make_scope_exit
detail::scope_exit< std::decay_t< Callable > > make_scope_exit(Callable &&F)
Definition: ScopeExit.h:59
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
llvm::MachineBasicBlock::isPredecessor
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
Definition: MachineBasicBlock.cpp:920
llvm::SwitchCG::JumpTable
Definition: SwitchLoweringUtils.h:165
llvm::cl::Optional
@ Optional
Definition: CommandLine.h:115
llvm::StackProtectorDescriptor::getParentMBB
MachineBasicBlock * getParentMBB()
Definition: CodeGenCommonISel.h:168
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:145
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:572
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetPassConfig::getCSEConfig
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
Definition: TargetPassConfig.cpp:1576
llvm::computeValueLLTs
void computeValueLLTs(const DataLayout &DL, Type &Ty, SmallVectorImpl< LLT > &ValueTys, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
computeValueLLTs - Given an LLVM IR type, compute a sequence of LLTs that represent all the individua...
Definition: Analysis.cpp:129
llvm::TargetLoweringBase::getSSPStackGuardCheck
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Definition: TargetLoweringBase.cpp:1981
j
return j(j<< 16)
llvm::MachineFunctionProperties::Property::FailedISel
@ FailedISel
llvm::APIntOps::umax
const APInt & umax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be unsigned.
Definition: APInt.h:2142
llvm::DataLayout::getIntPtrType
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
Definition: DataLayout.cpp:842
Constant.h
DEBUG_TYPE
#define DEBUG_TYPE
Definition: IRTranslator.cpp:91
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::minnum
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
Definition: APFloat.h:1296
llvm::TargetLoweringBase::getExceptionSelectorRegister
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: TargetLowering.h:1833
llvm::ConstantInt::getTrue
static ConstantInt * getTrue(LLVMContext &Context)
Definition: Constants.cpp:827
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::Constant::getNullValue
static Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
Definition: Constants.cpp:350
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::IndirectBrInst::getAddress
Value * getAddress()
Definition: Instructions.h:3751
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:94
llvm::IRTranslator::ID
static char ID
Definition: IRTranslator.h:66
llvm::MachineBasicBlock::sortUniqueLiveIns
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
Definition: MachineBasicBlock.cpp:597
uint16_t
llvm::ConstrainedFPIntrinsic::isUnaryOp
bool isUnaryOp() const
Definition: IntrinsicInst.cpp:298
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:652
llvm::AtomicRMWInst::FSub
@ FSub
*p = old - v
Definition: Instructions.h:755
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::StructLayout::getElementOffset
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:652
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:152
llvm::LLVMContext::OB_deopt
@ OB_deopt
Definition: LLVMContext.h:89
llvm::X86::FirstMacroFusionInstKind::Cmp
@ Cmp
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1327
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::FPOpFusion::Strict
@ Strict
Definition: TargetOptions.h:39
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:596
llvm::CallBase::arg_size
unsigned arg_size() const
Definition: InstrTypes.h:1339
llvm::MachineIRBuilder::buildDirectDbgValue
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
Definition: MachineIRBuilder.cpp:50
llvm::ExtractValueInst
This instruction extracts a struct member or array element value from an aggregate value.
Definition: Instructions.h:2446
Success
#define Success
Definition: AArch64Disassembler.cpp:280
llvm::AtomicRMWInst::And
@ And
*p = old & v
Definition: Instructions.h:735
llvm::TargetRegisterInfo::getCustomEHPadPreservedMask
virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...
Definition: TargetRegisterInfo.h:492
llvm::FunctionLoweringInfo::clear
void clear()
clear - Clear out all the function-specific state.
Definition: FunctionLoweringInfo.cpp:353
Casting.h
llvm::pdb::PDB_LocType::Slot
@ Slot
DiagnosticInfo.h
Function.h
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:102
llvm::Type::getPointerTo
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:774
llvm::MachineRegisterInfo::addPhysRegsUsedFromRegMask
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
Definition: MachineRegisterInfo.h:881
powi
This is blocked on not handling X *X *X powi(X, 3)(see note above). The issue is that we end up getting t
llvm::SwitchCG::CaseBlock::CmpLHS
const Value * CmpLHS
Definition: SwitchLoweringUtils.h:127
llvm::log2
static double log2(double V)
Definition: AMDGPULibCalls.cpp:794
llvm::CallLowering::fallBackToDAGISel
virtual bool fallBackToDAGISel(const MachineFunction &MF) const
Definition: CallLowering.h:524
llvm::fp::ebIgnore
@ ebIgnore
This corresponds to "fpexcept.ignore".
Definition: FPEnv.h:39
llvm::TargetSubtargetInfo::getInlineAsmLowering
virtual const InlineAsmLowering * getInlineAsmLowering() const
Definition: TargetSubtargetInfo.h:103
llvm::ConstrainedFPIntrinsic::isTernaryOp
bool isTernaryOp() const
Definition: IntrinsicInst.cpp:309
MemRef
Definition: Lint.cpp:81
llvm::SmallSet::insert
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:178
llvm::MachineFrameInfo::setStackProtectorIndex
void setStackProtectorIndex(int I)
Definition: MachineFrameInfo.h:358
llvm::GISelCSEAnalysisWrapper
Simple wrapper that does the following.
Definition: CSEInfo.h:202
llvm::Instruction::hasAllowReassoc
bool hasAllowReassoc() const
Determine whether the allow-reassociation flag is set.
Definition: Instruction.cpp:280
llvm::MachineBasicBlock::normalizeSuccProbs
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
Definition: MachineBasicBlock.h:704
llvm::UnivariateLinearPolyBase::isZero
bool isZero() const
Definition: TypeSize.h:229
llvm::CallBase::getCalledOperand
Value * getCalledOperand() const
Definition: InstrTypes.h:1389
llvm::Function::getPersonalityFn
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1908
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::ReversePostOrderTraversal
Definition: PostOrderIterator.h:291
llvm::SwitchCG::CaseBlock::PredInfoPair::Pred
CmpInst::Predicate Pred
Definition: SwitchLoweringUtils.h:112
llvm::IndirectBrInst
Indirect Branch Instruction.
Definition: Instructions.h:3676
llvm::TargetLoweringBase::fallBackToDAGISel
virtual bool fallBackToDAGISel(const Instruction &Inst) const
Definition: TargetLowering.h:561
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::IRTranslator::IRTranslator
IRTranslator(CodeGenOpt::Level OptLevel=CodeGenOpt::None)
Definition: IRTranslator.cpp:128
AA
CodeGen.h
llvm::Instruction::BinaryOps
BinaryOps
Definition: Instruction.h:773
llvm::BasicBlock::back
const Instruction & back() const
Definition: BasicBlock.h:320
llvm::Type::getVoidTy
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:222
llvm::StackProtectorDescriptor::shouldEmitFunctionBasedCheckStackProtector
bool shouldEmitFunctionBasedCheckStackProtector() const
Definition: CodeGenCommonISel.h:124
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
Instructions.h
PostOrderIterator.h
llvm::FunctionLoweringInfo::MF
MachineFunction * MF
Definition: FunctionLoweringInfo.h:55
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:267
llvm::User::getNumOperands
unsigned getNumOperands() const
Definition: User.h:191
llvm::TargetSubtargetInfo::getTargetLowering
virtual const TargetLowering * getTargetLowering() const
Definition: TargetSubtargetInfo.h:97
llvm::MachineIRBuilder::buildIntrinsic
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
Definition: MachineIRBuilder.cpp:736
llvm::BranchProbability::normalizeProbabilities
static void normalizeProbabilities(ProbabilityIter Begin, ProbabilityIter End)
Definition: BranchProbability.h:205
SmallVector.h
llvm::PatternMatch::m_Specific
specificval_ty m_Specific(const Value *V)
Match if we have a specific specified value.
Definition: PatternMatch.h:772
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1018
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
llvm::Instruction::getDebugLoc
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
Definition: Instruction.h:354
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:745
User.h
MachineInstrBuilder.h
llvm::IRTranslator::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition: IRTranslator.cpp:169
llvm::GISelObserverWrapper::addObserver
void addObserver(GISelChangeObserver *O)
Definition: GISelChangeObserver.h:75
llvm::MachineInstr::NoUWrap
@ NoUWrap
Definition: MachineInstr.h:104
llvm::SwitchCG::JumpTableHeader::SValue
const Value * SValue
Definition: SwitchLoweringUtils.h:183
llvm::getMVTForLLT
MVT getMVTForLLT(LLT Ty)
Get a rough equivalent of an MVT for a given LLT.
Definition: LowLevelType.cpp:45
TargetIntrinsicInfo.h
llvm::CmpInst::ICMP_UGT
@ ICMP_UGT
unsigned greater than
Definition: InstrTypes.h:742
llvm::DbgValueInst::getValue
Value * getValue(unsigned OpIdx=0) const
Definition: IntrinsicInst.h:356
llvm::fp::ExceptionBehavior
ExceptionBehavior
Exception behavior used for floating point operations.
Definition: FPEnv.h:38
llvm::CallBase::getArgOperand
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1341
llvm::TargetLowering::useLoadStackGuardNode
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition: TargetLowering.h:5034
llvm::AAResultsWrapperPass
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Definition: AliasAnalysis.h:1308
llvm::Instruction::getParent
const BasicBlock * getParent() const
Definition: Instruction.h:91
llvm::SwitchCG::CaseBlock::TrueBB
MachineBasicBlock * TrueBB
Definition: SwitchLoweringUtils.h:130
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:126
llvm::MachineIRBuilder::buildSub
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Definition: MachineIRBuilder.h:1500
llvm::PHINode::getIncomingBlock
BasicBlock * getIncomingBlock(unsigned i) const
Return incoming basic block number i.
Definition: Instructions.h:2815
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::AtomicRMWInst::FAdd
@ FAdd
*p = old + v
Definition: Instructions.h:752
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:277
llvm::BasicBlock::getFirstNonPHIOrDbg
const Instruction * getFirstNonPHIOrDbg(bool SkipPseudoOp=true) const
Returns a pointer to the first instruction in this block that is not a PHINode or a debug intrinsic,...
Definition: BasicBlock.cpp:216
getConstrainedOpcode
static unsigned getConstrainedOpcode(Intrinsic::ID ID)
Definition: IRTranslator.cpp:1842
llvm::pdb::PDB_DataKind::Global
@ Global
llvm::PHINode
Definition: Instructions.h:2699
ScopeExit.h
llvm::StackProtectorDescriptor::initialize
void initialize(const BasicBlock *BB, MachineBasicBlock *MBB, bool FunctionBasedInstrumentation)
Initialize the stack protector descriptor structure for a new basic block.
Definition: CodeGenCommonISel.h:130
llvm::IRTranslator
Definition: IRTranslator.h:64
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::reverse
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:365
MachineOperand.h
llvm::SwitchCG::CC_BitTests
@ CC_BitTests
A cluster of cases suitable for bit test lowering.
Definition: SwitchLoweringUtils.h:38
llvm::GISelObserverWrapper
Simple wrapper observer that takes several observers, and calls each one for each event.
Definition: GISelChangeObserver.h:66
isValInBlock
static bool isValInBlock(const Value *V, const BasicBlock *BB)
Definition: IRTranslator.cpp:408
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1174
DerivedTypes.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:412
checkForMustTailInVarArgFn
static bool checkForMustTailInVarArgFn(bool IsVarArg, const BasicBlock &BB)
Returns true if a BasicBlock BB within a variadic function contains a variadic musttail call.
Definition: IRTranslator.cpp:3350
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1474
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MachineFrameInfo::getStackProtectorIndex
int getStackProtectorIndex() const
Return the index for the stack protector object.
Definition: MachineFrameInfo.h:357
llvm::MIPatternMatch::m_Not
BinaryOp_match< SrcTy, SpecificConstantMatch, TargetOpcode::G_XOR, true > m_Not(const SrcTy &&Src)
Matches a register not-ed by a G_XOR.
Definition: MIPatternMatch.h:696
llvm::Type::isAggregateType
bool isAggregateType() const
Return true if the type is an aggregate type.
Definition: Type.h:262
llvm::MachineIRBuilder::buildFreeze
MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_FREEZE Src.
Definition: MachineIRBuilder.h:1458
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
LLVMContext.h
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3278
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::Type::TypeID
TypeID
Definitions of all of the base types for the Type system.
Definition: Type.h:54
llvm::AllocaInst
an instruction to allocate memory on the stack
Definition: Instructions.h:59
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::MachineFunction::addLandingPad
MCSymbol * addLandingPad(MachineBasicBlock *LandingPad)
Add a new panding pad, and extract the exception handling information from the landingpad instruction...
Definition: MachineFunction.cpp:748
GISelChangeObserver.h
llvm::cl::desc
Definition: CommandLine.h:412
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:425
llvm::TargetLoweringBase::getValueType
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition: TargetLowering.h:1490
llvm::LLVMContext::OB_cfguardtarget
@ OB_cfguardtarget
Definition: LLVMContext.h:92
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3134
llvm::AtomicRMWInst::UMax
@ UMax
*p = old >unsigned v ? old : v
Definition: Instructions.h:747
raw_ostream.h
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1326
llvm::MachineIRBuilder::buildAdd
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
Definition: MachineIRBuilder.h:1483
MachineFunction.h
llvm::InsertValueInst
This instruction inserts a struct field of array element value into an aggregate value.
Definition: Instructions.h:2557
llvm::CmpInst::FCMP_TRUE
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:736
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::AttributeList::getFnAttr
Attribute getFnAttr(Attribute::AttrKind Kind) const
Return the attribute object that exists for the function.
Definition: Attributes.h:816
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
Value.h
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1282
llvm::findSplitPointForStackProtector
MachineBasicBlock::iterator findSplitPointForStackProtector(MachineBasicBlock *BB, const TargetInstrInfo &TII)
Find the split point at which to splice the end of BB into its success stack protector check machine ...
Definition: CodeGenCommonISel.cpp:127
llvm::raw_string_ostream::str
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:646
llvm::MIPatternMatch::m_OneUse
OneUse_match< SubPat > m_OneUse(const SubPat &SP)
Definition: MIPatternMatch.h:45
llvm::TargetLoweringBase::getLibcallCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:3134
InitializePasses.h
llvm::FunctionType::getReturnType
Type * getReturnType() const
Definition: DerivedTypes.h:124
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:510
TargetRegisterInfo.h
Debug.h
llvm::MachineFunction::setVariableDbgInfo
void setVariableDbgInfo(const DILocalVariable *Var, const DIExpression *Expr, int Slot, const DILocation *Loc)
Collect information used to emit debugging information of a variable.
Definition: MachineFunction.h:1225
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:153
llvm::APIntOps::smax
const APInt & smax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be signed.
Definition: APInt.h:2132
llvm::PatternMatch::m_LogicalAnd
LogicalOp_match< LHS, RHS, Instruction::And > m_LogicalAnd(const LHS &L, const RHS &R)
Matches L && R either in the form of L & R or L ? R : false.
Definition: PatternMatch.h:2537
llvm::SwiftErrorValueTracking::getFunctionArg
const Value * getFunctionArg() const
Get the (unique) function argument that was marked swifterror, or nullptr if this function has no swi...
Definition: SwiftErrorValueTracking.h:72
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:56
llvm::BranchInst::getSuccessor
BasicBlock * getSuccessor(unsigned i) const
Definition: Instructions.h:3227
llvm::MemoryLocation
Representation for a specific memory location.
Definition: MemoryLocation.h:210
llvm::CallBase::args
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
Definition: InstrTypes.h:1332
llvm::BasicBlock::const_iterator
InstListType::const_iterator const_iterator
Definition: BasicBlock.h:88
llvm::SwiftErrorValueTracking::setCurrentVReg
void setCurrentVReg(const MachineBasicBlock *MBB, const Value *, Register)
Set the swifterror virtual register in the VRegDefMap for this basic block.
Definition: SwiftErrorValueTracking.cpp:45
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::isDereferenceableAndAlignedPointer
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:199
llvm::MachineIRBuilder::buildCast
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
Definition: MachineIRBuilder.cpp:551
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:103
SmallSet.h
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::AtomicRMWInst::Max
@ Max
*p = old >signed v ? old : v
Definition: Instructions.h:743
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:506
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::CallLowering::lowerCall
virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: CallLowering.h:550