LLVM  14.0.0git
RetireControlUnit.cpp
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1 //===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file simulates the hardware responsible for retiring instructions.
11 ///
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/Support/Debug.h"
16 
17 #define DEBUG_TYPE "llvm-mca"
18 
19 namespace llvm {
20 namespace mca {
21 
23  : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
24  AvailableEntries(SM.isOutOfOrder() ? SM.MicroOpBufferSize : 0),
25  MaxRetirePerCycle(0) {
26  assert(SM.isOutOfOrder() &&
27  "RetireControlUnit is not available for in-order processors");
28  // Check if the scheduling model provides extra information about the machine
29  // processor. If so, then use that information to set the reorder buffer size
30  // and the maximum number of instructions retired per cycle.
31  if (SM.hasExtraProcessorInfo()) {
33  if (EPI.ReorderBufferSize)
34  AvailableEntries = EPI.ReorderBufferSize;
35  MaxRetirePerCycle = EPI.MaxRetirePerCycle;
36  }
37  NumROBEntries = AvailableEntries;
38  assert(NumROBEntries && "Invalid reorder buffer size!");
39  Queue.resize(2 * NumROBEntries);
40 }
41 
42 // Reserves a number of slots, and returns a new token.
44  const Instruction &Inst = *IR.getInstruction();
45  unsigned Entries = normalizeQuantity(Inst.getNumMicroOps());
46  assert((AvailableEntries >= Entries) && "Reorder Buffer unavailable!");
47 
48  unsigned TokenID = NextAvailableSlotIdx;
49  Queue[NextAvailableSlotIdx] = {IR, Entries, false};
50  NextAvailableSlotIdx += std::max(1U, Entries);
51  NextAvailableSlotIdx %= Queue.size();
52  assert(TokenID < UnhandledTokenID && "Invalid token ID");
53 
54  AvailableEntries -= Entries;
55  return TokenID;
56 }
57 
59  const RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
60 #ifndef NDEBUG
61  const Instruction *Inst = Current.IR.getInstruction();
62  assert(Inst && "Invalid RUToken in the RCU queue.");
63 #endif
64  return Current;
65 }
66 
67 unsigned RetireControlUnit::computeNextSlotIdx() const {
69  unsigned NextSlotIdx = CurrentInstructionSlotIdx + std::max(1U, Current.NumSlots);
70  return NextSlotIdx % Queue.size();
71 }
72 
74  return Queue[computeNextSlotIdx()];
75 }
76 
78  RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
79  Current.IR.getInstruction()->retire();
80 
81  // Update the slot index to be the next item in the circular queue.
82  CurrentInstructionSlotIdx += std::max(1U, Current.NumSlots);
83  CurrentInstructionSlotIdx %= Queue.size();
84  AvailableEntries += Current.NumSlots;
85  Current = { InstRef(), 0U, false };
86 }
87 
89  assert(Queue.size() > TokenID);
90  assert(Queue[TokenID].IR.getInstruction() && "Instruction was not dispatched!");
91  assert(Queue[TokenID].Executed == false && "Instruction already executed!");
92  Queue[TokenID].Executed = true;
93 }
94 
95 #ifndef NDEBUG
97  dbgs() << "Retire Unit: { Total ROB Entries =" << NumROBEntries
98  << ", Available ROB entries=" << AvailableEntries << " }\n";
99 }
100 #endif
101 
102 } // namespace mca
103 } // namespace llvm
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
RetireControlUnit.h
llvm::MCSchedModel::isOutOfOrder
bool isOutOfOrder() const
Return true if machine supports out of order execution.
Definition: MCSchedule.h:333
llvm::mca::RetireControlUnit::getCurrentToken
const RUToken & getCurrentToken() const
Definition: RetireControlUnit.cpp:58
llvm::mca::Instruction
An instruction propagated through the simulated instruction pipeline.
Definition: Instruction.h:569
llvm::mca::RetireControlUnit::RetireControlUnit
RetireControlUnit(const MCSchedModel &SM)
Definition: RetireControlUnit.cpp:22
llvm::MCExtraProcessorInfo::MaxRetirePerCycle
unsigned MaxRetirePerCycle
Definition: MCSchedule.h:181
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::mca::InstRef::getInstruction
Instruction * getInstruction()
Definition: Instruction.h:700
llvm::mca::RetireControlUnit::dump
void dump() const
Definition: RetireControlUnit.cpp:96
llvm::mca::RetireControlUnit::UnhandledTokenID
static const unsigned UnhandledTokenID
Definition: RetireControlUnit.h:109
llvm::MCSchedModel::getExtraProcessorInfo
const MCExtraProcessorInfo & getExtraProcessorInfo() const
Definition: MCSchedule.h:322
IR
Statically lint checks LLVM IR
Definition: Lint.cpp:744
llvm::MCExtraProcessorInfo::ReorderBufferSize
unsigned ReorderBufferSize
Definition: MCSchedule.h:179
llvm::MCSchedModel::hasExtraProcessorInfo
bool hasExtraProcessorInfo() const
Definition: MCSchedule.h:315
llvm::mca::RetireControlUnit::onInstructionExecuted
void onInstructionExecuted(unsigned TokenID)
Definition: RetireControlUnit.cpp:88
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::mca::RetireControlUnit::dispatch
unsigned dispatch(const InstRef &IS)
Definition: RetireControlUnit.cpp:43
llvm::mca::InstRef
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:686
llvm::mca::RetireControlUnit::consumeCurrentToken
void consumeCurrentToken()
Definition: RetireControlUnit.cpp:77
llvm::mca::InstructionBase::getNumMicroOps
unsigned getNumMicroOps() const
Definition: Instruction.h:531
llvm::mca::RetireControlUnit::peekNextToken
const RUToken & peekNextToken() const
Definition: RetireControlUnit.cpp:73
llvm::mca::Instruction::retire
void retire()
Definition: Instruction.h:663
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::mca::RetireControlUnit::RUToken::IR
InstRef IR
Definition: RetireControlUnit.h:52
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::mca::RetireControlUnit::RUToken
Definition: RetireControlUnit.h:51
llvm::mca::RetireControlUnit::RUToken::NumSlots
unsigned NumSlots
Definition: RetireControlUnit.h:53
Debug.h
llvm::MCExtraProcessorInfo
Provide extra details about the machine processor.
Definition: MCSchedule.h:177