LLVM 17.0.0git
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1//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// This file defines the classes used to describe a subtarget's machine model
10// for scheduling and other instruction cost heuristics.
17#include "llvm/Config/llvm-config.h"
19#include <cassert>
21namespace llvm {
23template <typename T> class ArrayRef;
24struct InstrItinerary;
25class MCSubtargetInfo;
26class MCInstrInfo;
27class MCInst;
28class InstrItineraryData;
30/// Define a kind of processor resource that will be modeled by the scheduler.
32 const char *Name;
33 unsigned NumUnits; // Number of resource of this kind
34 unsigned SuperIdx; // Index of the resources kind that contains this kind.
36 // Number of resources that may be buffered.
37 //
38 // Buffered resources (BufferSize != 0) may be consumed at some indeterminate
39 // cycle after dispatch. This should be used for out-of-order cpus when
40 // instructions that use this resource can be buffered in a reservaton
41 // station.
42 //
43 // Unbuffered resources (BufferSize == 0) always consume their resource some
44 // fixed number of cycles after dispatch. If a resource is unbuffered, then
45 // the scheduler will avoid scheduling instructions with conflicting resources
46 // in the same cycle. This is for in-order cpus, or the in-order portion of
47 // an out-of-order cpus.
50 // If the resource has sub-units, a pointer to the first element of an array
51 // of `NumUnits` elements containing the ProcResourceIdx of the sub units.
52 // nullptr if the resource does not have sub-units.
53 const unsigned *SubUnitsIdxBegin;
55 bool operator==(const MCProcResourceDesc &Other) const {
56 return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
57 && BufferSize == Other.BufferSize;
58 }
61/// Identify one of the processor resource kinds consumed by a particular
62/// scheduling class for the specified number of cycles.
66 /// Cycle at which the resource will be grabbed by an instruction,
67 /// relatively to the cycle in which the instruction is issued
68 /// (assuming no stalls inbetween).
72 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles &&
73 StartAtCycle == Other.StartAtCycle;
74 }
77/// Specify the latency in cpu cycles for a particular scheduling class and def
78/// index. -1 indicates an invalid latency. Heuristics would typically consider
79/// an instruction with invalid latency to have infinite latency. Also identify
80/// the WriteResources of this def. When the operand expands to a sequence of
81/// writes, this ID is the last write in the sequence.
83 int16_t Cycles;
87 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
88 }
91/// Specify the number of cycles allowed after instruction issue before a
92/// particular use operand reads its registers. This effectively reduces the
93/// write's latency. Here we allow negative cycles for corner cases where
94/// latency increases. This rule only applies when the entry's WriteResource
95/// matches the write's WriteResource.
97/// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
98/// WriteResourceIdx.
100 unsigned UseIdx;
105 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
106 && Cycles == Other.Cycles;
107 }
110/// Summarize the scheduling resources required for an instruction of a
111/// particular scheduling class.
113/// Defined as an aggregate struct for creating tables with initializer lists.
115 static const unsigned short InvalidNumMicroOps = (1U << 13) - 1;
116 static const unsigned short VariantNumMicroOps = InvalidNumMicroOps - 1;
118#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
119 const char* Name;
125 uint16_t WriteProcResIdx; // First index into WriteProcResTable.
127 uint16_t WriteLatencyIdx; // First index into WriteLatencyTable.
129 uint16_t ReadAdvanceIdx; // First index into ReadAdvanceTable.
132 bool isValid() const {
134 }
135 bool isVariant() const {
137 }
140/// Specify the cost of a register definition in terms of number of physical
141/// register allocated at register renaming stage. For example, AMD Jaguar.
142/// natively supports 128-bit data types, and operations on 256-bit registers
143/// (i.e. YMM registers) are internally split into two COPs (complex operations)
144/// and each COP updates a physical register. Basically, on Jaguar, a YMM
145/// register write effectively consumes two physical registers. That means,
146/// the cost of a YMM write in the BtVer2 model is 2.
149 unsigned Cost;
153/// A register file descriptor.
155/// This struct allows to describe processor register files. In particular, it
156/// helps describing the size of the register file, as well as the cost of
157/// allocating a register file at register renaming stage.
158/// FIXME: this struct can be extended to provide information about the number
159/// of read/write ports to the register file. A value of zero for field
160/// 'NumPhysRegs' means: this register file has an unbounded number of physical
161/// registers.
163 const char *Name;
166 // Index of the first cost entry in MCExtraProcessorInfo::RegisterCostTable.
168 // A value of zero means: there is no limit in the number of moves that can be
169 // eliminated every cycle.
171 // Ture if this register file only knows how to optimize register moves from
172 // known zero registers.
176/// Provide extra details about the machine processor.
178/// This is a collection of "optional" processor information that is not
179/// normally used by the LLVM machine schedulers, but that can be consumed by
180/// external tools like llvm-mca to improve the quality of the peformance
181/// analysis.
183 // Actual size of the reorder buffer in hardware.
185 // Number of instructions retired per cycle.
191 unsigned LoadQueueID;
192 unsigned StoreQueueID;
195/// Machine model for scheduling, bundling, and heuristics.
197/// The machine model directly provides basic information about the
198/// microarchitecture to the scheduler in the form of properties. It also
199/// optionally refers to scheduler resource tables and itinerary
200/// tables. Scheduler resource tables model the latency and cost for each
201/// instruction type. Itinerary tables are an independent mechanism that
202/// provides a detailed reservation table describing each cycle of instruction
203/// execution. Subtargets may define any or all of the above categories of data
204/// depending on the type of CPU and selected scheduler.
206/// The machine independent properties defined here are used by the scheduler as
207/// an abstract machine model. A real micro-architecture has a number of
208/// buffers, queues, and stages. Declaring that a given machine-independent
209/// abstract property corresponds to a specific physical property across all
210/// subtargets can't be done. Nonetheless, the abstract model is
211/// useful. Futhermore, subtargets typically extend this model with processor
212/// specific resources to model any hardware features that can be exploited by
213/// scheduling heuristics and aren't sufficiently represented in the abstract.
215/// The abstract pipeline is built around the notion of an "issue point". This
216/// is merely a reference point for counting machine cycles. The physical
217/// machine will have pipeline stages that delay execution. The scheduler does
218/// not model those delays because they are irrelevant as long as they are
219/// consistent. Inaccuracies arise when instructions have different execution
220/// delays relative to each other, in addition to their intrinsic latency. Those
221/// special cases can be handled by TableGen constructs such as, ReadAdvance,
222/// which reduces latency when reading data, and ResourceCycles, which consumes
223/// a processor resource when writing data for a number of abstract
224/// cycles.
226/// TODO: One tool currently missing is the ability to add a delay to
227/// ResourceCycles. That would be easy to add and would likely cover all cases
228/// currently handled by the legacy itinerary tables.
230/// A note on out-of-order execution and, more generally, instruction
231/// buffers. Part of the CPU pipeline is always in-order. The issue point, which
232/// is the point of reference for counting cycles, only makes sense as an
233/// in-order part of the pipeline. Other parts of the pipeline are sometimes
234/// falling behind and sometimes catching up. It's only interesting to model
235/// those other, decoupled parts of the pipeline if they may be predictably
236/// resource constrained in a way that the scheduler can exploit.
238/// The LLVM machine model distinguishes between in-order constraints and
239/// out-of-order constraints so that the target's scheduling strategy can apply
240/// appropriate heuristics. For a well-balanced CPU pipeline, out-of-order
241/// resources would not typically be treated as a hard scheduling
242/// constraint. For example, in the GenericScheduler, a delay caused by limited
243/// out-of-order resources is not directly reflected in the number of cycles
244/// that the scheduler sees between issuing an instruction and its dependent
245/// instructions. In other words, out-of-order resources don't directly increase
246/// the latency between pairs of instructions. However, they can still be used
247/// to detect potential bottlenecks across a sequence of instructions and bias
248/// the scheduling heuristics appropriately.
250 // IssueWidth is the maximum number of instructions that may be scheduled in
251 // the same per-cycle group. This is meant to be a hard in-order constraint
252 // (a.k.a. "hazard"). In the GenericScheduler strategy, no more than
253 // IssueWidth micro-ops can ever be scheduled in a particular cycle.
254 //
255 // In practice, IssueWidth is useful to model any bottleneck between the
256 // decoder (after micro-op expansion) and the out-of-order reservation
257 // stations or the decoder bandwidth itself. If the total number of
258 // reservation stations is also a bottleneck, or if any other pipeline stage
259 // has a bandwidth limitation, then that can be naturally modeled by adding an
260 // out-of-order processor resource.
261 unsigned IssueWidth;
262 static const unsigned DefaultIssueWidth = 1;
264 // MicroOpBufferSize is the number of micro-ops that the processor may buffer
265 // for out-of-order execution.
266 //
267 // "0" means operations that are not ready in this cycle are not considered
268 // for scheduling (they go in the pending queue). Latency is paramount. This
269 // may be more efficient if many instructions are pending in a schedule.
270 //
271 // "1" means all instructions are considered for scheduling regardless of
272 // whether they are ready in this cycle. Latency still causes issue stalls,
273 // but we balance those stalls against other heuristics.
274 //
275 // "> 1" means the processor is out-of-order. This is a machine independent
276 // estimate of highly machine specific characteristics such as the register
277 // renaming pool and reorder buffer.
279 static const unsigned DefaultMicroOpBufferSize = 0;
281 // LoopMicroOpBufferSize is the number of micro-ops that the processor may
282 // buffer for optimized loop execution. More generally, this represents the
283 // optimal number of micro-ops in a loop body. A loop may be partially
284 // unrolled to bring the count of micro-ops in the loop body closer to this
285 // number.
287 static const unsigned DefaultLoopMicroOpBufferSize = 0;
289 // LoadLatency is the expected latency of load instructions.
290 unsigned LoadLatency;
291 static const unsigned DefaultLoadLatency = 4;
293 // HighLatency is the expected latency of "very high latency" operations.
294 // See TargetInstrInfo::isHighLatencyDef().
295 // By default, this is set to an arbitrarily high number of cycles
296 // likely to have some impact on scheduling heuristics.
297 unsigned HighLatency;
298 static const unsigned DefaultHighLatency = 10;
300 // MispredictPenalty is the typical number of extra cycles the processor
301 // takes to recover from a branch misprediction.
303 static const unsigned DefaultMispredictPenalty = 10;
305 bool PostRAScheduler; // default value is false
309 unsigned ProcID;
314 // Instruction itinerary tables used by InstrItineraryData.
315 friend class InstrItineraryData;
322 unsigned getProcessorID() const { return ProcID; }
324 /// Does this machine model include instruction-level scheduling.
325 bool hasInstrSchedModel() const { return SchedClassTable; }
329 "No extra information available for this model");
330 return *ExtraProcessorInfo;
331 }
333 /// Return true if this machine model data for all instructions with a
334 /// scheduling class (itinerary class or SchedRW list).
335 bool isComplete() const { return CompleteModel; }
337 /// Return true if machine supports out of order execution.
338 bool isOutOfOrder() const { return MicroOpBufferSize > 1; }
340 unsigned getNumProcResourceKinds() const {
342 }
344 const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
345 assert(hasInstrSchedModel() && "No scheduling machine model");
347 assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
348 return &ProcResourceTable[ProcResourceIdx];
349 }
351 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const {
352 assert(hasInstrSchedModel() && "No scheduling machine model");
354 assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
355 return &SchedClassTable[SchedClassIdx];
356 }
358 /// Returns the latency value for the scheduling class.
359 static int computeInstrLatency(const MCSubtargetInfo &STI,
360 const MCSchedClassDesc &SCDesc);
362 int computeInstrLatency(const MCSubtargetInfo &STI, unsigned SClass) const;
363 int computeInstrLatency(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
364 const MCInst &Inst) const;
366 // Returns the reciprocal throughput information from a MCSchedClassDesc.
367 static double
369 const MCSchedClassDesc &SCDesc);
371 static double
372 getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID);
374 double
376 const MCInst &Inst) const;
378 /// Returns the maximum forwarding delay for register reads dependent on
379 /// writes of scheduling class WriteResourceIdx.
381 unsigned WriteResourceIdx = 0);
383 /// Returns the default initialized model.
384 static const MCSchedModel &GetDefaultSchedModel() { return Default; }
385 static const MCSchedModel Default;
388} // namespace llvm
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Itinerary data supplied by a subtarget to be used by a target.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Generic base class for all target subtargets.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
ArrayRef(const T &OneElt) -> ArrayRef< T >
An itinerary represents the scheduling information for an instruction.
Provide extra details about the machine processor.
Definition: MCSchedule.h:182
const MCRegisterFileDesc * RegisterFiles
Definition: MCSchedule.h:187
const MCRegisterCostEntry * RegisterCostTable
Definition: MCSchedule.h:189
Define a kind of processor resource that will be modeled by the scheduler.
Definition: MCSchedule.h:31
bool operator==(const MCProcResourceDesc &Other) const
Definition: MCSchedule.h:55
const unsigned * SubUnitsIdxBegin
Definition: MCSchedule.h:53
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:99
bool operator==(const MCReadAdvanceEntry &Other) const
Definition: MCSchedule.h:104
Specify the cost of a register definition in terms of number of physical register allocated at regist...
Definition: MCSchedule.h:147
A register file descriptor.
Definition: MCSchedule.h:162
uint16_t NumRegisterCostEntries
Definition: MCSchedule.h:165
uint16_t MaxMovesEliminatedPerCycle
Definition: MCSchedule.h:170
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:114
bool isValid() const
Definition: MCSchedule.h:132
bool isVariant() const
Definition: MCSchedule.h:135
static const unsigned short InvalidNumMicroOps
Definition: MCSchedule.h:115
uint16_t NumWriteLatencyEntries
Definition: MCSchedule.h:128
uint16_t NumReadAdvanceEntries
Definition: MCSchedule.h:130
uint16_t NumWriteProcResEntries
Definition: MCSchedule.h:126
static const unsigned short VariantNumMicroOps
Definition: MCSchedule.h:116
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:249
unsigned LoadLatency
Definition: MCSchedule.h:290
static const MCSchedModel Default
Definition: MCSchedule.h:385
bool isOutOfOrder() const
Return true if machine supports out of order execution.
Definition: MCSchedule.h:338
bool hasExtraProcessorInfo() const
Definition: MCSchedule.h:320
unsigned HighLatency
Definition: MCSchedule.h:297
static unsigned getForwardingDelayCycles(ArrayRef< MCReadAdvanceEntry > Entries, unsigned WriteResourceIdx=0)
Returns the maximum forwarding delay for register reads dependent on writes of scheduling class Write...
Definition: MCSchedule.cpp:155
static const unsigned DefaultLoopMicroOpBufferSize
Definition: MCSchedule.h:287
static const MCSchedModel & GetDefaultSchedModel()
Returns the default initialized model.
Definition: MCSchedule.h:384
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:316
static const unsigned DefaultHighLatency
Definition: MCSchedule.h:298
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:351
unsigned getProcessorID() const
Definition: MCSchedule.h:322
const MCExtraProcessorInfo & getExtraProcessorInfo() const
Definition: MCSchedule.h:327
unsigned getNumProcResourceKinds() const
Definition: MCSchedule.h:340
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Definition: MCSchedule.h:325
static const unsigned DefaultLoadLatency
Definition: MCSchedule.h:291
unsigned LoopMicroOpBufferSize
Definition: MCSchedule.h:286
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
Definition: MCSchedule.cpp:41
static const unsigned DefaultMicroOpBufferSize
Definition: MCSchedule.h:279
const MCSchedClassDesc * SchedClassTable
Definition: MCSchedule.h:311
const MCProcResourceDesc * ProcResourceTable
Definition: MCSchedule.h:310
static const unsigned DefaultMispredictPenalty
Definition: MCSchedule.h:303
unsigned MicroOpBufferSize
Definition: MCSchedule.h:278
unsigned NumSchedClasses
Definition: MCSchedule.h:313
unsigned IssueWidth
Definition: MCSchedule.h:261
const MCExtraProcessorInfo * ExtraProcessorInfo
Definition: MCSchedule.h:318
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Definition: MCSchedule.h:344
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Definition: MCSchedule.cpp:89
static const unsigned DefaultIssueWidth
Definition: MCSchedule.h:262
unsigned NumProcResourceKinds
Definition: MCSchedule.h:312
bool isComplete() const
Return true if this machine model data for all instructions with a scheduling class (itinerary class ...
Definition: MCSchedule.h:335
unsigned MispredictPenalty
Definition: MCSchedule.h:302
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:82
bool operator==(const MCWriteLatencyEntry &Other) const
Definition: MCSchedule.h:86
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63
bool operator==(const MCWriteProcResEntry &Other) const
Definition: MCSchedule.h:71
uint16_t StartAtCycle
Cycle at which the resource will be grabbed by an instruction, relatively to the cycle in which the i...
Definition: MCSchedule.h:69