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14 #ifndef LLVM_MC_MCSCHEDULE_H
15 #define LLVM_MC_MCSCHEDULE_H
17 #include "llvm/Config/llvm-config.h"
23 template <
typename T>
class ArrayRef;
24 struct InstrItinerary;
25 class MCSubtargetInfo;
28 class InstrItineraryData;
113 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
324 "No extra information available for this model");
359 const MCInst &Inst)
const;
371 const MCInst &Inst)
const;
376 unsigned WriteResourceIdx = 0);
bool operator==(const MCWriteProcResEntry &Other) const
bool operator==(const MCWriteLatencyEntry &Other) const
This is an optimization pass for GlobalISel generic memory operations.
uint16_t NumWriteLatencyEntries
unsigned MicroOpBufferSize
uint16_t NumReadAdvanceEntries
static unsigned getForwardingDelayCycles(ArrayRef< MCReadAdvanceEntry > Entries, unsigned WriteResourceIdx=0)
Returns the maximum forwarding delay for register reads dependent on writes of scheduling class Write...
uint16_t MaxMovesEliminatedPerCycle
static const unsigned short VariantNumMicroOps
bool isOutOfOrder() const
Return true if machine supports out of order execution.
uint16_t NumWriteProcResEntries
uint16_t RegisterCostEntryIdx
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Instances of this class represent a single low-level machine instruction.
bool operator==(const MCProcResourceDesc &Other) const
A register file descriptor.
unsigned getNumProcResourceKinds() const
const MCProcResourceDesc * ProcResourceTable
uint16_t NumRegisterCostEntries
An itinerary represents the scheduling information for an instruction.
unsigned MispredictPenalty
const MCExtraProcessorInfo & getExtraProcessorInfo() const
Summarize the scheduling resources required for an instruction of a particular scheduling class.
const MCSchedClassDesc * SchedClassTable
unsigned NumProcResourceKinds
bool AllowMoveElimination
static const MCSchedModel Default
static const unsigned DefaultMispredictPenalty
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
static const unsigned DefaultMicroOpBufferSize
bool operator==(const MCReadAdvanceEntry &Other) const
Define a kind of processor resource that will be modeled by the scheduler.
Specify the latency in cpu cycles for a particular scheduling class and def index.
bool hasExtraProcessorInfo() const
static const unsigned short InvalidNumMicroOps
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Specify the cost of a register definition in terms of number of physical register allocated at regist...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
unsigned getProcessorID() const
const unsigned * SubUnitsIdxBegin
bool isComplete() const
Return true if this machine model data for all instructions with a scheduling class (itinerary class ...
static const unsigned DefaultHighLatency
static const MCSchedModel & GetDefaultSchedModel()
Returns the default initialized model.
Interface to description of machine instruction set.
bool AllowZeroMoveEliminationOnly
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
static const unsigned DefaultLoadLatency
Machine model for scheduling, bundling, and heuristics.
unsigned LoopMicroOpBufferSize
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
static const unsigned DefaultLoopMicroOpBufferSize
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Generic base class for all target subtargets.
const InstrItinerary * InstrItineraries
static const unsigned DefaultIssueWidth
Itinerary data supplied by a subtarget to be used by a target.
Optional< std::vector< StOtherPiece > > Other
const MCExtraProcessorInfo * ExtraProcessorInfo