LLVM 24.0.0git
Legalizer.cpp
Go to the documentation of this file.
1//===-- llvm/CodeGen/GlobalISel/Legalizer.cpp -----------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file implements the LegalizerHelper class to legalize individual
10/// instructions and the LegalizePass wrapper pass for the primary
11/// legalization.
12//
13//===----------------------------------------------------------------------===//
14
33#include "llvm/IR/Analysis.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/Error.h"
36
37#define DEBUG_TYPE "legalizer"
38
39using namespace llvm;
40
41static cl::opt<bool>
42 EnableCSEInLegalizer("enable-cse-in-legalizer",
43 cl::desc("Should enable CSE in Legalizer"),
44 cl::Optional, cl::init(false));
45
46// This is a temporary hack, should be removed soon.
48 "allow-ginsert-as-artifact",
49 cl::desc("Allow G_INSERT to be considered an artifact. Hack around AMDGPU "
50 "test infinite loops."),
51 cl::Optional, cl::init(true));
52
58#ifndef NDEBUG
60 "verify-legalizer-debug-locs",
61 cl::desc("Verify that debug locations are handled"),
63 clEnumValN(DebugLocVerifyLevel::None, "none", "No verification"),
65 "Verify legalizations"),
67 "legalizations+artifactcombiners",
68 "Verify legalizations and artifact combines")),
70#else
71// Always disable it for release builds by preventing the observer from being
72// installed.
74#endif
75
76char LegalizerLegacy::ID = 0;
78 "Legalize the Machine IR a function's Machine IR", false,
79 false)
85 "Legalize the Machine IR a function's Machine IR", false,
86 false)
87
89
100
101static bool isArtifact(const MachineInstr &MI) {
102 switch (MI.getOpcode()) {
103 default:
104 return false;
105 case TargetOpcode::G_TRUNC:
106 case TargetOpcode::G_ZEXT:
107 case TargetOpcode::G_ANYEXT:
108 case TargetOpcode::G_SEXT:
109 case TargetOpcode::G_MERGE_VALUES:
110 case TargetOpcode::G_UNMERGE_VALUES:
111 case TargetOpcode::G_CONCAT_VECTORS:
112 case TargetOpcode::G_BUILD_VECTOR:
113 case TargetOpcode::G_EXTRACT:
114 return true;
115 case TargetOpcode::G_INSERT:
117 }
118}
121
122namespace {
123class LegalizerWorkListManager : public GISelChangeObserver {
124 InstListTy &InstList;
125 ArtifactListTy &ArtifactList;
126#ifndef NDEBUG
128#endif
129
130public:
131 LegalizerWorkListManager(InstListTy &Insts, ArtifactListTy &Arts)
132 : InstList(Insts), ArtifactList(Arts) {}
133
134 void createdOrChangedInstr(MachineInstr &MI) {
135 // Only legalize pre-isel generic instructions.
136 // Legalization process could generate Target specific pseudo
137 // instructions with generic types. Don't record them
138 if (isPreISelGenericOpcode(MI.getOpcode())) {
139 if (isArtifact(MI))
140 ArtifactList.insert(&MI);
141 else
142 InstList.insert(&MI);
143 }
144 }
145
146 void createdInstr(MachineInstr &MI) override {
147 LLVM_DEBUG(NewMIs.push_back(&MI));
148 createdOrChangedInstr(MI);
149 }
150
151 void printNewInstrs() {
152 LLVM_DEBUG({
153 for (const auto *MI : NewMIs)
154 dbgs() << ".. .. New MI: " << *MI;
155 NewMIs.clear();
156 });
157 }
158
159 void erasingInstr(MachineInstr &MI) override {
160 LLVM_DEBUG(dbgs() << ".. .. Erasing: " << MI);
161 InstList.remove(&MI);
162 ArtifactList.remove(&MI);
163 }
164
165 void changingInstr(MachineInstr &MI) override {
166 LLVM_DEBUG(dbgs() << ".. .. Changing MI: " << MI);
167 }
168
169 void changedInstr(MachineInstr &MI) override {
170 // When insts change, we want to revisit them to legalize them again.
171 // We'll consider them the same as created.
172 LLVM_DEBUG(dbgs() << ".. .. Changed MI: " << MI);
173 createdOrChangedInstr(MI);
174 }
175};
176
177} // namespace
178
180 MachineFunction &MF, const LegalizerInfo &LI,
182 LostDebugLocObserver &LocObserver, MachineIRBuilder &MIRBuilder,
183 const LibcallLoweringInfo *Libcalls, GISelValueTracking *VT) {
184 MIRBuilder.setMF(MF);
186
187 // Populate worklists.
188 InstListTy InstList;
189 ArtifactListTy ArtifactList;
191 // Perform legalization bottom up so we can DCE as we legalize.
192 // Traverse BB in RPOT and within each basic block, add insts top down,
193 // so when we pop_back_val in the legalization process, we traverse bottom-up.
194 for (auto *MBB : RPOT) {
195 if (MBB->empty())
196 continue;
197 for (MachineInstr &MI : *MBB) {
198 // Only legalize pre-isel generic instructions: others don't have types
199 // and are assumed to be legal.
200 if (!isPreISelGenericOpcode(MI.getOpcode()))
201 continue;
202 if (isArtifact(MI))
203 ArtifactList.deferred_insert(&MI);
204 else
205 InstList.deferred_insert(&MI);
206 }
207 }
208 ArtifactList.finalize();
209 InstList.finalize();
210
211 // This observer keeps the worklists updated.
212 LegalizerWorkListManager WorkListObserver(InstList, ArtifactList);
213 // We want both WorkListObserver as well as all the auxiliary observers (e.g.
214 // CSEInfo) to observe all changes. Use the wrapper observer.
215 GISelObserverWrapper WrapperObserver(&WorkListObserver);
216 for (GISelChangeObserver *Observer : AuxObservers)
217 WrapperObserver.addObserver(Observer);
218
219 // Now install the observer as the delegate to MF.
220 // This will keep all the observers notified about new insertions/deletions.
221 RAIIMFObsDelInstaller Installer(MF, WrapperObserver);
222 LegalizerHelper Helper(MF, LI, WrapperObserver, MIRBuilder, Libcalls, VT);
223 LegalizationArtifactCombiner ArtCombiner(MIRBuilder, MRI, LI, VT);
224 bool Changed = false;
226 do {
227 LLVM_DEBUG(dbgs() << "=== New Iteration ===\n");
228 assert(RetryList.empty() && "Expected no instructions in RetryList");
229 unsigned NumArtifacts = ArtifactList.size();
230 while (!InstList.empty()) {
231 MachineInstr &MI = *InstList.pop_back_val();
232 assert(isPreISelGenericOpcode(MI.getOpcode()) &&
233 "Expecting generic opcode");
234 if (isTriviallyDead(MI, MRI)) {
235 salvageDebugInfo(MRI, MI);
236 eraseInstr(MI, MRI, &LocObserver);
237 continue;
238 }
239
240 // Do the legalization for this instruction.
241 auto Res = Helper.legalizeInstrStep(MI, LocObserver);
242 // Error out if we couldn't legalize this instruction. We may want to
243 // fall back to DAG ISel instead in the future.
245 // Move illegal artifacts to RetryList instead of aborting because
246 // legalizing InstList may generate artifacts that allow
247 // ArtifactCombiner to combine away them.
248 if (isArtifact(MI)) {
249 LLVM_DEBUG(dbgs() << ".. Not legalized, moving to artifacts retry\n");
250 assert(NumArtifacts == 0 &&
251 "Artifacts are only expected in instruction list starting the "
252 "second iteration, but each iteration starting second must "
253 "start with an empty artifacts list");
254 (void)NumArtifacts;
255 RetryList.push_back(&MI);
256 continue;
257 }
259 return {Changed, &MI};
260 }
261 WorkListObserver.printNewInstrs();
262 LocObserver.checkpoint();
264 }
265 // Try to combine the instructions in RetryList again if there
266 // are new artifacts. If not, stop legalizing.
267 if (!RetryList.empty()) {
268 if (!ArtifactList.empty()) {
269 while (!RetryList.empty())
270 ArtifactList.insert(RetryList.pop_back_val());
271 } else {
272 LLVM_DEBUG(dbgs() << "No new artifacts created, not retrying!\n");
274 return {Changed, RetryList.front()};
275 }
276 }
277 LocObserver.checkpoint();
278 while (!ArtifactList.empty()) {
279 MachineInstr &MI = *ArtifactList.pop_back_val();
280 assert(isPreISelGenericOpcode(MI.getOpcode()) &&
281 "Expecting generic opcode");
282 if (isTriviallyDead(MI, MRI)) {
283 salvageDebugInfo(MRI, MI);
284 eraseInstr(MI, MRI, &LocObserver);
285 continue;
286 }
287 SmallVector<MachineInstr *, 4> DeadInstructions;
288 LLVM_DEBUG(dbgs() << "Trying to combine: " << MI);
289 if (ArtCombiner.tryCombineInstruction(MI, DeadInstructions,
290 WrapperObserver)) {
291 WorkListObserver.printNewInstrs();
292 eraseInstrs(DeadInstructions, MRI, &LocObserver);
293 LocObserver.checkpoint(
296 Changed = true;
297 continue;
298 }
299 // If this was not an artifact (that could be combined away), this might
300 // need special handling. Add it to InstList, so when it's processed
301 // there, it has to be legal or specially handled.
302 else {
303 LLVM_DEBUG(dbgs() << ".. Not combined, moving to instructions list\n");
304 InstList.insert(&MI);
305 }
306 }
307 } while (!InstList.empty());
308
309 return {Changed, /*FailedOn*/ nullptr};
310}
311
312static bool isCSEEnabled() {
313 return EnableCSEInLegalizer.getNumOccurrences() ? EnableCSEInLegalizer : true;
314}
315
316static bool
318 function_ref<GISelCSEInfo *()> GetCSEInfo,
319 function_ref<GISelValueTracking *()> GetVTInfo,
320 const LibcallLoweringInfo *LibcallInfo) {
321 // If the ISel pipeline failed, do not bother running that pass.
322 if (MF.getProperties().hasFailedISel())
323 return false;
324 LLVM_DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
325 MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
326
327 std::unique_ptr<MachineIRBuilder> MIRBuilder;
328 GISelCSEInfo *CSEInfo = nullptr;
329 bool EnableCSE = isCSEEnabled();
330 if (EnableCSE) {
331 MIRBuilder = std::make_unique<CSEMIRBuilder>();
332 CSEInfo = GetCSEInfo();
333 MIRBuilder->setCSEInfo(CSEInfo);
334 } else {
335 MIRBuilder = std::make_unique<MachineIRBuilder>();
336 }
337
339 if (EnableCSE && CSEInfo) {
340 // We want CSEInfo in addition to WorkListObserver to observe all changes.
341 AuxObservers.push_back(CSEInfo);
342 }
343 assert(!CSEInfo || !errorToBool(CSEInfo->verify()));
344 LostDebugLocObserver LocObserver(DEBUG_TYPE);
346 AuxObservers.push_back(&LocObserver);
347
348 const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
349
350 // This allows Known Bits Analysis in the legalizer.
351 GISelValueTracking *VT = GetVTInfo();
352
353 const LegalizerInfo &LI = *Subtarget.getLegalizerInfo();
355 MF, LI, AuxObservers, LocObserver, *MIRBuilder, LibcallInfo, VT);
356
357 if (Result.FailedOn) {
358 reportGISelFailure(MF, MORE, "gisel-legalize",
359 "unable to legalize instruction", *Result.FailedOn);
360 return false;
361 }
362
363 if (LocObserver.getNumLostDebugLocs()) {
364 MachineOptimizationRemarkMissed R("gisel-legalize", "LostDebugLoc",
366 /*MBB=*/&*MF.begin());
367 R << "lost "
368 << ore::NV("NumLostDebugLocs", LocObserver.getNumLostDebugLocs())
369 << " debug locations during pass";
370 reportGISelWarning(MF, MORE, R);
371 // Example remark:
372 // --- !Missed
373 // Pass: gisel-legalize
374 // Name: GISelFailure
375 // DebugLoc: { File: '.../legalize-urem.mir', Line: 1, Column: 0 }
376 // Function: test_urem_s32
377 // Args:
378 // - String: 'lost '
379 // - NumLostDebugLocs: '1'
380 // - String: ' debug locations during pass'
381 // ...
382 }
383
384 return Result.Changed;
385}
386
390 const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
391 Function &F = MF.getFunction();
393 MF,
394 [&]() {
396 return &Wrapper.get(TPC.getCSEConfig());
397 },
398 [&]() {
400 },
401 &getAnalysis<LibcallLoweringInfoWrapper>().getLibcallLowering(
402 *F.getParent(), Subtarget));
403
404 // If for some reason CSE was not enabled, make sure that we invalidate the
405 // CSEInfo object (as we currently declare that the analysis is preserved).
406 // The next time get on the wrapper is called, it will force it to recompute
407 // the analysis.
408 if (!isCSEEnabled())
409 Wrapper.setComputed(false);
410
411 return Changed;
412}
413
417 Function &F = MF.getFunction();
418 auto &MAMProxy =
420 const ModuleLibcallLoweringInfo *MLLI =
421 MAMProxy.getCachedResult<LibcallLoweringModuleAnalysis>(*F.getParent());
422 const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
424 MF, [&]() { return MFAM.getResult<GISelCSEAnalysis>(MF).get(); },
425 [&]() { return &MFAM.getResult<GISelValueTrackingAnalysis>(MF); },
426 &getLibcallLowering(*MLLI, Subtarget));
427 if (!Changed)
428 return PreservedAnalyses::all();
432 return PA;
433}
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
MachineBasicBlock & MBB
Provides analysis for continuously CSEing during GISel passes.
This file implements a version of MachineIRBuilder which CSEs insts within a MachineBasicBlock.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
#define DEBUG_TYPE
#define _
IRTranslator LLVM IR MI
GISelWorkList< 128 > ArtifactListTy
DebugLocVerifyLevel
Definition Legalizer.cpp:53
static cl::opt< DebugLocVerifyLevel > VerifyDebugLocs("verify-legalizer-debug-locs", cl::desc("Verify that debug locations are handled"), cl::values(clEnumValN(DebugLocVerifyLevel::None, "none", "No verification"), clEnumValN(DebugLocVerifyLevel::Legalizations, "legalizations", "Verify legalizations"), clEnumValN(DebugLocVerifyLevel::LegalizationsAndArtifactCombiners, "legalizations+artifactcombiners", "Verify legalizations and artifact combines")), cl::init(DebugLocVerifyLevel::Legalizations))
static cl::opt< bool > EnableCSEInLegalizer("enable-cse-in-legalizer", cl::desc("Should enable CSE in Legalizer"), cl::Optional, cl::init(false))
static bool isCSEEnabled()
static bool runLegalizerOnMachineFunction(MachineFunction &MF, function_ref< GISelCSEInfo *()> GetCSEInfo, function_ref< GISelValueTracking *()> GetVTInfo, const LibcallLoweringInfo *LibcallInfo)
static cl::opt< bool > AllowGInsertAsArtifact("allow-ginsert-as-artifact", cl::desc("Allow G_INSERT to be considered an artifact. Hack around AMDGPU " "test infinite loops."), cl::Optional, cl::init(true))
GISelWorkList< 256 > InstListTy
static bool isArtifact(const MachineInstr &MI)
Tracks DebugLocs between checkpoints and verifies that they are transferred.
#define F(x, y, z)
Definition MD5.cpp:54
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition PassSupport.h:42
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition PassSupport.h:44
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition PassSupport.h:39
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
#define LLVM_DEBUG(...)
Definition Debug.h:119
Target-Independent Code Generator Pass Configuration Options pass.
PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)
Get the result of an analysis pass for a given IR unit.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
DISubprogram * getSubprogram() const
Get the attached subprogram.
The actual analysis pass wrapper.
Definition CSEInfo.h:243
Simple wrapper that does the following.
Definition CSEInfo.h:213
The CSE Analysis object.
Definition CSEInfo.h:72
Abstract class that contains various methods for clients to notify about changes.
Simple wrapper observer that takes several observers, and calls each one for each event.
void addObserver(GISelChangeObserver *O)
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelValueTrackingInfoAnal...
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
MachineInstr * pop_back_val()
unsigned size() const
void deferred_insert(MachineInstr *I)
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
bool tryCombineInstruction(MachineInstr &MI, SmallVectorImpl< MachineInstr * > &DeadInsts, GISelObserverWrapper &WrapperObserver)
Try to combine away MI.
@ Legalized
Instruction has been legalized and the MachineFunction changed.
@ UnableToLegalize
Some kind of error has occurred and we could not legalize this instruction.
MachineIRBuilder & MIRBuilder
Expose MIRBuilder so clients can set their own RecordInsertInstruction functions.
LLVM_ABI LegalizeResult legalizeInstrStep(MachineInstr &MI, LostDebugLocObserver &LocObserver)
Replace MI by a sequence of legal instructions that can implement the same operation.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition Legalizer.cpp:90
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
Tracks which library functions to use for a particular subtarget or function.
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
An RAII based helper class to modify MachineFunctionProperties when running pass.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineFunctionProperties & getProperties() const
Get the function properties.
Helper class to build MachineInstr.
void setMF(MachineFunction &MF)
Representation of each machine instruction.
Diagnostic information for missed-optimization remarks.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Records a mapping from an opaque lowering context to its LibcallLoweringInfo.
AnalysisType & getAnalysis() const
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information ...
A set of analyses that are preserved following a run of a transformation pass.
Definition Analysis.h:112
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition Analysis.h:118
PreservedAnalyses & preserve()
Mark an analysis as preserved.
Definition Analysis.h:132
Class to install both of the above.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Target-Independent Code Generator Pass Configuration Options.
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const LegalizerInfo * getLegalizerInfo() const
An efficient, type-erasing, non-owning reference to a callable.
Changed
Pass manager infrastructure for declaring and invalidating analyses.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
initializer< Ty > init(const Ty &Val)
DiagnosticInfoOptimizationBase::Argument NV
This is an optimization pass for GlobalISel generic memory operations.
bool errorToBool(Error Err)
Helper for converting an Error to a bool.
Definition Error.h:1129
OuterAnalysisManagerProxy< ModuleAnalysisManager, MachineFunction > ModuleAnalysisManagerMachineFunctionProxy
Provide the ModuleAnalysisManager to Function proxy.
LLVM_ABI void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition Utils.cpp:1675
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
LLVM_ABI void reportGISelWarning(MachineFunction &MF, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition Utils.cpp:255
LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
LLVM_ABI const LibcallLoweringInfo & getLibcallLowering(const ModuleLibcallLoweringInfo &ModuleInfo, const TargetSubtargetInfo &Subtarget)
Resolve the LibcallLoweringInfo for Subtarget from the module-level ModuleInfo, applying the subtarge...
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:209
LLVM_ABI void reportGISelFailure(MachineFunction &MF, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition Utils.cpp:261
LegalizerMFResult legalizeMachineFunction(MachineFunction &MF, const LegalizerInfo &LI, ArrayRef< GISelChangeObserver * > AuxObservers, LostDebugLocObserver &LocObserver, MachineIRBuilder &MIRBuilder, const LibcallLoweringInfo *Libcalls, GISelValueTracking *VT)
LLVM_ABI void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition Utils.cpp:1137
LLVM_ABI void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition Utils.cpp:1670
LLVM_ABI void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition Utils.cpp:1655
LLVM_ABI bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition Utils.cpp:224
#define MORE()
Definition regcomp.c:246