LLVM  16.0.0git
SPIRVMCTargetDesc.h
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1 //===-- SPIRVMCTargetDesc.h - SPIR-V Target Descriptions --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides SPIR-V specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVMCTARGETDESC_H
15 
16 #include "llvm/Support/DataTypes.h"
17 #include <memory>
18 
19 namespace llvm {
20 class MCAsmBackend;
21 class MCCodeEmitter;
22 class MCContext;
23 class MCInstrInfo;
24 class MCObjectTargetWriter;
25 class MCRegisterInfo;
26 class MCSubtargetInfo;
27 class MCTargetOptions;
28 class Target;
29 
30 MCCodeEmitter *createSPIRVMCCodeEmitter(const MCInstrInfo &MCII,
31  MCContext &Ctx);
32 
33 MCAsmBackend *createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
34  const MCRegisterInfo &MRI,
35  const MCTargetOptions &Options);
36 
37 std::unique_ptr<MCObjectTargetWriter> createSPIRVObjectTargetWriter();
38 } // namespace llvm
39 
40 // Defines symbolic names for SPIR-V registers. This defines a mapping from
41 // register name to register number.
42 #define GET_REGINFO_ENUM
43 #include "SPIRVGenRegisterInfo.inc"
44 
45 // Defines symbolic names for the SPIR-V instructions.
46 #define GET_INSTRINFO_ENUM
47 #define GET_INSTRINFO_MC_HELPER_DECLS
48 #include "SPIRVGenInstrInfo.inc"
49 
50 #define GET_SUBTARGETINFO_ENUM
51 #include "SPIRVGenSubtargetInfo.inc"
52 
53 #endif // LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVMCTARGETDESC_H
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:858
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createSPIRVMCCodeEmitter
MCCodeEmitter * createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: SPIRVMCCodeEmitter.cpp:53
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createSPIRVObjectTargetWriter
std::unique_ptr< MCObjectTargetWriter > createSPIRVObjectTargetWriter()
Definition: SPIRVObjectTargetWriter.cpp:23
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::createSPIRVAsmBackend
MCAsmBackend * createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: SPIRVAsmBackend.cpp:58
DataTypes.h