LLVM 22.0.0git
SPIRVMCTargetDesc.h
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1//===-- SPIRVMCTargetDesc.h - SPIR-V Target Descriptions --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides SPIR-V specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVMCTARGETDESC_H
14#define LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVMCTARGETDESC_H
15
17#include <cassert>
18
19namespace llvm {
20class MCAsmBackend;
21class MCCodeEmitter;
22class MCContext;
23class MCInstrInfo;
25class MCRegisterInfo;
26class MCSubtargetInfo;
27class MCTargetOptions;
28class Target;
29
31 MCContext &Ctx);
32
34 const MCRegisterInfo &MRI,
36} // namespace llvm
37
38// Defines symbolic names for SPIR-V registers. This defines a mapping from
39// register name to register number.
40#define GET_REGINFO_ENUM
41#include "SPIRVGenRegisterInfo.inc"
42
43// Defines symbolic names for the SPIR-V instructions.
44#define GET_INSTRINFO_ENUM
45#define GET_INSTRINFO_MC_HELPER_DECLS
46#include "SPIRVGenInstrInfo.inc"
47
48#define GET_SUBTARGETINFO_ENUM
49#include "SPIRVGenSubtargetInfo.inc"
50
51namespace llvm::SPIRV {
52inline unsigned getIDFromRegister(unsigned Reg) {
53 assert(Reg & (1U << 31));
54 return Reg & ~(1U << 31);
55}
56} // namespace llvm::SPIRV
57
58#endif // LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVMCTARGETDESC_H
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static LVOptions Options
Definition LVOptions.cpp:25
Register Reg
#define T
Generic interface to target specific assembler backends.
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
Definition MCContext.h:83
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
Base class for classes that define behaviour that is specific to both the target and the object forma...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
unsigned getIDFromRegister(unsigned Reg)
This is an optimization pass for GlobalISel generic memory operations.
MCCodeEmitter * createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCAsmBackend * createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)