LLVM  14.0.0git
SIDefines.h
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1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/MC/MCInstrDesc.h"
11 
12 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
13 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 
15 namespace llvm {
16 
17 namespace SIInstrFlags {
18 // This needs to be kept in sync with the field bits in InstSI.
19 enum : uint64_t {
20  // Low bits - basic encoding information.
21  SALU = 1 << 0,
22  VALU = 1 << 1,
23 
24  // SALU instruction formats.
25  SOP1 = 1 << 2,
26  SOP2 = 1 << 3,
27  SOPC = 1 << 4,
28  SOPK = 1 << 5,
29  SOPP = 1 << 6,
30 
31  // VALU instruction formats.
32  VOP1 = 1 << 7,
33  VOP2 = 1 << 8,
34  VOPC = 1 << 9,
35 
36  // TODO: Should this be spilt into VOP3 a and b?
37  VOP3 = 1 << 10,
38  VOP3P = 1 << 12,
39 
40  VINTRP = 1 << 13,
41  SDWA = 1 << 14,
42  DPP = 1 << 15,
43  TRANS = 1 << 16,
44 
45  // Memory instruction formats.
46  MUBUF = 1 << 17,
47  MTBUF = 1 << 18,
48  SMRD = 1 << 19,
49  MIMG = 1 << 20,
50  EXP = 1 << 21,
51  FLAT = 1 << 22,
52  DS = 1 << 23,
53 
54  // Pseudo instruction formats.
55  VGPRSpill = 1 << 24,
56  SGPRSpill = 1 << 25,
57 
58  // High bits - other information.
59  VM_CNT = UINT64_C(1) << 32,
60  EXP_CNT = UINT64_C(1) << 33,
61  LGKM_CNT = UINT64_C(1) << 34,
62 
63  WQM = UINT64_C(1) << 35,
64  DisableWQM = UINT64_C(1) << 36,
65  Gather4 = UINT64_C(1) << 37,
66  SOPK_ZEXT = UINT64_C(1) << 38,
67  SCALAR_STORE = UINT64_C(1) << 39,
68  FIXED_SIZE = UINT64_C(1) << 40,
69  VOPAsmPrefer32Bit = UINT64_C(1) << 41,
70  VOP3_OPSEL = UINT64_C(1) << 42,
71  maybeAtomic = UINT64_C(1) << 43,
72  renamedInGFX9 = UINT64_C(1) << 44,
73 
74  // Is a clamp on FP type.
75  FPClamp = UINT64_C(1) << 45,
76 
77  // Is an integer clamp
78  IntClamp = UINT64_C(1) << 46,
79 
80  // Clamps lo component of register.
81  ClampLo = UINT64_C(1) << 47,
82 
83  // Clamps hi component of register.
84  // ClampLo and ClampHi set for packed clamp.
85  ClampHi = UINT64_C(1) << 48,
86 
87  // Is a packed VOP3P instruction.
88  IsPacked = UINT64_C(1) << 49,
89 
90  // Is a D16 buffer instruction.
91  D16Buf = UINT64_C(1) << 50,
92 
93  // FLAT instruction accesses FLAT_GLBL segment.
94  FlatGlobal = UINT64_C(1) << 51,
95 
96  // Uses floating point double precision rounding mode
97  FPDPRounding = UINT64_C(1) << 52,
98 
99  // Instruction is FP atomic.
100  FPAtomic = UINT64_C(1) << 53,
101 
102  // Is a MFMA instruction.
103  IsMAI = UINT64_C(1) << 54,
104 
105  // Is a DOT instruction.
106  IsDOT = UINT64_C(1) << 55,
107 
108  // FLAT instruction accesses FLAT_SCRATCH segment.
109  FlatScratch = UINT64_C(1) << 56,
110 
111  // Atomic without return.
112  IsAtomicNoRet = UINT64_C(1) << 57,
113 
114  // Atomic with return.
115  IsAtomicRet = UINT64_C(1) << 58
116 };
117 
118 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
119 // The result is true if any of these tests are true.
120 enum ClassFlags : unsigned {
121  S_NAN = 1 << 0, // Signaling NaN
122  Q_NAN = 1 << 1, // Quiet NaN
123  N_INFINITY = 1 << 2, // Negative infinity
124  N_NORMAL = 1 << 3, // Negative normal
125  N_SUBNORMAL = 1 << 4, // Negative subnormal
126  N_ZERO = 1 << 5, // Negative zero
127  P_ZERO = 1 << 6, // Positive zero
128  P_SUBNORMAL = 1 << 7, // Positive subnormal
129  P_NORMAL = 1 << 8, // Positive normal
130  P_INFINITY = 1 << 9 // Positive infinity
131 };
132 }
133 
134 namespace AMDGPU {
135  enum OperandType : unsigned {
136  /// Operands with register or 32-bit immediate
147 
148  /// Operands with register or inline constant
159 
160  /// Operands with an AccVGPR register or inline constant
170 
173 
176 
179 
182 
183  // Operand for source modifiers for VOP instructions
185 
186  // Operand for SDWA instructions
188 
189  /// Operand with 32-bit immediate that uses the constant bus.
192  };
193 }
194 
195 // Input operand modifiers bit-masks
196 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
197 namespace SISrcMods {
198  enum : unsigned {
199  NEG = 1 << 0, // Floating-point negate modifier
200  ABS = 1 << 1, // Floating-point absolute modifier
201  SEXT = 1 << 0, // Integer sign-extend modifier
202  NEG_HI = ABS, // Floating-point negate high packed component modifier.
203  OP_SEL_0 = 1 << 2,
204  OP_SEL_1 = 1 << 3,
205  DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
206  };
207 }
208 
209 namespace SIOutMods {
210  enum : unsigned {
211  NONE = 0,
212  MUL2 = 1,
213  MUL4 = 2,
214  DIV2 = 3
215  };
216 }
217 
218 namespace AMDGPU {
219 namespace VGPRIndexMode {
220 
221 enum Id : unsigned { // id of symbolic names
222  ID_SRC0 = 0,
226 
229 };
230 
231 enum EncBits : unsigned {
232  OFF = 0,
238  UNDEF = 0xFFFF
239 };
240 
241 } // namespace VGPRIndexMode
242 } // namespace AMDGPU
243 
244 namespace AMDGPUAsmVariants {
245  enum : unsigned {
246  DEFAULT = 0,
247  VOP3 = 1,
248  SDWA = 2,
249  SDWA9 = 3,
250  DPP = 4
251  };
252 }
253 
254 namespace AMDGPU {
255 namespace EncValues { // Encoding values of enum9/8/7 operands
256 
257 enum : unsigned {
258  SGPR_MIN = 0,
259  SGPR_MAX_SI = 101,
261  TTMP_VI_MIN = 112,
262  TTMP_VI_MAX = 123,
271  VGPR_MIN = 256,
272  VGPR_MAX = 511
273 };
274 
275 } // namespace EncValues
276 } // namespace AMDGPU
277 
278 namespace AMDGPU {
279 namespace CPol {
280 
281 enum CPol {
282  GLC = 1,
283  SLC = 2,
284  DLC = 4,
285  SCC = 16,
286  ALL = GLC | SLC | DLC | SCC
287 };
288 
289 } // namespace CPol
290 
291 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
292 
293 enum Id { // Message ID, width(4) [3:0].
296  ID_GS = 2,
298  ID_SAVEWAVE = 4, // added in GFX8
299  ID_STALL_WAVE_GEN = 5, // added in GFX9
300  ID_HALT_WAVES = 6, // added in GFX9
301  ID_ORDERED_PS_DONE = 7, // added in GFX9
302  ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
303  ID_GS_ALLOC_REQ = 9, // added in GFX9
304  ID_GET_DOORBELL = 10, // added in GFX9
305  ID_GET_DDID = 11, // added in GFX10
306  ID_SYSMSG = 15,
307  ID_GAPS_LAST_, // Indicate that sequence has gaps.
311  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
312 };
313 
314 enum Op { // Both GS and SYS operation IDs.
317  OP_NONE_ = 0,
318  // Bits used for operation encoding
320  OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
321  // GS operations are encoded in bits 5:4
328  // SYS operations are encoded in bits 6:4
335 };
336 
337 enum StreamId : unsigned { // Stream ID, (2) [9:8].
345 };
346 
347 } // namespace SendMsg
348 
349 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
350 
351 enum Id { // HwRegCode, (6) [5:0]
353  ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
354  ID_MODE = 1,
357  ID_HW_ID = 4,
363  ID_TBA_LO = 16,
365  ID_TBA_HI = 17,
366  ID_TMA_LO = 18,
367  ID_TMA_HI = 19,
377  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
378 };
379 
380 enum Offset : unsigned { // Offset, (5) [10:6]
385 
387 
390 };
391 
392 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
397 
400 };
401 
402 // Some values from WidthMinusOne mapped into Width domain.
403 enum Width : unsigned {
405 };
406 
408  FP_ROUND_MASK = 0xf << 0, // Bits 0..3
409  FP_DENORM_MASK = 0xf << 4, // Bits 4..7
410  DX10_CLAMP_MASK = 1 << 8,
411  IEEE_MODE_MASK = 1 << 9,
412  LOD_CLAMP_MASK = 1 << 10,
413  DEBUG_MASK = 1 << 11,
414 
415  // EXCP_EN fields.
423 
424  GPR_IDX_EN_MASK = 1 << 27,
425  VSKIP_MASK = 1 << 28,
426  CSP_MASK = 0x7u << 29 // Bits 29..31
427 };
428 
429 } // namespace Hwreg
430 
431 namespace MTBUFFormat {
432 
433 enum DataFormat : int64_t {
450 
453 
456 
458  DFMT_MASK = 0xF
459 };
460 
461 enum NumFormat : int64_t {
468  NFMT_RESERVED_6, // VI and GFX9
469  NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
471 
474 
477 
480 };
481 
482 enum MergedFormat : int64_t {
486 
487 
489 
491 };
492 
493 enum UnifiedFormat : int64_t {
495 
502 
510 
517 
521 
529 
537 
545 
552 
559 
566 
570 
578 
585 
588 
589  UFMT_MAX = 127,
590 
593 };
594 
595 } // namespace MTBUFFormat
596 
597 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
598 
599 enum Id : unsigned { // id of symbolic names
605 };
606 
607 enum EncBits : unsigned {
608 
609  // swizzle mode encodings
610 
611  QUAD_PERM_ENC = 0x8000,
613 
616 
617  // QUAD_PERM encodings
618 
619  LANE_MASK = 0x3,
622  LANE_NUM = 4,
623 
624  // BITMASK_PERM encodings
625 
626  BITMASK_MASK = 0x1F,
629 
633 };
634 
635 } // namespace Swizzle
636 
637 namespace SDWA {
638 
639 enum SdwaSel : unsigned {
640  BYTE_0 = 0,
641  BYTE_1 = 1,
642  BYTE_2 = 2,
643  BYTE_3 = 3,
644  WORD_0 = 4,
645  WORD_1 = 5,
646  DWORD = 6,
647 };
648 
649 enum DstUnused : unsigned {
653 };
654 
655 enum SDWA9EncValues : unsigned {
656  SRC_SGPR_MASK = 0x100,
660 
668 };
669 
670 } // namespace SDWA
671 
672 namespace DPP {
673 
674 // clang-format off
675 enum DppCtrl : unsigned {
677  QUAD_PERM_ID = 0xE4, // identity permutation
679  DPP_UNUSED1 = 0x100,
680  ROW_SHL0 = 0x100,
681  ROW_SHL_FIRST = 0x101,
682  ROW_SHL_LAST = 0x10F,
683  DPP_UNUSED2 = 0x110,
684  ROW_SHR0 = 0x110,
685  ROW_SHR_FIRST = 0x111,
686  ROW_SHR_LAST = 0x11F,
687  DPP_UNUSED3 = 0x120,
688  ROW_ROR0 = 0x120,
689  ROW_ROR_FIRST = 0x121,
690  ROW_ROR_LAST = 0x12F,
691  WAVE_SHL1 = 0x130,
694  WAVE_ROL1 = 0x134,
697  WAVE_SHR1 = 0x138,
700  WAVE_ROR1 = 0x13C,
703  ROW_MIRROR = 0x140,
705  BCAST15 = 0x142,
706  BCAST31 = 0x143,
711  ROW_SHARE0 = 0x150,
713  ROW_SHARE_LAST = 0x15F,
714  ROW_XMASK0 = 0x160,
716  ROW_XMASK_LAST = 0x16F,
718 };
719 // clang-format on
720 
721 enum DppFiMode {
722  DPP_FI_0 = 0,
723  DPP_FI_1 = 1,
724  DPP8_FI_0 = 0xE9,
725  DPP8_FI_1 = 0xEA,
726 };
727 
728 } // namespace DPP
729 
730 namespace Exp {
731 
732 enum Target : unsigned {
733  ET_MRT0 = 0,
734  ET_MRT7 = 7,
735  ET_MRTZ = 8,
736  ET_NULL = 9,
737  ET_POS0 = 12,
738  ET_POS3 = 15,
739  ET_POS4 = 16, // GFX10+
740  ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
741  ET_PRIM = 20, // GFX10+
742  ET_PARAM0 = 32,
744 
751 
752  ET_INVALID = 255,
753 };
754 
755 } // namespace Exp
756 
757 namespace VOP3PEncoding {
758 
759 enum OpSel : uint64_t {
760  OP_SEL_HI_0 = UINT64_C(1) << 59,
761  OP_SEL_HI_1 = UINT64_C(1) << 60,
762  OP_SEL_HI_2 = UINT64_C(1) << 14,
763 };
764 
765 } // namespace VOP3PEncoding
766 
767 } // namespace AMDGPU
768 
769 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
770 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
771 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
772 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
773 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
774 #define C_00B028_MEM_ORDERED 0xFDFFFFFF
775 
776 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
777 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
778 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
779 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
780 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
781 #define C_00B128_MEM_ORDERED 0xF7FFFFFF
782 
783 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
784 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
785 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
786 #define C_00B228_WGP_MODE 0xF7FFFFFF
787 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
788 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
789 #define C_00B228_MEM_ORDERED 0xFDFFFFFF
790 
791 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
792 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
793 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
794 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
795 #define C_00B428_WGP_MODE 0xFBFFFFFF
796 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
797 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
798 #define C_00B428_MEM_ORDERED 0xFEFFFFFF
799 
800 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
801 
802 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
803 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
804 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
805 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
806 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
807 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
808 #define C_00B84C_USER_SGPR 0xFFFFFFC1
809 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
810 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
811 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
812 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
813 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
814 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
815 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
816 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
817 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
818 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
819 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
820 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
821 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
822 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
823 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
824 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
825 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
826 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
827 /* CIK */
828 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
829 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
830 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
831 /* */
832 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
833 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
834 #define C_00B84C_LDS_SIZE 0xFF007FFF
835 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
836 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
837 #define C_00B84C_EXCP_EN
838 
839 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
840 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
841 
842 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
843 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
844 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
845 #define C_00B848_VGPRS 0xFFFFFFC0
846 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
847 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
848 #define C_00B848_SGPRS 0xFFFFFC3F
849 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
850 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
851 #define C_00B848_PRIORITY 0xFFFFF3FF
852 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
853 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
854 #define C_00B848_FLOAT_MODE 0xFFF00FFF
855 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
856 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
857 #define C_00B848_PRIV 0xFFEFFFFF
858 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
859 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
860 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
861 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
862 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
863 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
864 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
865 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
866 #define C_00B848_IEEE_MODE 0xFF7FFFFF
867 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
868 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
869 #define C_00B848_WGP_MODE 0xDFFFFFFF
870 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
871 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
872 #define C_00B848_MEM_ORDERED 0xBFFFFFFF
873 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
874 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
875 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF
876 
877 
878 // Helpers for setting FLOAT_MODE
879 #define FP_ROUND_ROUND_TO_NEAREST 0
880 #define FP_ROUND_ROUND_TO_INF 1
881 #define FP_ROUND_ROUND_TO_NEGINF 2
882 #define FP_ROUND_ROUND_TO_ZERO 3
883 
884 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
885 // precision.
886 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
887 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
888 
889 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
890 #define FP_DENORM_FLUSH_OUT 1
891 #define FP_DENORM_FLUSH_IN 2
892 #define FP_DENORM_FLUSH_NONE 3
893 
894 
895 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
896 // precision.
897 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
898 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
899 
900 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
901 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
902 
903 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
904 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
905 
906 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
907 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
908 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
909 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
910 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
911 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
912 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
913 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
914 
915 #define R_SPILLED_SGPRS 0x4
916 #define R_SPILLED_VGPRS 0x8
917 } // End namespace llvm
918 
919 #endif
llvm::AMDGPU::MTBUFFormat::DataFormat
DataFormat
Definition: SIDefines.h:433
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:154
llvm::SISrcMods::SEXT
@ SEXT
Definition: SIDefines.h:201
llvm::AMDGPU::MTBUFFormat::DFMT_DEFAULT
@ DFMT_DEFAULT
Definition: SIDefines.h:455
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_SSCALED
@ UFMT_10_10_10_2_SSCALED
Definition: SIDefines.h:549
llvm::AMDGPU::Hwreg::EXCP_EN_INPUT_DENORMAL_MASK
@ EXCP_EN_INPUT_DENORMAL_MASK
Definition: SIDefines.h:417
llvm::SIOutMods::NONE
@ NONE
Definition: SIDefines.h:211
llvm::AMDGPUAsmVariants::SDWA9
@ SDWA9
Definition: SIDefines.h:249
llvm::AMDGPU::DPP::ROW_SHL_LAST
@ ROW_SHL_LAST
Definition: SIDefines.h:682
llvm::AMDGPU::DPP::ROW_SHR_FIRST
@ ROW_SHR_FIRST
Definition: SIDefines.h:685
llvm::AMDGPU::DPP::ROW_ROR_FIRST
@ ROW_ROR_FIRST
Definition: SIDefines.h:689
llvm::AMDGPUAsmVariants::VOP3
@ VOP3
Definition: SIDefines.h:247
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_32_SINT
@ UFMT_32_32_32_32_SINT
Definition: SIDefines.h:583
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_SNORM
@ UFMT_16_16_16_16_SNORM
Definition: SIDefines.h:572
llvm::AMDGPU::Hwreg::IEEE_MODE_MASK
@ IEEE_MODE_MASK
Definition: SIDefines.h:411
llvm::SIInstrFlags::IsAtomicNoRet
@ IsAtomicNoRet
Definition: SIDefines.h:112
llvm::AMDGPU::DPP::DPP_FI_0
@ DPP_FI_0
Definition: SIDefines.h:722
llvm::AMDGPU::DPP::QUAD_PERM_LAST
@ QUAD_PERM_LAST
Definition: SIDefines.h:678
llvm::SIInstrFlags::LGKM_CNT
@ LGKM_CNT
Definition: SIDefines.h:61
llvm::SIInstrFlags::VGPRSpill
@ VGPRSpill
Definition: SIDefines.h:55
llvm::AMDGPU::MTBUFFormat::UFMT_MAX
@ UFMT_MAX
Definition: SIDefines.h:589
llvm::AMDGPU::DPP::DPP_UNUSED7_LAST
@ DPP_UNUSED7_LAST
Definition: SIDefines.h:702
llvm::AMDGPU::MTBUFFormat::UFMT_16_SNORM
@ UFMT_16_SNORM
Definition: SIDefines.h:504
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:115
llvm::AMDGPU::DPP::ROW_SHR0
@ ROW_SHR0
Definition: SIDefines.h:684
llvm::AMDGPU::MTBUFFormat::NumFormat
NumFormat
Definition: SIDefines.h:461
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_SINT
@ UFMT_32_32_SINT
Definition: SIDefines.h:568
llvm::AMDGPU::DPP::DPP8_FI_0
@ DPP8_FI_0
Definition: SIDefines.h:724
llvm::AMDGPU::MTBUFFormat::DFMT_2_10_10_10
@ DFMT_2_10_10_10
Definition: SIDefines.h:443
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_0
@ OP_SEL_HI_0
Definition: SIDefines.h:760
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:149
llvm::AMDGPU::DPP::BCAST31
@ BCAST31
Definition: SIDefines.h:706
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_USCALED
@ UFMT_10_10_10_2_USCALED
Definition: SIDefines.h:548
llvm::AMDGPU::SDWA::BYTE_1
@ BYTE_1
Definition: SIDefines.h:641
llvm::SIInstrFlags::DisableWQM
@ DisableWQM
Definition: SIDefines.h:64
llvm::AMDGPU::Hwreg::ID_SHIFT_
@ ID_SHIFT_
Definition: SIDefines.h:375
MCInstrDesc.h
llvm::AMDGPU::MTBUFFormat::DFMT_32
@ DFMT_32
Definition: SIDefines.h:438
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_UINT
@ UFMT_8_8_UINT
Definition: SIDefines.h:515
llvm::AMDGPU::MTBUFFormat::DFMT_8_8
@ DFMT_8_8
Definition: SIDefines.h:437
llvm::SIInstrFlags::SOPK
@ SOPK
Definition: SIDefines.h:28
llvm::AMDGPU::Hwreg::WidthMinusOne
WidthMinusOne
Definition: SIDefines.h:392
llvm::AMDGPU::MTBUFFormat::NFMT_RESERVED_6
@ NFMT_RESERVED_6
Definition: SIDefines.h:468
llvm::AMDGPU::Hwreg::ID_LDS_ALLOC
@ ID_LDS_ALLOC
Definition: SIDefines.h:359
llvm::SIInstrFlags::IntClamp
@ IntClamp
Definition: SIDefines.h:78
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX
@ INLINE_FLOATING_C_MAX
Definition: SIDefines.h:269
llvm::AMDGPU::MTBUFFormat::DFMT_MASK
@ DFMT_MASK
Definition: SIDefines.h:458
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_SSCALED
@ UFMT_16_16_SSCALED
Definition: SIDefines.h:525
llvm::AMDGPU::Swizzle::BITMASK_OR_SHIFT
@ BITMASK_OR_SHIFT
Definition: SIDefines.h:631
llvm::AMDGPU::MTBUFFormat::DFMT_10_10_10_2
@ DFMT_10_10_10_2
Definition: SIDefines.h:442
llvm::SIInstrFlags::SDWA
@ SDWA
Definition: SIDefines.h:41
llvm::SIInstrFlags::FPAtomic
@ FPAtomic
Definition: SIDefines.h:100
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_USCALED
@ UFMT_8_8_8_8_USCALED
Definition: SIDefines.h:562
llvm::AMDGPU::OPERAND_KIMM16
@ OPERAND_KIMM16
Definition: SIDefines.h:191
llvm::AMDGPU::DPP::DPP_UNUSED3
@ DPP_UNUSED3
Definition: SIDefines.h:687
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:143
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_UNORM
@ UFMT_16_16_16_16_UNORM
Definition: SIDefines.h:571
llvm::AMDGPU::SendMsg::ID_STALL_WAVE_GEN
@ ID_STALL_WAVE_GEN
Definition: SIDefines.h:299
llvm::AMDGPU::Swizzle::QUAD_PERM_ENC
@ QUAD_PERM_ENC
Definition: SIDefines.h:611
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_UINT
@ UFMT_8_8_8_8_UINT
Definition: SIDefines.h:564
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_UINT
@ UFMT_32_32_32_UINT
Definition: SIDefines.h:579
llvm::SIInstrFlags::VOPAsmPrefer32Bit
@ VOPAsmPrefer32Bit
Definition: SIDefines.h:69
llvm::AMDGPU::DPP::DPP8_FI_1
@ DPP8_FI_1
Definition: SIDefines.h:725
llvm::AMDGPU::MTBUFFormat::NFMT_UNDEF
@ NFMT_UNDEF
Definition: SIDefines.h:475
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_USCALED
@ UFMT_16_16_USCALED
Definition: SIDefines.h:524
llvm::AMDGPU::VGPRIndexMode::ID_SRC0
@ ID_SRC0
Definition: SIDefines.h:222
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_FLOAT
@ UFMT_16_16_16_16_FLOAT
Definition: SIDefines.h:577
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_USCALED
@ UFMT_16_16_16_16_USCALED
Definition: SIDefines.h:573
llvm::AMDGPU::Exp::ET_NULL
@ ET_NULL
Definition: SIDefines.h:736
llvm::AMDGPU::SendMsg::STREAM_ID_MASK_
@ STREAM_ID_MASK_
Definition: SIDefines.h:344
llvm::AMDGPU::MTBUFFormat::DFMT_32_32_32
@ DFMT_32_32_32
Definition: SIDefines.h:447
llvm::AMDGPU::MTBUFFormat::DFMT_8
@ DFMT_8
Definition: SIDefines.h:435
llvm::SIOutMods::DIV2
@ DIV2
Definition: SIDefines.h:214
llvm::AMDGPU::SendMsg::OP_GS_LAST_
@ OP_GS_LAST_
Definition: SIDefines.h:326
llvm::AMDGPU::SendMsg::ID_WIDTH_
@ ID_WIDTH_
Definition: SIDefines.h:310
llvm::AMDGPUAsmVariants::DEFAULT
@ DEFAULT
Definition: SIDefines.h:246
llvm::AMDGPU::VOP3PEncoding::OpSel
OpSel
Definition: SIDefines.h:759
llvm::AMDGPU::Swizzle::LANE_MASK
@ LANE_MASK
Definition: SIDefines.h:619
llvm::AMDGPU::SendMsg::STREAM_ID_WIDTH_
@ STREAM_ID_WIDTH_
Definition: SIDefines.h:343
llvm::AMDGPU::Hwreg::EXCP_EN_INVALID_MASK
@ EXCP_EN_INVALID_MASK
Definition: SIDefines.h:416
llvm::SIInstrFlags::IsPacked
@ IsPacked
Definition: SIDefines.h:88
llvm::SIInstrFlags::SCALAR_STORE
@ SCALAR_STORE
Definition: SIDefines.h:67
llvm::AMDGPU::SDWA::BYTE_0
@ BYTE_0
Definition: SIDefines.h:640
llvm::AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE
@ WIDTH_M1_SRC_PRIVATE_BASE
Definition: SIDefines.h:399
llvm::AMDGPU::DPP::DPP_UNUSED4_LAST
@ DPP_UNUSED4_LAST
Definition: SIDefines.h:693
llvm::AMDGPU::Hwreg::OFFSET_WIDTH_
@ OFFSET_WIDTH_
Definition: SIDefines.h:383
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX1030_
@ ID_SYMBOLIC_FIRST_GFX1030_
Definition: SIDefines.h:373
llvm::AMDGPU::EncValues::SGPR_MAX_GFX10
@ SGPR_MAX_GFX10
Definition: SIDefines.h:260
llvm::AMDGPU::Hwreg::ID_MASK_
@ ID_MASK_
Definition: SIDefines.h:377
llvm::AMDGPU::Exp::ET_POS0
@ ET_POS0
Definition: SIDefines.h:737
llvm::AMDGPU::OperandType
OperandType
Definition: SIDefines.h:135
llvm::AMDGPU::MTBUFFormat::DFMT_11_11_10
@ DFMT_11_11_10
Definition: SIDefines.h:441
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MAX
@ DFMT_NFMT_MAX
Definition: SIDefines.h:490
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_UNORM
@ UFMT_8_8_UNORM
Definition: SIDefines.h:511
llvm::AMDGPU::OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:145
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_SINT
@ UFMT_10_10_10_2_SINT
Definition: SIDefines.h:551
llvm::AMDGPU::SendMsg::OP_GS_CUT
@ OP_GS_CUT
Definition: SIDefines.h:323
llvm::AMDGPU::SendMsg::ID_EARLY_PRIM_DEALLOC
@ ID_EARLY_PRIM_DEALLOC
Definition: SIDefines.h:302
llvm::AMDGPU::DPP::ROW_XMASK0
@ ROW_XMASK0
Definition: SIDefines.h:714
llvm::AMDGPU::MTBUFFormat::NFMT_DEFAULT
@ NFMT_DEFAULT
Definition: SIDefines.h:476
llvm::AMDGPU::SDWA::UNUSED_PRESERVE
@ UNUSED_PRESERVE
Definition: SIDefines.h:652
llvm::AMDGPU::MTBUFFormat::NFMT_SNORM
@ NFMT_SNORM
Definition: SIDefines.h:463
llvm::AMDGPU::Swizzle::BITMASK_XOR_SHIFT
@ BITMASK_XOR_SHIFT
Definition: SIDefines.h:632
llvm::AMDGPU::MTBUFFormat::UFMT_8_SINT
@ UFMT_8_SINT
Definition: SIDefines.h:501
llvm::AMDGPU::DPP::ROW_MIRROR
@ ROW_MIRROR
Definition: SIDefines.h:703
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:732
llvm::AMDGPU::Swizzle::BITMASK_WIDTH
@ BITMASK_WIDTH
Definition: SIDefines.h:628
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_SI
@ SRC_SGPR_MAX_SI
Definition: SIDefines.h:664
llvm::AMDGPU::DPP::DPP_UNUSED1
@ DPP_UNUSED1
Definition: SIDefines.h:679
llvm::AMDGPU::MTBUFFormat::UFMT_16_UNORM
@ UFMT_16_UNORM
Definition: SIDefines.h:503
llvm::AMDGPU::MTBUFFormat::UFMT_8_SNORM
@ UFMT_8_SNORM
Definition: SIDefines.h:497
llvm::AMDGPU::SendMsg::OP_GS_EMIT
@ OP_GS_EMIT
Definition: SIDefines.h:324
llvm::AMDGPU::DPP::DPP_UNUSED7_FIRST
@ DPP_UNUSED7_FIRST
Definition: SIDefines.h:701
llvm::AMDGPU::Swizzle::LANE_MAX
@ LANE_MAX
Definition: SIDefines.h:620
llvm::AMDGPU::Hwreg::WIDTH_M1_DEFAULT_
@ WIDTH_M1_DEFAULT_
Definition: SIDefines.h:393
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_SNORM
@ UFMT_2_10_10_10_SNORM
Definition: SIDefines.h:554
llvm::AMDGPU::MTBUFFormat::UFMT_32_UINT
@ UFMT_32_UINT
Definition: SIDefines.h:518
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN
@ INLINE_INTEGER_C_MIN
Definition: SIDefines.h:265
llvm::SIInstrFlags::FIXED_SIZE
@ FIXED_SIZE
Definition: SIDefines.h:68
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_FLOAT
@ UFMT_10_11_11_FLOAT
Definition: SIDefines.h:536
llvm::AMDGPU::OPERAND_REG_IMM_LAST
@ OPERAND_REG_IMM_LAST
Definition: SIDefines.h:172
llvm::AMDGPU::SDWA::VOPC_DST_SGPR_MASK
@ VOPC_DST_SGPR_MASK
Definition: SIDefines.h:659
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX
@ INLINE_INTEGER_C_MAX
Definition: SIDefines.h:267
llvm::AMDGPU::VGPRIndexMode::SRC0_ENABLE
@ SRC0_ENABLE
Definition: SIDefines.h:233
llvm::SIInstrFlags::SOP2
@ SOP2
Definition: SIDefines.h:26
llvm::AMDGPU::SendMsg::Id
Id
Definition: SIDefines.h:293
llvm::AMDGPU::SendMsg::ID_GAPS_LAST_
@ ID_GAPS_LAST_
Definition: SIDefines.h:307
llvm::SIInstrFlags::renamedInGFX9
@ renamedInGFX9
Definition: SIDefines.h:72
llvm::AMDGPU::DPP::ROW_SHL_FIRST
@ ROW_SHL_FIRST
Definition: SIDefines.h:681
llvm::AMDGPU::Hwreg::EXCP_EN_INEXACT_MASK
@ EXCP_EN_INEXACT_MASK
Definition: SIDefines.h:421
Swizzle
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
Definition: R600InstrInfo.cpp:351
llvm::AMDGPU::Exp::ET_PARAM0
@ ET_PARAM0
Definition: SIDefines.h:742
llvm::SIOutMods::MUL2
@ MUL2
Definition: SIDefines.h:212
llvm::AMDGPU::SDWA::SRC_VGPR_MAX
@ SRC_VGPR_MAX
Definition: SIDefines.h:662
llvm::AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE
@ OFFSET_SRC_PRIVATE_BASE
Definition: SIDefines.h:389
llvm::AMDGPUAsmVariants::DPP
@ DPP
Definition: SIDefines.h:250
llvm::AMDGPU::SDWA::DstUnused
DstUnused
Definition: SIDefines.h:649
llvm::AMDGPU::Hwreg::ID_IB_STS
@ ID_IB_STS
Definition: SIDefines.h:360
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_UNORM
@ UFMT_11_11_10_UNORM
Definition: SIDefines.h:538
llvm::SIInstrFlags::Gather4
@ Gather4
Definition: SIDefines.h:65
llvm::AMDGPU::SendMsg::ID_SAVEWAVE
@ ID_SAVEWAVE
Definition: SIDefines.h:298
llvm::AMDGPU::MTBUFFormat::MergedFormat
MergedFormat
Definition: SIDefines.h:482
llvm::AMDGPU::MTBUFFormat::UFMT_16_FLOAT
@ UFMT_16_FLOAT
Definition: SIDefines.h:509
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:51
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_USCALED
@ UFMT_11_11_10_USCALED
Definition: SIDefines.h:540
llvm::AMDGPU::SendMsg::ID_MASK_
@ ID_MASK_
Definition: SIDefines.h:311
llvm::AMDGPU::SDWA::UNUSED_SEXT
@ UNUSED_SEXT
Definition: SIDefines.h:651
llvm::AMDGPU::SendMsg::OP_GS_EMIT_CUT
@ OP_GS_EMIT_CUT
Definition: SIDefines.h:325
llvm::AMDGPU::Hwreg::ID_TBA_HI
@ ID_TBA_HI
Definition: SIDefines.h:365
llvm::SIInstrFlags::VOP3
@ VOP3
Definition: SIDefines.h:37
llvm::AMDGPU::Hwreg::ID_UNKNOWN_
@ ID_UNKNOWN_
Definition: SIDefines.h:352
llvm::SIInstrFlags::IsMAI
@ IsMAI
Definition: SIDefines.h:103
llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC_MASK
@ BITMASK_PERM_ENC_MASK
Definition: SIDefines.h:615
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:49
llvm::AMDGPU::SDWA::SDWA9EncValues
SDWA9EncValues
Definition: SIDefines.h:655
llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST
@ OPERAND_REG_INLINE_AC_LAST
Definition: SIDefines.h:178
llvm::AMDGPU::SendMsg::OP_GS_FIRST_
@ OP_GS_FIRST_
Definition: SIDefines.h:327
llvm::AMDGPU::SendMsg::ID_GET_DOORBELL
@ ID_GET_DOORBELL
Definition: SIDefines.h:304
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:140
llvm::AMDGPU::CPol::CPol
CPol
Definition: SIDefines.h:281
llvm::AMDGPU::MTBUFFormat::DFMT_32_32_32_32
@ DFMT_32_32_32_32
Definition: SIDefines.h:448
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:48
llvm::AMDGPU::MTBUFFormat::UFMT_32_SINT
@ UFMT_32_SINT
Definition: SIDefines.h:519
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN
@ INLINE_FLOATING_C_MIN
Definition: SIDefines.h:268
llvm::SISrcMods::NEG_HI
@ NEG_HI
Definition: SIDefines.h:202
llvm::AMDGPU::SDWA::UNUSED_PAD
@ UNUSED_PAD
Definition: SIDefines.h:650
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_USCALED
@ UFMT_2_10_10_10_USCALED
Definition: SIDefines.h:555
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_32_UINT
@ UFMT_32_32_32_32_UINT
Definition: SIDefines.h:582
llvm::AMDGPU::VGPRIndexMode::ID_SRC2
@ ID_SRC2
Definition: SIDefines.h:224
llvm::AMDGPU::Exp::ET_INVALID
@ ET_INVALID
Definition: SIDefines.h:752
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT32
@ OPERAND_REG_INLINE_AC_V2INT32
Definition: SIDefines.h:168
llvm::AMDGPU::Hwreg::ID_WIDTH_
@ ID_WIDTH_
Definition: SIDefines.h:376
llvm::AMDGPU::Exp::ET_MRTZ_MAX_IDX
@ ET_MRTZ_MAX_IDX
Definition: SIDefines.h:746
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:150
llvm::AMDGPU::VGPRIndexMode::ENABLE_MASK
@ ENABLE_MASK
Definition: SIDefines.h:237
llvm::AMDGPU::Hwreg::ID_MODE
@ ID_MODE
Definition: SIDefines.h:354
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_SINT
@ UFMT_10_11_11_SINT
Definition: SIDefines.h:535
llvm::AMDGPU::DPP::DPP_UNUSED8_FIRST
@ DPP_UNUSED8_FIRST
Definition: SIDefines.h:707
llvm::AMDGPU::SendMsg::OP_SYS_LAST_
@ OP_SYS_LAST_
Definition: SIDefines.h:333
llvm::AMDGPU::SendMsg::ID_GS_ALLOC_REQ
@ ID_GS_ALLOC_REQ
Definition: SIDefines.h:303
llvm::AMDGPU::MTBUFFormat::UFMT_DEFAULT
@ UFMT_DEFAULT
Definition: SIDefines.h:592
llvm::SIInstrFlags::N_INFINITY
@ N_INFINITY
Definition: SIDefines.h:123
llvm::AMDGPU::Hwreg::ID_POPS_PACKER
@ ID_POPS_PACKER
Definition: SIDefines.h:371
llvm::AMDGPU::CPol::DLC
@ DLC
Definition: SIDefines.h:284
llvm::AMDGPU::Swizzle::BITMASK_MAX
@ BITMASK_MAX
Definition: SIDefines.h:627
llvm::AMDGPU::MTBUFFormat::UFMT_16_SSCALED
@ UFMT_16_SSCALED
Definition: SIDefines.h:506
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:163
llvm::AMDGPU::DPP::ROW_SHL0
@ ROW_SHL0
Definition: SIDefines.h:680
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_FLOAT
@ UFMT_11_11_10_FLOAT
Definition: SIDefines.h:544
llvm::AMDGPU::DPP::ROW_XMASK_FIRST
@ ROW_XMASK_FIRST
Definition: SIDefines.h:715
llvm::AMDGPU::EncValues::VGPR_MAX
@ VGPR_MAX
Definition: SIDefines.h:272
llvm::AMDGPU::SDWA::SRC_TTMP_MAX
@ SRC_TTMP_MAX
Definition: SIDefines.h:667
llvm::SIInstrFlags::WQM
@ WQM
Definition: SIDefines.h:63
llvm::AMDGPU::DPP::DPP_UNUSED4_FIRST
@ DPP_UNUSED4_FIRST
Definition: SIDefines.h:692
llvm::AMDGPU::SendMsg::STREAM_ID_LAST_
@ STREAM_ID_LAST_
Definition: SIDefines.h:340
llvm::AMDGPU::SendMsg::ID_SYSMSG
@ ID_SYSMSG
Definition: SIDefines.h:306
llvm::AMDGPU::Hwreg::Id
Id
Definition: SIDefines.h:351
llvm::SIOutMods::MUL4
@ MUL4
Definition: SIDefines.h:213
llvm::AMDGPU::SDWA::BYTE_2
@ BYTE_2
Definition: SIDefines.h:642
llvm::AMDGPU::SendMsg::ID_SHIFT_
@ ID_SHIFT_
Definition: SIDefines.h:309
llvm::AMDGPU::Hwreg::GPR_IDX_EN_MASK
@ GPR_IDX_EN_MASK
Definition: SIDefines.h:424
llvm::SIInstrFlags::VOP1
@ VOP1
Definition: SIDefines.h:32
llvm::AMDGPU::MTBUFFormat::DFMT_16_16_16_16
@ DFMT_16_16_16_16
Definition: SIDefines.h:446
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_SNORM
@ UFMT_8_8_8_8_SNORM
Definition: SIDefines.h:561
llvm::SIInstrFlags::SOPK_ZEXT
@ SOPK_ZEXT
Definition: SIDefines.h:66
llvm::AMDGPU::Exp::ET_PRIM
@ ET_PRIM
Definition: SIDefines.h:741
llvm::AMDGPU::MTBUFFormat::DFMT_16
@ DFMT_16
Definition: SIDefines.h:436
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_SSCALED
@ UFMT_10_11_11_SSCALED
Definition: SIDefines.h:533
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_SINT
@ UFMT_11_11_10_SINT
Definition: SIDefines.h:543
llvm::AMDGPU::SendMsg::OP_GS_NOP
@ OP_GS_NOP
Definition: SIDefines.h:322
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:141
llvm::AMDGPU::MTBUFFormat::UFMT_8_USCALED
@ UFMT_8_USCALED
Definition: SIDefines.h:498
llvm::AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE
@ WIDTH_M1_SRC_SHARED_BASE
Definition: SIDefines.h:398
llvm::AMDGPU::SendMsg::OP_SHIFT_
@ OP_SHIFT_
Definition: SIDefines.h:316
llvm::AMDGPU::SendMsg::STREAM_ID_DEFAULT_
@ STREAM_ID_DEFAULT_
Definition: SIDefines.h:339
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX9_
@ ID_SYMBOLIC_FIRST_GFX9_
Definition: SIDefines.h:362
llvm::AMDGPU::VGPRIndexMode::SRC1_ENABLE
@ SRC1_ENABLE
Definition: SIDefines.h:234
llvm::AMDGPU::SendMsg::OP_SYS_ECC_ERR_INTERRUPT
@ OP_SYS_ECC_ERR_INTERRUPT
Definition: SIDefines.h:329
llvm::AMDGPU::MTBUFFormat::DFMT_8_8_8_8
@ DFMT_8_8_8_8
Definition: SIDefines.h:444
llvm::AMDGPU::MTBUFFormat::DFMT_UNDEF
@ DFMT_UNDEF
Definition: SIDefines.h:454
llvm::SIInstrFlags::TRANS
@ TRANS
Definition: SIDefines.h:43
llvm::AMDGPU::Hwreg::ID_TBA_LO
@ ID_TBA_LO
Definition: SIDefines.h:363
llvm::AMDGPU::MTBUFFormat::DFMT_INVALID
@ DFMT_INVALID
Definition: SIDefines.h:434
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:146
llvm::AMDGPU::Hwreg::VSKIP_MASK
@ VSKIP_MASK
Definition: SIDefines.h:425
llvm::AMDGPU::Hwreg::ID_TMA_LO
@ ID_TMA_LO
Definition: SIDefines.h:366
llvm::AMDGPU::Hwreg::EXCP_EN_INT_DIV0_MASK
@ EXCP_EN_INT_DIV0_MASK
Definition: SIDefines.h:422
llvm::SIInstrFlags::VOPC
@ VOPC
Definition: SIDefines.h:34
llvm::AMDGPU::MTBUFFormat::UFMT_FIRST
@ UFMT_FIRST
Definition: SIDefines.h:586
llvm::SIInstrFlags::VM_CNT
@ VM_CNT
Definition: SIDefines.h:59
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:157
llvm::AMDGPU::MTBUFFormat::UFMT_UNDEF
@ UFMT_UNDEF
Definition: SIDefines.h:591
llvm::AMDGPU::SendMsg::StreamId
StreamId
Definition: SIDefines.h:337
llvm::SIInstrFlags::SOP1
@ SOP1
Definition: SIDefines.h:25
llvm::AMDGPU::SendMsg::ID_GAPS_FIRST_
@ ID_GAPS_FIRST_
Definition: SIDefines.h:308
llvm::SIInstrFlags::VALU
@ VALU
Definition: SIDefines.h:22
llvm::AMDGPU::Exp::ET_POS_LAST
@ ET_POS_LAST
Definition: SIDefines.h:740
llvm::AMDGPU::Swizzle::ID_REVERSE
@ ID_REVERSE
Definition: SIDefines.h:603
llvm::AMDGPU::SendMsg::ID_ORDERED_PS_DONE
@ ID_ORDERED_PS_DONE
Definition: SIDefines.h:301
llvm::AMDGPU::MTBUFFormat::NFMT_MIN
@ NFMT_MIN
Definition: SIDefines.h:472
llvm::AMDGPU::MTBUFFormat::UFMT_8_UNORM
@ UFMT_8_UNORM
Definition: SIDefines.h:496
llvm::AMDGPU::Hwreg::OFFSET_MASK_
@ OFFSET_MASK_
Definition: SIDefines.h:384
llvm::AMDGPU::EncValues::SGPR_MAX_SI
@ SGPR_MAX_SI
Definition: SIDefines.h:259
llvm::AMDGPU::OPERAND_SDWA_VOPC_DST
@ OPERAND_SDWA_VOPC_DST
Definition: SIDefines.h:187
llvm::SIInstrFlags::Q_NAN
@ Q_NAN
Definition: SIDefines.h:122
llvm::SIInstrFlags::FPDPRounding
@ FPDPRounding
Definition: SIDefines.h:97
llvm::AMDGPU::DPP::DPP_UNUSED6_FIRST
@ DPP_UNUSED6_FIRST
Definition: SIDefines.h:698
llvm::AMDGPU::Hwreg::WIDTH_M1_SHIFT_
@ WIDTH_M1_SHIFT_
Definition: SIDefines.h:394
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_USCALED
@ UFMT_10_11_11_USCALED
Definition: SIDefines.h:532
llvm::SIInstrFlags::D16Buf
@ D16Buf
Definition: SIDefines.h:91
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_2
@ OP_SEL_HI_2
Definition: SIDefines.h:762
llvm::AMDGPU::Swizzle::QUAD_PERM_ENC_MASK
@ QUAD_PERM_ENC_MASK
Definition: SIDefines.h:612
llvm::SIInstrFlags::SOPP
@ SOPP
Definition: SIDefines.h:29
llvm::SIInstrFlags::N_NORMAL
@ N_NORMAL
Definition: SIDefines.h:124
llvm::SISrcMods::NEG
@ NEG
Definition: SIDefines.h:199
llvm::AMDGPU::SDWA::SRC_VGPR_MASK
@ SRC_VGPR_MASK
Definition: SIDefines.h:657
llvm::AMDGPU::Hwreg::WIDTH_M1_WIDTH_
@ WIDTH_M1_WIDTH_
Definition: SIDefines.h:395
llvm::AMDGPU::Exp::ET_PARAM_MAX_IDX
@ ET_PARAM_MAX_IDX
Definition: SIDefines.h:750
llvm::AMDGPU::SendMsg::OP_SYS_REG_RD
@ OP_SYS_REG_RD
Definition: SIDefines.h:330
llvm::AMDGPU::MTBUFFormat::NFMT_MAX
@ NFMT_MAX
Definition: SIDefines.h:473
llvm::AMDGPU::Swizzle::LANE_NUM
@ LANE_NUM
Definition: SIDefines.h:622
llvm::SIInstrFlags::FlatScratch
@ FlatScratch
Definition: SIDefines.h:109
llvm::AMDGPU::VGPRIndexMode::ID_MIN
@ ID_MIN
Definition: SIDefines.h:227
llvm::AMDGPU::Hwreg::ID_FLAT_SCR_HI
@ ID_FLAT_SCR_HI
Definition: SIDefines.h:369
llvm::SIInstrFlags::SOPC
@ SOPC
Definition: SIDefines.h:27
llvm::AMDGPU::SDWA::SRC_VGPR_MIN
@ SRC_VGPR_MIN
Definition: SIDefines.h:661
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:380
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:151
llvm::SIInstrFlags::SALU
@ SALU
Definition: SIDefines.h:21
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_UINT
@ UFMT_16_16_UINT
Definition: SIDefines.h:526
llvm::SIInstrFlags::S_NAN
@ S_NAN
Definition: SIDefines.h:121
llvm::AMDGPU::CPol::GLC
@ GLC
Definition: SIDefines.h:282
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_FLOAT
@ UFMT_16_16_FLOAT
Definition: SIDefines.h:528
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_UNDEF
@ DFMT_NFMT_UNDEF
Definition: SIDefines.h:483
llvm::AMDGPU::VGPRIndexMode::EncBits
EncBits
Definition: SIDefines.h:231
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_SINT
@ UFMT_16_16_16_16_SINT
Definition: SIDefines.h:576
llvm::AMDGPU::MTBUFFormat::NFMT_MASK
@ NFMT_MASK
Definition: SIDefines.h:479
llvm::AMDGPU::MTBUFFormat::NFMT_SNORM_OGL
@ NFMT_SNORM_OGL
Definition: SIDefines.h:469
llvm::AMDGPU::DPP::DPP_UNUSED6_LAST
@ DPP_UNUSED6_LAST
Definition: SIDefines.h:699
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:153
llvm::SIInstrFlags::DPP
@ DPP
Definition: SIDefines.h:42
llvm::AMDGPU::MTBUFFormat::DFMT_SHIFT
@ DFMT_SHIFT
Definition: SIDefines.h:457
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_SINT
@ UFMT_32_32_32_SINT
Definition: SIDefines.h:580
llvm::AMDGPU::DPP::DppCtrl
DppCtrl
Definition: SIDefines.h:675
llvm::AMDGPU::DPP::DPP_UNUSED8_LAST
@ DPP_UNUSED8_LAST
Definition: SIDefines.h:708
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_UINT
@ UFMT_2_10_10_10_UINT
Definition: SIDefines.h:557
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_UINT
@ UFMT_10_11_11_UINT
Definition: SIDefines.h:534
llvm::AMDGPU::OPERAND_SRC_FIRST
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:180
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_SINT
@ UFMT_8_8_8_8_SINT
Definition: SIDefines.h:565
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_FLOAT
@ UFMT_32_32_32_FLOAT
Definition: SIDefines.h:581
llvm::AMDGPU::DPP::DPP_UNUSED2
@ DPP_UNUSED2
Definition: SIDefines.h:683
llvm::AMDGPU::MTBUFFormat::UFMT_32_FLOAT
@ UFMT_32_FLOAT
Definition: SIDefines.h:520
llvm::AMDGPU::Swizzle::ID_BROADCAST
@ ID_BROADCAST
Definition: SIDefines.h:604
llvm::AMDGPU::DPP::WAVE_SHL1
@ WAVE_SHL1
Definition: SIDefines.h:691
llvm::AMDGPU::Swizzle::ID_QUAD_PERM
@ ID_QUAD_PERM
Definition: SIDefines.h:600
llvm::AMDGPU::SDWA::DWORD
@ DWORD
Definition: SIDefines.h:646
llvm::AMDGPU::DPP::DPP_LAST
@ DPP_LAST
Definition: SIDefines.h:717
llvm::AMDGPU::MTBUFFormat::DFMT_32_32
@ DFMT_32_32
Definition: SIDefines.h:445
llvm::AMDGPU::Hwreg::FP_DENORM_MASK
@ FP_DENORM_MASK
Definition: SIDefines.h:409
llvm::AMDGPU::Hwreg::ID_HW_ID
@ ID_HW_ID
Definition: SIDefines.h:357
llvm::AMDGPU::SendMsg::OP_UNKNOWN_
@ OP_UNKNOWN_
Definition: SIDefines.h:315
llvm::AMDGPU::EncValues::TTMP_VI_MAX
@ TTMP_VI_MAX
Definition: SIDefines.h:262
llvm::AMDGPU::EncValues::VGPR_MIN
@ VGPR_MIN
Definition: SIDefines.h:271
llvm::AMDGPU::SendMsg::ID_INTERRUPT
@ ID_INTERRUPT
Definition: SIDefines.h:295
llvm::AMDGPU::EncValues::SGPR_MIN
@ SGPR_MIN
Definition: SIDefines.h:258
llvm::SIInstrFlags::ClassFlags
ClassFlags
Definition: SIDefines.h:120
llvm::SIInstrFlags::VOP3P
@ VOP3P
Definition: SIDefines.h:38
llvm::AMDGPU::DPP::BCAST15
@ BCAST15
Definition: SIDefines.h:705
llvm::AMDGPU::MTBUFFormat::DFMT_RESERVED_15
@ DFMT_RESERVED_15
Definition: SIDefines.h:449
llvm::AMDGPU::Hwreg::OFFSET_DEFAULT_
@ OFFSET_DEFAULT_
Definition: SIDefines.h:381
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:161
llvm::AMDGPU::Hwreg::ID_MEM_BASES
@ ID_MEM_BASES
Definition: SIDefines.h:361
llvm::AMDGPU::Swizzle::BITMASK_MASK
@ BITMASK_MASK
Definition: SIDefines.h:626
llvm::SIInstrFlags::ClampLo
@ ClampLo
Definition: SIDefines.h:81
llvm::AMDGPU::Hwreg::EXCP_EN_UNDERFLOW_MASK
@ EXCP_EN_UNDERFLOW_MASK
Definition: SIDefines.h:420
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_1
@ OP_SEL_HI_1
Definition: SIDefines.h:761
llvm::AMDGPU::CPol::ALL
@ ALL
Definition: SIDefines.h:286
llvm::AMDGPU::SDWA::SdwaSel
SdwaSel
Definition: SIDefines.h:639
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:155
llvm::AMDGPU::Exp::ET_MRT0
@ ET_MRT0
Definition: SIDefines.h:733
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MAX
@ TTMP_GFX9PLUS_MAX
Definition: SIDefines.h:264
llvm::SIInstrFlags::maybeAtomic
@ maybeAtomic
Definition: SIDefines.h:71
llvm::AMDGPU::Swizzle::BITMASK_AND_SHIFT
@ BITMASK_AND_SHIFT
Definition: SIDefines.h:630
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:164
llvm::AMDGPU::SDWA::SRC_SGPR_MIN
@ SRC_SGPR_MIN
Definition: SIDefines.h:663
llvm::AMDGPU::MTBUFFormat::DFMT_MIN
@ DFMT_MIN
Definition: SIDefines.h:451
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_SSCALED
@ UFMT_8_8_SSCALED
Definition: SIDefines.h:514
llvm::AMDGPU::OPERAND_REG_IMM_INT16
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:139
llvm::AMDGPU::CPol::SCC
@ SCC
Definition: SIDefines.h:285
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:162
llvm::SISrcMods::OP_SEL_0
@ OP_SEL_0
Definition: SIDefines.h:203
llvm::AMDGPU::VGPRIndexMode::UNDEF
@ UNDEF
Definition: SIDefines.h:238
llvm::AMDGPU::Exp::ET_MRTZ
@ ET_MRTZ
Definition: SIDefines.h:735
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_SINT
@ UFMT_2_10_10_10_SINT
Definition: SIDefines.h:558
llvm::AMDGPU::Hwreg::ID_XNACK_MASK
@ ID_XNACK_MASK
Definition: SIDefines.h:370
llvm::AMDGPU::Hwreg::WIDTH_DEFAULT_
@ WIDTH_DEFAULT_
Definition: SIDefines.h:404
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:46
llvm::AMDGPU::MTBUFFormat::UFMT_16_USCALED
@ UFMT_16_USCALED
Definition: SIDefines.h:505
llvm::AMDGPU::DPP::ROW_HALF_MIRROR
@ ROW_HALF_MIRROR
Definition: SIDefines.h:704
llvm::AMDGPU::Hwreg::OFFSET_SHIFT_
@ OFFSET_SHIFT_
Definition: SIDefines.h:382
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MIN
@ TTMP_GFX9PLUS_MIN
Definition: SIDefines.h:263
uint32_t
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_UINT
@ UFMT_10_10_10_2_UINT
Definition: SIDefines.h:550
llvm::SIInstrFlags::IsDOT
@ IsDOT
Definition: SIDefines.h:106
llvm::SIInstrFlags::FlatGlobal
@ FlatGlobal
Definition: SIDefines.h:94
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_SNORM
@ UFMT_10_11_11_SNORM
Definition: SIDefines.h:531
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_USCALED
@ UFMT_8_8_USCALED
Definition: SIDefines.h:513
llvm::AMDGPU::VGPRIndexMode::ID_MAX
@ ID_MAX
Definition: SIDefines.h:228
llvm::AMDGPU::Hwreg::LOD_CLAMP_MASK
@ LOD_CLAMP_MASK
Definition: SIDefines.h:412
llvm::AMDGPU::SendMsg::OP_SYS_HOST_TRAP_ACK
@ OP_SYS_HOST_TRAP_ACK
Definition: SIDefines.h:331
llvm::AMDGPU::SendMsg::ID_GS
@ ID_GS
Definition: SIDefines.h:296
llvm::AMDGPU::Hwreg::OFFSET_MEM_VIOL
@ OFFSET_MEM_VIOL
Definition: SIDefines.h:386
llvm::AMDGPU::SendMsg::ID_GS_DONE
@ ID_GS_DONE
Definition: SIDefines.h:297
llvm::AMDGPU::MTBUFFormat::UFMT_INVALID
@ UFMT_INVALID
Definition: SIDefines.h:494
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_GFX10
@ SRC_SGPR_MAX_GFX10
Definition: SIDefines.h:665
llvm::SISrcMods::DST_OP_SEL
@ DST_OP_SEL
Definition: SIDefines.h:205
llvm::AMDGPU::DPP::ROW_XMASK_LAST
@ ROW_XMASK_LAST
Definition: SIDefines.h:716
llvm::AMDGPU::VGPRIndexMode::DST_ENABLE
@ DST_ENABLE
Definition: SIDefines.h:236
llvm::AMDGPU::SendMsg::STREAM_ID_FIRST_
@ STREAM_ID_FIRST_
Definition: SIDefines.h:341
llvm::AMDGPU::MTBUFFormat::UFMT_LAST
@ UFMT_LAST
Definition: SIDefines.h:587
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_SSCALED
@ UFMT_8_8_8_8_SSCALED
Definition: SIDefines.h:563
llvm::SIInstrFlags::P_SUBNORMAL
@ P_SUBNORMAL
Definition: SIDefines.h:128
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_SINT
@ UFMT_16_16_SINT
Definition: SIDefines.h:527
llvm::AMDGPU::OPERAND_INPUT_MODS
@ OPERAND_INPUT_MODS
Definition: SIDefines.h:184
llvm::AMDGPU::Swizzle::EncBits
EncBits
Definition: SIDefines.h:607
llvm::SIInstrFlags::P_INFINITY
@ P_INFINITY
Definition: SIDefines.h:130
llvm::AMDGPU::EncValues::LITERAL_CONST
@ LITERAL_CONST
Definition: SIDefines.h:270
llvm::AMDGPU::SendMsg::OP_SYS_FIRST_
@ OP_SYS_FIRST_
Definition: SIDefines.h:334
llvm::AMDGPU::MTBUFFormat::NFMT_UINT
@ NFMT_UINT
Definition: SIDefines.h:466
llvm::AMDGPU::Hwreg::FP_ROUND_MASK
@ FP_ROUND_MASK
Definition: SIDefines.h:408
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:165
llvm::AMDGPU::SDWA::WORD_1
@ WORD_1
Definition: SIDefines.h:645
llvm::AMDGPUAsmVariants::SDWA
@ SDWA
Definition: SIDefines.h:248
llvm::AMDGPU::VGPRIndexMode::OFF
@ OFF
Definition: SIDefines.h:232
llvm::AMDGPU::DPP::WAVE_ROL1
@ WAVE_ROL1
Definition: SIDefines.h:694
llvm::AMDGPU::Hwreg::DEBUG_MASK
@ DEBUG_MASK
Definition: SIDefines.h:413
llvm::AMDGPU::Hwreg::ID_SHADER_CYCLES
@ ID_SHADER_CYCLES
Definition: SIDefines.h:372
llvm::AMDGPU::DPP::ROW_ROR0
@ ROW_ROR0
Definition: SIDefines.h:688
llvm::AMDGPU::SDWA::SRC_SGPR_MASK
@ SRC_SGPR_MASK
Definition: SIDefines.h:656
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_UINT
@ UFMT_16_16_16_16_UINT
Definition: SIDefines.h:575
llvm::AMDGPU::OPERAND_SRC_LAST
@ OPERAND_SRC_LAST
Definition: SIDefines.h:181
llvm::AMDGPU::OPERAND_KIMM32
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:190
llvm::SIInstrFlags::P_ZERO
@ P_ZERO
Definition: SIDefines.h:127
llvm::AMDGPU::Exp::ET_MRT7
@ ET_MRT7
Definition: SIDefines.h:734
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_SNORM
@ UFMT_16_16_SNORM
Definition: SIDefines.h:523
llvm::AMDGPU::MTBUFFormat::DFMT_10_11_11
@ DFMT_10_11_11
Definition: SIDefines.h:440
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:144
SDWA
@ SDWA
Definition: SIInstrInfo.cpp:7543
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_DEFAULT
@ DFMT_NFMT_DEFAULT
Definition: SIDefines.h:484
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::AMDGPU::Exp::ET_POS4
@ ET_POS4
Definition: SIDefines.h:739
llvm::AMDGPU::MTBUFFormat::NFMT_SSCALED
@ NFMT_SSCALED
Definition: SIDefines.h:465
llvm::SISrcMods::OP_SEL_1
@ OP_SEL_1
Definition: SIDefines.h:204
llvm::AMDGPU::SendMsg::ID_GET_DDID
@ ID_GET_DDID
Definition: SIDefines.h:305
llvm::SIInstrFlags::EXP
@ EXP
Definition: SIDefines.h:50
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:156
llvm::AMDGPU::Exp::ET_POS3
@ ET_POS3
Definition: SIDefines.h:738
llvm::AMDGPU::VGPRIndexMode::ID_SRC1
@ ID_SRC1
Definition: SIDefines.h:223
llvm::AMDGPU::CPol::SLC
@ SLC
Definition: SIDefines.h:283
llvm::AMDGPU::DPP::ROW_SHR_LAST
@ ROW_SHR_LAST
Definition: SIDefines.h:686
llvm::AMDGPU::MTBUFFormat::NFMT_SINT
@ NFMT_SINT
Definition: SIDefines.h:467
llvm::AMDGPU::Swizzle::ID_SWAP
@ ID_SWAP
Definition: SIDefines.h:602
llvm::AMDGPU::SendMsg::OP_WIDTH_
@ OP_WIDTH_
Definition: SIDefines.h:319
llvm::AMDGPU::DPP::QUAD_PERM_ID
@ QUAD_PERM_ID
Definition: SIDefines.h:677
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_UNORM
@ UFMT_8_8_8_8_UNORM
Definition: SIDefines.h:560
llvm::AMDGPU::DPP::DppFiMode
DppFiMode
Definition: SIDefines.h:721
llvm::AMDGPU::OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:174
llvm::SIInstrFlags::SGPRSpill
@ SGPRSpill
Definition: SIDefines.h:56
llvm::AMDGPU::DPP::ROW_SHARE_LAST
@ ROW_SHARE_LAST
Definition: SIDefines.h:713
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_UNORM
@ UFMT_2_10_10_10_UNORM
Definition: SIDefines.h:553
llvm::AMDGPU::SendMsg::ID_UNKNOWN_
@ ID_UNKNOWN_
Definition: SIDefines.h:294
llvm::AMDGPU::DPP::ROW_SHARE0
@ ROW_SHARE0
Definition: SIDefines.h:711
llvm::AMDGPU::SendMsg::STREAM_ID_NONE_
@ STREAM_ID_NONE_
Definition: SIDefines.h:338
llvm::AMDGPU::Hwreg::ID_GPR_ALLOC
@ ID_GPR_ALLOC
Definition: SIDefines.h:358
llvm::AMDGPU::MTBUFFormat::NFMT_SHIFT
@ NFMT_SHIFT
Definition: SIDefines.h:478
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:158
llvm::AMDGPU::Swizzle::LANE_SHIFT
@ LANE_SHIFT
Definition: SIDefines.h:621
llvm::AMDGPU::SendMsg::OP_SYS_TTRACE_PC
@ OP_SYS_TTRACE_PC
Definition: SIDefines.h:332
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_
@ ID_SYMBOLIC_FIRST_
Definition: SIDefines.h:353
llvm::AMDGPU::Hwreg::EXCP_EN_OVERFLOW_MASK
@ EXCP_EN_OVERFLOW_MASK
Definition: SIDefines.h:419
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::AMDGPU::MTBUFFormat::NFMT_UNORM
@ NFMT_UNORM
Definition: SIDefines.h:462
llvm::AMDGPU::SendMsg::STREAM_ID_SHIFT_
@ STREAM_ID_SHIFT_
Definition: SIDefines.h:342
llvm::AMDGPU::OPERAND_REG_IMM_FIRST
@ OPERAND_REG_IMM_FIRST
Definition: SIDefines.h:171
llvm::AMDGPU::Hwreg::ID_TMA_HI
@ ID_TMA_HI
Definition: SIDefines.h:367
llvm::AMDGPU::VGPRIndexMode::SRC2_ENABLE
@ SRC2_ENABLE
Definition: SIDefines.h:235
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:76
llvm::AMDGPU::MTBUFFormat::UFMT_8_UINT
@ UFMT_8_UINT
Definition: SIDefines.h:500
llvm::AMDGPU::Hwreg::WIDTH_M1_MASK_
@ WIDTH_M1_MASK_
Definition: SIDefines.h:396
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_32_FLOAT
@ UFMT_32_32_32_32_FLOAT
Definition: SIDefines.h:584
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:52
llvm::AMDGPU::Exp::ET_POS_MAX_IDX
@ ET_POS_MAX_IDX
Definition: SIDefines.h:749
llvm::SIInstrFlags::EXP_CNT
@ EXP_CNT
Definition: SIDefines.h:60
llvm::SIInstrFlags::N_ZERO
@ N_ZERO
Definition: SIDefines.h:126
llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST
@ ROW_NEWBCAST_FIRST
Definition: SIDefines.h:709
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_SNORM
@ UFMT_11_11_10_SNORM
Definition: SIDefines.h:539
llvm::AMDGPU::SDWA::WORD_0
@ WORD_0
Definition: SIDefines.h:644
llvm::AMDGPU::SDWA::VOPC_DST_VCC_MASK
@ VOPC_DST_VCC_MASK
Definition: SIDefines.h:658
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_UNORM
@ UFMT_16_16_UNORM
Definition: SIDefines.h:522
llvm::AMDGPU::DPP::DPP_UNUSED5_FIRST
@ DPP_UNUSED5_FIRST
Definition: SIDefines.h:695
llvm::AMDGPU::DPP::ROW_ROR_LAST
@ ROW_ROR_LAST
Definition: SIDefines.h:690
llvm::AMDGPU::Swizzle::ID_BITMASK_PERM
@ ID_BITMASK_PERM
Definition: SIDefines.h:601
llvm::AMDGPU::Exp::ET_PRIM_MAX_IDX
@ ET_PRIM_MAX_IDX
Definition: SIDefines.h:747
llvm::AMDGPU::Hwreg::DX10_CLAMP_MASK
@ DX10_CLAMP_MASK
Definition: SIDefines.h:410
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MASK
@ DFMT_NFMT_MASK
Definition: SIDefines.h:488
llvm::AMDGPU::Swizzle::Id
Id
Definition: SIDefines.h:599
llvm::SIInstrFlags::VOP2
@ VOP2
Definition: SIDefines.h:33
llvm::SIInstrFlags::ClampHi
@ ClampHi
Definition: SIDefines.h:85
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_SSCALED
@ UFMT_11_11_10_SSCALED
Definition: SIDefines.h:541
llvm::AMDGPU::Hwreg::ModeRegisterMasks
ModeRegisterMasks
Definition: SIDefines.h:407
llvm::AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE
@ OFFSET_SRC_SHARED_BASE
Definition: SIDefines.h:388
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:137
llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST
@ ROW_NEWBCAST_LAST
Definition: SIDefines.h:710
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_UINT
@ UFMT_32_32_UINT
Definition: SIDefines.h:567
llvm::AMDGPU::Exp::ET_NULL_MAX_IDX
@ ET_NULL_MAX_IDX
Definition: SIDefines.h:745
llvm::SIInstrFlags::N_SUBNORMAL
@ N_SUBNORMAL
Definition: SIDefines.h:125
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:152
llvm::AMDGPU::Hwreg::ID_STATUS
@ ID_STATUS
Definition: SIDefines.h:355
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_SINT
@ UFMT_8_8_SINT
Definition: SIDefines.h:516
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:47
llvm::AMDGPU::MTBUFFormat::UnifiedFormat
UnifiedFormat
Definition: SIDefines.h:493
llvm::AMDGPU::MTBUFFormat::NFMT_FLOAT
@ NFMT_FLOAT
Definition: SIDefines.h:470
llvm::AMDGPU::Hwreg::ID_FLAT_SCR_LO
@ ID_FLAT_SCR_LO
Definition: SIDefines.h:368
llvm::AMDGPU::SDWA::SRC_TTMP_MIN
@ SRC_TTMP_MIN
Definition: SIDefines.h:666
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_LAST_
@ ID_SYMBOLIC_LAST_
Definition: SIDefines.h:374
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_AC_FIRST
Definition: SIDefines.h:177
llvm::SISrcMods::ABS
@ ABS
Definition: SIDefines.h:200
llvm::AMDGPU::Hwreg::ID_TRAPSTS
@ ID_TRAPSTS
Definition: SIDefines.h:356
llvm::AMDGPU::SendMsg::OP_NONE_
@ OP_NONE_
Definition: SIDefines.h:317
llvm::AMDGPU::DPP::DPP_FI_1
@ DPP_FI_1
Definition: SIDefines.h:723
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:142
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_POSITIVE_MAX
@ INLINE_INTEGER_C_POSITIVE_MAX
Definition: SIDefines.h:266
llvm::AMDGPU::Exp::ET_PARAM31
@ ET_PARAM31
Definition: SIDefines.h:743
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_SNORM
@ UFMT_8_8_SNORM
Definition: SIDefines.h:512
llvm::AMDGPU::Hwreg::EXCP_EN_FLOAT_DIV0_MASK
@ EXCP_EN_FLOAT_DIV0_MASK
Definition: SIDefines.h:418
llvm::AMDGPU::MTBUFFormat::UFMT_16_UINT
@ UFMT_16_UINT
Definition: SIDefines.h:507
llvm::SIInstrFlags::VINTRP
@ VINTRP
Definition: SIDefines.h:40
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:166
llvm::AMDGPU::SDWA::BYTE_3
@ BYTE_3
Definition: SIDefines.h:643
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:221
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_UNORM
@ UFMT_10_10_10_2_UNORM
Definition: SIDefines.h:546
llvm::AMDGPU::VGPRIndexMode::ID_DST
@ ID_DST
Definition: SIDefines.h:225
llvm::AMDGPU::Hwreg::CSP_MASK
@ CSP_MASK
Definition: SIDefines.h:426
llvm::AMDGPU::MTBUFFormat::UFMT_8_SSCALED
@ UFMT_8_SSCALED
Definition: SIDefines.h:499
llvm::AMDGPU::DPP::QUAD_PERM_FIRST
@ QUAD_PERM_FIRST
Definition: SIDefines.h:676
llvm::AMDGPU::SendMsg::OP_MASK_
@ OP_MASK_
Definition: SIDefines.h:320
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_SSCALED
@ UFMT_16_16_16_16_SSCALED
Definition: SIDefines.h:574
llvm::SIInstrFlags::P_NORMAL
@ P_NORMAL
Definition: SIDefines.h:129
llvm::AMDGPU::Exp::ET_MRT_MAX_IDX
@ ET_MRT_MAX_IDX
Definition: SIDefines.h:748
llvm::AMDGPU::SendMsg::ID_HALT_WAVES
@ ID_HALT_WAVES
Definition: SIDefines.h:300
llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC
@ BITMASK_PERM_ENC
Definition: SIDefines.h:614
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_SNORM
@ UFMT_10_10_10_2_SNORM
Definition: SIDefines.h:547
llvm::SIInstrFlags::FPClamp
@ FPClamp
Definition: SIDefines.h:75
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX10_
@ ID_SYMBOLIC_FIRST_GFX10_
Definition: SIDefines.h:364
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_FLOAT
@ UFMT_32_32_FLOAT
Definition: SIDefines.h:569
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:138
llvm::AMDGPU::DPP::WAVE_ROR1
@ WAVE_ROR1
Definition: SIDefines.h:700
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_UNORM
@ UFMT_10_11_11_UNORM
Definition: SIDefines.h:530
llvm::AMDGPU::MTBUFFormat::NFMT_USCALED
@ NFMT_USCALED
Definition: SIDefines.h:464
llvm::SIInstrFlags::VOP3_OPSEL
@ VOP3_OPSEL
Definition: SIDefines.h:70
llvm::AMDGPU::MTBUFFormat::DFMT_16_16
@ DFMT_16_16
Definition: SIDefines.h:439
llvm::AMDGPU::DPP::DPP_UNUSED5_LAST
@ DPP_UNUSED5_LAST
Definition: SIDefines.h:696
llvm::AMDGPU::EncValues::TTMP_VI_MIN
@ TTMP_VI_MIN
Definition: SIDefines.h:261
llvm::AMDGPU::MTBUFFormat::UFMT_16_SINT
@ UFMT_16_SINT
Definition: SIDefines.h:508
llvm::AMDGPU::DPP::WAVE_SHR1
@ WAVE_SHR1
Definition: SIDefines.h:697
llvm::AMDGPU::OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:175
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_SSCALED
@ UFMT_2_10_10_10_SSCALED
Definition: SIDefines.h:556
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP32
@ OPERAND_REG_INLINE_AC_V2FP32
Definition: SIDefines.h:169
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:167
llvm::AMDGPU::MTBUFFormat::DFMT_MAX
@ DFMT_MAX
Definition: SIDefines.h:452
llvm::AMDGPU::DPP::ROW_SHARE_FIRST
@ ROW_SHARE_FIRST
Definition: SIDefines.h:712
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_UINT
@ UFMT_11_11_10_UINT
Definition: SIDefines.h:542