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10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
25 namespace SIInstrFlags {
77 WQM = UINT64_C(1) << 35,
214 namespace SISrcMods {
226 namespace SIOutMods {
236 namespace VGPRIndexMode {
261 namespace AMDGPUAsmVariants {
273 namespace EncValues {
464 namespace MTBUFFormat {
534 namespace UfmtGFX10 {
634 namespace UfmtGFX11 {
883 namespace VOP3PEncoding {
893 namespace ImplicitArg {
907 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
908 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
909 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
910 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
911 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
912 #define C_00B028_MEM_ORDERED 0xFDFFFFFF
914 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
915 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
916 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
917 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
918 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
919 #define C_00B128_MEM_ORDERED 0xF7FFFFFF
921 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
922 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
923 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
924 #define C_00B228_WGP_MODE 0xF7FFFFFF
925 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
926 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
927 #define C_00B228_MEM_ORDERED 0xFDFFFFFF
929 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
930 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
931 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
932 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
933 #define C_00B428_WGP_MODE 0xFBFFFFFF
934 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
935 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
936 #define C_00B428_MEM_ORDERED 0xFEFFFFFF
938 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
940 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
941 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
942 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
943 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
944 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
945 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
946 #define C_00B84C_USER_SGPR 0xFFFFFFC1
947 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
948 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
949 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
950 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
951 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
952 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
953 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
954 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
955 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
956 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
957 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
958 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
959 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
960 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
961 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
962 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
963 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
964 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
966 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
967 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
968 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
970 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
971 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
972 #define C_00B84C_LDS_SIZE 0xFF007FFF
973 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
974 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
975 #define C_00B84C_EXCP_EN
977 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
978 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
980 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
981 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
982 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
983 #define C_00B848_VGPRS 0xFFFFFFC0
984 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
985 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
986 #define C_00B848_SGPRS 0xFFFFFC3F
987 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
988 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
989 #define C_00B848_PRIORITY 0xFFFFF3FF
990 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
991 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
992 #define C_00B848_FLOAT_MODE 0xFFF00FFF
993 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
994 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
995 #define C_00B848_PRIV 0xFFEFFFFF
996 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
997 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
998 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
999 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1000 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1001 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
1002 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1003 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1004 #define C_00B848_IEEE_MODE 0xFF7FFFFF
1005 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1006 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1007 #define C_00B848_WGP_MODE 0xDFFFFFFF
1008 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1009 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1010 #define C_00B848_MEM_ORDERED 0xBFFFFFFF
1011 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1012 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1013 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1017 #define FP_ROUND_ROUND_TO_NEAREST 0
1018 #define FP_ROUND_ROUND_TO_INF 1
1019 #define FP_ROUND_ROUND_TO_NEGINF 2
1020 #define FP_ROUND_ROUND_TO_ZERO 3
1024 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1025 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1027 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1028 #define FP_DENORM_FLUSH_OUT 1
1029 #define FP_DENORM_FLUSH_IN 2
1030 #define FP_DENORM_FLUSH_NONE 3
1035 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1036 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1038 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1039 #define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1040 #define S_00B860_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1042 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1043 #define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1044 #define S_0286E8_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1046 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1047 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1048 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1049 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1050 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1051 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1052 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1053 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1055 #define R_SPILLED_SGPRS 0x4
1056 #define R_SPILLED_VGPRS 0x8
@ OPERAND_REG_INLINE_C_FP64
@ EXCP_EN_INPUT_DENORMAL_MASK
@ UFMT_16_16_16_16_USCALED
This is an optimization pass for GlobalISel generic memory operations.
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ UFMT_10_10_10_2_USCALED
@ ID_HS_TESSFACTOR_GFX11Plus
@ WIDTH_M1_SRC_PRIVATE_BASE
@ OPERAND_REG_IMM_V2INT32
@ UFMT_16_16_16_16_SSCALED
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
@ OFFSET_SRC_PRIVATE_BASE
@ ID_SQ_PERF_SNAPSHOT_PC_LO
@ ID_DEALLOC_VGPRS_GFX11Plus
@ OPERAND_REG_INLINE_AC_LAST
@ OPERAND_REG_INLINE_AC_V2INT32
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_AC_FP16
@ WIDTH_M1_SRC_SHARED_BASE
@ OP_SYS_ECC_ERR_INTERRUPT
@ OPERAND_REG_INLINE_C_V2INT32
@ ID_SQ_PERF_SNAPSHOT_DATA
@ OPERAND_REG_IMM_FP16_DEFERRED
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_FP32
@ UFMT_2_10_10_10_USCALED
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_IMM_FP32_DEFERRED
@ UFMT_10_10_10_2_SSCALED
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_INT32
@ ID_SQ_PERF_SNAPSHOT_PC_HI
@ UFMT_2_10_10_10_USCALED
@ INLINE_INTEGER_C_POSITIVE_MAX
@ OPERAND_REG_INLINE_AC_FP64
@ MULTIGRID_SYNC_ARG_OFFSET
@ ET_DUAL_SRC_BLEND_MAX_IDX
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
@ OPERAND_REG_IMM_V2INT16
@ UFMT_2_10_10_10_SSCALED
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_V2FP32
@ UFMT_2_10_10_10_SSCALED
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_AC_FIRST
@ ID_SQ_PERF_SNAPSHOT_DATA1
@ EXCP_EN_FLOAT_DIV0_MASK
@ OPERAND_REG_INLINE_AC_V2INT16
@ UFMT_16_16_16_16_USCALED
@ UFMT_16_16_16_16_SSCALED
@ OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_AC_V2FP32
@ OPERAND_REG_INLINE_AC_V2FP16