LLVM  14.0.0git
SIDefines.h
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1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12 
13 #include "llvm/MC/MCInstrDesc.h"
14 
15 namespace llvm {
16 
17 // This needs to be kept in sync with the field bits in SIRegisterClass.
18 enum SIRCFlags : uint8_t {
19  // For vector registers.
20  HasVGPR = 1 << 0,
21  HasAGPR = 1 << 1,
22  HasSGPR = 1 << 2
23 }; // enum SIRCFlags
24 
25 namespace SIInstrFlags {
26 // This needs to be kept in sync with the field bits in InstSI.
27 enum : uint64_t {
28  // Low bits - basic encoding information.
29  SALU = 1 << 0,
30  VALU = 1 << 1,
31 
32  // SALU instruction formats.
33  SOP1 = 1 << 2,
34  SOP2 = 1 << 3,
35  SOPC = 1 << 4,
36  SOPK = 1 << 5,
37  SOPP = 1 << 6,
38 
39  // VALU instruction formats.
40  VOP1 = 1 << 7,
41  VOP2 = 1 << 8,
42  VOPC = 1 << 9,
43 
44  // TODO: Should this be spilt into VOP3 a and b?
45  VOP3 = 1 << 10,
46  VOP3P = 1 << 12,
47 
48  VINTRP = 1 << 13,
49  SDWA = 1 << 14,
50  DPP = 1 << 15,
51  TRANS = 1 << 16,
52 
53  // Memory instruction formats.
54  MUBUF = 1 << 17,
55  MTBUF = 1 << 18,
56  SMRD = 1 << 19,
57  MIMG = 1 << 20,
58  EXP = 1 << 21,
59  FLAT = 1 << 22,
60  DS = 1 << 23,
61 
62  // Pseudo instruction formats.
63  VGPRSpill = 1 << 24,
64  SGPRSpill = 1 << 25,
65 
66  // High bits - other information.
67  VM_CNT = UINT64_C(1) << 32,
68  EXP_CNT = UINT64_C(1) << 33,
69  LGKM_CNT = UINT64_C(1) << 34,
70 
71  WQM = UINT64_C(1) << 35,
72  DisableWQM = UINT64_C(1) << 36,
73  Gather4 = UINT64_C(1) << 37,
74  SOPK_ZEXT = UINT64_C(1) << 38,
75  SCALAR_STORE = UINT64_C(1) << 39,
76  FIXED_SIZE = UINT64_C(1) << 40,
77  VOPAsmPrefer32Bit = UINT64_C(1) << 41,
78  VOP3_OPSEL = UINT64_C(1) << 42,
79  maybeAtomic = UINT64_C(1) << 43,
80  renamedInGFX9 = UINT64_C(1) << 44,
81 
82  // Is a clamp on FP type.
83  FPClamp = UINT64_C(1) << 45,
84 
85  // Is an integer clamp
86  IntClamp = UINT64_C(1) << 46,
87 
88  // Clamps lo component of register.
89  ClampLo = UINT64_C(1) << 47,
90 
91  // Clamps hi component of register.
92  // ClampLo and ClampHi set for packed clamp.
93  ClampHi = UINT64_C(1) << 48,
94 
95  // Is a packed VOP3P instruction.
96  IsPacked = UINT64_C(1) << 49,
97 
98  // Is a D16 buffer instruction.
99  D16Buf = UINT64_C(1) << 50,
100 
101  // FLAT instruction accesses FLAT_GLBL segment.
102  FlatGlobal = UINT64_C(1) << 51,
103 
104  // Uses floating point double precision rounding mode
105  FPDPRounding = UINT64_C(1) << 52,
106 
107  // Instruction is FP atomic.
108  FPAtomic = UINT64_C(1) << 53,
109 
110  // Is a MFMA instruction.
111  IsMAI = UINT64_C(1) << 54,
112 
113  // Is a DOT instruction.
114  IsDOT = UINT64_C(1) << 55,
115 
116  // FLAT instruction accesses FLAT_SCRATCH segment.
117  FlatScratch = UINT64_C(1) << 56,
118 
119  // Atomic without return.
120  IsAtomicNoRet = UINT64_C(1) << 57,
121 
122  // Atomic with return.
123  IsAtomicRet = UINT64_C(1) << 58
124 };
125 
126 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
127 // The result is true if any of these tests are true.
128 enum ClassFlags : unsigned {
129  S_NAN = 1 << 0, // Signaling NaN
130  Q_NAN = 1 << 1, // Quiet NaN
131  N_INFINITY = 1 << 2, // Negative infinity
132  N_NORMAL = 1 << 3, // Negative normal
133  N_SUBNORMAL = 1 << 4, // Negative subnormal
134  N_ZERO = 1 << 5, // Negative zero
135  P_ZERO = 1 << 6, // Positive zero
136  P_SUBNORMAL = 1 << 7, // Positive subnormal
137  P_NORMAL = 1 << 8, // Positive normal
138  P_INFINITY = 1 << 9 // Positive infinity
139 };
140 }
141 
142 namespace AMDGPU {
143 enum OperandType : unsigned {
144  /// Operands with register or 32-bit immediate
157 
158  /// Operands with register or inline constant
169 
170  /// Operand with 32-bit immediate that uses the constant bus.
173 
174  /// Operands with an AccVGPR register or inline constant
184 
187 
190 
193 
196 
197  // Operand for source modifiers for VOP instructions
199 
200  // Operand for SDWA instructions
202 
203 };
204 }
205 
206 // Input operand modifiers bit-masks
207 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
208 namespace SISrcMods {
209  enum : unsigned {
210  NEG = 1 << 0, // Floating-point negate modifier
211  ABS = 1 << 1, // Floating-point absolute modifier
212  SEXT = 1 << 0, // Integer sign-extend modifier
213  NEG_HI = ABS, // Floating-point negate high packed component modifier.
214  OP_SEL_0 = 1 << 2,
215  OP_SEL_1 = 1 << 3,
216  DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
217  };
218 }
219 
220 namespace SIOutMods {
221  enum : unsigned {
222  NONE = 0,
223  MUL2 = 1,
224  MUL4 = 2,
225  DIV2 = 3
226  };
227 }
228 
229 namespace AMDGPU {
230 namespace VGPRIndexMode {
231 
232 enum Id : unsigned { // id of symbolic names
233  ID_SRC0 = 0,
237 
240 };
241 
242 enum EncBits : unsigned {
243  OFF = 0,
249  UNDEF = 0xFFFF
250 };
251 
252 } // namespace VGPRIndexMode
253 } // namespace AMDGPU
254 
255 namespace AMDGPUAsmVariants {
256  enum : unsigned {
257  DEFAULT = 0,
258  VOP3 = 1,
259  SDWA = 2,
260  SDWA9 = 3,
261  DPP = 4
262  };
263 }
264 
265 namespace AMDGPU {
266 namespace EncValues { // Encoding values of enum9/8/7 operands
267 
268 enum : unsigned {
269  SGPR_MIN = 0,
270  SGPR_MAX_SI = 101,
272  TTMP_VI_MIN = 112,
273  TTMP_VI_MAX = 123,
282  VGPR_MIN = 256,
283  VGPR_MAX = 511
284 };
285 
286 } // namespace EncValues
287 } // namespace AMDGPU
288 
289 namespace AMDGPU {
290 namespace CPol {
291 
292 enum CPol {
293  GLC = 1,
294  SLC = 2,
295  DLC = 4,
296  SCC = 16,
297  ALL = GLC | SLC | DLC | SCC
298 };
299 
300 } // namespace CPol
301 
302 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
303 
304 enum Id { // Message ID, width(4) [3:0].
307  ID_GS = 2,
309  ID_SAVEWAVE = 4, // added in GFX8
310  ID_STALL_WAVE_GEN = 5, // added in GFX9
311  ID_HALT_WAVES = 6, // added in GFX9
312  ID_ORDERED_PS_DONE = 7, // added in GFX9
313  ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
314  ID_GS_ALLOC_REQ = 9, // added in GFX9
315  ID_GET_DOORBELL = 10, // added in GFX9
316  ID_GET_DDID = 11, // added in GFX10
317  ID_SYSMSG = 15,
318  ID_GAPS_LAST_, // Indicate that sequence has gaps.
322  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
323 };
324 
325 enum Op { // Both GS and SYS operation IDs.
328  OP_NONE_ = 0,
329  // Bits used for operation encoding
331  OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
332  // GS operations are encoded in bits 5:4
339  // SYS operations are encoded in bits 6:4
346 };
347 
348 enum StreamId : unsigned { // Stream ID, (2) [9:8].
356 };
357 
358 } // namespace SendMsg
359 
360 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
361 
362 enum Id { // HwRegCode, (6) [5:0]
364  ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
365  ID_MODE = 1,
368  ID_HW_ID = 4,
374  ID_TBA_LO = 16,
376  ID_TBA_HI = 17,
377  ID_TMA_LO = 18,
378  ID_TMA_HI = 19,
382  ID_HW_ID1 = 23,
383  ID_HW_ID2 = 24,
390  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
391 };
392 
393 enum Offset : unsigned { // Offset, (5) [10:6]
398 
400 
403 };
404 
405 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
410 
413 };
414 
415 // Some values from WidthMinusOne mapped into Width domain.
416 enum Width : unsigned {
418 };
419 
421  FP_ROUND_MASK = 0xf << 0, // Bits 0..3
422  FP_DENORM_MASK = 0xf << 4, // Bits 4..7
423  DX10_CLAMP_MASK = 1 << 8,
424  IEEE_MODE_MASK = 1 << 9,
425  LOD_CLAMP_MASK = 1 << 10,
426  DEBUG_MASK = 1 << 11,
427 
428  // EXCP_EN fields.
436 
437  GPR_IDX_EN_MASK = 1 << 27,
438  VSKIP_MASK = 1 << 28,
439  CSP_MASK = 0x7u << 29 // Bits 29..31
440 };
441 
442 } // namespace Hwreg
443 
444 namespace MTBUFFormat {
445 
446 enum DataFormat : int64_t {
463 
466 
469 
471  DFMT_MASK = 0xF
472 };
473 
474 enum NumFormat : int64_t {
481  NFMT_RESERVED_6, // VI and GFX9
482  NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
484 
487 
490 
493 };
494 
495 enum MergedFormat : int64_t {
499 
500 
502 
504 };
505 
506 enum UnifiedFormat : int64_t {
508 
515 
523 
530 
534 
542 
550 
558 
565 
572 
579 
583 
591 
598 
601 
602  UFMT_MAX = 127,
603 
606 };
607 
608 } // namespace MTBUFFormat
609 
610 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
611 
612 enum Id : unsigned { // id of symbolic names
618 };
619 
620 enum EncBits : unsigned {
621 
622  // swizzle mode encodings
623 
624  QUAD_PERM_ENC = 0x8000,
626 
629 
630  // QUAD_PERM encodings
631 
632  LANE_MASK = 0x3,
635  LANE_NUM = 4,
636 
637  // BITMASK_PERM encodings
638 
639  BITMASK_MASK = 0x1F,
642 
646 };
647 
648 } // namespace Swizzle
649 
650 namespace SDWA {
651 
652 enum SdwaSel : unsigned {
653  BYTE_0 = 0,
654  BYTE_1 = 1,
655  BYTE_2 = 2,
656  BYTE_3 = 3,
657  WORD_0 = 4,
658  WORD_1 = 5,
659  DWORD = 6,
660 };
661 
662 enum DstUnused : unsigned {
666 };
667 
668 enum SDWA9EncValues : unsigned {
669  SRC_SGPR_MASK = 0x100,
673 
681 };
682 
683 } // namespace SDWA
684 
685 namespace DPP {
686 
687 // clang-format off
688 enum DppCtrl : unsigned {
690  QUAD_PERM_ID = 0xE4, // identity permutation
692  DPP_UNUSED1 = 0x100,
693  ROW_SHL0 = 0x100,
694  ROW_SHL_FIRST = 0x101,
695  ROW_SHL_LAST = 0x10F,
696  DPP_UNUSED2 = 0x110,
697  ROW_SHR0 = 0x110,
698  ROW_SHR_FIRST = 0x111,
699  ROW_SHR_LAST = 0x11F,
700  DPP_UNUSED3 = 0x120,
701  ROW_ROR0 = 0x120,
702  ROW_ROR_FIRST = 0x121,
703  ROW_ROR_LAST = 0x12F,
704  WAVE_SHL1 = 0x130,
707  WAVE_ROL1 = 0x134,
710  WAVE_SHR1 = 0x138,
713  WAVE_ROR1 = 0x13C,
716  ROW_MIRROR = 0x140,
718  BCAST15 = 0x142,
719  BCAST31 = 0x143,
724  ROW_SHARE0 = 0x150,
726  ROW_SHARE_LAST = 0x15F,
727  ROW_XMASK0 = 0x160,
729  ROW_XMASK_LAST = 0x16F,
731 };
732 // clang-format on
733 
734 enum DppFiMode {
735  DPP_FI_0 = 0,
736  DPP_FI_1 = 1,
737  DPP8_FI_0 = 0xE9,
738  DPP8_FI_1 = 0xEA,
739 };
740 
741 } // namespace DPP
742 
743 namespace Exp {
744 
745 enum Target : unsigned {
746  ET_MRT0 = 0,
747  ET_MRT7 = 7,
748  ET_MRTZ = 8,
749  ET_NULL = 9,
750  ET_POS0 = 12,
751  ET_POS3 = 15,
752  ET_POS4 = 16, // GFX10+
753  ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
754  ET_PRIM = 20, // GFX10+
755  ET_PARAM0 = 32,
757 
764 
765  ET_INVALID = 255,
766 };
767 
768 } // namespace Exp
769 
770 namespace VOP3PEncoding {
771 
772 enum OpSel : uint64_t {
773  OP_SEL_HI_0 = UINT64_C(1) << 59,
774  OP_SEL_HI_1 = UINT64_C(1) << 60,
775  OP_SEL_HI_2 = UINT64_C(1) << 14,
776 };
777 
778 } // namespace VOP3PEncoding
779 
780 } // namespace AMDGPU
781 
782 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
783 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
784 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
785 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
786 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
787 #define C_00B028_MEM_ORDERED 0xFDFFFFFF
788 
789 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
790 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
791 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
792 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
793 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
794 #define C_00B128_MEM_ORDERED 0xF7FFFFFF
795 
796 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
797 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
798 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
799 #define C_00B228_WGP_MODE 0xF7FFFFFF
800 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
801 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
802 #define C_00B228_MEM_ORDERED 0xFDFFFFFF
803 
804 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
805 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
806 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
807 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
808 #define C_00B428_WGP_MODE 0xFBFFFFFF
809 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
810 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
811 #define C_00B428_MEM_ORDERED 0xFEFFFFFF
812 
813 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
814 
815 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
816 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
817 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
818 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
819 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
820 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
821 #define C_00B84C_USER_SGPR 0xFFFFFFC1
822 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
823 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
824 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
825 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
826 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
827 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
828 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
829 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
830 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
831 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
832 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
833 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
834 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
835 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
836 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
837 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
838 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
839 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
840 /* CIK */
841 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
842 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
843 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
844 /* */
845 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
846 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
847 #define C_00B84C_LDS_SIZE 0xFF007FFF
848 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
849 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
850 #define C_00B84C_EXCP_EN
851 
852 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
853 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
854 
855 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
856 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
857 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
858 #define C_00B848_VGPRS 0xFFFFFFC0
859 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
860 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
861 #define C_00B848_SGPRS 0xFFFFFC3F
862 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
863 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
864 #define C_00B848_PRIORITY 0xFFFFF3FF
865 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
866 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
867 #define C_00B848_FLOAT_MODE 0xFFF00FFF
868 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
869 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
870 #define C_00B848_PRIV 0xFFEFFFFF
871 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
872 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
873 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
874 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
875 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
876 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
877 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
878 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
879 #define C_00B848_IEEE_MODE 0xFF7FFFFF
880 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
881 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
882 #define C_00B848_WGP_MODE 0xDFFFFFFF
883 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
884 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
885 #define C_00B848_MEM_ORDERED 0xBFFFFFFF
886 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
887 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
888 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF
889 
890 
891 // Helpers for setting FLOAT_MODE
892 #define FP_ROUND_ROUND_TO_NEAREST 0
893 #define FP_ROUND_ROUND_TO_INF 1
894 #define FP_ROUND_ROUND_TO_NEGINF 2
895 #define FP_ROUND_ROUND_TO_ZERO 3
896 
897 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
898 // precision.
899 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
900 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
901 
902 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
903 #define FP_DENORM_FLUSH_OUT 1
904 #define FP_DENORM_FLUSH_IN 2
905 #define FP_DENORM_FLUSH_NONE 3
906 
907 
908 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
909 // precision.
910 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
911 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
912 
913 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
914 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
915 
916 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
917 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
918 
919 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
920 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
921 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
922 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
923 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
924 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
925 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
926 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
927 
928 #define R_SPILLED_SGPRS 0x4
929 #define R_SPILLED_VGPRS 0x8
930 } // End namespace llvm
931 
932 #endif
llvm::AMDGPU::MTBUFFormat::DataFormat
DataFormat
Definition: SIDefines.h:446
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:164
llvm::AMDGPU::MTBUFFormat::DFMT_DEFAULT
@ DFMT_DEFAULT
Definition: SIDefines.h:468
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_SSCALED
@ UFMT_10_10_10_2_SSCALED
Definition: SIDefines.h:562
llvm::AMDGPU::Hwreg::EXCP_EN_INPUT_DENORMAL_MASK
@ EXCP_EN_INPUT_DENORMAL_MASK
Definition: SIDefines.h:430
llvm::AMDGPU::DPP::ROW_SHL_LAST
@ ROW_SHL_LAST
Definition: SIDefines.h:695
llvm::AMDGPU::DPP::ROW_SHR_FIRST
@ ROW_SHR_FIRST
Definition: SIDefines.h:698
llvm::SIInstrFlags::VGPRSpill
@ VGPRSpill
Definition: SIDefines.h:63
llvm::AMDGPU::DPP::ROW_ROR_FIRST
@ ROW_ROR_FIRST
Definition: SIDefines.h:702
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_32_SINT
@ UFMT_32_32_32_32_SINT
Definition: SIDefines.h:596
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_SNORM
@ UFMT_16_16_16_16_SNORM
Definition: SIDefines.h:585
llvm::AMDGPU::Hwreg::IEEE_MODE_MASK
@ IEEE_MODE_MASK
Definition: SIDefines.h:424
llvm::AMDGPU::DPP::DPP_FI_0
@ DPP_FI_0
Definition: SIDefines.h:735
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MIN
@ TTMP_GFX9PLUS_MIN
Definition: SIDefines.h:274
llvm::AMDGPU::DPP::QUAD_PERM_LAST
@ QUAD_PERM_LAST
Definition: SIDefines.h:691
llvm::AMDGPU::MTBUFFormat::UFMT_MAX
@ UFMT_MAX
Definition: SIDefines.h:602
llvm::AMDGPU::DPP::DPP_UNUSED7_LAST
@ DPP_UNUSED7_LAST
Definition: SIDefines.h:715
llvm::AMDGPU::MTBUFFormat::UFMT_16_SNORM
@ UFMT_16_SNORM
Definition: SIDefines.h:517
llvm::SIInstrFlags::FPAtomic
@ FPAtomic
Definition: SIDefines.h:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_POSITIVE_MAX
@ INLINE_INTEGER_C_POSITIVE_MAX
Definition: SIDefines.h:277
llvm::AMDGPU::DPP::ROW_SHR0
@ ROW_SHR0
Definition: SIDefines.h:697
llvm::AMDGPU::MTBUFFormat::NumFormat
NumFormat
Definition: SIDefines.h:474
llvm::SIInstrFlags::TRANS
@ TRANS
Definition: SIDefines.h:51
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_SINT
@ UFMT_32_32_SINT
Definition: SIDefines.h:581
llvm::AMDGPU::DPP::DPP8_FI_0
@ DPP8_FI_0
Definition: SIDefines.h:737
llvm::AMDGPU::MTBUFFormat::DFMT_2_10_10_10
@ DFMT_2_10_10_10
Definition: SIDefines.h:456
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_0
@ OP_SEL_HI_0
Definition: SIDefines.h:773
llvm::SISrcMods::NEG_HI
@ NEG_HI
Definition: SIDefines.h:213
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX
@ INLINE_INTEGER_C_MAX
Definition: SIDefines.h:278
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:159
llvm::AMDGPU::DPP::BCAST31
@ BCAST31
Definition: SIDefines.h:719
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_USCALED
@ UFMT_10_10_10_2_USCALED
Definition: SIDefines.h:561
llvm::SIInstrFlags::VOPC
@ VOPC
Definition: SIDefines.h:42
llvm::AMDGPU::EncValues::TTMP_VI_MAX
@ TTMP_VI_MAX
Definition: SIDefines.h:273
llvm::AMDGPU::SDWA::BYTE_1
@ BYTE_1
Definition: SIDefines.h:654
llvm::AMDGPU::Hwreg::ID_SHIFT_
@ ID_SHIFT_
Definition: SIDefines.h:388
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:55
MCInstrDesc.h
llvm::AMDGPU::MTBUFFormat::DFMT_32
@ DFMT_32
Definition: SIDefines.h:451
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_UINT
@ UFMT_8_8_UINT
Definition: SIDefines.h:528
llvm::AMDGPU::MTBUFFormat::DFMT_8_8
@ DFMT_8_8
Definition: SIDefines.h:450
llvm::AMDGPU::Hwreg::WidthMinusOne
WidthMinusOne
Definition: SIDefines.h:405
llvm::AMDGPU::MTBUFFormat::NFMT_RESERVED_6
@ NFMT_RESERVED_6
Definition: SIDefines.h:481
llvm::SIInstrFlags::VALU
@ VALU
Definition: SIDefines.h:30
llvm::AMDGPU::Hwreg::ID_LDS_ALLOC
@ ID_LDS_ALLOC
Definition: SIDefines.h:370
llvm::AMDGPU::MTBUFFormat::DFMT_MASK
@ DFMT_MASK
Definition: SIDefines.h:471
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_SSCALED
@ UFMT_16_16_SSCALED
Definition: SIDefines.h:538
llvm::AMDGPU::Swizzle::BITMASK_OR_SHIFT
@ BITMASK_OR_SHIFT
Definition: SIDefines.h:644
llvm::SIInstrFlags::SOPK
@ SOPK
Definition: SIDefines.h:36
llvm::AMDGPU::MTBUFFormat::DFMT_10_10_10_2
@ DFMT_10_10_10_2
Definition: SIDefines.h:455
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_USCALED
@ UFMT_8_8_8_8_USCALED
Definition: SIDefines.h:575
llvm::AMDGPU::OPERAND_KIMM16
@ OPERAND_KIMM16
Definition: SIDefines.h:172
llvm::AMDGPU::DPP::DPP_UNUSED3
@ DPP_UNUSED3
Definition: SIDefines.h:700
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:153
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_UNORM
@ UFMT_16_16_16_16_UNORM
Definition: SIDefines.h:584
llvm::AMDGPU::EncValues::LITERAL_CONST
@ LITERAL_CONST
Definition: SIDefines.h:281
llvm::AMDGPU::SendMsg::ID_STALL_WAVE_GEN
@ ID_STALL_WAVE_GEN
Definition: SIDefines.h:310
llvm::AMDGPU::EncValues::TTMP_VI_MIN
@ TTMP_VI_MIN
Definition: SIDefines.h:272
llvm::AMDGPUAsmVariants::DEFAULT
@ DEFAULT
Definition: SIDefines.h:257
llvm::AMDGPU::Swizzle::QUAD_PERM_ENC
@ QUAD_PERM_ENC
Definition: SIDefines.h:624
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_UINT
@ UFMT_8_8_8_8_UINT
Definition: SIDefines.h:577
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_UINT
@ UFMT_32_32_32_UINT
Definition: SIDefines.h:592
llvm::AMDGPU::DPP::DPP8_FI_1
@ DPP8_FI_1
Definition: SIDefines.h:738
llvm::AMDGPU::MTBUFFormat::NFMT_UNDEF
@ NFMT_UNDEF
Definition: SIDefines.h:488
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_USCALED
@ UFMT_16_16_USCALED
Definition: SIDefines.h:537
llvm::SIInstrFlags::VOP3
@ VOP3
Definition: SIDefines.h:45
llvm::AMDGPU::VGPRIndexMode::ID_SRC0
@ ID_SRC0
Definition: SIDefines.h:233
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_FLOAT
@ UFMT_16_16_16_16_FLOAT
Definition: SIDefines.h:590
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_USCALED
@ UFMT_16_16_16_16_USCALED
Definition: SIDefines.h:586
llvm::AMDGPU::Exp::ET_NULL
@ ET_NULL
Definition: SIDefines.h:749
llvm::AMDGPU::SendMsg::STREAM_ID_MASK_
@ STREAM_ID_MASK_
Definition: SIDefines.h:355
llvm::AMDGPU::MTBUFFormat::DFMT_32_32_32
@ DFMT_32_32_32
Definition: SIDefines.h:460
llvm::AMDGPU::MTBUFFormat::DFMT_8
@ DFMT_8
Definition: SIDefines.h:448
llvm::AMDGPU::SendMsg::OP_GS_LAST_
@ OP_GS_LAST_
Definition: SIDefines.h:337
llvm::AMDGPU::SendMsg::ID_WIDTH_
@ ID_WIDTH_
Definition: SIDefines.h:321
llvm::AMDGPU::VOP3PEncoding::OpSel
OpSel
Definition: SIDefines.h:772
llvm::AMDGPU::Swizzle::LANE_MASK
@ LANE_MASK
Definition: SIDefines.h:632
llvm::AMDGPU::SendMsg::STREAM_ID_WIDTH_
@ STREAM_ID_WIDTH_
Definition: SIDefines.h:354
llvm::AMDGPU::Hwreg::EXCP_EN_INVALID_MASK
@ EXCP_EN_INVALID_MASK
Definition: SIDefines.h:429
llvm::AMDGPU::SDWA::BYTE_0
@ BYTE_0
Definition: SIDefines.h:653
llvm::SIInstrFlags::DisableWQM
@ DisableWQM
Definition: SIDefines.h:72
llvm::AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE
@ WIDTH_M1_SRC_PRIVATE_BASE
Definition: SIDefines.h:412
llvm::AMDGPU::DPP::DPP_UNUSED4_LAST
@ DPP_UNUSED4_LAST
Definition: SIDefines.h:706
llvm::AMDGPU::Hwreg::OFFSET_WIDTH_
@ OFFSET_WIDTH_
Definition: SIDefines.h:396
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX1030_
@ ID_SYMBOLIC_FIRST_GFX1030_
Definition: SIDefines.h:386
llvm::AMDGPU::Hwreg::ID_MASK_
@ ID_MASK_
Definition: SIDefines.h:390
llvm::AMDGPU::Exp::ET_POS0
@ ET_POS0
Definition: SIDefines.h:750
llvm::AMDGPU::OperandType
OperandType
Definition: SIDefines.h:143
llvm::AMDGPU::MTBUFFormat::DFMT_11_11_10
@ DFMT_11_11_10
Definition: SIDefines.h:454
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MAX
@ DFMT_NFMT_MAX
Definition: SIDefines.h:503
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_UNORM
@ UFMT_8_8_UNORM
Definition: SIDefines.h:524
llvm::AMDGPU::OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:155
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_SINT
@ UFMT_10_10_10_2_SINT
Definition: SIDefines.h:564
llvm::AMDGPU::SendMsg::OP_GS_CUT
@ OP_GS_CUT
Definition: SIDefines.h:334
llvm::AMDGPU::SendMsg::ID_EARLY_PRIM_DEALLOC
@ ID_EARLY_PRIM_DEALLOC
Definition: SIDefines.h:313
llvm::SISrcMods::DST_OP_SEL
@ DST_OP_SEL
Definition: SIDefines.h:216
llvm::AMDGPU::DPP::ROW_XMASK0
@ ROW_XMASK0
Definition: SIDefines.h:727
llvm::AMDGPU::MTBUFFormat::NFMT_DEFAULT
@ NFMT_DEFAULT
Definition: SIDefines.h:489
llvm::AMDGPU::SDWA::UNUSED_PRESERVE
@ UNUSED_PRESERVE
Definition: SIDefines.h:665
llvm::AMDGPU::MTBUFFormat::NFMT_SNORM
@ NFMT_SNORM
Definition: SIDefines.h:476
llvm::AMDGPU::Swizzle::BITMASK_XOR_SHIFT
@ BITMASK_XOR_SHIFT
Definition: SIDefines.h:645
llvm::AMDGPU::MTBUFFormat::UFMT_8_SINT
@ UFMT_8_SINT
Definition: SIDefines.h:514
llvm::AMDGPU::DPP::ROW_MIRROR
@ ROW_MIRROR
Definition: SIDefines.h:716
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:745
llvm::AMDGPU::Swizzle::BITMASK_WIDTH
@ BITMASK_WIDTH
Definition: SIDefines.h:641
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_SI
@ SRC_SGPR_MAX_SI
Definition: SIDefines.h:677
llvm::AMDGPU::Hwreg::ID_HW_ID1
@ ID_HW_ID1
Definition: SIDefines.h:382
llvm::AMDGPU::DPP::DPP_UNUSED1
@ DPP_UNUSED1
Definition: SIDefines.h:692
llvm::AMDGPU::MTBUFFormat::UFMT_16_UNORM
@ UFMT_16_UNORM
Definition: SIDefines.h:516
llvm::AMDGPU::MTBUFFormat::UFMT_8_SNORM
@ UFMT_8_SNORM
Definition: SIDefines.h:510
llvm::SIOutMods::MUL4
@ MUL4
Definition: SIDefines.h:224
llvm::AMDGPU::SendMsg::OP_GS_EMIT
@ OP_GS_EMIT
Definition: SIDefines.h:335
llvm::SIInstrFlags::SOPP
@ SOPP
Definition: SIDefines.h:37
llvm::AMDGPU::DPP::DPP_UNUSED7_FIRST
@ DPP_UNUSED7_FIRST
Definition: SIDefines.h:714
llvm::AMDGPU::Swizzle::LANE_MAX
@ LANE_MAX
Definition: SIDefines.h:633
llvm::AMDGPU::Hwreg::WIDTH_M1_DEFAULT_
@ WIDTH_M1_DEFAULT_
Definition: SIDefines.h:406
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_SNORM
@ UFMT_2_10_10_10_SNORM
Definition: SIDefines.h:567
llvm::AMDGPU::MTBUFFormat::UFMT_32_UINT
@ UFMT_32_UINT
Definition: SIDefines.h:531
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_FLOAT
@ UFMT_10_11_11_FLOAT
Definition: SIDefines.h:549
llvm::AMDGPU::OPERAND_REG_IMM_LAST
@ OPERAND_REG_IMM_LAST
Definition: SIDefines.h:186
llvm::AMDGPU::SDWA::VOPC_DST_SGPR_MASK
@ VOPC_DST_SGPR_MASK
Definition: SIDefines.h:672
llvm::AMDGPU::VGPRIndexMode::SRC0_ENABLE
@ SRC0_ENABLE
Definition: SIDefines.h:244
llvm::SIInstrFlags::EXP_CNT
@ EXP_CNT
Definition: SIDefines.h:68
llvm::AMDGPU::SendMsg::Id
Id
Definition: SIDefines.h:304
llvm::AMDGPU::SendMsg::ID_GAPS_LAST_
@ ID_GAPS_LAST_
Definition: SIDefines.h:318
llvm::SIInstrFlags::FIXED_SIZE
@ FIXED_SIZE
Definition: SIDefines.h:76
llvm::AMDGPU::DPP::ROW_SHL_FIRST
@ ROW_SHL_FIRST
Definition: SIDefines.h:694
llvm::AMDGPU::Hwreg::EXCP_EN_INEXACT_MASK
@ EXCP_EN_INEXACT_MASK
Definition: SIDefines.h:434
llvm::SIRCFlags
SIRCFlags
Definition: SIDefines.h:18
Swizzle
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
Definition: R600InstrInfo.cpp:349
llvm::AMDGPU::Exp::ET_PARAM0
@ ET_PARAM0
Definition: SIDefines.h:755
llvm::AMDGPU::SDWA::SRC_VGPR_MAX
@ SRC_VGPR_MAX
Definition: SIDefines.h:675
llvm::AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE
@ OFFSET_SRC_PRIVATE_BASE
Definition: SIDefines.h:402
llvm::AMDGPU::SDWA::DstUnused
DstUnused
Definition: SIDefines.h:662
llvm::AMDGPU::Hwreg::ID_IB_STS
@ ID_IB_STS
Definition: SIDefines.h:371
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_UNORM
@ UFMT_11_11_10_UNORM
Definition: SIDefines.h:551
llvm::AMDGPU::SendMsg::ID_SAVEWAVE
@ ID_SAVEWAVE
Definition: SIDefines.h:309
llvm::AMDGPU::MTBUFFormat::MergedFormat
MergedFormat
Definition: SIDefines.h:495
llvm::AMDGPU::MTBUFFormat::UFMT_16_FLOAT
@ UFMT_16_FLOAT
Definition: SIDefines.h:522
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_USCALED
@ UFMT_11_11_10_USCALED
Definition: SIDefines.h:553
llvm::SIInstrFlags::SGPRSpill
@ SGPRSpill
Definition: SIDefines.h:64
llvm::AMDGPU::SendMsg::ID_MASK_
@ ID_MASK_
Definition: SIDefines.h:322
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:56
llvm::AMDGPU::SDWA::UNUSED_SEXT
@ UNUSED_SEXT
Definition: SIDefines.h:664
llvm::AMDGPU::SendMsg::OP_GS_EMIT_CUT
@ OP_GS_EMIT_CUT
Definition: SIDefines.h:336
llvm::AMDGPU::Hwreg::ID_TBA_HI
@ ID_TBA_HI
Definition: SIDefines.h:376
llvm::SIOutMods::MUL2
@ MUL2
Definition: SIDefines.h:223
llvm::AMDGPU::Hwreg::ID_UNKNOWN_
@ ID_UNKNOWN_
Definition: SIDefines.h:363
llvm::SIInstrFlags::D16Buf
@ D16Buf
Definition: SIDefines.h:99
llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC_MASK
@ BITMASK_PERM_ENC_MASK
Definition: SIDefines.h:628
llvm::SIInstrFlags::FPClamp
@ FPClamp
Definition: SIDefines.h:83
llvm::AMDGPU::SDWA::SDWA9EncValues
SDWA9EncValues
Definition: SIDefines.h:668
llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST
@ OPERAND_REG_INLINE_AC_LAST
Definition: SIDefines.h:192
llvm::AMDGPU::SendMsg::OP_GS_FIRST_
@ OP_GS_FIRST_
Definition: SIDefines.h:338
llvm::AMDGPU::SendMsg::ID_GET_DOORBELL
@ ID_GET_DOORBELL
Definition: SIDefines.h:315
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:148
llvm::AMDGPU::CPol::CPol
CPol
Definition: SIDefines.h:292
llvm::AMDGPU::MTBUFFormat::DFMT_32_32_32_32
@ DFMT_32_32_32_32
Definition: SIDefines.h:461
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MAX
@ TTMP_GFX9PLUS_MAX
Definition: SIDefines.h:275
llvm::AMDGPU::MTBUFFormat::UFMT_32_SINT
@ UFMT_32_SINT
Definition: SIDefines.h:532
llvm::AMDGPU::SDWA::UNUSED_PAD
@ UNUSED_PAD
Definition: SIDefines.h:663
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_USCALED
@ UFMT_2_10_10_10_USCALED
Definition: SIDefines.h:568
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_32_UINT
@ UFMT_32_32_32_32_UINT
Definition: SIDefines.h:595
llvm::SIInstrFlags::WQM
@ WQM
Definition: SIDefines.h:71
llvm::AMDGPU::VGPRIndexMode::ID_SRC2
@ ID_SRC2
Definition: SIDefines.h:235
llvm::AMDGPU::Exp::ET_INVALID
@ ET_INVALID
Definition: SIDefines.h:765
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT32
@ OPERAND_REG_INLINE_AC_V2INT32
Definition: SIDefines.h:182
llvm::AMDGPU::Hwreg::ID_WIDTH_
@ ID_WIDTH_
Definition: SIDefines.h:389
llvm::AMDGPU::Exp::ET_MRTZ_MAX_IDX
@ ET_MRTZ_MAX_IDX
Definition: SIDefines.h:759
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:160
llvm::AMDGPU::VGPRIndexMode::ENABLE_MASK
@ ENABLE_MASK
Definition: SIDefines.h:248
llvm::AMDGPU::Hwreg::ID_MODE
@ ID_MODE
Definition: SIDefines.h:365
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_SINT
@ UFMT_10_11_11_SINT
Definition: SIDefines.h:548
llvm::AMDGPU::DPP::DPP_UNUSED8_FIRST
@ DPP_UNUSED8_FIRST
Definition: SIDefines.h:720
llvm::AMDGPU::SendMsg::OP_SYS_LAST_
@ OP_SYS_LAST_
Definition: SIDefines.h:344
llvm::AMDGPU::SendMsg::ID_GS_ALLOC_REQ
@ ID_GS_ALLOC_REQ
Definition: SIDefines.h:314
llvm::AMDGPU::MTBUFFormat::UFMT_DEFAULT
@ UFMT_DEFAULT
Definition: SIDefines.h:605
llvm::SIInstrFlags::N_INFINITY
@ N_INFINITY
Definition: SIDefines.h:131
llvm::AMDGPU::Hwreg::ID_POPS_PACKER
@ ID_POPS_PACKER
Definition: SIDefines.h:384
llvm::AMDGPU::CPol::DLC
@ DLC
Definition: SIDefines.h:295
llvm::AMDGPU::Swizzle::BITMASK_MAX
@ BITMASK_MAX
Definition: SIDefines.h:640
llvm::AMDGPU::MTBUFFormat::UFMT_16_SSCALED
@ UFMT_16_SSCALED
Definition: SIDefines.h:519
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:177
llvm::AMDGPU::DPP::ROW_SHL0
@ ROW_SHL0
Definition: SIDefines.h:693
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_FLOAT
@ UFMT_11_11_10_FLOAT
Definition: SIDefines.h:557
llvm::AMDGPU::EncValues::SGPR_MAX_SI
@ SGPR_MAX_SI
Definition: SIDefines.h:270
llvm::AMDGPU::DPP::ROW_XMASK_FIRST
@ ROW_XMASK_FIRST
Definition: SIDefines.h:728
llvm::SIOutMods::DIV2
@ DIV2
Definition: SIDefines.h:225
llvm::SIInstrFlags::FPDPRounding
@ FPDPRounding
Definition: SIDefines.h:105
llvm::AMDGPU::SDWA::SRC_TTMP_MAX
@ SRC_TTMP_MAX
Definition: SIDefines.h:680
llvm::AMDGPU::DPP::DPP_UNUSED4_FIRST
@ DPP_UNUSED4_FIRST
Definition: SIDefines.h:705
llvm::AMDGPU::SendMsg::STREAM_ID_LAST_
@ STREAM_ID_LAST_
Definition: SIDefines.h:351
llvm::AMDGPU::SendMsg::ID_SYSMSG
@ ID_SYSMSG
Definition: SIDefines.h:317
llvm::AMDGPU::Hwreg::Id
Id
Definition: SIDefines.h:362
llvm::AMDGPU::SDWA::BYTE_2
@ BYTE_2
Definition: SIDefines.h:655
llvm::AMDGPU::SendMsg::ID_SHIFT_
@ ID_SHIFT_
Definition: SIDefines.h:320
llvm::AMDGPU::Hwreg::GPR_IDX_EN_MASK
@ GPR_IDX_EN_MASK
Definition: SIDefines.h:437
llvm::AMDGPU::EncValues::SGPR_MIN
@ SGPR_MIN
Definition: SIDefines.h:269
llvm::SISrcMods::OP_SEL_0
@ OP_SEL_0
Definition: SIDefines.h:214
llvm::AMDGPU::MTBUFFormat::DFMT_16_16_16_16
@ DFMT_16_16_16_16
Definition: SIDefines.h:459
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_SNORM
@ UFMT_8_8_8_8_SNORM
Definition: SIDefines.h:574
llvm::SIInstrFlags::SDWA
@ SDWA
Definition: SIDefines.h:49
llvm::AMDGPU::Exp::ET_PRIM
@ ET_PRIM
Definition: SIDefines.h:754
llvm::AMDGPU::MTBUFFormat::DFMT_16
@ DFMT_16
Definition: SIDefines.h:449
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_SSCALED
@ UFMT_10_11_11_SSCALED
Definition: SIDefines.h:546
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_SINT
@ UFMT_11_11_10_SINT
Definition: SIDefines.h:556
llvm::AMDGPU::SendMsg::OP_GS_NOP
@ OP_GS_NOP
Definition: SIDefines.h:333
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:149
llvm::AMDGPU::MTBUFFormat::UFMT_8_USCALED
@ UFMT_8_USCALED
Definition: SIDefines.h:511
llvm::AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE
@ WIDTH_M1_SRC_SHARED_BASE
Definition: SIDefines.h:411
llvm::SIInstrFlags::IsDOT
@ IsDOT
Definition: SIDefines.h:114
llvm::AMDGPU::SendMsg::OP_SHIFT_
@ OP_SHIFT_
Definition: SIDefines.h:327
llvm::AMDGPU::SendMsg::STREAM_ID_DEFAULT_
@ STREAM_ID_DEFAULT_
Definition: SIDefines.h:350
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX9_
@ ID_SYMBOLIC_FIRST_GFX9_
Definition: SIDefines.h:373
llvm::AMDGPU::VGPRIndexMode::SRC1_ENABLE
@ SRC1_ENABLE
Definition: SIDefines.h:245
llvm::AMDGPU::SendMsg::OP_SYS_ECC_ERR_INTERRUPT
@ OP_SYS_ECC_ERR_INTERRUPT
Definition: SIDefines.h:340
llvm::SIInstrFlags::VOP3_OPSEL
@ VOP3_OPSEL
Definition: SIDefines.h:78
llvm::AMDGPU::MTBUFFormat::DFMT_8_8_8_8
@ DFMT_8_8_8_8
Definition: SIDefines.h:457
llvm::AMDGPU::MTBUFFormat::DFMT_UNDEF
@ DFMT_UNDEF
Definition: SIDefines.h:467
llvm::AMDGPU::Hwreg::ID_TBA_LO
@ ID_TBA_LO
Definition: SIDefines.h:374
llvm::AMDGPU::MTBUFFormat::DFMT_INVALID
@ DFMT_INVALID
Definition: SIDefines.h:447
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:156
llvm::AMDGPU::Hwreg::VSKIP_MASK
@ VSKIP_MASK
Definition: SIDefines.h:438
llvm::AMDGPU::Hwreg::ID_TMA_LO
@ ID_TMA_LO
Definition: SIDefines.h:377
llvm::AMDGPU::Hwreg::EXCP_EN_INT_DIV0_MASK
@ EXCP_EN_INT_DIV0_MASK
Definition: SIDefines.h:435
llvm::SIInstrFlags::SOPC
@ SOPC
Definition: SIDefines.h:35
llvm::AMDGPU::MTBUFFormat::UFMT_FIRST
@ UFMT_FIRST
Definition: SIDefines.h:599
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:167
llvm::AMDGPU::MTBUFFormat::UFMT_UNDEF
@ UFMT_UNDEF
Definition: SIDefines.h:604
llvm::AMDGPU::SendMsg::StreamId
StreamId
Definition: SIDefines.h:348
llvm::AMDGPU::SendMsg::ID_GAPS_FIRST_
@ ID_GAPS_FIRST_
Definition: SIDefines.h:319
llvm::AMDGPU::Exp::ET_POS_LAST
@ ET_POS_LAST
Definition: SIDefines.h:753
llvm::AMDGPU::Swizzle::ID_REVERSE
@ ID_REVERSE
Definition: SIDefines.h:616
llvm::AMDGPU::SendMsg::ID_ORDERED_PS_DONE
@ ID_ORDERED_PS_DONE
Definition: SIDefines.h:312
llvm::AMDGPU::MTBUFFormat::NFMT_MIN
@ NFMT_MIN
Definition: SIDefines.h:485
llvm::AMDGPU::MTBUFFormat::UFMT_8_UNORM
@ UFMT_8_UNORM
Definition: SIDefines.h:509
llvm::AMDGPU::Hwreg::OFFSET_MASK_
@ OFFSET_MASK_
Definition: SIDefines.h:397
llvm::AMDGPU::OPERAND_SDWA_VOPC_DST
@ OPERAND_SDWA_VOPC_DST
Definition: SIDefines.h:201
llvm::SIInstrFlags::Q_NAN
@ Q_NAN
Definition: SIDefines.h:130
llvm::AMDGPU::DPP::DPP_UNUSED6_FIRST
@ DPP_UNUSED6_FIRST
Definition: SIDefines.h:711
llvm::AMDGPU::Hwreg::WIDTH_M1_SHIFT_
@ WIDTH_M1_SHIFT_
Definition: SIDefines.h:407
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_USCALED
@ UFMT_10_11_11_USCALED
Definition: SIDefines.h:545
llvm::SIInstrFlags::ClampHi
@ ClampHi
Definition: SIDefines.h:93
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_2
@ OP_SEL_HI_2
Definition: SIDefines.h:775
llvm::AMDGPU::Swizzle::QUAD_PERM_ENC_MASK
@ QUAD_PERM_ENC_MASK
Definition: SIDefines.h:625
llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:151
llvm::SIInstrFlags::N_NORMAL
@ N_NORMAL
Definition: SIDefines.h:132
llvm::AMDGPU::SDWA::SRC_VGPR_MASK
@ SRC_VGPR_MASK
Definition: SIDefines.h:670
llvm::AMDGPU::Hwreg::WIDTH_M1_WIDTH_
@ WIDTH_M1_WIDTH_
Definition: SIDefines.h:408
llvm::AMDGPU::Exp::ET_PARAM_MAX_IDX
@ ET_PARAM_MAX_IDX
Definition: SIDefines.h:763
llvm::AMDGPU::SendMsg::OP_SYS_REG_RD
@ OP_SYS_REG_RD
Definition: SIDefines.h:341
llvm::AMDGPU::MTBUFFormat::NFMT_MAX
@ NFMT_MAX
Definition: SIDefines.h:486
llvm::AMDGPU::Swizzle::LANE_NUM
@ LANE_NUM
Definition: SIDefines.h:635
llvm::AMDGPU::VGPRIndexMode::ID_MIN
@ ID_MIN
Definition: SIDefines.h:238
llvm::AMDGPU::Hwreg::ID_FLAT_SCR_HI
@ ID_FLAT_SCR_HI
Definition: SIDefines.h:380
llvm::AMDGPU::SDWA::SRC_VGPR_MIN
@ SRC_VGPR_MIN
Definition: SIDefines.h:674
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:393
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:161
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_UINT
@ UFMT_16_16_UINT
Definition: SIDefines.h:539
llvm::SIInstrFlags::S_NAN
@ S_NAN
Definition: SIDefines.h:129
llvm::AMDGPU::CPol::GLC
@ GLC
Definition: SIDefines.h:293
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_FLOAT
@ UFMT_16_16_FLOAT
Definition: SIDefines.h:541
uint64_t
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_UNDEF
@ DFMT_NFMT_UNDEF
Definition: SIDefines.h:496
llvm::AMDGPU::VGPRIndexMode::EncBits
EncBits
Definition: SIDefines.h:242
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:54
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_SINT
@ UFMT_16_16_16_16_SINT
Definition: SIDefines.h:589
llvm::AMDGPU::MTBUFFormat::NFMT_MASK
@ NFMT_MASK
Definition: SIDefines.h:492
llvm::AMDGPU::MTBUFFormat::NFMT_SNORM_OGL
@ NFMT_SNORM_OGL
Definition: SIDefines.h:482
llvm::AMDGPU::DPP::DPP_UNUSED6_LAST
@ DPP_UNUSED6_LAST
Definition: SIDefines.h:712
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:163
llvm::AMDGPU::MTBUFFormat::DFMT_SHIFT
@ DFMT_SHIFT
Definition: SIDefines.h:470
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_SINT
@ UFMT_32_32_32_SINT
Definition: SIDefines.h:593
llvm::AMDGPU::DPP::DppCtrl
DppCtrl
Definition: SIDefines.h:688
llvm::SIInstrFlags::VOPAsmPrefer32Bit
@ VOPAsmPrefer32Bit
Definition: SIDefines.h:77
llvm::AMDGPU::DPP::DPP_UNUSED8_LAST
@ DPP_UNUSED8_LAST
Definition: SIDefines.h:721
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_UINT
@ UFMT_2_10_10_10_UINT
Definition: SIDefines.h:570
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_UINT
@ UFMT_10_11_11_UINT
Definition: SIDefines.h:547
llvm::AMDGPU::EncValues::SGPR_MAX_GFX10
@ SGPR_MAX_GFX10
Definition: SIDefines.h:271
llvm::AMDGPU::OPERAND_SRC_FIRST
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:194
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_SINT
@ UFMT_8_8_8_8_SINT
Definition: SIDefines.h:578
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_FLOAT
@ UFMT_32_32_32_FLOAT
Definition: SIDefines.h:594
llvm::AMDGPU::DPP::DPP_UNUSED2
@ DPP_UNUSED2
Definition: SIDefines.h:696
llvm::AMDGPU::MTBUFFormat::UFMT_32_FLOAT
@ UFMT_32_FLOAT
Definition: SIDefines.h:533
llvm::AMDGPU::Swizzle::ID_BROADCAST
@ ID_BROADCAST
Definition: SIDefines.h:617
llvm::AMDGPU::DPP::WAVE_SHL1
@ WAVE_SHL1
Definition: SIDefines.h:704
llvm::AMDGPU::Swizzle::ID_QUAD_PERM
@ ID_QUAD_PERM
Definition: SIDefines.h:613
llvm::AMDGPU::SDWA::DWORD
@ DWORD
Definition: SIDefines.h:659
llvm::AMDGPU::DPP::DPP_LAST
@ DPP_LAST
Definition: SIDefines.h:730
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX
@ INLINE_FLOATING_C_MAX
Definition: SIDefines.h:280
llvm::AMDGPU::MTBUFFormat::DFMT_32_32
@ DFMT_32_32
Definition: SIDefines.h:458
llvm::AMDGPU::Hwreg::FP_DENORM_MASK
@ FP_DENORM_MASK
Definition: SIDefines.h:422
llvm::AMDGPU::Hwreg::ID_HW_ID
@ ID_HW_ID
Definition: SIDefines.h:368
llvm::AMDGPU::SendMsg::OP_UNKNOWN_
@ OP_UNKNOWN_
Definition: SIDefines.h:326
llvm::AMDGPU::EncValues::VGPR_MIN
@ VGPR_MIN
Definition: SIDefines.h:282
llvm::AMDGPU::SendMsg::ID_INTERRUPT
@ ID_INTERRUPT
Definition: SIDefines.h:306
llvm::SIInstrFlags::ClassFlags
ClassFlags
Definition: SIDefines.h:128
llvm::SISrcMods::NEG
@ NEG
Definition: SIDefines.h:210
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:123
llvm::AMDGPU::DPP::BCAST15
@ BCAST15
Definition: SIDefines.h:718
llvm::AMDGPU::MTBUFFormat::DFMT_RESERVED_15
@ DFMT_RESERVED_15
Definition: SIDefines.h:462
llvm::AMDGPU::Hwreg::OFFSET_DEFAULT_
@ OFFSET_DEFAULT_
Definition: SIDefines.h:394
llvm::HasVGPR
@ HasVGPR
Definition: SIDefines.h:20
llvm::SIInstrFlags::FlatGlobal
@ FlatGlobal
Definition: SIDefines.h:102
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:175
llvm::AMDGPU::Hwreg::ID_MEM_BASES
@ ID_MEM_BASES
Definition: SIDefines.h:372
llvm::AMDGPU::Swizzle::BITMASK_MASK
@ BITMASK_MASK
Definition: SIDefines.h:639
llvm::HasSGPR
@ HasSGPR
Definition: SIDefines.h:22
llvm::AMDGPU::Hwreg::EXCP_EN_UNDERFLOW_MASK
@ EXCP_EN_UNDERFLOW_MASK
Definition: SIDefines.h:433
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_1
@ OP_SEL_HI_1
Definition: SIDefines.h:774
llvm::AMDGPU::CPol::ALL
@ ALL
Definition: SIDefines.h:297
llvm::AMDGPUAsmVariants::VOP3
@ VOP3
Definition: SIDefines.h:258
llvm::AMDGPU::SDWA::SdwaSel
SdwaSel
Definition: SIDefines.h:652
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:165
llvm::SIInstrFlags::SOP2
@ SOP2
Definition: SIDefines.h:34
llvm::AMDGPU::Exp::ET_MRT0
@ ET_MRT0
Definition: SIDefines.h:746
llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:152
llvm::AMDGPU::Swizzle::BITMASK_AND_SHIFT
@ BITMASK_AND_SHIFT
Definition: SIDefines.h:643
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:59
llvm::AMDGPUAsmVariants::SDWA
@ SDWA
Definition: SIDefines.h:259
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:178
llvm::AMDGPU::SDWA::SRC_SGPR_MIN
@ SRC_SGPR_MIN
Definition: SIDefines.h:676
llvm::SIInstrFlags::IsAtomicNoRet
@ IsAtomicNoRet
Definition: SIDefines.h:120
llvm::AMDGPU::MTBUFFormat::DFMT_MIN
@ DFMT_MIN
Definition: SIDefines.h:464
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_SSCALED
@ UFMT_8_8_SSCALED
Definition: SIDefines.h:527
llvm::AMDGPU::OPERAND_REG_IMM_INT16
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:147
llvm::SIInstrFlags::EXP
@ EXP
Definition: SIDefines.h:58
llvm::AMDGPU::CPol::SCC
@ SCC
Definition: SIDefines.h:296
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:176
llvm::AMDGPU::VGPRIndexMode::UNDEF
@ UNDEF
Definition: SIDefines.h:249
llvm::AMDGPU::Exp::ET_MRTZ
@ ET_MRTZ
Definition: SIDefines.h:748
llvm::SIInstrFlags::LGKM_CNT
@ LGKM_CNT
Definition: SIDefines.h:69
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_SINT
@ UFMT_2_10_10_10_SINT
Definition: SIDefines.h:571
llvm::AMDGPU::Hwreg::ID_XNACK_MASK
@ ID_XNACK_MASK
Definition: SIDefines.h:381
llvm::AMDGPU::Hwreg::WIDTH_DEFAULT_
@ WIDTH_DEFAULT_
Definition: SIDefines.h:417
llvm::AMDGPU::MTBUFFormat::UFMT_16_USCALED
@ UFMT_16_USCALED
Definition: SIDefines.h:518
llvm::SIInstrFlags::VOP2
@ VOP2
Definition: SIDefines.h:41
llvm::HasAGPR
@ HasAGPR
Definition: SIDefines.h:21
llvm::AMDGPU::DPP::ROW_HALF_MIRROR
@ ROW_HALF_MIRROR
Definition: SIDefines.h:717
llvm::AMDGPU::Hwreg::OFFSET_SHIFT_
@ OFFSET_SHIFT_
Definition: SIDefines.h:395
llvm::SISrcMods::OP_SEL_1
@ OP_SEL_1
Definition: SIDefines.h:215
uint32_t
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_UINT
@ UFMT_10_10_10_2_UINT
Definition: SIDefines.h:563
llvm::SIInstrFlags::VOP1
@ VOP1
Definition: SIDefines.h:40
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_SNORM
@ UFMT_10_11_11_SNORM
Definition: SIDefines.h:544
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_USCALED
@ UFMT_8_8_USCALED
Definition: SIDefines.h:526
llvm::AMDGPU::VGPRIndexMode::ID_MAX
@ ID_MAX
Definition: SIDefines.h:239
llvm::SIInstrFlags::IsPacked
@ IsPacked
Definition: SIDefines.h:96
llvm::AMDGPUAsmVariants::SDWA9
@ SDWA9
Definition: SIDefines.h:260
llvm::SISrcMods::SEXT
@ SEXT
Definition: SIDefines.h:212
llvm::AMDGPU::Hwreg::LOD_CLAMP_MASK
@ LOD_CLAMP_MASK
Definition: SIDefines.h:425
llvm::AMDGPU::SendMsg::OP_SYS_HOST_TRAP_ACK
@ OP_SYS_HOST_TRAP_ACK
Definition: SIDefines.h:342
llvm::AMDGPU::SendMsg::ID_GS
@ ID_GS
Definition: SIDefines.h:307
llvm::AMDGPU::Hwreg::OFFSET_MEM_VIOL
@ OFFSET_MEM_VIOL
Definition: SIDefines.h:399
llvm::SIInstrFlags::DPP
@ DPP
Definition: SIDefines.h:50
llvm::AMDGPU::SendMsg::ID_GS_DONE
@ ID_GS_DONE
Definition: SIDefines.h:308
llvm::AMDGPU::MTBUFFormat::UFMT_INVALID
@ UFMT_INVALID
Definition: SIDefines.h:507
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_GFX10
@ SRC_SGPR_MAX_GFX10
Definition: SIDefines.h:678
llvm::AMDGPU::DPP::ROW_XMASK_LAST
@ ROW_XMASK_LAST
Definition: SIDefines.h:729
llvm::AMDGPU::VGPRIndexMode::DST_ENABLE
@ DST_ENABLE
Definition: SIDefines.h:247
llvm::AMDGPU::SendMsg::STREAM_ID_FIRST_
@ STREAM_ID_FIRST_
Definition: SIDefines.h:352
llvm::AMDGPU::MTBUFFormat::UFMT_LAST
@ UFMT_LAST
Definition: SIDefines.h:600
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_SSCALED
@ UFMT_8_8_8_8_SSCALED
Definition: SIDefines.h:576
llvm::SIInstrFlags::P_SUBNORMAL
@ P_SUBNORMAL
Definition: SIDefines.h:136
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_SINT
@ UFMT_16_16_SINT
Definition: SIDefines.h:540
llvm::AMDGPU::OPERAND_INPUT_MODS
@ OPERAND_INPUT_MODS
Definition: SIDefines.h:198
llvm::AMDGPU::Swizzle::EncBits
EncBits
Definition: SIDefines.h:620
llvm::SIInstrFlags::P_INFINITY
@ P_INFINITY
Definition: SIDefines.h:138
llvm::AMDGPU::SendMsg::OP_SYS_FIRST_
@ OP_SYS_FIRST_
Definition: SIDefines.h:345
llvm::AMDGPU::MTBUFFormat::NFMT_UINT
@ NFMT_UINT
Definition: SIDefines.h:479
llvm::AMDGPU::Hwreg::FP_ROUND_MASK
@ FP_ROUND_MASK
Definition: SIDefines.h:421
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:179
llvm::AMDGPU::SDWA::WORD_1
@ WORD_1
Definition: SIDefines.h:658
llvm::AMDGPU::VGPRIndexMode::OFF
@ OFF
Definition: SIDefines.h:243
llvm::AMDGPU::DPP::WAVE_ROL1
@ WAVE_ROL1
Definition: SIDefines.h:707
llvm::AMDGPU::Hwreg::DEBUG_MASK
@ DEBUG_MASK
Definition: SIDefines.h:426
llvm::AMDGPU::Hwreg::ID_SHADER_CYCLES
@ ID_SHADER_CYCLES
Definition: SIDefines.h:385
llvm::AMDGPU::DPP::ROW_ROR0
@ ROW_ROR0
Definition: SIDefines.h:701
llvm::AMDGPU::SDWA::SRC_SGPR_MASK
@ SRC_SGPR_MASK
Definition: SIDefines.h:669
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_UINT
@ UFMT_16_16_16_16_UINT
Definition: SIDefines.h:588
llvm::AMDGPU::OPERAND_SRC_LAST
@ OPERAND_SRC_LAST
Definition: SIDefines.h:195
llvm::AMDGPU::OPERAND_KIMM32
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:171
llvm::SIInstrFlags::P_ZERO
@ P_ZERO
Definition: SIDefines.h:135
llvm::AMDGPU::Exp::ET_MRT7
@ ET_MRT7
Definition: SIDefines.h:747
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_SNORM
@ UFMT_16_16_SNORM
Definition: SIDefines.h:536
llvm::AMDGPU::MTBUFFormat::DFMT_10_11_11
@ DFMT_10_11_11
Definition: SIDefines.h:453
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:154
SDWA
@ SDWA
Definition: SIInstrInfo.cpp:7667
llvm::SIInstrFlags::VINTRP
@ VINTRP
Definition: SIDefines.h:48
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_DEFAULT
@ DFMT_NFMT_DEFAULT
Definition: SIDefines.h:497
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::AMDGPU::Exp::ET_POS4
@ ET_POS4
Definition: SIDefines.h:752
llvm::AMDGPU::MTBUFFormat::NFMT_SSCALED
@ NFMT_SSCALED
Definition: SIDefines.h:478
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:60
llvm::SIInstrFlags::renamedInGFX9
@ renamedInGFX9
Definition: SIDefines.h:80
llvm::AMDGPU::SendMsg::ID_GET_DDID
@ ID_GET_DDID
Definition: SIDefines.h:316
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:166
llvm::AMDGPU::Exp::ET_POS3
@ ET_POS3
Definition: SIDefines.h:751
llvm::AMDGPU::VGPRIndexMode::ID_SRC1
@ ID_SRC1
Definition: SIDefines.h:234
llvm::AMDGPU::CPol::SLC
@ SLC
Definition: SIDefines.h:294
llvm::AMDGPU::DPP::ROW_SHR_LAST
@ ROW_SHR_LAST
Definition: SIDefines.h:699
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN
@ INLINE_FLOATING_C_MIN
Definition: SIDefines.h:279
llvm::AMDGPU::MTBUFFormat::NFMT_SINT
@ NFMT_SINT
Definition: SIDefines.h:480
llvm::AMDGPU::Swizzle::ID_SWAP
@ ID_SWAP
Definition: SIDefines.h:615
llvm::SIInstrFlags::IsMAI
@ IsMAI
Definition: SIDefines.h:111
llvm::AMDGPU::SendMsg::OP_WIDTH_
@ OP_WIDTH_
Definition: SIDefines.h:330
llvm::AMDGPU::DPP::QUAD_PERM_ID
@ QUAD_PERM_ID
Definition: SIDefines.h:690
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_8_8_UNORM
@ UFMT_8_8_8_8_UNORM
Definition: SIDefines.h:573
llvm::SIInstrFlags::FlatScratch
@ FlatScratch
Definition: SIDefines.h:117
llvm::AMDGPU::DPP::DppFiMode
DppFiMode
Definition: SIDefines.h:734
llvm::AMDGPU::OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:188
llvm::AMDGPU::DPP::ROW_SHARE_LAST
@ ROW_SHARE_LAST
Definition: SIDefines.h:726
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_UNORM
@ UFMT_2_10_10_10_UNORM
Definition: SIDefines.h:566
llvm::SIOutMods::NONE
@ NONE
Definition: SIDefines.h:222
llvm::AMDGPU::SendMsg::ID_UNKNOWN_
@ ID_UNKNOWN_
Definition: SIDefines.h:305
llvm::SIInstrFlags::SALU
@ SALU
Definition: SIDefines.h:29
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN
@ INLINE_INTEGER_C_MIN
Definition: SIDefines.h:276
llvm::AMDGPU::DPP::ROW_SHARE0
@ ROW_SHARE0
Definition: SIDefines.h:724
llvm::AMDGPU::SendMsg::STREAM_ID_NONE_
@ STREAM_ID_NONE_
Definition: SIDefines.h:349
llvm::AMDGPU::Hwreg::ID_GPR_ALLOC
@ ID_GPR_ALLOC
Definition: SIDefines.h:369
llvm::AMDGPU::MTBUFFormat::NFMT_SHIFT
@ NFMT_SHIFT
Definition: SIDefines.h:491
llvm::SIInstrFlags::VM_CNT
@ VM_CNT
Definition: SIDefines.h:67
llvm::SIInstrFlags::Gather4
@ Gather4
Definition: SIDefines.h:73
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:168
llvm::AMDGPU::Swizzle::LANE_SHIFT
@ LANE_SHIFT
Definition: SIDefines.h:634
llvm::AMDGPU::SendMsg::OP_SYS_TTRACE_PC
@ OP_SYS_TTRACE_PC
Definition: SIDefines.h:343
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_
@ ID_SYMBOLIC_FIRST_
Definition: SIDefines.h:364
llvm::AMDGPU::Hwreg::EXCP_EN_OVERFLOW_MASK
@ EXCP_EN_OVERFLOW_MASK
Definition: SIDefines.h:432
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:416
llvm::AMDGPU::MTBUFFormat::NFMT_UNORM
@ NFMT_UNORM
Definition: SIDefines.h:475
llvm::AMDGPU::SendMsg::STREAM_ID_SHIFT_
@ STREAM_ID_SHIFT_
Definition: SIDefines.h:353
llvm::AMDGPU::OPERAND_REG_IMM_FIRST
@ OPERAND_REG_IMM_FIRST
Definition: SIDefines.h:185
llvm::SISrcMods::ABS
@ ABS
Definition: SIDefines.h:211
llvm::AMDGPU::Hwreg::ID_TMA_HI
@ ID_TMA_HI
Definition: SIDefines.h:378
llvm::AMDGPU::VGPRIndexMode::SRC2_ENABLE
@ SRC2_ENABLE
Definition: SIDefines.h:246
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:76
llvm::AMDGPU::MTBUFFormat::UFMT_8_UINT
@ UFMT_8_UINT
Definition: SIDefines.h:513
llvm::AMDGPU::Hwreg::WIDTH_M1_MASK_
@ WIDTH_M1_MASK_
Definition: SIDefines.h:409
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:57
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_32_32_FLOAT
@ UFMT_32_32_32_32_FLOAT
Definition: SIDefines.h:597
llvm::SIInstrFlags::maybeAtomic
@ maybeAtomic
Definition: SIDefines.h:79
llvm::AMDGPU::Exp::ET_POS_MAX_IDX
@ ET_POS_MAX_IDX
Definition: SIDefines.h:762
llvm::SIInstrFlags::N_ZERO
@ N_ZERO
Definition: SIDefines.h:134
llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST
@ ROW_NEWBCAST_FIRST
Definition: SIDefines.h:722
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_SNORM
@ UFMT_11_11_10_SNORM
Definition: SIDefines.h:552
llvm::AMDGPU::SDWA::WORD_0
@ WORD_0
Definition: SIDefines.h:657
llvm::AMDGPU::SDWA::VOPC_DST_VCC_MASK
@ VOPC_DST_VCC_MASK
Definition: SIDefines.h:671
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_UNORM
@ UFMT_16_16_UNORM
Definition: SIDefines.h:535
llvm::AMDGPU::DPP::DPP_UNUSED5_FIRST
@ DPP_UNUSED5_FIRST
Definition: SIDefines.h:708
llvm::AMDGPU::DPP::ROW_ROR_LAST
@ ROW_ROR_LAST
Definition: SIDefines.h:703
llvm::AMDGPU::Swizzle::ID_BITMASK_PERM
@ ID_BITMASK_PERM
Definition: SIDefines.h:614
llvm::AMDGPU::Exp::ET_PRIM_MAX_IDX
@ ET_PRIM_MAX_IDX
Definition: SIDefines.h:760
llvm::AMDGPU::Hwreg::DX10_CLAMP_MASK
@ DX10_CLAMP_MASK
Definition: SIDefines.h:423
llvm::SIInstrFlags::VOP3P
@ VOP3P
Definition: SIDefines.h:46
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MASK
@ DFMT_NFMT_MASK
Definition: SIDefines.h:501
llvm::AMDGPU::Swizzle::Id
Id
Definition: SIDefines.h:612
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_SSCALED
@ UFMT_11_11_10_SSCALED
Definition: SIDefines.h:554
llvm::SIInstrFlags::ClampLo
@ ClampLo
Definition: SIDefines.h:89
llvm::AMDGPU::Hwreg::ModeRegisterMasks
ModeRegisterMasks
Definition: SIDefines.h:420
llvm::AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE
@ OFFSET_SRC_SHARED_BASE
Definition: SIDefines.h:401
llvm::SIInstrFlags::SOP1
@ SOP1
Definition: SIDefines.h:33
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:145
llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST
@ ROW_NEWBCAST_LAST
Definition: SIDefines.h:723
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_UINT
@ UFMT_32_32_UINT
Definition: SIDefines.h:580
llvm::AMDGPU::Exp::ET_NULL_MAX_IDX
@ ET_NULL_MAX_IDX
Definition: SIDefines.h:758
llvm::SIInstrFlags::N_SUBNORMAL
@ N_SUBNORMAL
Definition: SIDefines.h:133
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:162
llvm::AMDGPU::Hwreg::ID_STATUS
@ ID_STATUS
Definition: SIDefines.h:366
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_SINT
@ UFMT_8_8_SINT
Definition: SIDefines.h:529
llvm::AMDGPU::MTBUFFormat::UnifiedFormat
UnifiedFormat
Definition: SIDefines.h:506
llvm::AMDGPU::MTBUFFormat::NFMT_FLOAT
@ NFMT_FLOAT
Definition: SIDefines.h:483
llvm::AMDGPU::Hwreg::ID_FLAT_SCR_LO
@ ID_FLAT_SCR_LO
Definition: SIDefines.h:379
llvm::AMDGPU::SDWA::SRC_TTMP_MIN
@ SRC_TTMP_MIN
Definition: SIDefines.h:679
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_LAST_
@ ID_SYMBOLIC_LAST_
Definition: SIDefines.h:387
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_AC_FIRST
Definition: SIDefines.h:191
llvm::AMDGPU::Hwreg::ID_TRAPSTS
@ ID_TRAPSTS
Definition: SIDefines.h:367
llvm::AMDGPU::SendMsg::OP_NONE_
@ OP_NONE_
Definition: SIDefines.h:328
llvm::AMDGPU::DPP::DPP_FI_1
@ DPP_FI_1
Definition: SIDefines.h:736
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:150
llvm::AMDGPU::Exp::ET_PARAM31
@ ET_PARAM31
Definition: SIDefines.h:756
llvm::SIInstrFlags::SCALAR_STORE
@ SCALAR_STORE
Definition: SIDefines.h:75
llvm::AMDGPU::MTBUFFormat::UFMT_8_8_SNORM
@ UFMT_8_8_SNORM
Definition: SIDefines.h:525
llvm::AMDGPU::Hwreg::EXCP_EN_FLOAT_DIV0_MASK
@ EXCP_EN_FLOAT_DIV0_MASK
Definition: SIDefines.h:431
llvm::SIInstrFlags::IntClamp
@ IntClamp
Definition: SIDefines.h:86
llvm::AMDGPU::MTBUFFormat::UFMT_16_UINT
@ UFMT_16_UINT
Definition: SIDefines.h:520
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:180
llvm::AMDGPU::SDWA::BYTE_3
@ BYTE_3
Definition: SIDefines.h:656
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:232
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_UNORM
@ UFMT_10_10_10_2_UNORM
Definition: SIDefines.h:559
llvm::AMDGPU::VGPRIndexMode::ID_DST
@ ID_DST
Definition: SIDefines.h:236
llvm::AMDGPU::Hwreg::CSP_MASK
@ CSP_MASK
Definition: SIDefines.h:439
llvm::AMDGPU::MTBUFFormat::UFMT_8_SSCALED
@ UFMT_8_SSCALED
Definition: SIDefines.h:512
llvm::AMDGPU::DPP::QUAD_PERM_FIRST
@ QUAD_PERM_FIRST
Definition: SIDefines.h:689
llvm::AMDGPU::SendMsg::OP_MASK_
@ OP_MASK_
Definition: SIDefines.h:331
llvm::AMDGPU::MTBUFFormat::UFMT_16_16_16_16_SSCALED
@ UFMT_16_16_16_16_SSCALED
Definition: SIDefines.h:587
llvm::SIInstrFlags::P_NORMAL
@ P_NORMAL
Definition: SIDefines.h:137
llvm::AMDGPU::Exp::ET_MRT_MAX_IDX
@ ET_MRT_MAX_IDX
Definition: SIDefines.h:761
llvm::AMDGPU::SendMsg::ID_HALT_WAVES
@ ID_HALT_WAVES
Definition: SIDefines.h:311
llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC
@ BITMASK_PERM_ENC
Definition: SIDefines.h:627
llvm::AMDGPU::MTBUFFormat::UFMT_10_10_10_2_SNORM
@ UFMT_10_10_10_2_SNORM
Definition: SIDefines.h:560
llvm::AMDGPUAsmVariants::DPP
@ DPP
Definition: SIDefines.h:261
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX10_
@ ID_SYMBOLIC_FIRST_GFX10_
Definition: SIDefines.h:375
llvm::AMDGPU::MTBUFFormat::UFMT_32_32_FLOAT
@ UFMT_32_32_FLOAT
Definition: SIDefines.h:582
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:146
llvm::AMDGPU::DPP::WAVE_ROR1
@ WAVE_ROR1
Definition: SIDefines.h:713
llvm::AMDGPU::MTBUFFormat::UFMT_10_11_11_UNORM
@ UFMT_10_11_11_UNORM
Definition: SIDefines.h:543
llvm::AMDGPU::MTBUFFormat::NFMT_USCALED
@ NFMT_USCALED
Definition: SIDefines.h:477
llvm::AMDGPU::MTBUFFormat::DFMT_16_16
@ DFMT_16_16
Definition: SIDefines.h:452
llvm::AMDGPU::DPP::DPP_UNUSED5_LAST
@ DPP_UNUSED5_LAST
Definition: SIDefines.h:709
llvm::AMDGPU::MTBUFFormat::UFMT_16_SINT
@ UFMT_16_SINT
Definition: SIDefines.h:521
llvm::AMDGPU::DPP::WAVE_SHR1
@ WAVE_SHR1
Definition: SIDefines.h:710
llvm::AMDGPU::OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:189
llvm::AMDGPU::MTBUFFormat::UFMT_2_10_10_10_SSCALED
@ UFMT_2_10_10_10_SSCALED
Definition: SIDefines.h:569
llvm::AMDGPU::Hwreg::ID_HW_ID2
@ ID_HW_ID2
Definition: SIDefines.h:383
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP32
@ OPERAND_REG_INLINE_AC_V2FP32
Definition: SIDefines.h:183
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:181
llvm::AMDGPU::MTBUFFormat::DFMT_MAX
@ DFMT_MAX
Definition: SIDefines.h:465
llvm::AMDGPU::DPP::ROW_SHARE_FIRST
@ ROW_SHARE_FIRST
Definition: SIDefines.h:725
llvm::SIInstrFlags::SOPK_ZEXT
@ SOPK_ZEXT
Definition: SIDefines.h:74
llvm::AMDGPU::EncValues::VGPR_MAX
@ VGPR_MAX
Definition: SIDefines.h:283
llvm::AMDGPU::MTBUFFormat::UFMT_11_11_10_UINT
@ UFMT_11_11_10_UINT
Definition: SIDefines.h:555