LLVM  16.0.0git
SIDefines.h
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1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12 
13 #include "llvm/MC/MCInstrDesc.h"
14 
15 namespace llvm {
16 
17 // This needs to be kept in sync with the field bits in SIRegisterClass.
18 enum SIRCFlags : uint8_t {
19  // For vector registers.
20  HasVGPR = 1 << 0,
21  HasAGPR = 1 << 1,
22  HasSGPR = 1 << 2
23 }; // enum SIRCFlags
24 
25 namespace SIInstrFlags {
26 // This needs to be kept in sync with the field bits in InstSI.
27 enum : uint64_t {
28  // Low bits - basic encoding information.
29  SALU = 1 << 0,
30  VALU = 1 << 1,
31 
32  // SALU instruction formats.
33  SOP1 = 1 << 2,
34  SOP2 = 1 << 3,
35  SOPC = 1 << 4,
36  SOPK = 1 << 5,
37  SOPP = 1 << 6,
38 
39  // VALU instruction formats.
40  VOP1 = 1 << 7,
41  VOP2 = 1 << 8,
42  VOPC = 1 << 9,
43 
44  // TODO: Should this be spilt into VOP3 a and b?
45  VOP3 = 1 << 10,
46  VOP3P = 1 << 12,
47 
48  VINTRP = 1 << 13,
49  SDWA = 1 << 14,
50  DPP = 1 << 15,
51  TRANS = 1 << 16,
52 
53  // Memory instruction formats.
54  MUBUF = 1 << 17,
55  MTBUF = 1 << 18,
56  SMRD = 1 << 19,
57  MIMG = 1 << 20,
58  EXP = 1 << 21,
59  FLAT = 1 << 22,
60  DS = 1 << 23,
61 
62  // Pseudo instruction formats.
63  VGPRSpill = 1 << 24,
64  SGPRSpill = 1 << 25,
65 
66  // LDSDIR instruction format.
67  LDSDIR = 1 << 26,
68 
69  // VINTERP instruction format.
70  VINTERP = 1 << 27,
71 
72  // High bits - other information.
73  VM_CNT = UINT64_C(1) << 32,
74  EXP_CNT = UINT64_C(1) << 33,
75  LGKM_CNT = UINT64_C(1) << 34,
76 
77  WQM = UINT64_C(1) << 35,
78  DisableWQM = UINT64_C(1) << 36,
79  Gather4 = UINT64_C(1) << 37,
80  SOPK_ZEXT = UINT64_C(1) << 38,
81  SCALAR_STORE = UINT64_C(1) << 39,
82  FIXED_SIZE = UINT64_C(1) << 40,
83  VOPAsmPrefer32Bit = UINT64_C(1) << 41,
84  VOP3_OPSEL = UINT64_C(1) << 42,
85  maybeAtomic = UINT64_C(1) << 43,
86  renamedInGFX9 = UINT64_C(1) << 44,
87 
88  // Is a clamp on FP type.
89  FPClamp = UINT64_C(1) << 45,
90 
91  // Is an integer clamp
92  IntClamp = UINT64_C(1) << 46,
93 
94  // Clamps lo component of register.
95  ClampLo = UINT64_C(1) << 47,
96 
97  // Clamps hi component of register.
98  // ClampLo and ClampHi set for packed clamp.
99  ClampHi = UINT64_C(1) << 48,
100 
101  // Is a packed VOP3P instruction.
102  IsPacked = UINT64_C(1) << 49,
103 
104  // Is a D16 buffer instruction.
105  D16Buf = UINT64_C(1) << 50,
106 
107  // FLAT instruction accesses FLAT_GLBL segment.
108  FlatGlobal = UINT64_C(1) << 51,
109 
110  // Uses floating point double precision rounding mode
111  FPDPRounding = UINT64_C(1) << 52,
112 
113  // Instruction is FP atomic.
114  FPAtomic = UINT64_C(1) << 53,
115 
116  // Is a MFMA instruction.
117  IsMAI = UINT64_C(1) << 54,
118 
119  // Is a DOT instruction.
120  IsDOT = UINT64_C(1) << 55,
121 
122  // FLAT instruction accesses FLAT_SCRATCH segment.
123  FlatScratch = UINT64_C(1) << 56,
124 
125  // Atomic without return.
126  IsAtomicNoRet = UINT64_C(1) << 57,
127 
128  // Atomic with return.
129  IsAtomicRet = UINT64_C(1) << 58,
130 
131  // Is a WMMA instruction.
132  IsWMMA = UINT64_C(1) << 59,
133 };
134 
135 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
136 // The result is true if any of these tests are true.
137 enum ClassFlags : unsigned {
138  S_NAN = 1 << 0, // Signaling NaN
139  Q_NAN = 1 << 1, // Quiet NaN
140  N_INFINITY = 1 << 2, // Negative infinity
141  N_NORMAL = 1 << 3, // Negative normal
142  N_SUBNORMAL = 1 << 4, // Negative subnormal
143  N_ZERO = 1 << 5, // Negative zero
144  P_ZERO = 1 << 6, // Positive zero
145  P_SUBNORMAL = 1 << 7, // Positive subnormal
146  P_NORMAL = 1 << 8, // Positive normal
147  P_INFINITY = 1 << 9 // Positive infinity
148 };
149 }
150 
151 namespace AMDGPU {
152 enum OperandType : unsigned {
153  /// Operands with register or 32-bit immediate
166 
167  /// Operands with register or inline constant
178 
179  /// Operand with 32-bit immediate that uses the constant bus.
182 
183  /// Operands with an AccVGPR register or inline constant
193 
196 
199 
202 
205 
206  // Operand for source modifiers for VOP instructions
208 
209  // Operand for SDWA instructions
211 
212 };
213 }
214 
215 // Input operand modifiers bit-masks
216 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
217 namespace SISrcMods {
218  enum : unsigned {
219  NEG = 1 << 0, // Floating-point negate modifier
220  ABS = 1 << 1, // Floating-point absolute modifier
221  SEXT = 1 << 0, // Integer sign-extend modifier
222  NEG_HI = ABS, // Floating-point negate high packed component modifier.
223  OP_SEL_0 = 1 << 2,
224  OP_SEL_1 = 1 << 3,
225  DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
226  };
227 }
228 
229 namespace SIOutMods {
230  enum : unsigned {
231  NONE = 0,
232  MUL2 = 1,
233  MUL4 = 2,
234  DIV2 = 3
235  };
236 }
237 
238 namespace AMDGPU {
239 namespace VGPRIndexMode {
240 
241 enum Id : unsigned { // id of symbolic names
242  ID_SRC0 = 0,
246 
249 };
250 
251 enum EncBits : unsigned {
252  OFF = 0,
258  UNDEF = 0xFFFF
259 };
260 
261 } // namespace VGPRIndexMode
262 } // namespace AMDGPU
263 
264 namespace AMDGPUAsmVariants {
265  enum : unsigned {
266  DEFAULT = 0,
267  VOP3 = 1,
268  SDWA = 2,
269  SDWA9 = 3,
270  DPP = 4,
272  };
273 } // namespace AMDGPUAsmVariants
274 
275 namespace AMDGPU {
276 namespace EncValues { // Encoding values of enum9/8/7 operands
277 
278 enum : unsigned {
279  SGPR_MIN = 0,
280  SGPR_MAX_SI = 101,
282  TTMP_VI_MIN = 112,
283  TTMP_VI_MAX = 123,
292  VGPR_MIN = 256,
293  VGPR_MAX = 511,
294  IS_VGPR = 256 // Indicates VGPR or AGPR
295 };
296 
297 } // namespace EncValues
298 } // namespace AMDGPU
299 
300 namespace AMDGPU {
301 namespace CPol {
302 
303 enum CPol {
304  GLC = 1,
305  SLC = 2,
306  DLC = 4,
307  SCC = 16,
308  SC0 = GLC,
309  SC1 = SCC,
310  NT = SLC,
311  ALL = GLC | SLC | DLC | SCC
312 };
313 
314 } // namespace CPol
315 
316 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
317 
318 enum Id { // Message ID, width(4) [3:0].
320 
321  ID_GS_PreGFX11 = 2, // replaced in GFX11
322  ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
323 
324  ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
325  ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
326 
327  ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
328  ID_STALL_WAVE_GEN = 5, // added in GFX9
329  ID_HALT_WAVES = 6, // added in GFX9
330  ID_ORDERED_PS_DONE = 7, // added in GFX9
331  ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
332  ID_GS_ALLOC_REQ = 9, // added in GFX9
333  ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
334  ID_GET_DDID = 11, // added in GFX10, removed in GFX11
335  ID_SYSMSG = 15,
336 
343 
346 };
347 
348 enum Op { // Both GS and SYS operation IDs.
351  OP_NONE_ = 0,
352  // Bits used for operation encoding
354  OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
355  // GS operations are encoded in bits 5:4
362  // SYS operations are encoded in bits 6:4
369 };
370 
371 enum StreamId : unsigned { // Stream ID, (2) [9:8].
379 };
380 
381 } // namespace SendMsg
382 
383 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
384 
385 enum Id { // HwRegCode, (6) [5:0]
386  ID_MODE = 1,
389  ID_HW_ID = 4,
394  ID_TBA_LO = 16,
395  ID_TBA_HI = 17,
396  ID_TMA_LO = 18,
397  ID_TMA_HI = 19,
398  ID_XCC_ID = 20,
406  ID_HW_ID1 = 23,
407  ID_HW_ID2 = 24,
410 
413  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
414 };
415 
416 enum Offset : unsigned { // Offset, (5) [10:6]
421 
423 
426 };
427 
428 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
433 
436 };
437 
438 // Some values from WidthMinusOne mapped into Width domain.
439 enum Width : unsigned {
441 };
442 
444  FP_ROUND_MASK = 0xf << 0, // Bits 0..3
445  FP_DENORM_MASK = 0xf << 4, // Bits 4..7
446  DX10_CLAMP_MASK = 1 << 8,
447  IEEE_MODE_MASK = 1 << 9,
448  LOD_CLAMP_MASK = 1 << 10,
449  DEBUG_MASK = 1 << 11,
450 
451  // EXCP_EN fields.
459 
460  GPR_IDX_EN_MASK = 1 << 27,
461  VSKIP_MASK = 1 << 28,
462  CSP_MASK = 0x7u << 29 // Bits 29..31
463 };
464 
465 } // namespace Hwreg
466 
467 namespace MTBUFFormat {
468 
469 enum DataFormat : int64_t {
486 
489 
492 
494  DFMT_MASK = 0xF
495 };
496 
497 enum NumFormat : int64_t {
504  NFMT_RESERVED_6, // VI and GFX9
505  NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
507 
510 
513 
516 };
517 
518 enum MergedFormat : int64_t {
522 
523 
525 
527 };
528 
529 enum UnifiedFormatCommon : int64_t {
530  UFMT_MAX = 127,
533 };
534 
535 } // namespace MTBUFFormat
536 
537 namespace UfmtGFX10 {
538 enum UnifiedFormat : int64_t {
540 
547 
555 
562 
566 
574 
582 
590 
597 
604 
611 
615 
623 
630 
633 };
634 
635 } // namespace UfmtGFX10
636 
637 namespace UfmtGFX11 {
638 enum UnifiedFormat : int64_t {
640 
647 
655 
662 
666 
674 
676 
678 
683 
690 
697 
701 
709 
716 
719 };
720 
721 } // namespace UfmtGFX11
722 
723 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
724 
725 enum Id : unsigned { // id of symbolic names
731 };
732 
733 enum EncBits : unsigned {
734 
735  // swizzle mode encodings
736 
737  QUAD_PERM_ENC = 0x8000,
739 
742 
743  // QUAD_PERM encodings
744 
745  LANE_MASK = 0x3,
748  LANE_NUM = 4,
749 
750  // BITMASK_PERM encodings
751 
752  BITMASK_MASK = 0x1F,
755 
759 };
760 
761 } // namespace Swizzle
762 
763 namespace SDWA {
764 
765 enum SdwaSel : unsigned {
766  BYTE_0 = 0,
767  BYTE_1 = 1,
768  BYTE_2 = 2,
769  BYTE_3 = 3,
770  WORD_0 = 4,
771  WORD_1 = 5,
772  DWORD = 6,
773 };
774 
775 enum DstUnused : unsigned {
779 };
780 
781 enum SDWA9EncValues : unsigned {
782  SRC_SGPR_MASK = 0x100,
786 
794 };
795 
796 } // namespace SDWA
797 
798 namespace DPP {
799 
800 // clang-format off
801 enum DppCtrl : unsigned {
803  QUAD_PERM_ID = 0xE4, // identity permutation
805  DPP_UNUSED1 = 0x100,
806  ROW_SHL0 = 0x100,
807  ROW_SHL_FIRST = 0x101,
808  ROW_SHL_LAST = 0x10F,
809  DPP_UNUSED2 = 0x110,
810  ROW_SHR0 = 0x110,
811  ROW_SHR_FIRST = 0x111,
812  ROW_SHR_LAST = 0x11F,
813  DPP_UNUSED3 = 0x120,
814  ROW_ROR0 = 0x120,
815  ROW_ROR_FIRST = 0x121,
816  ROW_ROR_LAST = 0x12F,
817  WAVE_SHL1 = 0x130,
820  WAVE_ROL1 = 0x134,
823  WAVE_SHR1 = 0x138,
826  WAVE_ROR1 = 0x13C,
829  ROW_MIRROR = 0x140,
831  BCAST15 = 0x142,
832  BCAST31 = 0x143,
837  ROW_SHARE0 = 0x150,
839  ROW_SHARE_LAST = 0x15F,
840  ROW_XMASK0 = 0x160,
842  ROW_XMASK_LAST = 0x16F,
844 };
845 // clang-format on
846 
847 enum DppFiMode {
848  DPP_FI_0 = 0,
849  DPP_FI_1 = 1,
850  DPP8_FI_0 = 0xE9,
851  DPP8_FI_1 = 0xEA,
852 };
853 
854 } // namespace DPP
855 
856 namespace Exp {
857 
858 enum Target : unsigned {
859  ET_MRT0 = 0,
860  ET_MRT7 = 7,
861  ET_MRTZ = 8,
862  ET_NULL = 9, // Pre-GFX11
863  ET_POS0 = 12,
864  ET_POS3 = 15,
865  ET_POS4 = 16, // GFX10+
866  ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
867  ET_PRIM = 20, // GFX10+
868  ET_DUAL_SRC_BLEND0 = 21, // GFX11+
869  ET_DUAL_SRC_BLEND1 = 22, // GFX11+
870  ET_PARAM0 = 32, // Pre-GFX11
871  ET_PARAM31 = 63, // Pre-GFX11
872 
880 
881  ET_INVALID = 255,
882 };
883 
884 } // namespace Exp
885 
886 namespace VOP3PEncoding {
887 
888 enum OpSel : uint64_t {
889  OP_SEL_HI_0 = UINT64_C(1) << 59,
890  OP_SEL_HI_1 = UINT64_C(1) << 60,
891  OP_SEL_HI_2 = UINT64_C(1) << 14,
892 };
893 
894 } // namespace VOP3PEncoding
895 
896 namespace ImplicitArg {
897 // Implicit kernel argument offset for code object version 5.
898 enum Offset_COV5 : unsigned {
905 };
906 
907 } // namespace ImplicitArg
908 } // namespace AMDGPU
909 
910 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
911 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
912 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
913 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
914 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
915 #define C_00B028_MEM_ORDERED 0xFDFFFFFF
916 
917 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
918 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
919 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
920 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
921 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
922 #define C_00B128_MEM_ORDERED 0xF7FFFFFF
923 
924 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
925 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
926 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
927 #define C_00B228_WGP_MODE 0xF7FFFFFF
928 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
929 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
930 #define C_00B228_MEM_ORDERED 0xFDFFFFFF
931 
932 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
933 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
934 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
935 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
936 #define C_00B428_WGP_MODE 0xFBFFFFFF
937 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
938 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
939 #define C_00B428_MEM_ORDERED 0xFEFFFFFF
940 
941 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
942 
943 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
944 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
945 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
946 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
947 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
948 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
949 #define C_00B84C_USER_SGPR 0xFFFFFFC1
950 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
951 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
952 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
953 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
954 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
955 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
956 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
957 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
958 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
959 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
960 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
961 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
962 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
963 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
964 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
965 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
966 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
967 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
968 /* CIK */
969 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
970 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
971 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
972 /* */
973 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
974 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
975 #define C_00B84C_LDS_SIZE 0xFF007FFF
976 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
977 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
978 #define C_00B84C_EXCP_EN
979 
980 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
981 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
982 
983 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
984 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
985 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
986 #define C_00B848_VGPRS 0xFFFFFFC0
987 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
988 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
989 #define C_00B848_SGPRS 0xFFFFFC3F
990 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
991 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
992 #define C_00B848_PRIORITY 0xFFFFF3FF
993 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
994 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
995 #define C_00B848_FLOAT_MODE 0xFFF00FFF
996 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
997 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
998 #define C_00B848_PRIV 0xFFEFFFFF
999 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1000 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1001 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
1002 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1003 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1004 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
1005 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1006 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1007 #define C_00B848_IEEE_MODE 0xFF7FFFFF
1008 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1009 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1010 #define C_00B848_WGP_MODE 0xDFFFFFFF
1011 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1012 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1013 #define C_00B848_MEM_ORDERED 0xBFFFFFFF
1014 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1015 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1016 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1017 
1018 
1019 // Helpers for setting FLOAT_MODE
1020 #define FP_ROUND_ROUND_TO_NEAREST 0
1021 #define FP_ROUND_ROUND_TO_INF 1
1022 #define FP_ROUND_ROUND_TO_NEGINF 2
1023 #define FP_ROUND_ROUND_TO_ZERO 3
1024 
1025 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1026 // precision.
1027 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1028 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1029 
1030 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1031 #define FP_DENORM_FLUSH_OUT 1
1032 #define FP_DENORM_FLUSH_IN 2
1033 #define FP_DENORM_FLUSH_NONE 3
1034 
1035 
1036 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1037 // precision.
1038 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1039 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1040 
1041 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1042 #define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1043 #define S_00B860_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1044 
1045 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1046 #define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1047 #define S_0286E8_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1048 
1049 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1050 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1051 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1052 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1053 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1054 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1055 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1056 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1057 
1058 #define R_SPILLED_SGPRS 0x4
1059 #define R_SPILLED_VGPRS 0x8
1060 } // End namespace llvm
1061 
1062 #endif
llvm::AMDGPU::MTBUFFormat::DataFormat
DataFormat
Definition: SIDefines.h:469
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:173
llvm::AMDGPU::MTBUFFormat::DFMT_DEFAULT
@ DFMT_DEFAULT
Definition: SIDefines.h:491
llvm::AMDGPU::Hwreg::EXCP_EN_INPUT_DENORMAL_MASK
@ EXCP_EN_INPUT_DENORMAL_MASK
Definition: SIDefines.h:453
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_POSITIVE_MAX
@ INLINE_INTEGER_C_POSITIVE_MAX
Definition: SIDefines.h:287
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_USCALED
@ UFMT_16_16_16_16_USCALED
Definition: SIDefines.h:704
llvm::SIInstrFlags::VOP3
@ VOP3
Definition: SIDefines.h:45
llvm::AMDGPU::SendMsg::ID_RTN_GET_DDID
@ ID_RTN_GET_DDID
Definition: SIDefines.h:338
llvm::AMDGPU::DPP::ROW_SHL_LAST
@ ROW_SHL_LAST
Definition: SIDefines.h:808
llvm::AMDGPU::DPP::ROW_SHR_FIRST
@ ROW_SHR_FIRST
Definition: SIDefines.h:811
llvm::AMDGPU::UfmtGFX10::UFMT_FIRST
@ UFMT_FIRST
Definition: SIDefines.h:631
llvm::SISrcMods::DST_OP_SEL
@ DST_OP_SEL
Definition: SIDefines.h:225
llvm::AMDGPU::DPP::ROW_ROR_FIRST
@ ROW_ROR_FIRST
Definition: SIDefines.h:815
llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_SNORM
@ UFMT_2_10_10_10_SNORM
Definition: SIDefines.h:599
llvm::AMDGPU::Hwreg::IEEE_MODE_MASK
@ IEEE_MODE_MASK
Definition: SIDefines.h:447
llvm::AMDGPU::DPP::DPP_FI_0
@ DPP_FI_0
Definition: SIDefines.h:848
llvm::AMDGPU::DPP::QUAD_PERM_LAST
@ QUAD_PERM_LAST
Definition: SIDefines.h:804
llvm::AMDGPU::UfmtGFX11::UFMT_16_SNORM
@ UFMT_16_SNORM
Definition: SIDefines.h:649
llvm::AMDGPU::DPP::DPP_UNUSED7_LAST
@ DPP_UNUSED7_LAST
Definition: SIDefines.h:828
llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_UINT
@ UFMT_11_11_10_UINT
Definition: SIDefines.h:587
llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_SSCALED
@ UFMT_11_11_10_SSCALED
Definition: SIDefines.h:586
llvm::SIInstrFlags::FPAtomic
@ FPAtomic
Definition: SIDefines.h:114
llvm::AMDGPU::UfmtGFX10::UFMT_INVALID
@ UFMT_INVALID
Definition: SIDefines.h:539
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::SIInstrFlags::FlatScratch
@ FlatScratch
Definition: SIDefines.h:123
llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_32_SINT
@ UFMT_32_32_32_32_SINT
Definition: SIDefines.h:714
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_SNORM
@ UFMT_16_16_16_16_SNORM
Definition: SIDefines.h:617
llvm::AMDGPU::DPP::ROW_SHR0
@ ROW_SHR0
Definition: SIDefines.h:810
llvm::AMDGPU::MTBUFFormat::NumFormat
NumFormat
Definition: SIDefines.h:497
llvm::SIOutMods::MUL2
@ MUL2
Definition: SIDefines.h:232
llvm::AMDGPU::SendMsg::ID_RTN_GET_DOORBELL
@ ID_RTN_GET_DOORBELL
Definition: SIDefines.h:337
llvm::AMDGPU::DPP::DPP8_FI_0
@ DPP8_FI_0
Definition: SIDefines.h:850
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_SSCALED
@ UFMT_8_8_8_8_SSCALED
Definition: SIDefines.h:608
llvm::AMDGPU::MTBUFFormat::DFMT_2_10_10_10
@ DFMT_2_10_10_10
Definition: SIDefines.h:479
llvm::AMDGPU::UfmtGFX10::UFMT_16_FLOAT
@ UFMT_16_FLOAT
Definition: SIDefines.h:554
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_0
@ OP_SEL_HI_0
Definition: SIDefines.h:889
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:168
llvm::AMDGPU::UfmtGFX10::UFMT_8_SSCALED
@ UFMT_8_SSCALED
Definition: SIDefines.h:544
llvm::AMDGPU::DPP::BCAST31
@ BCAST31
Definition: SIDefines.h:832
llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_SINT
@ UFMT_2_10_10_10_SINT
Definition: SIDefines.h:603
llvm::SISrcMods::ABS
@ ABS
Definition: SIDefines.h:220
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_UNORM
@ UFMT_8_8_8_8_UNORM
Definition: SIDefines.h:605
llvm::AMDGPU::SDWA::BYTE_1
@ BYTE_1
Definition: SIDefines.h:767
llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_UNORM
@ UFMT_2_10_10_10_UNORM
Definition: SIDefines.h:598
llvm::AMDGPU::Hwreg::ID_SHIFT_
@ ID_SHIFT_
Definition: SIDefines.h:411
MCInstrDesc.h
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_UINT
@ UFMT_8_8_UINT
Definition: SIDefines.h:660
llvm::AMDGPU::MTBUFFormat::DFMT_32
@ DFMT_32
Definition: SIDefines.h:474
llvm::AMDGPU::MTBUFFormat::DFMT_8_8
@ DFMT_8_8
Definition: SIDefines.h:473
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MIN
@ TTMP_GFX9PLUS_MIN
Definition: SIDefines.h:284
llvm::AMDGPU::Hwreg::WidthMinusOne
WidthMinusOne
Definition: SIDefines.h:428
llvm::AMDGPU::MTBUFFormat::NFMT_RESERVED_6
@ NFMT_RESERVED_6
Definition: SIDefines.h:504
llvm::AMDGPU::Hwreg::ID_LDS_ALLOC
@ ID_LDS_ALLOC
Definition: SIDefines.h:391
llvm::AMDGPU::UfmtGFX11::UFMT_10_10_10_2_SINT
@ UFMT_10_10_10_2_SINT
Definition: SIDefines.h:682
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_SSCALED
@ UFMT_8_8_SSCALED
Definition: SIDefines.h:659
llvm::SIInstrFlags::SOPK
@ SOPK
Definition: SIDefines.h:36
llvm::AMDGPU::MTBUFFormat::DFMT_MASK
@ DFMT_MASK
Definition: SIDefines.h:494
llvm::AMDGPU::Swizzle::BITMASK_OR_SHIFT
@ BITMASK_OR_SHIFT
Definition: SIDefines.h:757
llvm::AMDGPU::MTBUFFormat::DFMT_10_10_10_2
@ DFMT_10_10_10_2
Definition: SIDefines.h:478
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_USCALED
@ UFMT_8_8_USCALED
Definition: SIDefines.h:558
llvm::AMDGPU::UfmtGFX11::UFMT_INVALID
@ UFMT_INVALID
Definition: SIDefines.h:639
llvm::SIInstrFlags::EXP
@ EXP
Definition: SIDefines.h:58
llvm::AMDGPU::UfmtGFX11::UFMT_8_SINT
@ UFMT_8_SINT
Definition: SIDefines.h:646
llvm::AMDGPU::OPERAND_KIMM16
@ OPERAND_KIMM16
Definition: SIDefines.h:181
llvm::AMDGPU::DPP::DPP_UNUSED3
@ DPP_UNUSED3
Definition: SIDefines.h:813
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:162
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_SINT
@ UFMT_8_8_8_8_SINT
Definition: SIDefines.h:696
llvm::AMDGPUAsmVariants::VOP3_DPP
@ VOP3_DPP
Definition: SIDefines.h:271
llvm::AMDGPU::SendMsg::ID_STALL_WAVE_GEN
@ ID_STALL_WAVE_GEN
Definition: SIDefines.h:328
llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_USCALED
@ UFMT_10_10_10_2_USCALED
Definition: SIDefines.h:593
llvm::AMDGPU::UfmtGFX11::UFMT_32_32_UINT
@ UFMT_32_32_UINT
Definition: SIDefines.h:698
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_SINT
@ UFMT_16_16_SINT
Definition: SIDefines.h:572
llvm::AMDGPU::Swizzle::QUAD_PERM_ENC
@ QUAD_PERM_ENC
Definition: SIDefines.h:737
llvm::AMDGPU::DPP::DPP8_FI_1
@ DPP8_FI_1
Definition: SIDefines.h:851
llvm::AMDGPU::MTBUFFormat::NFMT_UNDEF
@ NFMT_UNDEF
Definition: SIDefines.h:511
llvm::AMDGPU::UfmtGFX11::UFMT_32_SINT
@ UFMT_32_SINT
Definition: SIDefines.h:664
llvm::AMDGPU::VGPRIndexMode::ID_SRC0
@ ID_SRC0
Definition: SIDefines.h:242
llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_SNORM
@ UFMT_11_11_10_SNORM
Definition: SIDefines.h:584
llvm::SIInstrFlags::IsAtomicNoRet
@ IsAtomicNoRet
Definition: SIDefines.h:126
llvm::SIInstrFlags::LGKM_CNT
@ LGKM_CNT
Definition: SIDefines.h:75
llvm::AMDGPU::Exp::ET_NULL
@ ET_NULL
Definition: SIDefines.h:862
llvm::AMDGPU::SendMsg::STREAM_ID_MASK_
@ STREAM_ID_MASK_
Definition: SIDefines.h:378
llvm::AMDGPU::MTBUFFormat::DFMT_32_32_32
@ DFMT_32_32_32
Definition: SIDefines.h:483
llvm::AMDGPU::UfmtGFX10::UFMT_32_32_UINT
@ UFMT_32_32_UINT
Definition: SIDefines.h:612
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_UNORM
@ UFMT_8_8_8_8_UNORM
Definition: SIDefines.h:691
llvm::AMDGPU::MTBUFFormat::DFMT_8
@ DFMT_8
Definition: SIDefines.h:471
llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_SINT
@ UFMT_10_10_10_2_SINT
Definition: SIDefines.h:596
llvm::AMDGPU::ImplicitArg::PRIVATE_BASE_OFFSET
@ PRIVATE_BASE_OFFSET
Definition: SIDefines.h:902
llvm::AMDGPU::SendMsg::OP_GS_LAST_
@ OP_GS_LAST_
Definition: SIDefines.h:360
llvm::AMDGPU::VOP3PEncoding::OpSel
OpSel
Definition: SIDefines.h:888
llvm::AMDGPU::Swizzle::LANE_MASK
@ LANE_MASK
Definition: SIDefines.h:745
llvm::AMDGPU::SendMsg::STREAM_ID_WIDTH_
@ STREAM_ID_WIDTH_
Definition: SIDefines.h:377
llvm::AMDGPU::Hwreg::EXCP_EN_INVALID_MASK
@ EXCP_EN_INVALID_MASK
Definition: SIDefines.h:452
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_UNORM
@ UFMT_8_8_UNORM
Definition: SIDefines.h:556
llvm::AMDGPU::SendMsg::ID_HS_TESSFACTOR_GFX11Plus
@ ID_HS_TESSFACTOR_GFX11Plus
Definition: SIDefines.h:324
llvm::AMDGPU::SDWA::BYTE_0
@ BYTE_0
Definition: SIDefines.h:766
llvm::AMDGPUAsmVariants::DEFAULT
@ DEFAULT
Definition: SIDefines.h:266
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_SNORM
@ UFMT_16_16_SNORM
Definition: SIDefines.h:668
llvm::AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE
@ WIDTH_M1_SRC_PRIVATE_BASE
Definition: SIDefines.h:435
llvm::AMDGPU::DPP::DPP_UNUSED4_LAST
@ DPP_UNUSED4_LAST
Definition: SIDefines.h:819
llvm::AMDGPU::Hwreg::OFFSET_WIDTH_
@ OFFSET_WIDTH_
Definition: SIDefines.h:419
llvm::AMDGPU::Hwreg::ID_MASK_
@ ID_MASK_
Definition: SIDefines.h:413
llvm::AMDGPU::Exp::ET_POS0
@ ET_POS0
Definition: SIDefines.h:863
llvm::AMDGPU::OperandType
OperandType
Definition: SIDefines.h:152
llvm::AMDGPU::MTBUFFormat::DFMT_11_11_10
@ DFMT_11_11_10
Definition: SIDefines.h:477
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MAX
@ DFMT_NFMT_MAX
Definition: SIDefines.h:526
llvm::AMDGPU::OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:164
llvm::SISrcMods::NEG
@ NEG
Definition: SIDefines.h:219
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_SSCALED
@ UFMT_16_16_16_16_SSCALED
Definition: SIDefines.h:705
llvm::AMDGPU::SendMsg::OP_GS_CUT
@ OP_GS_CUT
Definition: SIDefines.h:357
llvm::AMDGPU::SendMsg::ID_EARLY_PRIM_DEALLOC
@ ID_EARLY_PRIM_DEALLOC
Definition: SIDefines.h:331
llvm::AMDGPU::DPP::ROW_XMASK0
@ ROW_XMASK0
Definition: SIDefines.h:840
llvm::AMDGPU::MTBUFFormat::NFMT_DEFAULT
@ NFMT_DEFAULT
Definition: SIDefines.h:512
llvm::AMDGPU::SDWA::UNUSED_PRESERVE
@ UNUSED_PRESERVE
Definition: SIDefines.h:778
llvm::AMDGPU::MTBUFFormat::NFMT_SNORM
@ NFMT_SNORM
Definition: SIDefines.h:499
llvm::AMDGPU::Swizzle::BITMASK_XOR_SHIFT
@ BITMASK_XOR_SHIFT
Definition: SIDefines.h:758
llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_UNORM
@ UFMT_2_10_10_10_UNORM
Definition: SIDefines.h:684
llvm::AMDGPU::DPP::ROW_MIRROR
@ ROW_MIRROR
Definition: SIDefines.h:829
llvm::AMDGPU::UfmtGFX10::UFMT_8_SINT
@ UFMT_8_SINT
Definition: SIDefines.h:546
llvm::SIInstrFlags::DPP
@ DPP
Definition: SIDefines.h:50
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:858
llvm::AMDGPU::UfmtGFX10::UFMT_32_32_FLOAT
@ UFMT_32_32_FLOAT
Definition: SIDefines.h:614
llvm::AMDGPU::Swizzle::BITMASK_WIDTH
@ BITMASK_WIDTH
Definition: SIDefines.h:754
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_SI
@ SRC_SGPR_MAX_SI
Definition: SIDefines.h:790
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:129
llvm::SISrcMods::NEG_HI
@ NEG_HI
Definition: SIDefines.h:222
llvm::AMDGPU::Hwreg::ID_HW_ID1
@ ID_HW_ID1
Definition: SIDefines.h:406
llvm::AMDGPU::DPP::DPP_UNUSED1
@ DPP_UNUSED1
Definition: SIDefines.h:805
llvm::AMDGPU::SendMsg::OP_GS_EMIT
@ OP_GS_EMIT
Definition: SIDefines.h:358
llvm::AMDGPU::DPP::DPP_UNUSED7_FIRST
@ DPP_UNUSED7_FIRST
Definition: SIDefines.h:827
llvm::AMDGPU::Swizzle::LANE_MAX
@ LANE_MAX
Definition: SIDefines.h:746
llvm::AMDGPU::Hwreg::WIDTH_M1_DEFAULT_
@ WIDTH_M1_DEFAULT_
Definition: SIDefines.h:429
llvm::SIInstrFlags::EXP_CNT
@ EXP_CNT
Definition: SIDefines.h:74
llvm::AMDGPU::OPERAND_REG_IMM_LAST
@ OPERAND_REG_IMM_LAST
Definition: SIDefines.h:195
llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_FLOAT
@ UFMT_32_32_32_FLOAT
Definition: SIDefines.h:712
llvm::SIInstrFlags::FIXED_SIZE
@ FIXED_SIZE
Definition: SIDefines.h:82
llvm::AMDGPU::SDWA::VOPC_DST_SGPR_MASK
@ VOPC_DST_SGPR_MASK
Definition: SIDefines.h:785
llvm::AMDGPU::VGPRIndexMode::SRC0_ENABLE
@ SRC0_ENABLE
Definition: SIDefines.h:253
llvm::AMDGPU::SendMsg::Id
Id
Definition: SIDefines.h:318
llvm::AMDGPU::DPP::ROW_SHL_FIRST
@ ROW_SHL_FIRST
Definition: SIDefines.h:807
llvm::AMDGPU::Hwreg::EXCP_EN_INEXACT_MASK
@ EXCP_EN_INEXACT_MASK
Definition: SIDefines.h:457
llvm::SIRCFlags
SIRCFlags
Definition: SIDefines.h:18
Swizzle
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
Definition: R600InstrInfo.cpp:350
llvm::SIInstrFlags::SOPC
@ SOPC
Definition: SIDefines.h:35
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_UINT
@ UFMT_16_16_UINT
Definition: SIDefines.h:671
llvm::AMDGPU::Exp::ET_PARAM0
@ ET_PARAM0
Definition: SIDefines.h:870
llvm::AMDGPU::UfmtGFX10::UFMT_32_FLOAT
@ UFMT_32_FLOAT
Definition: SIDefines.h:565
llvm::AMDGPUAsmVariants::SDWA9
@ SDWA9
Definition: SIDefines.h:269
llvm::AMDGPU::SDWA::SRC_VGPR_MAX
@ SRC_VGPR_MAX
Definition: SIDefines.h:788
llvm::AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE
@ OFFSET_SRC_PRIVATE_BASE
Definition: SIDefines.h:425
llvm::SIInstrFlags::VALU
@ VALU
Definition: SIDefines.h:30
llvm::AMDGPU::SDWA::DstUnused
DstUnused
Definition: SIDefines.h:775
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_SNORM
@ UFMT_8_8_SNORM
Definition: SIDefines.h:557
llvm::SIInstrFlags::SOPP
@ SOPP
Definition: SIDefines.h:37
llvm::AMDGPU::Hwreg::ID_IB_STS
@ ID_IB_STS
Definition: SIDefines.h:392
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN
@ INLINE_INTEGER_C_MIN
Definition: SIDefines.h:286
llvm::SIOutMods::MUL4
@ MUL4
Definition: SIDefines.h:233
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_UINT
@ UFMT_8_8_8_8_UINT
Definition: SIDefines.h:609
llvm::AMDGPU::SendMsg::ID_SAVEWAVE
@ ID_SAVEWAVE
Definition: SIDefines.h:327
llvm::SIInstrFlags::WQM
@ WQM
Definition: SIDefines.h:77
llvm::AMDGPU::MTBUFFormat::MergedFormat
MergedFormat
Definition: SIDefines.h:518
llvm::AMDGPU::UfmtGFX11::UFMT_32_32_FLOAT
@ UFMT_32_32_FLOAT
Definition: SIDefines.h:700
llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_SINT
@ UFMT_32_32_32_SINT
Definition: SIDefines.h:711
llvm::AMDGPU::SendMsg::ID_MASK_PreGFX11_
@ ID_MASK_PreGFX11_
Definition: SIDefines.h:344
llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_32_FLOAT
@ UFMT_32_32_32_32_FLOAT
Definition: SIDefines.h:629
llvm::AMDGPU::SDWA::UNUSED_SEXT
@ UNUSED_SEXT
Definition: SIDefines.h:777
llvm::AMDGPU::EncValues::IS_VGPR
@ IS_VGPR
Definition: SIDefines.h:294
llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_PC_LO
@ ID_SQ_PERF_SNAPSHOT_PC_LO
Definition: SIDefines.h:401
llvm::AMDGPU::SendMsg::OP_GS_EMIT_CUT
@ OP_GS_EMIT_CUT
Definition: SIDefines.h:359
llvm::AMDGPU::Hwreg::ID_TBA_HI
@ ID_TBA_HI
Definition: SIDefines.h:395
llvm::SIInstrFlags::VINTERP
@ VINTERP
Definition: SIDefines.h:70
llvm::SIInstrFlags::VOP2
@ VOP2
Definition: SIDefines.h:41
llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC_MASK
@ BITMASK_PERM_ENC_MASK
Definition: SIDefines.h:741
llvm::AMDGPU::SendMsg::ID_DEALLOC_VGPRS_GFX11Plus
@ ID_DEALLOC_VGPRS_GFX11Plus
Definition: SIDefines.h:325
llvm::AMDGPU::SDWA::SDWA9EncValues
SDWA9EncValues
Definition: SIDefines.h:781
llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_SSCALED
@ UFMT_10_11_11_SSCALED
Definition: SIDefines.h:578
llvm::AMDGPU::UfmtGFX10::UFMT_16_UINT
@ UFMT_16_UINT
Definition: SIDefines.h:552
llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST
@ OPERAND_REG_INLINE_AC_LAST
Definition: SIDefines.h:201
llvm::AMDGPU::SendMsg::OP_GS_FIRST_
@ OP_GS_FIRST_
Definition: SIDefines.h:361
llvm::AMDGPU::SendMsg::ID_GET_DOORBELL
@ ID_GET_DOORBELL
Definition: SIDefines.h:333
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:157
llvm::AMDGPU::CPol::CPol
CPol
Definition: SIDefines.h:303
llvm::AMDGPU::UfmtGFX10::UnifiedFormat
UnifiedFormat
Definition: SIDefines.h:538
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_UINT
@ UFMT_16_16_16_16_UINT
Definition: SIDefines.h:620
llvm::AMDGPU::UfmtGFX11::UFMT_16_SSCALED
@ UFMT_16_SSCALED
Definition: SIDefines.h:651
llvm::AMDGPU::MTBUFFormat::DFMT_32_32_32_32
@ DFMT_32_32_32_32
Definition: SIDefines.h:484
llvm::AMDGPU::SDWA::UNUSED_PAD
@ UNUSED_PAD
Definition: SIDefines.h:776
llvm::AMDGPU::SendMsg::ID_RTN_SAVE_WAVE
@ ID_RTN_SAVE_WAVE
Definition: SIDefines.h:341
llvm::AMDGPU::VGPRIndexMode::ID_SRC2
@ ID_SRC2
Definition: SIDefines.h:244
llvm::AMDGPU::Exp::ET_INVALID
@ ET_INVALID
Definition: SIDefines.h:881
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT32
@ OPERAND_REG_INLINE_AC_V2INT32
Definition: SIDefines.h:191
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_UINT
@ UFMT_16_16_UINT
Definition: SIDefines.h:571
llvm::AMDGPU::Hwreg::ID_WIDTH_
@ ID_WIDTH_
Definition: SIDefines.h:412
llvm::AMDGPU::Exp::ET_MRTZ_MAX_IDX
@ ET_MRTZ_MAX_IDX
Definition: SIDefines.h:874
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:169
llvm::SIOutMods::DIV2
@ DIV2
Definition: SIDefines.h:234
llvm::AMDGPU::VGPRIndexMode::ENABLE_MASK
@ ENABLE_MASK
Definition: SIDefines.h:257
llvm::AMDGPU::Hwreg::ID_MODE
@ ID_MODE
Definition: SIDefines.h:386
llvm::AMDGPU::DPP::DPP_UNUSED8_FIRST
@ DPP_UNUSED8_FIRST
Definition: SIDefines.h:833
llvm::AMDGPU::SendMsg::OP_SYS_LAST_
@ OP_SYS_LAST_
Definition: SIDefines.h:367
llvm::AMDGPU::SendMsg::ID_GS_ALLOC_REQ
@ ID_GS_ALLOC_REQ
Definition: SIDefines.h:332
llvm::SIInstrFlags::N_INFINITY
@ N_INFINITY
Definition: SIDefines.h:140
llvm::AMDGPU::Hwreg::ID_POPS_PACKER
@ ID_POPS_PACKER
Definition: SIDefines.h:408
llvm::AMDGPU::CPol::DLC
@ DLC
Definition: SIDefines.h:306
llvm::AMDGPU::EncValues::SGPR_MIN
@ SGPR_MIN
Definition: SIDefines.h:279
llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_32_FLOAT
@ UFMT_32_32_32_32_FLOAT
Definition: SIDefines.h:715
llvm::AMDGPU::Swizzle::BITMASK_MAX
@ BITMASK_MAX
Definition: SIDefines.h:753
llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_32_SINT
@ UFMT_32_32_32_32_SINT
Definition: SIDefines.h:628
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:186
llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_UNORM
@ UFMT_10_11_11_UNORM
Definition: SIDefines.h:575
llvm::SIInstrFlags::IsDOT
@ IsDOT
Definition: SIDefines.h:120
llvm::AMDGPU::DPP::ROW_SHL0
@ ROW_SHL0
Definition: SIDefines.h:806
llvm::AMDGPU::UfmtGFX10::UFMT_32_SINT
@ UFMT_32_SINT
Definition: SIDefines.h:564
llvm::AMDGPU::DPP::ROW_XMASK_FIRST
@ ROW_XMASK_FIRST
Definition: SIDefines.h:841
llvm::SIInstrFlags::VGPRSpill
@ VGPRSpill
Definition: SIDefines.h:63
llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_SNORM
@ UFMT_10_11_11_SNORM
Definition: SIDefines.h:576
llvm::AMDGPU::SDWA::SRC_TTMP_MAX
@ SRC_TTMP_MAX
Definition: SIDefines.h:793
llvm::SIInstrFlags::DisableWQM
@ DisableWQM
Definition: SIDefines.h:78
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_USCALED
@ UFMT_8_8_8_8_USCALED
Definition: SIDefines.h:693
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_SSCALED
@ UFMT_16_16_SSCALED
Definition: SIDefines.h:570
llvm::AMDGPU::DPP::DPP_UNUSED4_FIRST
@ DPP_UNUSED4_FIRST
Definition: SIDefines.h:818
llvm::AMDGPU::SendMsg::STREAM_ID_LAST_
@ STREAM_ID_LAST_
Definition: SIDefines.h:374
llvm::SIInstrFlags::LDSDIR
@ LDSDIR
Definition: SIDefines.h:67
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_SINT
@ UFMT_8_8_8_8_SINT
Definition: SIDefines.h:610
llvm::AMDGPU::SendMsg::ID_SYSMSG
@ ID_SYSMSG
Definition: SIDefines.h:335
llvm::AMDGPU::Hwreg::Id
Id
Definition: SIDefines.h:385
llvm::AMDGPU::UfmtGFX11::UFMT_8_USCALED
@ UFMT_8_USCALED
Definition: SIDefines.h:643
llvm::AMDGPU::SDWA::BYTE_2
@ BYTE_2
Definition: SIDefines.h:768
llvm::AMDGPU::Hwreg::GPR_IDX_EN_MASK
@ GPR_IDX_EN_MASK
Definition: SIDefines.h:460
llvm::AMDGPU::UfmtGFX10::UFMT_16_SSCALED
@ UFMT_16_SSCALED
Definition: SIDefines.h:551
llvm::AMDGPU::CPol::NT
@ NT
Definition: SIDefines.h:310
llvm::AMDGPU::MTBUFFormat::DFMT_16_16_16_16
@ DFMT_16_16_16_16
Definition: SIDefines.h:482
llvm::AMDGPU::Exp::ET_PRIM
@ ET_PRIM
Definition: SIDefines.h:867
llvm::AMDGPU::MTBUFFormat::DFMT_16
@ DFMT_16
Definition: SIDefines.h:472
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::SIInstrFlags::FlatGlobal
@ FlatGlobal
Definition: SIDefines.h:108
llvm::SISrcMods::SEXT
@ SEXT
Definition: SIDefines.h:221
llvm::AMDGPU::SendMsg::OP_GS_NOP
@ OP_GS_NOP
Definition: SIDefines.h:356
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:158
llvm::AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE
@ WIDTH_M1_SRC_SHARED_BASE
Definition: SIDefines.h:434
llvm::AMDGPU::SendMsg::OP_SHIFT_
@ OP_SHIFT_
Definition: SIDefines.h:350
llvm::AMDGPU::SendMsg::STREAM_ID_DEFAULT_
@ STREAM_ID_DEFAULT_
Definition: SIDefines.h:373
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_SNORM
@ UFMT_8_8_8_8_SNORM
Definition: SIDefines.h:692
llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_SINT
@ UFMT_32_32_32_SINT
Definition: SIDefines.h:625
llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_FLOAT
@ UFMT_10_11_11_FLOAT
Definition: SIDefines.h:581
llvm::AMDGPU::VGPRIndexMode::SRC1_ENABLE
@ SRC1_ENABLE
Definition: SIDefines.h:254
llvm::AMDGPU::SendMsg::OP_SYS_ECC_ERR_INTERRUPT
@ OP_SYS_ECC_ERR_INTERRUPT
Definition: SIDefines.h:363
llvm::SIInstrFlags::TRANS
@ TRANS
Definition: SIDefines.h:51
llvm::AMDGPUAsmVariants::DPP
@ DPP
Definition: SIDefines.h:270
llvm::AMDGPU::CPol::SC0
@ SC0
Definition: SIDefines.h:308
llvm::AMDGPU::MTBUFFormat::DFMT_8_8_8_8
@ DFMT_8_8_8_8
Definition: SIDefines.h:480
llvm::AMDGPU::MTBUFFormat::DFMT_UNDEF
@ DFMT_UNDEF
Definition: SIDefines.h:490
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN
@ INLINE_FLOATING_C_MIN
Definition: SIDefines.h:289
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX
@ INLINE_INTEGER_C_MAX
Definition: SIDefines.h:288
llvm::AMDGPU::Hwreg::ID_TBA_LO
@ ID_TBA_LO
Definition: SIDefines.h:394
llvm::AMDGPU::MTBUFFormat::DFMT_INVALID
@ DFMT_INVALID
Definition: SIDefines.h:470
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:165
llvm::AMDGPU::UfmtGFX10::UFMT_16_SNORM
@ UFMT_16_SNORM
Definition: SIDefines.h:549
llvm::SIInstrFlags::ClampHi
@ ClampHi
Definition: SIDefines.h:99
llvm::AMDGPU::Hwreg::VSKIP_MASK
@ VSKIP_MASK
Definition: SIDefines.h:461
llvm::AMDGPU::Hwreg::ID_TMA_LO
@ ID_TMA_LO
Definition: SIDefines.h:396
llvm::SIInstrFlags::IsPacked
@ IsPacked
Definition: SIDefines.h:102
llvm::AMDGPU::UfmtGFX11::UFMT_32_32_SINT
@ UFMT_32_32_SINT
Definition: SIDefines.h:699
llvm::AMDGPU::Hwreg::EXCP_EN_INT_DIV0_MASK
@ EXCP_EN_INT_DIV0_MASK
Definition: SIDefines.h:458
llvm::AMDGPU::SendMsg::ID_RTN_GET_REALTIME
@ ID_RTN_GET_REALTIME
Definition: SIDefines.h:340
llvm::AMDGPU::UfmtGFX10::UFMT_8_UNORM
@ UFMT_8_UNORM
Definition: SIDefines.h:541
llvm::SIInstrFlags::SOP1
@ SOP1
Definition: SIDefines.h:33
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:176
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_UINT
@ UFMT_16_16_16_16_UINT
Definition: SIDefines.h:706
llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_DATA
@ ID_SQ_PERF_SNAPSHOT_DATA
Definition: SIDefines.h:399
llvm::AMDGPU::EncValues::SGPR_MAX_SI
@ SGPR_MAX_SI
Definition: SIDefines.h:280
llvm::AMDGPU::SendMsg::StreamId
StreamId
Definition: SIDefines.h:371
llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND0
@ ET_DUAL_SRC_BLEND0
Definition: SIDefines.h:868
llvm::AMDGPU::Exp::ET_POS_LAST
@ ET_POS_LAST
Definition: SIDefines.h:866
llvm::AMDGPU::UfmtGFX11::UFMT_32_FLOAT
@ UFMT_32_FLOAT
Definition: SIDefines.h:665
llvm::AMDGPU::Swizzle::ID_REVERSE
@ ID_REVERSE
Definition: SIDefines.h:729
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_SSCALED
@ UFMT_8_8_SSCALED
Definition: SIDefines.h:559
llvm::AMDGPU::SendMsg::ID_ORDERED_PS_DONE
@ ID_ORDERED_PS_DONE
Definition: SIDefines.h:330
llvm::AMDGPU::MTBUFFormat::NFMT_MIN
@ NFMT_MIN
Definition: SIDefines.h:508
llvm::AMDGPU::Hwreg::OFFSET_MASK_
@ OFFSET_MASK_
Definition: SIDefines.h:420
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_UNORM
@ UFMT_16_16_16_16_UNORM
Definition: SIDefines.h:702
llvm::AMDGPU::OPERAND_SDWA_VOPC_DST
@ OPERAND_SDWA_VOPC_DST
Definition: SIDefines.h:210
llvm::SIInstrFlags::Q_NAN
@ Q_NAN
Definition: SIDefines.h:139
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_USCALED
@ UFMT_8_8_USCALED
Definition: SIDefines.h:658
llvm::AMDGPU::DPP::DPP_UNUSED6_FIRST
@ DPP_UNUSED6_FIRST
Definition: SIDefines.h:824
llvm::AMDGPU::Hwreg::WIDTH_M1_SHIFT_
@ WIDTH_M1_SHIFT_
Definition: SIDefines.h:430
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_2
@ OP_SEL_HI_2
Definition: SIDefines.h:891
llvm::AMDGPU::Swizzle::QUAD_PERM_ENC_MASK
@ QUAD_PERM_ENC_MASK
Definition: SIDefines.h:738
llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_SINT
@ UFMT_10_11_11_SINT
Definition: SIDefines.h:580
llvm::AMDGPU::UfmtGFX11::UFMT_FIRST
@ UFMT_FIRST
Definition: SIDefines.h:717
llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:160
llvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET
@ HOSTCALL_PTR_OFFSET
Definition: SIDefines.h:899
llvm::SIInstrFlags::N_NORMAL
@ N_NORMAL
Definition: SIDefines.h:141
llvm::AMDGPU::UfmtGFX11::UFMT_8_SSCALED
@ UFMT_8_SSCALED
Definition: SIDefines.h:644
llvm::AMDGPU::SDWA::SRC_VGPR_MASK
@ SRC_VGPR_MASK
Definition: SIDefines.h:783
llvm::AMDGPU::Hwreg::WIDTH_M1_WIDTH_
@ WIDTH_M1_WIDTH_
Definition: SIDefines.h:431
llvm::AMDGPU::Exp::ET_PARAM_MAX_IDX
@ ET_PARAM_MAX_IDX
Definition: SIDefines.h:879
llvm::AMDGPU::SendMsg::OP_SYS_REG_RD
@ OP_SYS_REG_RD
Definition: SIDefines.h:364
llvm::AMDGPU::MTBUFFormat::NFMT_MAX
@ NFMT_MAX
Definition: SIDefines.h:509
llvm::AMDGPU::Swizzle::LANE_NUM
@ LANE_NUM
Definition: SIDefines.h:748
llvm::AMDGPU::VGPRIndexMode::ID_MIN
@ ID_MIN
Definition: SIDefines.h:247
llvm::AMDGPU::Hwreg::ID_FLAT_SCR_HI
@ ID_FLAT_SCR_HI
Definition: SIDefines.h:404
llvm::AMDGPU::SDWA::SRC_VGPR_MIN
@ SRC_VGPR_MIN
Definition: SIDefines.h:787
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:170
llvm::SIInstrFlags::S_NAN
@ S_NAN
Definition: SIDefines.h:138
llvm::SIInstrFlags::Gather4
@ Gather4
Definition: SIDefines.h:79
llvm::SISrcMods::OP_SEL_0
@ OP_SEL_0
Definition: SIDefines.h:223
llvm::AMDGPU::CPol::GLC
@ GLC
Definition: SIDefines.h:304
uint64_t
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_UNDEF
@ DFMT_NFMT_UNDEF
Definition: SIDefines.h:519
llvm::AMDGPU::VGPRIndexMode::EncBits
EncBits
Definition: SIDefines.h:251
llvm::AMDGPU::MTBUFFormat::NFMT_MASK
@ NFMT_MASK
Definition: SIDefines.h:515
llvm::AMDGPU::UfmtGFX11::UFMT_10_11_11_FLOAT
@ UFMT_10_11_11_FLOAT
Definition: SIDefines.h:675
llvm::AMDGPU::MTBUFFormat::NFMT_SNORM_OGL
@ NFMT_SNORM_OGL
Definition: SIDefines.h:505
llvm::AMDGPU::DPP::DPP_UNUSED6_LAST
@ DPP_UNUSED6_LAST
Definition: SIDefines.h:825
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:172
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_SSCALED
@ UFMT_8_8_8_8_SSCALED
Definition: SIDefines.h:694
llvm::AMDGPU::MTBUFFormat::DFMT_SHIFT
@ DFMT_SHIFT
Definition: SIDefines.h:493
llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_32_UINT
@ UFMT_32_32_32_32_UINT
Definition: SIDefines.h:713
llvm::AMDGPU::SendMsg::ID_MASK_GFX11Plus_
@ ID_MASK_GFX11Plus_
Definition: SIDefines.h:345
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_USCALED
@ UFMT_16_16_USCALED
Definition: SIDefines.h:569
llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_32_UINT
@ UFMT_32_32_32_32_UINT
Definition: SIDefines.h:627
llvm::AMDGPU::DPP::DppCtrl
DppCtrl
Definition: SIDefines.h:801
llvm::AMDGPU::DPP::DPP_UNUSED8_LAST
@ DPP_UNUSED8_LAST
Definition: SIDefines.h:834
llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND1
@ ET_DUAL_SRC_BLEND1
Definition: SIDefines.h:869
llvm::SIInstrFlags::VM_CNT
@ VM_CNT
Definition: SIDefines.h:73
llvm::AMDGPU::OPERAND_SRC_FIRST
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:203
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_SINT
@ UFMT_8_8_SINT
Definition: SIDefines.h:561
llvm::SIInstrFlags::VOPAsmPrefer32Bit
@ VOPAsmPrefer32Bit
Definition: SIDefines.h:83
llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_UINT
@ UFMT_10_11_11_UINT
Definition: SIDefines.h:579
llvm::AMDGPU::SendMsg::ID_RTN_GET_TBA
@ ID_RTN_GET_TBA
Definition: SIDefines.h:342
llvm::AMDGPU::DPP::DPP_UNUSED2
@ DPP_UNUSED2
Definition: SIDefines.h:809
llvm::AMDGPU::Swizzle::ID_BROADCAST
@ ID_BROADCAST
Definition: SIDefines.h:730
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_FLOAT
@ UFMT_16_16_16_16_FLOAT
Definition: SIDefines.h:708
llvm::AMDGPU::DPP::WAVE_SHL1
@ WAVE_SHL1
Definition: SIDefines.h:817
llvm::AMDGPU::Swizzle::ID_QUAD_PERM
@ ID_QUAD_PERM
Definition: SIDefines.h:726
llvm::SIInstrFlags::FPClamp
@ FPClamp
Definition: SIDefines.h:89
llvm::AMDGPU::SDWA::DWORD
@ DWORD
Definition: SIDefines.h:772
llvm::AMDGPU::DPP::DPP_LAST
@ DPP_LAST
Definition: SIDefines.h:843
llvm::AMDGPU::MTBUFFormat::DFMT_32_32
@ DFMT_32_32
Definition: SIDefines.h:481
llvm::AMDGPU::Hwreg::FP_DENORM_MASK
@ FP_DENORM_MASK
Definition: SIDefines.h:445
llvm::AMDGPU::Hwreg::ID_HW_ID
@ ID_HW_ID
Definition: SIDefines.h:389
llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_USCALED
@ UFMT_2_10_10_10_USCALED
Definition: SIDefines.h:600
llvm::AMDGPU::SendMsg::OP_UNKNOWN_
@ OP_UNKNOWN_
Definition: SIDefines.h:349
llvm::AMDGPU::SendMsg::ID_INTERRUPT
@ ID_INTERRUPT
Definition: SIDefines.h:319
llvm::SIInstrFlags::ClassFlags
ClassFlags
Definition: SIDefines.h:137
llvm::AMDGPU::UfmtGFX10::UFMT_8_UINT
@ UFMT_8_UINT
Definition: SIDefines.h:545
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_SNORM
@ UFMT_16_16_SNORM
Definition: SIDefines.h:568
llvm::AMDGPU::DPP::BCAST15
@ BCAST15
Definition: SIDefines.h:831
llvm::AMDGPU::MTBUFFormat::DFMT_RESERVED_15
@ DFMT_RESERVED_15
Definition: SIDefines.h:485
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MAX
@ TTMP_GFX9PLUS_MAX
Definition: SIDefines.h:285
llvm::AMDGPU::Hwreg::OFFSET_DEFAULT_
@ OFFSET_DEFAULT_
Definition: SIDefines.h:417
llvm::AMDGPU::UfmtGFX11::UFMT_16_SINT
@ UFMT_16_SINT
Definition: SIDefines.h:653
llvm::AMDGPU::EncValues::TTMP_VI_MAX
@ TTMP_VI_MAX
Definition: SIDefines.h:283
llvm::HasVGPR
@ HasVGPR
Definition: SIDefines.h:20
llvm::SIInstrFlags::SOP2
@ SOP2
Definition: SIDefines.h:34
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:184
llvm::AMDGPU::Hwreg::ID_MEM_BASES
@ ID_MEM_BASES
Definition: SIDefines.h:393
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:54
llvm::AMDGPU::Swizzle::BITMASK_MASK
@ BITMASK_MASK
Definition: SIDefines.h:752
llvm::HasSGPR
@ HasSGPR
Definition: SIDefines.h:22
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_UINT
@ UFMT_8_8_UINT
Definition: SIDefines.h:560
llvm::AMDGPU::Hwreg::EXCP_EN_UNDERFLOW_MASK
@ EXCP_EN_UNDERFLOW_MASK
Definition: SIDefines.h:456
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_1
@ OP_SEL_HI_1
Definition: SIDefines.h:890
llvm::AMDGPU::CPol::ALL
@ ALL
Definition: SIDefines.h:311
llvm::AMDGPU::EncValues::VGPR_MIN
@ VGPR_MIN
Definition: SIDefines.h:292
llvm::AMDGPU::SDWA::SdwaSel
SdwaSel
Definition: SIDefines.h:765
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:174
llvm::AMDGPU::Exp::ET_MRT0
@ ET_MRT0
Definition: SIDefines.h:859
llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:161
llvm::SIInstrFlags::IsMAI
@ IsMAI
Definition: SIDefines.h:117
llvm::AMDGPU::Swizzle::BITMASK_AND_SHIFT
@ BITMASK_AND_SHIFT
Definition: SIDefines.h:756
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:55
llvm::AMDGPU::UfmtGFX11::UFMT_32_32_32_UINT
@ UFMT_32_32_32_UINT
Definition: SIDefines.h:710
llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_SSCALED
@ UFMT_10_10_10_2_SSCALED
Definition: SIDefines.h:594
llvm::AMDGPU::UfmtGFX11::UFMT_16_UINT
@ UFMT_16_UINT
Definition: SIDefines.h:652
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:187
llvm::AMDGPU::SDWA::SRC_SGPR_MIN
@ SRC_SGPR_MIN
Definition: SIDefines.h:789
llvm::AMDGPU::MTBUFFormat::DFMT_MIN
@ DFMT_MIN
Definition: SIDefines.h:487
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_UNORM
@ UFMT_8_8_UNORM
Definition: SIDefines.h:656
llvm::AMDGPU::OPERAND_REG_IMM_INT16
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:156
llvm::AMDGPU::CPol::SCC
@ SCC
Definition: SIDefines.h:307
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:185
llvm::AMDGPU::VGPRIndexMode::UNDEF
@ UNDEF
Definition: SIDefines.h:258
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_USCALED
@ UFMT_16_16_USCALED
Definition: SIDefines.h:669
llvm::AMDGPU::EncValues::LITERAL_CONST
@ LITERAL_CONST
Definition: SIDefines.h:291
llvm::SIInstrFlags::maybeAtomic
@ maybeAtomic
Definition: SIDefines.h:85
llvm::AMDGPU::Exp::ET_MRTZ
@ ET_MRTZ
Definition: SIDefines.h:861
llvm::AMDGPU::MTBUFFormat::UFMT_UNDEF
@ UFMT_UNDEF
Definition: SIDefines.h:531
llvm::AMDGPU::Hwreg::ID_XNACK_MASK
@ ID_XNACK_MASK
Definition: SIDefines.h:405
llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_PC_HI
@ ID_SQ_PERF_SNAPSHOT_PC_HI
Definition: SIDefines.h:402
llvm::AMDGPU::Hwreg::WIDTH_DEFAULT_
@ WIDTH_DEFAULT_
Definition: SIDefines.h:440
llvm::HasAGPR
@ HasAGPR
Definition: SIDefines.h:21
llvm::AMDGPU::UfmtGFX11::UFMT_8_UNORM
@ UFMT_8_UNORM
Definition: SIDefines.h:641
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_UNORM
@ UFMT_16_16_UNORM
Definition: SIDefines.h:567
llvm::AMDGPU::DPP::ROW_HALF_MIRROR
@ ROW_HALF_MIRROR
Definition: SIDefines.h:830
llvm::AMDGPU::UfmtGFX10::UFMT_32_32_SINT
@ UFMT_32_32_SINT
Definition: SIDefines.h:613
llvm::AMDGPU::Hwreg::OFFSET_SHIFT_
@ OFFSET_SHIFT_
Definition: SIDefines.h:418
llvm::SIInstrFlags::SCALAR_STORE
@ SCALAR_STORE
Definition: SIDefines.h:81
llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_USCALED
@ UFMT_2_10_10_10_USCALED
Definition: SIDefines.h:686
llvm::AMDGPU::UfmtGFX11::UFMT_8_UINT
@ UFMT_8_UINT
Definition: SIDefines.h:645
llvm::AMDGPU::UfmtGFX10::UFMT_16_USCALED
@ UFMT_16_USCALED
Definition: SIDefines.h:550
uint32_t
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_SNORM
@ UFMT_8_8_8_8_SNORM
Definition: SIDefines.h:606
llvm::AMDGPU::UfmtGFX10::UFMT_32_UINT
@ UFMT_32_UINT
Definition: SIDefines.h:563
llvm::AMDGPU::VGPRIndexMode::ID_MAX
@ ID_MAX
Definition: SIDefines.h:248
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_SNORM
@ UFMT_8_8_SNORM
Definition: SIDefines.h:657
llvm::AMDGPU::UfmtGFX11::UFMT_11_11_10_FLOAT
@ UFMT_11_11_10_FLOAT
Definition: SIDefines.h:677
llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_UINT
@ UFMT_10_10_10_2_UINT
Definition: SIDefines.h:595
llvm::AMDGPU::Hwreg::LOD_CLAMP_MASK
@ LOD_CLAMP_MASK
Definition: SIDefines.h:448
llvm::AMDGPU::SendMsg::OP_SYS_HOST_TRAP_ACK
@ OP_SYS_HOST_TRAP_ACK
Definition: SIDefines.h:365
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_FLOAT
@ UFMT_16_16_FLOAT
Definition: SIDefines.h:673
llvm::SIInstrFlags::SDWA
@ SDWA
Definition: SIDefines.h:49
llvm::AMDGPU::Hwreg::OFFSET_MEM_VIOL
@ OFFSET_MEM_VIOL
Definition: SIDefines.h:422
llvm::AMDGPU::MTBUFFormat::UFMT_DEFAULT
@ UFMT_DEFAULT
Definition: SIDefines.h:532
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_GFX10
@ SRC_SGPR_MAX_GFX10
Definition: SIDefines.h:791
llvm::AMDGPU::DPP::ROW_XMASK_LAST
@ ROW_XMASK_LAST
Definition: SIDefines.h:842
llvm::AMDGPU::VGPRIndexMode::DST_ENABLE
@ DST_ENABLE
Definition: SIDefines.h:256
llvm::AMDGPU::EncValues::SGPR_MAX_GFX10
@ SGPR_MAX_GFX10
Definition: SIDefines.h:281
llvm::SIOutMods::NONE
@ NONE
Definition: SIDefines.h:231
llvm::AMDGPU::SendMsg::STREAM_ID_FIRST_
@ STREAM_ID_FIRST_
Definition: SIDefines.h:375
llvm::SIInstrFlags::P_SUBNORMAL
@ P_SUBNORMAL
Definition: SIDefines.h:145
llvm::AMDGPU::OPERAND_INPUT_MODS
@ OPERAND_INPUT_MODS
Definition: SIDefines.h:207
llvm::AMDGPU::UfmtGFX11::UFMT_10_10_10_2_UNORM
@ UFMT_10_10_10_2_UNORM
Definition: SIDefines.h:679
llvm::AMDGPU::Swizzle::EncBits
EncBits
Definition: SIDefines.h:733
llvm::SIInstrFlags::P_INFINITY
@ P_INFINITY
Definition: SIDefines.h:147
llvm::SIInstrFlags::ClampLo
@ ClampLo
Definition: SIDefines.h:95
llvm::AMDGPU::SendMsg::OP_SYS_FIRST_
@ OP_SYS_FIRST_
Definition: SIDefines.h:368
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:56
llvm::AMDGPU::MTBUFFormat::NFMT_UINT
@ NFMT_UINT
Definition: SIDefines.h:502
llvm::AMDGPU::Hwreg::FP_ROUND_MASK
@ FP_ROUND_MASK
Definition: SIDefines.h:444
llvm::SISrcMods::OP_SEL_1
@ OP_SEL_1
Definition: SIDefines.h:224
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:188
llvm::AMDGPU::SDWA::WORD_1
@ WORD_1
Definition: SIDefines.h:771
llvm::SIInstrFlags::IsWMMA
@ IsWMMA
Definition: SIDefines.h:132
llvm::AMDGPU::VGPRIndexMode::OFF
@ OFF
Definition: SIDefines.h:252
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_FLOAT
@ UFMT_16_16_16_16_FLOAT
Definition: SIDefines.h:622
llvm::AMDGPU::DPP::WAVE_ROL1
@ WAVE_ROL1
Definition: SIDefines.h:820
llvm::AMDGPU::Hwreg::DEBUG_MASK
@ DEBUG_MASK
Definition: SIDefines.h:449
llvm::AMDGPU::Hwreg::ID_SHADER_CYCLES
@ ID_SHADER_CYCLES
Definition: SIDefines.h:409
llvm::AMDGPU::DPP::ROW_ROR0
@ ROW_ROR0
Definition: SIDefines.h:814
llvm::AMDGPU::SDWA::SRC_SGPR_MASK
@ SRC_SGPR_MASK
Definition: SIDefines.h:782
llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_USCALED
@ UFMT_11_11_10_USCALED
Definition: SIDefines.h:585
llvm::AMDGPU::OPERAND_SRC_LAST
@ OPERAND_SRC_LAST
Definition: SIDefines.h:204
llvm::AMDGPU::UfmtGFX11::UFMT_LAST
@ UFMT_LAST
Definition: SIDefines.h:718
llvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET
@ MULTIGRID_SYNC_ARG_OFFSET
Definition: SIDefines.h:900
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:59
llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND_MAX_IDX
@ ET_DUAL_SRC_BLEND_MAX_IDX
Definition: SIDefines.h:878
llvm::AMDGPU::OPERAND_KIMM32
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:180
llvm::SIInstrFlags::P_ZERO
@ P_ZERO
Definition: SIDefines.h:144
llvm::AMDGPU::EncValues::TTMP_VI_MIN
@ TTMP_VI_MIN
Definition: SIDefines.h:282
llvm::AMDGPU::Exp::ET_MRT7
@ ET_MRT7
Definition: SIDefines.h:860
llvm::AMDGPU::MTBUFFormat::DFMT_10_11_11
@ DFMT_10_11_11
Definition: SIDefines.h:476
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:163
llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_SSCALED
@ UFMT_2_10_10_10_SSCALED
Definition: SIDefines.h:687
SDWA
@ SDWA
Definition: SIInstrInfo.cpp:7878
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_DEFAULT
@ DFMT_NFMT_DEFAULT
Definition: SIDefines.h:520
llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_SNORM
@ UFMT_10_10_10_2_SNORM
Definition: SIDefines.h:592
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX
@ INLINE_FLOATING_C_MAX
Definition: SIDefines.h:290
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::AMDGPU::Exp::ET_POS4
@ ET_POS4
Definition: SIDefines.h:865
llvm::AMDGPU::MTBUFFormat::NFMT_SSCALED
@ NFMT_SSCALED
Definition: SIDefines.h:501
llvm::AMDGPU::UfmtGFX10::UFMT_10_11_11_USCALED
@ UFMT_10_11_11_USCALED
Definition: SIDefines.h:577
llvm::AMDGPU::SendMsg::ID_GET_DDID
@ ID_GET_DDID
Definition: SIDefines.h:334
llvm::SIInstrFlags::VOP3_OPSEL
@ VOP3_OPSEL
Definition: SIDefines.h:84
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_SINT
@ UFMT_16_16_16_16_SINT
Definition: SIDefines.h:707
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:175
llvm::AMDGPU::Exp::ET_POS3
@ ET_POS3
Definition: SIDefines.h:864
llvm::AMDGPU::VGPRIndexMode::ID_SRC1
@ ID_SRC1
Definition: SIDefines.h:243
llvm::AMDGPU::CPol::SLC
@ SLC
Definition: SIDefines.h:305
llvm::AMDGPU::DPP::ROW_SHR_LAST
@ ROW_SHR_LAST
Definition: SIDefines.h:812
llvm::AMDGPU::MTBUFFormat::NFMT_SINT
@ NFMT_SINT
Definition: SIDefines.h:503
llvm::AMDGPU::Swizzle::ID_SWAP
@ ID_SWAP
Definition: SIDefines.h:728
llvm::AMDGPU::SendMsg::OP_WIDTH_
@ OP_WIDTH_
Definition: SIDefines.h:353
llvm::AMDGPU::DPP::QUAD_PERM_ID
@ QUAD_PERM_ID
Definition: SIDefines.h:803
llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_FLOAT
@ UFMT_32_32_32_FLOAT
Definition: SIDefines.h:626
llvm::SIInstrFlags::VINTRP
@ VINTRP
Definition: SIDefines.h:48
llvm::AMDGPU::DPP::DppFiMode
DppFiMode
Definition: SIDefines.h:847
llvm::AMDGPU::OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:197
llvm::AMDGPU::UfmtGFX11::UFMT_16_USCALED
@ UFMT_16_USCALED
Definition: SIDefines.h:650
llvm::AMDGPU::DPP::ROW_SHARE_LAST
@ ROW_SHARE_LAST
Definition: SIDefines.h:839
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_8_8_UINT
@ UFMT_8_8_8_8_UINT
Definition: SIDefines.h:695
llvm::AMDGPU::DPP::ROW_SHARE0
@ ROW_SHARE0
Definition: SIDefines.h:837
llvm::AMDGPU::SendMsg::STREAM_ID_NONE_
@ STREAM_ID_NONE_
Definition: SIDefines.h:372
llvm::AMDGPU::UfmtGFX10::UFMT_10_10_10_2_UNORM
@ UFMT_10_10_10_2_UNORM
Definition: SIDefines.h:591
llvm::AMDGPU::Hwreg::ID_GPR_ALLOC
@ ID_GPR_ALLOC
Definition: SIDefines.h:390
llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_SINT
@ UFMT_11_11_10_SINT
Definition: SIDefines.h:588
llvm::AMDGPU::MTBUFFormat::NFMT_SHIFT
@ NFMT_SHIFT
Definition: SIDefines.h:514
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:177
llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_FLOAT
@ UFMT_11_11_10_FLOAT
Definition: SIDefines.h:589
llvm::AMDGPU::UfmtGFX10::UFMT_16_UNORM
@ UFMT_16_UNORM
Definition: SIDefines.h:548
llvm::AMDGPU::Swizzle::LANE_SHIFT
@ LANE_SHIFT
Definition: SIDefines.h:747
llvm::AMDGPU::SendMsg::OP_SYS_TTRACE_PC
@ OP_SYS_TTRACE_PC
Definition: SIDefines.h:366
llvm::AMDGPU::Hwreg::EXCP_EN_OVERFLOW_MASK
@ EXCP_EN_OVERFLOW_MASK
Definition: SIDefines.h:455
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_SINT
@ UFMT_16_16_SINT
Definition: SIDefines.h:672
llvm::AMDGPU::MTBUFFormat::NFMT_UNORM
@ NFMT_UNORM
Definition: SIDefines.h:498
llvm::AMDGPU::SendMsg::STREAM_ID_SHIFT_
@ STREAM_ID_SHIFT_
Definition: SIDefines.h:376
llvm::SIInstrFlags::renamedInGFX9
@ renamedInGFX9
Definition: SIDefines.h:86
llvm::AMDGPU::OPERAND_REG_IMM_FIRST
@ OPERAND_REG_IMM_FIRST
Definition: SIDefines.h:194
llvm::AMDGPU::Hwreg::ID_TMA_HI
@ ID_TMA_HI
Definition: SIDefines.h:397
llvm::AMDGPU::VGPRIndexMode::SRC2_ENABLE
@ SRC2_ENABLE
Definition: SIDefines.h:255
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:77
llvm::AMDGPU::Hwreg::WIDTH_M1_MASK_
@ WIDTH_M1_MASK_
Definition: SIDefines.h:432
llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_SSCALED
@ UFMT_2_10_10_10_SSCALED
Definition: SIDefines.h:601
llvm::AMDGPU::Exp::ET_POS_MAX_IDX
@ ET_POS_MAX_IDX
Definition: SIDefines.h:877
llvm::AMDGPU::Hwreg::ID_XCC_ID
@ ID_XCC_ID
Definition: SIDefines.h:398
llvm::SIInstrFlags::N_ZERO
@ N_ZERO
Definition: SIDefines.h:143
llvm::SIInstrFlags::VOPC
@ VOPC
Definition: SIDefines.h:42
llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST
@ ROW_NEWBCAST_FIRST
Definition: SIDefines.h:835
llvm::SIInstrFlags::IntClamp
@ IntClamp
Definition: SIDefines.h:92
llvm::AMDGPU::SDWA::WORD_0
@ WORD_0
Definition: SIDefines.h:770
llvm::AMDGPU::SDWA::VOPC_DST_VCC_MASK
@ VOPC_DST_VCC_MASK
Definition: SIDefines.h:784
llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_SINT
@ UFMT_2_10_10_10_SINT
Definition: SIDefines.h:689
llvm::SIInstrFlags::SGPRSpill
@ SGPRSpill
Definition: SIDefines.h:64
llvm::AMDGPU::DPP::DPP_UNUSED5_FIRST
@ DPP_UNUSED5_FIRST
Definition: SIDefines.h:821
llvm::AMDGPU::DPP::ROW_ROR_LAST
@ ROW_ROR_LAST
Definition: SIDefines.h:816
llvm::AMDGPU::Swizzle::ID_BITMASK_PERM
@ ID_BITMASK_PERM
Definition: SIDefines.h:727
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_UNORM
@ UFMT_16_16_UNORM
Definition: SIDefines.h:667
llvm::AMDGPU::Exp::ET_PRIM_MAX_IDX
@ ET_PRIM_MAX_IDX
Definition: SIDefines.h:875
llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_UINT
@ UFMT_2_10_10_10_UINT
Definition: SIDefines.h:688
llvm::AMDGPU::Hwreg::DX10_CLAMP_MASK
@ DX10_CLAMP_MASK
Definition: SIDefines.h:446
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MASK
@ DFMT_NFMT_MASK
Definition: SIDefines.h:524
llvm::AMDGPU::SendMsg::ID_GS_DONE_PreGFX11
@ ID_GS_DONE_PreGFX11
Definition: SIDefines.h:322
llvm::AMDGPU::UfmtGFX11::UFMT_10_10_10_2_UINT
@ UFMT_10_10_10_2_UINT
Definition: SIDefines.h:681
llvm::AMDGPU::Swizzle::Id
Id
Definition: SIDefines.h:725
llvm::AMDGPU::Hwreg::ModeRegisterMasks
ModeRegisterMasks
Definition: SIDefines.h:443
llvm::AMDGPU::UfmtGFX10::UFMT_8_USCALED
@ UFMT_8_USCALED
Definition: SIDefines.h:543
llvm::AMDGPU::UfmtGFX11::UFMT_16_FLOAT
@ UFMT_16_FLOAT
Definition: SIDefines.h:654
llvm::AMDGPU::UfmtGFX10::UFMT_32_32_32_UINT
@ UFMT_32_32_32_UINT
Definition: SIDefines.h:624
llvm::AMDGPUAsmVariants::VOP3
@ VOP3
Definition: SIDefines.h:267
llvm::AMDGPU::MTBUFFormat::UFMT_MAX
@ UFMT_MAX
Definition: SIDefines.h:530
llvm::AMDGPU::EncValues::VGPR_MAX
@ VGPR_MAX
Definition: SIDefines.h:293
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_SSCALED
@ UFMT_16_16_SSCALED
Definition: SIDefines.h:670
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_UNORM
@ UFMT_16_16_16_16_UNORM
Definition: SIDefines.h:616
llvm::AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE
@ OFFSET_SRC_SHARED_BASE
Definition: SIDefines.h:424
llvm::AMDGPU::UfmtGFX11::UFMT_16_16_16_16_SNORM
@ UFMT_16_16_16_16_SNORM
Definition: SIDefines.h:703
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:154
llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST
@ ROW_NEWBCAST_LAST
Definition: SIDefines.h:836
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:57
llvm::AMDGPU::Exp::ET_NULL_MAX_IDX
@ ET_NULL_MAX_IDX
Definition: SIDefines.h:873
llvm::AMDGPU::ImplicitArg::QUEUE_PTR_OFFSET
@ QUEUE_PTR_OFFSET
Definition: SIDefines.h:904
llvm::SIInstrFlags::N_SUBNORMAL
@ N_SUBNORMAL
Definition: SIDefines.h:142
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:171
llvm::SIInstrFlags::VOP1
@ VOP1
Definition: SIDefines.h:40
llvm::AMDGPU::ImplicitArg::SHARED_BASE_OFFSET
@ SHARED_BASE_OFFSET
Definition: SIDefines.h:903
llvm::AMDGPU::Hwreg::ID_STATUS
@ ID_STATUS
Definition: SIDefines.h:387
llvm::AMDGPU::UfmtGFX10::UFMT_8_8_8_8_USCALED
@ UFMT_8_8_8_8_USCALED
Definition: SIDefines.h:607
llvm::AMDGPU::MTBUFFormat::NFMT_FLOAT
@ NFMT_FLOAT
Definition: SIDefines.h:506
llvm::AMDGPU::Hwreg::ID_FLAT_SCR_LO
@ ID_FLAT_SCR_LO
Definition: SIDefines.h:403
llvm::AMDGPU::SDWA::SRC_TTMP_MIN
@ SRC_TTMP_MIN
Definition: SIDefines.h:792
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_AC_FIRST
Definition: SIDefines.h:200
llvm::AMDGPU::Hwreg::ID_TRAPSTS
@ ID_TRAPSTS
Definition: SIDefines.h:388
llvm::AMDGPU::SendMsg::OP_NONE_
@ OP_NONE_
Definition: SIDefines.h:351
llvm::AMDGPU::CPol::SC1
@ SC1
Definition: SIDefines.h:309
llvm::AMDGPU::DPP::DPP_FI_1
@ DPP_FI_1
Definition: SIDefines.h:849
llvm::AMDGPU::UfmtGFX11::UFMT_8_8_SINT
@ UFMT_8_8_SINT
Definition: SIDefines.h:661
llvm::SIInstrFlags::SOPK_ZEXT
@ SOPK_ZEXT
Definition: SIDefines.h:80
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:159
llvm::AMDGPU::SendMsg::ID_RTN_GET_TMA
@ ID_RTN_GET_TMA
Definition: SIDefines.h:339
llvm::AMDGPU::Exp::ET_PARAM31
@ ET_PARAM31
Definition: SIDefines.h:871
llvm::SIInstrFlags::D16Buf
@ D16Buf
Definition: SIDefines.h:105
llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_DATA1
@ ID_SQ_PERF_SNAPSHOT_DATA1
Definition: SIDefines.h:400
llvm::AMDGPU::Hwreg::EXCP_EN_FLOAT_DIV0_MASK
@ EXCP_EN_FLOAT_DIV0_MASK
Definition: SIDefines.h:454
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:189
llvm::SIInstrFlags::SALU
@ SALU
Definition: SIDefines.h:29
llvm::AMDGPU::SDWA::BYTE_3
@ BYTE_3
Definition: SIDefines.h:769
llvm::AMDGPU::UfmtGFX11::UFMT_32_UINT
@ UFMT_32_UINT
Definition: SIDefines.h:663
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:241
llvm::AMDGPU::UfmtGFX11::UFMT_8_SNORM
@ UFMT_8_SNORM
Definition: SIDefines.h:642
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_USCALED
@ UFMT_16_16_16_16_USCALED
Definition: SIDefines.h:618
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_SSCALED
@ UFMT_16_16_16_16_SSCALED
Definition: SIDefines.h:619
llvm::AMDGPU::SendMsg::ID_GS_PreGFX11
@ ID_GS_PreGFX11
Definition: SIDefines.h:321
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:60
llvm::AMDGPU::VGPRIndexMode::ID_DST
@ ID_DST
Definition: SIDefines.h:245
llvm::AMDGPU::Hwreg::CSP_MASK
@ CSP_MASK
Definition: SIDefines.h:462
llvm::AMDGPU::UfmtGFX11::UFMT_2_10_10_10_SNORM
@ UFMT_2_10_10_10_SNORM
Definition: SIDefines.h:685
llvm::AMDGPU::DPP::QUAD_PERM_FIRST
@ QUAD_PERM_FIRST
Definition: SIDefines.h:802
llvm::AMDGPU::SendMsg::OP_MASK_
@ OP_MASK_
Definition: SIDefines.h:354
llvm::SIInstrFlags::P_NORMAL
@ P_NORMAL
Definition: SIDefines.h:146
llvm::AMDGPU::UfmtGFX11::UFMT_10_10_10_2_SNORM
@ UFMT_10_10_10_2_SNORM
Definition: SIDefines.h:680
llvm::AMDGPU::Exp::ET_MRT_MAX_IDX
@ ET_MRT_MAX_IDX
Definition: SIDefines.h:876
llvm::AMDGPU::SendMsg::ID_HALT_WAVES
@ ID_HALT_WAVES
Definition: SIDefines.h:329
llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC
@ BITMASK_PERM_ENC
Definition: SIDefines.h:740
llvm::SIInstrFlags::VOP3P
@ VOP3P
Definition: SIDefines.h:46
llvm::AMDGPU::MTBUFFormat::UnifiedFormatCommon
UnifiedFormatCommon
Definition: SIDefines.h:529
llvm::SIInstrFlags::FPDPRounding
@ FPDPRounding
Definition: SIDefines.h:111
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:155
llvm::AMDGPU::UfmtGFX11::UnifiedFormat
UnifiedFormat
Definition: SIDefines.h:638
llvm::AMDGPU::ImplicitArg::Offset_COV5
Offset_COV5
Definition: SIDefines.h:898
llvm::AMDGPU::DPP::WAVE_ROR1
@ WAVE_ROR1
Definition: SIDefines.h:826
llvm::AMDGPU::UfmtGFX10::UFMT_16_SINT
@ UFMT_16_SINT
Definition: SIDefines.h:553
llvm::AMDGPU::MTBUFFormat::NFMT_USCALED
@ NFMT_USCALED
Definition: SIDefines.h:500
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_16_16_SINT
@ UFMT_16_16_16_16_SINT
Definition: SIDefines.h:621
llvm::AMDGPU::MTBUFFormat::DFMT_16_16
@ DFMT_16_16
Definition: SIDefines.h:475
llvm::AMDGPU::DPP::DPP_UNUSED5_LAST
@ DPP_UNUSED5_LAST
Definition: SIDefines.h:822
llvm::AMDGPU::UfmtGFX10::UFMT_16_16_FLOAT
@ UFMT_16_16_FLOAT
Definition: SIDefines.h:573
llvm::AMDGPU::UfmtGFX10::UFMT_11_11_10_UNORM
@ UFMT_11_11_10_UNORM
Definition: SIDefines.h:583
llvm::AMDGPU::UfmtGFX10::UFMT_2_10_10_10_UINT
@ UFMT_2_10_10_10_UINT
Definition: SIDefines.h:602
llvm::AMDGPU::DPP::WAVE_SHR1
@ WAVE_SHR1
Definition: SIDefines.h:823
llvm::AMDGPU::OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:198
llvm::AMDGPU::UfmtGFX10::UFMT_LAST
@ UFMT_LAST
Definition: SIDefines.h:632
llvm::AMDGPUAsmVariants::SDWA
@ SDWA
Definition: SIDefines.h:268
llvm::AMDGPU::Hwreg::ID_HW_ID2
@ ID_HW_ID2
Definition: SIDefines.h:407
llvm::AMDGPU::ImplicitArg::HEAP_PTR_OFFSET
@ HEAP_PTR_OFFSET
Definition: SIDefines.h:901
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP32
@ OPERAND_REG_INLINE_AC_V2FP32
Definition: SIDefines.h:192
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:190
llvm::AMDGPU::MTBUFFormat::DFMT_MAX
@ DFMT_MAX
Definition: SIDefines.h:488
llvm::AMDGPU::UfmtGFX11::UFMT_16_UNORM
@ UFMT_16_UNORM
Definition: SIDefines.h:648
llvm::AMDGPU::DPP::ROW_SHARE_FIRST
@ ROW_SHARE_FIRST
Definition: SIDefines.h:838
llvm::AMDGPU::UfmtGFX10::UFMT_8_SNORM
@ UFMT_8_SNORM
Definition: SIDefines.h:542