LLVM  17.0.0git
SPIRVAsmBackend.cpp
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1 //===-- SPIRVAsmBackend.cpp - SPIR-V Assembler Backend ---------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/MC/MCAsmBackend.h"
11 #include "llvm/MC/MCAssembler.h"
12 #include "llvm/MC/MCObjectWriter.h"
14 
15 using namespace llvm;
16 
17 namespace {
18 
19 class SPIRVAsmBackend : public MCAsmBackend {
20 public:
21  SPIRVAsmBackend(support::endianness Endian) : MCAsmBackend(Endian) {}
22 
23  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
25  uint64_t Value, bool IsResolved,
26  const MCSubtargetInfo *STI) const override {}
27 
28  std::unique_ptr<MCObjectTargetWriter>
29  createObjectTargetWriter() const override {
31  }
32 
33  // No instruction requires relaxation.
34  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
35  const MCRelaxableFragment *DF,
36  const MCAsmLayout &Layout) const override {
37  return false;
38  }
39 
40  unsigned getNumFixupKinds() const override { return 1; }
41 
42  bool mayNeedRelaxation(const MCInst &Inst,
43  const MCSubtargetInfo &STI) const override {
44  return false;
45  }
46 
47  void relaxInstruction(MCInst &Inst,
48  const MCSubtargetInfo &STI) const override {}
49 
50  bool writeNopData(raw_ostream &OS, uint64_t Count,
51  const MCSubtargetInfo *STI) const override {
52  return false;
53  }
54 };
55 
56 } // end anonymous namespace
57 
59  const MCSubtargetInfo &STI,
60  const MCRegisterInfo &MRI,
61  const MCTargetOptions &) {
62  return new SPIRVAsmBackend(support::little);
63 }
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MCRelaxableFragment
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
T
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
MCAssembler.h
SPIRVMCTargetDesc.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
MCAsmBackend.h
llvm::MutableArrayRef< char >
llvm::support::little
@ little
Definition: Endian.h:27
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
DF
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
llvm::MCAssembler
Definition: MCAssembler.h:73
uint64_t
llvm::createSPIRVObjectTargetWriter
std::unique_ptr< MCObjectTargetWriter > createSPIRVObjectTargetWriter()
Definition: SPIRVObjectTargetWriter.cpp:23
llvm::MCTargetOptions
Definition: MCTargetOptions.h:37
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
MCObjectWriter.h
EndianStream.h
llvm::MCAsmLayout
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
llvm::support::endianness
endianness
Definition: Endian.h:27
llvm::createSPIRVAsmBackend
MCAsmBackend * createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: SPIRVAsmBackend.cpp:58
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:35
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:36
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::Value
LLVM Value Representation.
Definition: Value.h:74