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27 #define DEBUG_TYPE "spirv-mccodeemitter"
35 SPIRVMCCodeEmitter(
const MCInstrInfo &mcii) : MCII(mcii) {}
36 SPIRVMCCodeEmitter(
const SPIRVMCCodeEmitter &) =
delete;
37 void operator=(
const SPIRVMCCodeEmitter &) =
delete;
38 ~SPIRVMCCodeEmitter()
override =
default;
53 verifyInstructionPredicates(
const MCInst &
MI,
61 return new SPIRVMCCodeEmitter(MCII);
76 return (DefOpInfo->RegClass == SPIRV::IDRegClassID ||
77 DefOpInfo->RegClass == SPIRV::ANYIDRegClassID) &&
78 FirstArgOpInfo->
RegClass == SPIRV::TYPERegClassID;
87 }
else if (
Op.isImm()) {
97 unsigned NumOps =
MI.getNumOperands();
100 for (
unsigned i = 2;
i < NumOps; ++
i)
106 for (
const auto &
Op :
MI)
114 verifyInstructionPredicates(
MI, Features);
120 const uint32_t NumWords =
MI.getNumOperands() + 1;
121 const uint32_t FirstWord = (NumWords << 16) | OpCode;
131 #define ENABLE_INSTR_PREDICATE_VERIFIER
132 #include "SPIRVGenMCCodeEmitter.inc"
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
This is an optimization pass for GlobalISel generic memory operations.
static void emitTypedInstrOperands(const MCInst &MI, EndianWriter &OSE)
Context object for machine code objects.
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Adapter to write values to a stream in a particular byte order.
MCCodeEmitter * createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Describe properties that are true of each instruction in the target description file.
const FeatureBitset & getFeatureBits() const
This class implements an extremely fast bulk output stream that can only output to a stream.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
static void emitUntypedInstrOperands(const MCInst &MI, EndianWriter &OSE)
void write(ArrayRef< value_type > Val)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Interface to description of machine instruction set.
MCCodeEmitter - Generic instruction encoding interface.
const_opInfo_iterator opInfo_begin() const
static bool hasType(const MCInst &MI, const MCInstrInfo &MII)
static void emitOperand(const MCOperand &Op, EndianWriter &OSE)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Instances of this class represent operands of the MCInst class.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Generic base class for all target subtargets.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.