LLVM  17.0.0git
SSAContext.cpp
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1 //===- SSAContext.cpp -------------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file defines a specialization of the GenericSSAContext<X>
11 /// template class for LLVM IR.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/IR/SSAContext.h"
16 #include "llvm/IR/Argument.h"
17 #include "llvm/IR/BasicBlock.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/IR/Instruction.h"
20 #include "llvm/IR/Instructions.h"
22 
23 using namespace llvm;
24 
26 
27 void SSAContext::setFunction(Function &Fn) { F = &Fn; }
28 
30  return &F.getEntryBlock();
31 }
32 
34  return &F.getEntryBlock();
35 }
36 
38  BasicBlock &block) {
39  for (auto &instr : block.instructionsWithoutDebug(/*SkipPseudoOp=*/true)) {
40  if (instr.isTerminator())
41  break;
42  if (instr.getType()->isVoidTy())
43  continue;
44  auto *def = &instr;
45  defs.push_back(def);
46  }
47 }
48 
50  const BasicBlock &block) {
51  for (auto &instr : block) {
52  if (instr.isTerminator())
53  break;
54  defs.push_back(&instr);
55  }
56 }
57 
59  BasicBlock &block) {
60  terms.push_back(block.getTerminator());
61 }
62 
64  const BasicBlock &block) {
65  terms.push_back(block.getTerminator());
66 }
67 
68 const BasicBlock *SSAContext::getDefBlock(const Value *value) const {
69  if (const auto *instruction = dyn_cast<Instruction>(value))
70  return instruction->getParent();
71  return nullptr;
72 }
73 
74 bool SSAContext::comesBefore(const Instruction *lhs, const Instruction *rhs) {
75  return lhs->comesBefore(rhs);
76 }
77 
79  if (auto *Phi = dyn_cast<PHINode>(&Instr))
80  return Phi->hasConstantValue();
81  return false;
82 }
83 
85  return Printable([V](raw_ostream &Out) { V->print(Out); });
86 }
87 
89  return print(cast<Value>(Inst));
90 }
91 
93  if (!BB)
94  return Printable([](raw_ostream &Out) { Out << "<nullptr>"; });
95  if (BB->hasName())
96  return Printable([BB](raw_ostream &Out) { Out << BB->getName(); });
97 
98  return Printable([BB](raw_ostream &Out) {
99  ModuleSlotTracker MST{BB->getParent()->getParent(), false};
100  MST.incorporateFunction(*BB->getParent());
101  Out << MST.getLocalSlot(BB);
102  });
103 }
block
we get the following basic block
Definition: README_ALTIVEC.txt:95
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Function
Definition: Function.h:59
llvm::GenericSSAContext< Function >::print
Printable print(const BasicBlock *Block) const
Definition: SSAContext.cpp:92
llvm::Instruction::comesBefore
bool comesBefore(const Instruction *Other) const
Given an instruction Other in the same basic block as this instruction, return true if this instructi...
Definition: Instruction.cpp:122
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
Instruction.h
llvm::Instruction
Definition: Instruction.h:41
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::GenericSSAContext< Function >::getEntryBlock
static BasicBlock * getEntryBlock(Function &F)
Definition: SSAContext.cpp:29
llvm::GenericSSAContext< Function >::getDefBlock
const BasicBlock * getDefBlock(const Value *value) const
Definition: SSAContext.cpp:68
BasicBlock.h
llvm::GenericSSAContext< Function >::appendBlockDefs
static void appendBlockDefs(SmallVectorImpl< Value * > &defs, BasicBlock &block)
Definition: SSAContext.cpp:37
llvm::Value::print
void print(raw_ostream &O, bool IsForDebug=false) const
Implement operator<< on Value.
Definition: AsmWriter.cpp:4695
llvm::print
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
Definition: GCNRegPressure.cpp:138
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:806
instruction
Since we know that Vector is byte aligned and we know the element offset of we should change the load into a lve *x instruction
Definition: README_ALTIVEC.txt:37
llvm::GenericSSAContext< Function >::ValueRefNull
static Value * ValueRefNull
Definition: SSAContext.h:46
Argument.h
Function.h
SSAContext.h
instr
@ instr
Definition: HWAddressSanitizer.cpp:194
Instructions.h
llvm::GenericSSAContext< Function >::appendBlockTerms
static void appendBlockTerms(SmallVectorImpl< Instruction * > &terms, BasicBlock &block)
Definition: SSAContext.cpp:58
llvm::Printable
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
llvm::SmallVectorImpl< Value * >
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::GenericSSAContext< Function >::comesBefore
static bool comesBefore(const Instruction *lhs, const Instruction *rhs)
Definition: SSAContext.cpp:74
raw_ostream.h
llvm::GenericSSAContext< Function >::setFunction
void setFunction(Function &Fn)
Definition: SSAContext.cpp:27
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::GenericSSAContext< Function >::isConstantValuePhi
static bool isConstantValuePhi(const Instruction &Instr)
Definition: SSAContext.cpp:78