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HexagonMCInstrInfo.cpp
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1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
10 //
11 //===----------------------------------------------------------------------===//
12 
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/Support/Casting.h"
29 #include <cassert>
30 #include <cstdint>
31 #include <limits>
32 
33 using namespace llvm;
34 
36  return Register != Hexagon::NoRegister;
37 }
38 
40  MCInst const &Inst)
41  : MCII(MCII), BundleCurrent(Inst.begin() +
42  HexagonMCInstrInfo::bundleInstructionsOffset),
43  BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
44 
46  MCInst const &Inst, std::nullptr_t)
47  : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
48  DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
49 
51  if (DuplexCurrent != DuplexEnd) {
52  ++DuplexCurrent;
53  if (DuplexCurrent == DuplexEnd) {
54  DuplexCurrent = BundleEnd;
55  DuplexEnd = BundleEnd;
56  ++BundleCurrent;
57  }
58  return *this;
59  }
60  ++BundleCurrent;
61  if (BundleCurrent != BundleEnd) {
62  MCInst const &Inst = *BundleCurrent->getInst();
63  if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
64  DuplexCurrent = Inst.begin();
65  DuplexEnd = Inst.end();
66  }
67  }
68  return *this;
69 }
70 
72  if (DuplexCurrent != DuplexEnd)
73  return *DuplexCurrent->getInst();
74  return *BundleCurrent->getInst();
75 }
76 
78  return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
79  DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
80 }
81 
83  MCContext &Context) {
85 }
86 
88  MCInstrInfo const &MCII, MCInst &MCB,
89  MCInst const &MCI) {
91  MCOperand const &exOp =
93 
94  // Create the extender.
95  MCInst *XMCI =
96  new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
97  XMCI->setLoc(MCI.getLoc());
98 
100 }
101 
104  MCInst const &MCI) {
105  assert(isBundle(MCI));
106  return make_range(Hexagon::PacketIterator(MCII, MCI),
107  Hexagon::PacketIterator(MCII, MCI, nullptr));
108 }
109 
112  assert(isBundle(MCI));
114 }
115 
118  return (MCI.size() - bundleInstructionsOffset);
119  else
120  return (1);
121 }
122 
123 namespace {
124 bool canonicalizePacketImpl(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
125  MCContext &Context, MCInst &MCB,
127  // Check the bundle for errors.
128  bool CheckOk = Check ? Check->check(false) : true;
129  if (!CheckOk)
130  return false;
131 
132  MCInst OrigMCB = MCB;
133 
134  // Examine the packet and convert pairs of instructions to compound
135  // instructions when possible.
137  HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
138  HexagonMCShuffle(Context, false, MCII, STI, MCB);
139 
140  const SmallVector<DuplexCandidate, 8> possibleDuplexes =
141  (STI.getFeatureBits()[Hexagon::FeatureDuplex])
144 
145  // Examine the packet and convert pairs of instructions to duplex
146  // instructions when possible.
147  HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
148 
149  // Examines packet and pad the packet, if needed, when an
150  // end-loop is in the bundle.
152 
153  // If compounding and duplexing didn't reduce the size below
154  // 4 or less we have a packet that is too big.
156  if (Check)
157  Check->reportError("invalid instruction packet: out of slots");
158  return false;
159  }
160  // Check the bundle for errors.
161  CheckOk = Check ? Check->check(true) : true;
162  if (!CheckOk)
163  return false;
164 
165  HexagonMCShuffle(Context, true, MCII, STI, MCB);
166 
167  return true;
168 }
169 } // namespace
170 
172  MCSubtargetInfo const &STI,
173  MCContext &Context, MCInst &MCB,
175  bool AttemptCompatibility) {
176  auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
177  if (!AttemptCompatibility || ArchSTI == nullptr)
178  return canonicalizePacketImpl(MCII, STI, Context, MCB, Check);
179 
180  const MCRegisterInfo *RI = Context.getRegisterInfo();
181  HexagonMCChecker DefaultCheck(Context, MCII, STI, MCB, *RI, false);
182  HexagonMCChecker *BaseCheck = (Check == nullptr) ? &DefaultCheck : Check;
183  HexagonMCChecker PerfCheck(*BaseCheck, STI, false);
184  if (canonicalizePacketImpl(MCII, STI, Context, MCB, &PerfCheck))
185  return true;
186 
187  HexagonMCChecker ArchCheck(*BaseCheck, *ArchSTI, true);
188  return canonicalizePacketImpl(MCII, *ArchSTI, Context, MCB, &ArchCheck);
189 }
190 
192  MCInst const &Inst,
193  MCOperand const &MO) {
195  HexagonMCInstrInfo::isExtended(MCII, Inst));
196 
197  MCInst XMI;
198  XMI.setOpcode(Hexagon::A4_ext);
199  if (MO.isImm())
200  XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
201  else if (MO.isExpr())
203  else
204  llvm_unreachable("invalid extendable operand");
205  return XMI;
206 }
207 
209  MCInst const &inst0,
210  MCInst const &inst1) {
211  assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
212  MCInst *duplexInst = new (Context) MCInst;
213  duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
214 
215  MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
216  MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
217  duplexInst->addOperand(MCOperand::createInst(SubInst0));
218  duplexInst->addOperand(MCOperand::createInst(SubInst1));
219  return duplexInst;
220 }
221 
223  size_t Index) {
224  assert(Index <= bundleSize(MCB));
225  if (Index == 0)
226  return nullptr;
227  MCInst const *Inst =
228  MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
229  if (isImmext(*Inst))
230  return Inst;
231  return nullptr;
232 }
233 
235  MCInstrInfo const &MCII, MCInst &MCB,
236  MCInst const &MCI) {
237  if (isConstExtended(MCII, MCI))
238  addConstExtender(Context, MCII, MCB, MCI);
239 }
240 
242  MCInst const &MCI) {
246 }
247 
249  MCInst const &MCI) {
250  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
251  return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
253 }
254 
256  MCInst const &MCI) {
257  return MCII.get(MCI.getOpcode());
258 }
259 
261  using namespace Hexagon;
262 
263  switch (Reg) {
264  default:
265  llvm_unreachable("unknown duplex register");
266  // Rs Rss
267  case R0:
268  case D0:
269  return 0;
270  case R1:
271  case D1:
272  return 1;
273  case R2:
274  case D2:
275  return 2;
276  case R3:
277  case D3:
278  return 3;
279  case R4:
280  case D8:
281  return 4;
282  case R5:
283  case D9:
284  return 5;
285  case R6:
286  case D10:
287  return 6;
288  case R7:
289  case D11:
290  return 7;
291  case R16:
292  return 8;
293  case R17:
294  return 9;
295  case R18:
296  return 10;
297  case R19:
298  return 11;
299  case R20:
300  return 12;
301  case R21:
302  return 13;
303  case R22:
304  return 14;
305  case R23:
306  return 15;
307  }
308 }
309 
311  const auto &HExpr = cast<HexagonMCExpr>(Expr);
312  assert(HExpr.getExpr());
313  return *HExpr.getExpr();
314 }
315 
317  MCInst const &MCI) {
318  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
320 }
321 
322 MCOperand const &
324  MCInst const &MCI) {
325  unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
326  MCOperand const &MO = MCI.getOperand(O);
327 
329  HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
330  (MO.isImm() || MO.isExpr()));
331  return (MO);
332 }
333 
335  MCInst const &MCI) {
336  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
338 }
339 
341  MCInst const &MCI) {
342  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
344 }
345 
347  MCInst const &MCI) {
348  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
350 }
351 
352 /// Return the maximum value of an extendable operand.
354  MCInst const &MCI) {
356  HexagonMCInstrInfo::isExtended(MCII, MCI));
357 
358  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
359  return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
360  return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
361 }
362 
363 /// Return the minimum value of an extendable operand.
365  MCInst const &MCI) {
367  HexagonMCInstrInfo::isExtended(MCII, MCI));
368 
369  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
370  return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
371  return 0;
372 }
373 
375  MCInst const &MCI) {
376  return MCII.getName(MCI.getOpcode());
377 }
378 
380  MCInst const &MCI) {
381  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
383 }
384 
386  MCInst const &MCI) {
387  if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
388  // VTMP doesn't actually exist in the encodings for these 184
389  // 3 instructions so go ahead and create it here.
390  static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
391  return (MCO);
392  } else {
393  unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
394  MCOperand const &MCO = MCI.getOperand(O);
395 
397  HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
398  MCO.isReg());
399  return (MCO);
400  }
401 }
402 
403 /// Return the new value or the newly produced value.
405  MCInst const &MCI) {
406  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
408 }
409 
410 MCOperand const &
412  MCInst const &MCI) {
413  unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
414  MCOperand const &MCO = MCI.getOperand(O);
415 
417  HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
418  MCO.isReg());
419  return (MCO);
420 }
421 
422 /// Return the Hexagon ISA class for the insn.
424  MCInst const &MCI) {
425  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
426  return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
427 }
428 
429 /// Return the resources used by this instruction
431  MCSubtargetInfo const &STI,
432  MCInst const &MCI) {
433 
435  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
436  int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage;
437 
438  // HVX resources used are currenty located at the second to last stage.
439  // This could also be done with a linear search of the stages looking for:
440  // CVI_ALL, CVI_MPY01, CVI_XLSHF, CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE,
441  // CVI_ZW
442  unsigned Stage = II[SchedClass].LastStage - 1;
443 
444  if (Size < 2)
445  return 0;
446  return ((Stage + HexagonStages)->getUnits());
447 }
448 
449 /// Return the slots this instruction can execute out of
451  MCSubtargetInfo const &STI,
452  MCInst const &MCI) {
454  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
455  return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
456 }
457 
458 /// Return the slots this instruction consumes in addition to
459 /// the slot(s) it can execute out of
460 
462  MCSubtargetInfo const &STI,
463  MCInst const &MCI) {
465  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
466  unsigned Slots = 0;
467 
468  // FirstStage are slots that this instruction can execute in.
469  // FirstStage+1 are slots that are also consumed by this instruction.
470  // For example: vmemu can only execute in slot 0 but also consumes slot 1.
471  for (unsigned Stage = II[SchedClass].FirstStage + 1;
472  Stage < II[SchedClass].LastStage; ++Stage) {
473  unsigned Units = (Stage + HexagonStages)->getUnits();
474  if (Units > HexagonGetLastSlot())
475  break;
476  // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
477  Slots |= Units;
478  }
479 
480  // if 0 is returned, then no additional slots are consumed by this inst.
481  return Slots;
482 }
483 
484 bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
486  return false;
487 
488  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
489  if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
490  return true;
491  }
492 
493  return false;
494 }
495 
496 bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
497  return extenderForIndex(MCB, Index) != nullptr;
498 }
499 
502  return false;
503 
504  for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
505  if (isImmext(*I.getInst()))
506  return true;
507  }
508 
509  return false;
510 }
511 
512 /// Return whether the insn produces a value.
514  MCInst const &MCI) {
515  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
517 }
518 
519 /// Return whether the insn produces a second value.
521  MCInst const &MCI) {
522  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
524 }
525 
526 MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
527  assert(isBundle(MCB));
529  return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
530 }
531 
532 /// Return where the instruction is an accumulator.
534  MCInst const &MCI) {
535  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
537 }
538 
540  auto Result = Hexagon::BUNDLE == MCI.getOpcode();
541  assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
542  return Result;
543 }
544 
546  MCInst const &MCI) {
547  if (HexagonMCInstrInfo::isExtended(MCII, MCI))
548  return true;
549  if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
550  return false;
552  if (isa<HexagonMCExpr>(MO.getExpr()) &&
554  return true;
555  // Branch insns are handled as necessary by relaxation.
556  if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
558  HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
561  return false;
562  // Otherwise loop instructions and other CR insts are handled by relaxation
563  else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
564  (MCI.getOpcode() != Hexagon::C4_addipc))
565  return false;
566 
567  assert(!MO.isImm());
568  if (isa<HexagonMCExpr>(MO.getExpr()) &&
570  return false;
571  int64_t Value;
572  if (!MO.getExpr()->evaluateAsAbsolute(Value))
573  return true;
574  int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
575  int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
576  return (MinValue > Value || Value > MaxValue);
577 }
578 
579 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
580  return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
581  !HexagonMCInstrInfo::isPrefix(MCII, MCI);
582 }
583 
584 bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
585  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
587 }
588 
590  MCInst const &MCI) {
591  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
593 }
594 
596  MCInst const &MCI) {
597  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
599 }
600 
602  MCInst const &MCI) {
603  return (getType(MCII, MCI) == HexagonII::TypeCJ);
604 }
605 
606 bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
607  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
609 }
610 
612  return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
613  (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
614 }
615 
616 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
618 }
619 
621  MCInst const &MCI) {
622  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
624 }
625 
627  MCInst const &MCI) {
628  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
630 }
631 
632 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
633  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
634  return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
635 }
636 
637 bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
638  const uint64_t V = getType(MCII, MCI);
640 }
641 
643  return MCI.getOpcode() == Hexagon::A4_ext;
644 }
645 
647  assert(isBundle(MCI));
648  int64_t Flags = MCI.getOperand(0).getImm();
649  return (Flags & innerLoopMask) != 0;
650 }
651 
653  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
654 }
655 
657  return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
658  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
659 }
660 
661 /// Return whether the insn expects newly produced value.
663  MCInst const &MCI) {
664  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
666 }
667 
669  MCInst const &MCI) {
670  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
672 }
673 
674 /// Return whether the operand is extendable.
676  MCInst const &MCI, unsigned short O) {
677  return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
678 }
679 
681  assert(isBundle(MCI));
682  int64_t Flags = MCI.getOperand(0).getImm();
683  return (Flags & outerLoopMask) != 0;
684 }
685 
686 bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) {
687  return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) ||
688  (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
689 }
690 
692  return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
693 }
694 
695 bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) {
696  return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31);
697 }
698 
699 std::pair<unsigned, unsigned>
701  assert(IsVecRegPair(VecRegPair) &&
702  "VecRegPair must be a vector register pair");
703 
704  const bool IsRev = IsReverseVecRegPair(VecRegPair);
705  const unsigned PairIndex =
706  2 * (IsRev ? VecRegPair - Hexagon::WR0 : VecRegPair - Hexagon::W0);
707 
708  return IsRev ? std::make_pair(PairIndex, PairIndex + 1)
709  : std::make_pair(PairIndex + 1, PairIndex);
710 }
711 
713  unsigned Consumer) {
714  if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) {
715  const unsigned ProdPairIndex = IsReverseVecRegPair(Producer)
716  ? Producer - Hexagon::WR0
717  : Producer - Hexagon::W0;
718  const unsigned ConsumerSingleIndex = (Consumer - Hexagon::V0) >> 1;
719 
720  return ConsumerSingleIndex == ProdPairIndex;
721  }
722  return false;
723 }
724 
726  MCInst const &MCI) {
727  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
729 }
730 
731 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
733 }
734 
736  MCInst const &MCI) {
737  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
739 }
740 
741 /// Return whether the insn is newly predicated.
743  MCInst const &MCI) {
744  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
746 }
747 
749  MCInst const &MCI) {
750  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
751  return (
753 }
754 
756  auto &PredRegClass = MRI.getRegClass(Hexagon::PredRegsRegClassID);
757  return PredRegClass.contains(Reg);
758 }
759 
761  MCInst const &Inst, unsigned I) {
762  MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);
763 
764  return Inst.getOperand(I).isReg() &&
765  Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID;
766 }
767 
768 /// Return whether the insn can be packaged only with A and X-type insns.
769 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
770  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
772 }
773 
774 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
776  MCInst const &MCI) {
777  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
778  return ((F >> HexagonII::RestrictSlot1AOKPos) &
780 }
781 
783  MCInst const &MCI) {
784  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
787 }
788 
789 /// Return whether the insn is solo, i.e., cannot be in a packet.
790 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
791  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
792  return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
793 }
794 
796  assert(isBundle(MCI));
797  auto Flags = MCI.getOperand(0).getImm();
798  return (Flags & memReorderDisabledMask) != 0;
799 }
800 
802  switch (MCI.getOpcode()) {
803  default:
804  return false;
805  case Hexagon::SA1_addi:
806  case Hexagon::SA1_addrx:
807  case Hexagon::SA1_addsp:
808  case Hexagon::SA1_and1:
809  case Hexagon::SA1_clrf:
810  case Hexagon::SA1_clrfnew:
811  case Hexagon::SA1_clrt:
812  case Hexagon::SA1_clrtnew:
813  case Hexagon::SA1_cmpeqi:
814  case Hexagon::SA1_combine0i:
815  case Hexagon::SA1_combine1i:
816  case Hexagon::SA1_combine2i:
817  case Hexagon::SA1_combine3i:
818  case Hexagon::SA1_combinerz:
819  case Hexagon::SA1_combinezr:
820  case Hexagon::SA1_dec:
821  case Hexagon::SA1_inc:
822  case Hexagon::SA1_seti:
823  case Hexagon::SA1_setin1:
824  case Hexagon::SA1_sxtb:
825  case Hexagon::SA1_sxth:
826  case Hexagon::SA1_tfr:
827  case Hexagon::SA1_zxtb:
828  case Hexagon::SA1_zxth:
829  case Hexagon::SL1_loadri_io:
830  case Hexagon::SL1_loadrub_io:
831  case Hexagon::SL2_deallocframe:
832  case Hexagon::SL2_jumpr31:
833  case Hexagon::SL2_jumpr31_f:
834  case Hexagon::SL2_jumpr31_fnew:
835  case Hexagon::SL2_jumpr31_t:
836  case Hexagon::SL2_jumpr31_tnew:
837  case Hexagon::SL2_loadrb_io:
838  case Hexagon::SL2_loadrd_sp:
839  case Hexagon::SL2_loadrh_io:
840  case Hexagon::SL2_loadri_sp:
841  case Hexagon::SL2_loadruh_io:
842  case Hexagon::SL2_return:
843  case Hexagon::SL2_return_f:
844  case Hexagon::SL2_return_fnew:
845  case Hexagon::SL2_return_t:
846  case Hexagon::SL2_return_tnew:
847  case Hexagon::SS1_storeb_io:
848  case Hexagon::SS1_storew_io:
849  case Hexagon::SS2_allocframe:
850  case Hexagon::SS2_storebi0:
851  case Hexagon::SS2_storebi1:
852  case Hexagon::SS2_stored_sp:
853  case Hexagon::SS2_storeh_io:
854  case Hexagon::SS2_storew_sp:
855  case Hexagon::SS2_storewi0:
856  case Hexagon::SS2_storewi1:
857  return true;
858  }
859 }
860 
861 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
862  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
864 }
865 
866 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
867  auto Sentinel = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
868  << 8;
869  if (MCI.size() <= Index)
870  return Sentinel;
871  MCOperand const &MCO = MCI.getOperand(Index);
872  if (!MCO.isExpr())
873  return Sentinel;
874  int64_t Value;
875  if (!MCO.getExpr()->evaluateAsAbsolute(Value))
876  return Sentinel;
877  return Value;
878 }
879 
880 void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
881  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
882  HExpr.setMustExtend(Val);
883 }
884 
886  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
887  return HExpr.mustExtend();
888 }
889 void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
890  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
891  HExpr.setMustNotExtend(Val);
892 }
894  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
895  return HExpr.mustNotExtend();
896 }
897 void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
898  HexagonMCExpr &HExpr =
899  const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
900  HExpr.setS27_2_reloc(Val);
901 }
903  HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
904  if (!HExpr)
905  return false;
906  return HExpr->s27_2_reloc();
907 }
908 
910  const bool IsTiny = STI.getFeatureBits()[Hexagon::ProcTinyCore];
911 
912  return IsTiny ? (HEXAGON_PACKET_SIZE - 1) : HEXAGON_PACKET_SIZE;
913 }
914 
916  return llvm::StringSwitch<unsigned>(CPU)
917  .Case("hexagonv67t", 3)
918  .Default(4);
919 }
920 
922  MCInst Nop;
923  Nop.setOpcode(Hexagon::A2_nop);
924  assert(isBundle(MCB));
925  while (LoopNeedsPadding(MCB))
927 }
928 
931  if (!isPredicated(MCII, MCI))
932  return {0, 0, false};
933  MCInstrDesc const &Desc = getDesc(MCII, MCI);
934  for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
935  if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
936  return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
937  return {0, 0, false};
938 }
939 
941  MCInst const &MCI) {
942  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
944 }
945 
946 bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
947  switch (MCI.getOpcode()) {
948  default:
949  return false;
950  case Hexagon::V6_vgathermh:
951  case Hexagon::V6_vgathermhq:
952  case Hexagon::V6_vgathermhw:
953  case Hexagon::V6_vgathermhwq:
954  case Hexagon::V6_vgathermw:
955  case Hexagon::V6_vgathermwq:
956  return true;
957  }
958  return false;
959 }
960 
961 bool HexagonMCInstrInfo::hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI) {
962  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
964 }
965 
967  MCInst const &MCI) {
968  const unsigned OpCode = MCI.getOpcode();
969  const bool IsTiny = STI.getFeatureBits() [Hexagon::ProcTinyCore];
970  const bool NoSlotReqd = Hexagon::A4_ext == OpCode ||
971  (IsTiny && Hexagon::A2_nop == OpCode) ||
972  (IsTiny && Hexagon::J4_hintjumpr == OpCode);
973 
974  return !NoSlotReqd;
975 }
976 
978  MCSubtargetInfo const &STI,
979  MCInst const &MCI) {
980  unsigned slotsUsed = 0;
981  for (auto HMI : bundleInstructions(MCI)) {
982  MCInst const &MCI = *HMI.getInst();
983  if (!requiresSlot(STI, MCI))
984  continue;
985  if (isDuplex(MCII, MCI))
986  slotsUsed += 2;
987  else
988  ++slotsUsed;
989  }
990  return slotsUsed;
991 }
992 
994  DuplexCandidate Candidate) {
995  assert(Candidate.packetIndexI < MCB.size());
996  assert(Candidate.packetIndexJ < MCB.size());
997  assert(isBundle(MCB));
998  MCInst *Duplex =
999  deriveDuplex(Context, Candidate.iClass,
1000  *MCB.getOperand(Candidate.packetIndexJ).getInst(),
1001  *MCB.getOperand(Candidate.packetIndexI).getInst());
1002  assert(Duplex != nullptr);
1003  MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
1004  MCB.erase(MCB.begin() + Candidate.packetIndexJ);
1005 }
1006 
1008  assert(isBundle(MCI));
1009  MCOperand &Operand = MCI.getOperand(0);
1010  Operand.setImm(Operand.getImm() | innerLoopMask);
1011 }
1012 
1014  assert(isBundle(MCI));
1015  MCOperand &Operand = MCI.getOperand(0);
1016  Operand.setImm(Operand.getImm() | memReorderDisabledMask);
1018 }
1019 
1021  assert(isBundle(MCI));
1022  MCOperand &Operand = MCI.getOperand(0);
1023  Operand.setImm(Operand.getImm() | outerLoopMask);
1024 }
1025 
1026 unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
1027  unsigned Producer,
1028  unsigned Producer2) {
1029  // If we're a single vector consumer of a double producer, set subreg bit
1030  // based on if we're accessing the lower or upper register component
1031  if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer))
1032  return (Consumer - Hexagon::V0) & 0x1;
1033  if (Producer2 != Hexagon::NoRegister)
1034  return Consumer == Producer;
1035  return 0;
1036 }
1037 
1039  return (
1044 }
1045 
1047  MCSubtargetInfo const &STI,
1048  MCInst const &I) {
1050  MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
1051  return (Desc.isBranch() || Desc.isCall() || Desc.isReturn());
1052 }
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
llvm::HexagonII::ExtentSignedMask
@ ExtentSignedMask
Definition: HexagonBaseInfo.h:109
HexagonMCTargetDesc.h
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::HexagonII::RestrictSlot1AOKMask
@ RestrictSlot1AOKMask
Definition: HexagonBaseInfo.h:64
llvm::HexagonII::CofRelax2Mask
@ CofRelax2Mask
Definition: HexagonBaseInfo.h:122
llvm::HexagonMCInstrInfo::mustNotExtend
bool mustNotExtend(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:893
llvm::HexagonMCInstrInfo::setMustExtend
void setMustExtend(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:880
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:255
llvm::HexagonII::SoloMask
@ SoloMask
Definition: HexagonBaseInfo.h:58
llvm::DuplexCandidate
Definition: HexagonMCInstrInfo.h:34
llvm::HexagonMCInstrInfo::minConstant
int64_t minConstant(MCInst const &MCI, size_t Index)
Definition: HexagonMCInstrInfo.cpp:866
llvm::HexagonMCInstrInfo::isAccumulator
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
Definition: HexagonMCInstrInfo.cpp:533
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:280
llvm::HexagonMCInstrInfo::setMustNotExtend
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:889
llvm::HexagonII::PredicatedPos
@ PredicatedPos
Definition: HexagonBaseInfo.h:67
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::WebAssembly::Nop
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
Definition: WebAssemblyMCTargetDesc.h:133
llvm::HexagonII::hasNewValueMask2
@ hasNewValueMask2
Definition: HexagonBaseInfo.h:144
llvm::HexagonMCInstrInfo::isPredReg
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:755
llvm::HexagonII::CofRelax1Mask
@ CofRelax1Mask
Definition: HexagonBaseInfo.h:120
llvm::HexagonII::TypeCR
@ TypeCR
Definition: HexagonDepITypes.h:23
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCInstrDesc::isBranch
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:304
llvm::HexagonMCInstrInfo::isRestrictSlot1AOK
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
Definition: HexagonMCInstrInfo.cpp:775
llvm::HexagonDisableCompound
cl::opt< bool > HexagonDisableCompound
llvm::MCSubtargetInfo::getSchedModel
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Definition: MCSubtargetInfo.h:163
llvm::HexagonMCInstrInfo::IsABranchingInst
bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &I)
Definition: HexagonMCInstrInfo.cpp:1046
llvm::HexagonMCInstrInfo::getDuplexRegisterNumbering
unsigned getDuplexRegisterNumbering(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:260
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
llvm::MCInstrDesc::isPseudo
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MCInstrDesc.h:266
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:183
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
llvm::HexagonMCInstrInfo::isCofMax1
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:584
llvm::HexagonMCInstrInfo::hasDuplex
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:484
llvm::HexagonII::hasNewValueMask
@ hasNewValueMask
Definition: HexagonBaseInfo.h:81
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::HexagonMCInstrInfo::isCofRelax2
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:595
llvm::MCInstrDesc::getSchedClass
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:618
llvm::HexagonII::NewValueOpMask
@ NewValueOpMask
Definition: HexagonBaseInfo.h:84
ErrorHandling.h
llvm::HexagonII::TypeEXTENDER
@ TypeEXTENDER
Definition: HexagonDepITypes.h:52
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::HexagonII::AccumulatorMask
@ AccumulatorMask
Definition: HexagonBaseInfo.h:151
llvm::HexagonMCInstrInfo::getCVIResources
unsigned getCVIResources(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the resources used by this instruction.
Definition: HexagonMCInstrInfo.cpp:430
llvm::HexagonMCShuffle
bool HexagonMCShuffle(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
Definition: HexagonMCShuffler.cpp:103
llvm::HexagonMCExpr::mustExtend
bool mustExtend() const
Definition: HexagonMCExpr.cpp:90
llvm::Hexagon::PacketIterator::operator*
const MCInst & operator*() const
Definition: HexagonMCInstrInfo.cpp:71
llvm::HexagonMCInstrInfo::getNewValueOp
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:379
R4
#define R4(n)
llvm::HexagonMCInstrInfo::hasTmpDst
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:946
llvm::HexagonMCInstrInfo::getMemAccessSize
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:241
llvm::HexagonMCInstrInfo::getExtentAlignment
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:334
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::HexagonMCInstrInfo::addConstExtender
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:87
llvm::HexagonII::ExtentBitsPos
@ ExtentBitsPos
Definition: HexagonBaseInfo.h:111
llvm::HexagonMCInstrInfo::hasExtenderForIndex
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:496
llvm::HexagonMCInstrInfo::PredicateInfo::isPredicated
bool isPredicated() const
Definition: HexagonMCInstrInfo.cpp:35
llvm::HexagonMCInstrInfo::isImmext
bool isImmext(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:642
llvm::HexagonMCInstrInfo::extendIfNeeded
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:234
llvm::HexagonMCInstrInfo::isSubInstruction
bool isSubInstruction(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:801
llvm::HexagonII::getMemAccessSizeInBytes
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
Definition: HexagonBaseInfo.h:270
llvm::HexagonII::hasNewValuePos2
@ hasNewValuePos2
Definition: HexagonBaseInfo.h:143
llvm::HexagonMCInstrInfo::extenderForIndex
const MCInst * extenderForIndex(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:222
llvm::HexagonII::ExtentAlignPos
@ ExtentAlignPos
Definition: HexagonBaseInfo.h:114
llvm::HexagonMCInstrInfo::setInnerLoop
void setInnerLoop(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:1007
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::HexagonMCInstrInfo::replaceDuplex
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
Definition: HexagonMCInstrInfo.cpp:993
llvm::HexagonMCInstrInfo::prefersSlot3
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:940
llvm::HexagonMCExpr
Definition: HexagonMCExpr.h:15
llvm::HexagonMCInstrInfo::isCofRelax1
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:589
llvm::Hexagon_MC::getArchSubtarget
const MCSubtargetInfo * getArchSubtarget(MCSubtargetInfo const *STI)
Definition: HexagonMCTargetDesc.cpp:431
HexagonBaseInfo.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::HexagonMCInstrInfo::getOtherReservedSlots
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of.
Definition: HexagonMCInstrInfo.cpp:461
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::HexagonMCInstrInfo::isMemReorderDisabled
bool isMemReorderDisabled(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:795
llvm::HexagonII::SoloAXMask
@ SoloAXMask
Definition: HexagonBaseInfo.h:61
llvm::HexagonII::NVStorePos
@ NVStorePos
Definition: HexagonBaseInfo.h:89
llvm::HexagonMCInstrInfo::isDblRegForSubInst
bool isDblRegForSubInst(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:611
llvm::HexagonMCInstrInfo::setS27_2_reloc
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:897
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1366
R2
#define R2(n)
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:94
llvm::HexagonII::TypeMask
@ TypeMask
Definition: HexagonBaseInfo.h:54
llvm::HexagonII::MemAccessSize
MemAccessSize
Definition: HexagonBaseInfo.h:40
llvm::HexagonMCInstrInfo::PredicateInfo
Definition: HexagonMCInstrInfo.h:335
HexagonMCShuffler.h
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
llvm::InstrItinerary
An itinerary represents the scheduling information for an instruction.
Definition: MCInstrItineraries.h:98
MCInstrItineraries.h
llvm::HexagonII::RestrictSlot1AOKPos
@ RestrictSlot1AOKPos
Definition: HexagonBaseInfo.h:63
HEXAGON_PRESHUFFLE_PACKET_SIZE
#define HEXAGON_PRESHUFFLE_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:43
llvm::HexagonMCInstrInfo::isPredicatedTrue
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:748
llvm::DXIL::OpCode
OpCode
Definition: DXILConstants.h:18
llvm::ARM_MC::isPredicated
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
Definition: ARMMCTargetDesc.cpp:169
HexagonMCChecker.h
llvm::HexagonII::CofRelax1Pos
@ CofRelax1Pos
Definition: HexagonBaseInfo.h:119
llvm::HexagonMCInstrInfo::s27_2_reloc
bool s27_2_reloc(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:902
llvm::HexagonMCInstrInfo::hasImmExt
bool hasImmExt(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:500
llvm::HexagonMCInstrInfo::requiresSlot
bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:966
llvm::HexagonII::NVStoreMask
@ NVStoreMask
Definition: HexagonBaseInfo.h:90
HexagonMCInstrInfo.h
llvm::HexagonMCInstrInfo::setMemReorderDisabled
void setMemReorderDisabled(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:1013
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition: HexagonMCInstrInfo.cpp:520
llvm::HexagonII::CofRelax2Pos
@ CofRelax2Pos
Definition: HexagonBaseInfo.h:121
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition: HexagonMCInstrInfo.cpp:662
llvm::HexagonMCInstrInfo::isPredicated
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:725
llvm::MCOperand::getInst
const MCInst * getInst() const
Definition: MCInst.h:124
llvm::HexagonMCExpr::s27_2_reloc
bool s27_2_reloc() const
Definition: HexagonMCExpr.cpp:97
MCContext.h
llvm::HexagonMCInstrInfo::isVector
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:861
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:539
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
Check
#define Check(C,...)
Definition: Lint.cpp:170
llvm::HexagonMCInstrInfo::predicateInfo
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:930
llvm::HexagonII::MemAccesSizeMask
@ MemAccesSizeMask
Definition: HexagonBaseInfo.h:132
MCInst.h
llvm::HexagonMCInstrInfo::getName
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:374
HexagonMCExpr.h
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::HexagonMCInstrInfo::isCanon
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:579
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:103
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::HexagonMCInstrInfo::memReorderDisabledMask
constexpr int64_t memReorderDisabledMask
Definition: HexagonMCInstrInfo.h:77
llvm::HexagonII::hasNewValuePos
@ hasNewValuePos
Definition: HexagonBaseInfo.h:80
llvm::HexagonMCInstrInfo::getExtentBits
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:340
llvm::HexagonMCInstrInfo::hasHvxTmp
bool hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:961
llvm::Hexagon::PacketIterator::operator==
bool operator==(PacketIterator const &Other) const
Definition: HexagonMCInstrInfo.cpp:77
llvm::HexagonMCInstrInfo::isRestrictNoSlot1Store
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:782
llvm::MCInst::end
iterator end()
Definition: MCInst.h:221
llvm::HexagonII::CVINewPos
@ CVINewPos
Definition: HexagonBaseInfo.h:160
llvm::HexagonMCInstrInfo::isConstExtended
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:545
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::HexagonMCInstrInfo::hasNewValue
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
Definition: HexagonMCInstrInfo.cpp:513
llvm::HexagonMCInstrInfo::IsVecRegSingle
bool IsVecRegSingle(unsigned VecReg)
Definition: HexagonMCInstrInfo.cpp:695
llvm::DuplexCandidate::iClass
unsigned iClass
Definition: HexagonMCInstrInfo.h:36
llvm::HexagonMCInstrInfo::LoopNeedsPadding
bool LoopNeedsPadding(MCInst const &MCB)
Definition: HexagonMCInstrInfo.cpp:1038
llvm::HexagonMCInstrInfo::addConstant
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
Definition: HexagonMCInstrInfo.cpp:82
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::MCInst::erase
void erase(iterator I)
Definition: MCInst.h:216
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:169
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MCOperand::setInst
void setInst(const MCInst *Val)
Definition: MCInst.h:129
llvm::HexagonMCInstrInfo::getDuplexPossibilties
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
Definition: HexagonMCDuplexInfo.cpp:1028
llvm::HexagonII::ExtendedMask
@ ExtendedMask
Definition: HexagonBaseInfo.h:103
llvm::HexagonII::PrefersSlot3Pos
@ PrefersSlot3Pos
Definition: HexagonBaseInfo.h:154
llvm::HexagonMCInstrInfo::isIntRegForSubInst
bool isIntRegForSubInst(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:656
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::HexagonMCInstrInfo::isOpExtendable
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
Definition: HexagonMCInstrInfo.cpp:675
llvm::HexagonMCInstrInfo::mustExtend
bool mustExtend(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:885
llvm::HexagonMCInstrInfo::deriveSubInst
MCInst deriveSubInst(MCInst const &Inst)
Definition: HexagonMCDuplexInfo.cpp:696
llvm::HexagonMCInstrInfo::isSoloAX
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
Definition: HexagonMCInstrInfo.cpp:769
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:239
llvm::HexagonMCInstrInfo::packetSize
unsigned packetSize(StringRef CPU)
Definition: HexagonMCInstrInfo.cpp:915
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::HexagonMCInstrInfo::isCVINew
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:606
uint64_t
llvm::HexagonMCInstrInfo::isCompound
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:601
llvm::Hexagon::PacketIterator
Definition: HexagonMCInstrInfo.h:44
llvm::HexagonMCInstrInfo::tryCompound
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
Definition: HexagonMCCompound.cpp:401
llvm::HexagonII::PredicatedNewPos
@ PredicatedNewPos
Definition: HexagonBaseInfo.h:71
llvm::MCInstrDesc::isCall
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:285
llvm::HexagonMCInstrInfo::SubregisterBit
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
Definition: HexagonMCInstrInfo.cpp:1026
llvm::HexagonII::PrefersSlot3Mask
@ PrefersSlot3Mask
Definition: HexagonBaseInfo.h:155
llvm::HexagonII::HasHvxTmpPos
@ HasHvxTmpPos
Definition: HexagonBaseInfo.h:157
llvm::HexagonMCInstrInfo::canonicalizePacket
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)
Definition: HexagonMCInstrInfo.cpp:171
llvm::HexagonII::RestrictNoSlot1StorePos
@ RestrictNoSlot1StorePos
Definition: HexagonBaseInfo.h:124
llvm::MCInst::begin
iterator begin()
Definition: MCInst.h:219
llvm::HexagonII::ExtentAlignMask
@ ExtentAlignMask
Definition: HexagonBaseInfo.h:115
llvm::DuplexCandidate::packetIndexJ
unsigned packetIndexJ
Definition: HexagonMCInstrInfo.h:36
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::InstrItinerary::FirstStage
uint16_t FirstStage
Index of first stage in itinerary.
Definition: MCInstrItineraries.h:100
llvm::HexagonII::ExtendedPos
@ ExtendedPos
Definition: HexagonBaseInfo.h:102
llvm::HexagonMCExpr::setMustNotExtend
void setMustNotExtend(bool Val=true)
Definition: HexagonMCExpr.cpp:91
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:616
llvm::HexagonGetLastSlot
unsigned HexagonGetLastSlot()
Definition: HexagonMCTargetDesc.cpp:159
llvm::Hexagon::PacketIterator::operator++
PacketIterator & operator++()
Definition: HexagonMCInstrInfo.cpp:50
llvm::HexagonII::PredicatedFalsePos
@ PredicatedFalsePos
Definition: HexagonBaseInfo.h:69
llvm::HexagonII::PredicateLateMask
@ PredicateLateMask
Definition: HexagonBaseInfo.h:74
llvm::HexagonMCInstrInfo::deriveExtender
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
Definition: HexagonMCInstrInfo.cpp:191
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::HexagonMCInstrInfo::IsReverseVecRegPair
bool IsReverseVecRegPair(unsigned VecReg)
Definition: HexagonMCInstrInfo.cpp:691
llvm::HexagonMCInstrInfo::outerLoopMask
constexpr int64_t outerLoopMask
Definition: HexagonMCInstrInfo.h:72
llvm::HexagonII::PredicatedFalseMask
@ PredicatedFalseMask
Definition: HexagonBaseInfo.h:70
llvm::HexagonMCInstrInfo::isIntReg
bool isIntReg(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:652
llvm::HexagonMCInstrInfo::innerLoopMask
constexpr int64_t innerLoopMask
Definition: HexagonMCInstrInfo.h:69
llvm::HexagonMCInstrInfo::IsVecRegPair
bool IsVecRegPair(unsigned VecReg)
Definition: HexagonMCInstrInfo.cpp:686
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::HexagonII::PredicatedNewMask
@ PredicatedNewMask
Definition: HexagonBaseInfo.h:72
llvm::MCInst::size
size_t size() const
Definition: MCInst.h:218
llvm::MCOperand::setImm
void setImm(int64_t Val)
Definition: MCInst.h:85
llvm::HexagonMCInstrInfo::isFloat
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
Definition: HexagonMCInstrInfo.cpp:632
isBranch
static bool isBranch(unsigned Opcode)
Definition: R600InstrInfo.cpp:642
llvm::HexagonII::SoloPos
@ SoloPos
Definition: HexagonBaseInfo.h:57
R6
#define R6(n)
llvm::MCInstrInfo::getName
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:69
llvm::HexagonII::RestrictNoSlot1StoreMask
@ RestrictNoSlot1StoreMask
Definition: HexagonBaseInfo.h:125
llvm::HexagonII::MemAccessSizePos
@ MemAccessSizePos
Definition: HexagonBaseInfo.h:131
llvm::HexagonMCInstrInfo::getNewValueOp2
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
Definition: HexagonMCInstrInfo.cpp:404
llvm::HexagonMCInstrInfo::isOuterLoop
bool isOuterLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:680
llvm::HexagonMCInstrInfo::isPrefix
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:731
llvm::HexagonMCInstrInfo::isExtentSigned
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:346
llvm::HexagonII::TypeDUPLEX
@ TypeDUPLEX
Definition: HexagonDepITypes.h:50
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::HexagonII::CofMax1Pos
@ CofMax1Pos
Definition: HexagonBaseInfo.h:117
llvm::HexagonStages
const InstrStage HexagonStages[]
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::HexagonMCInstrInfo::getNewValueOperand
const MCOperand & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:385
llvm::HexagonII::TypeCJ
@ TypeCJ
Definition: HexagonDepITypes.h:22
llvm::HexagonMCExpr::setS27_2_reloc
void setS27_2_reloc(bool Val=true)
Definition: HexagonMCExpr.cpp:98
llvm::HexagonII::FPMask
@ FPMask
Definition: HexagonBaseInfo.h:140
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::HexagonMCInstrInfo::getExtendableOp
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:316
llvm::HexagonMCInstrInfo::setOuterLoop
void setOuterLoop(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:1020
llvm::HexagonMCInstrInfo::getAddrMode
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:248
llvm::HexagonMCExpr::mustNotExtend
bool mustNotExtend() const
Definition: HexagonMCExpr.cpp:95
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
HEXAGON_PACKET_INNER_SIZE
#define HEXAGON_PACKET_INNER_SIZE
Definition: HexagonMCTargetDesc.h:39
llvm::HexagonII::PredicateLatePos
@ PredicateLatePos
Definition: HexagonBaseInfo.h:73
llvm::HexagonMCInstrInfo::getNewValueOperand2
const MCOperand & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:411
llvm::HexagonII::isCVIPos
@ isCVIPos
Definition: HexagonBaseInfo.h:163
llvm::HexagonII::NewValueOpPos2
@ NewValueOpPos2
Definition: HexagonBaseInfo.h:146
llvm::HexagonII::TypeCVI_FIRST
const unsigned TypeCVI_FIRST
Definition: HexagonBaseInfo.h:27
llvm::HexagonII::CofMax1Mask
@ CofMax1Mask
Definition: HexagonBaseInfo.h:118
llvm::MCInst::getLoc
SMLoc getLoc() const
Definition: MCInst.h:204
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCInst::setLoc
void setLoc(SMLoc loc)
Definition: MCInst.h:203
llvm::DuplexCandidate::packetIndexI
unsigned packetIndexI
Definition: HexagonMCInstrInfo.h:36
llvm::HexagonMCChecker
Check for a valid bundle.
Definition: HexagonMCChecker.h:34
llvm::HexagonMCInstrInfo::getType
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
Definition: HexagonMCInstrInfo.cpp:423
llvm::HexagonII::ExtentBitsMask
@ ExtentBitsMask
Definition: HexagonBaseInfo.h:112
llvm::HexagonII::HasHvxTmpMask
@ HasHvxTmpMask
Definition: HexagonBaseInfo.h:158
llvm::HexagonII::ExtendablePos
@ ExtendablePos
Definition: HexagonBaseInfo.h:99
llvm::HexagonMCInstrInfo::deriveDuplex
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
Definition: HexagonMCInstrInfo.cpp:208
llvm::HexagonII::ExtendableOpPos
@ ExtendableOpPos
Definition: HexagonBaseInfo.h:105
Casting.h
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::HexagonII::ExtentSignedPos
@ ExtentSignedPos
Definition: HexagonBaseInfo.h:108
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::HexagonII::CVINewMask
@ CVINewMask
Definition: HexagonBaseInfo.h:161
llvm::HexagonMCInstrInfo::getExtendableOperand
const MCOperand & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:323
llvm::HexagonII::AddrModePos
@ AddrModePos
Definition: HexagonBaseInfo.h:128
llvm::HexagonII::AddrModeMask
@ AddrModeMask
Definition: HexagonBaseInfo.h:129
StringSwitch.h
llvm::HexagonMCInstrInfo::getUnits
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
Definition: HexagonMCInstrInfo.cpp:450
llvm::HexagonMCInstrInfo::IsSingleConsumerRefPairProducer
bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer)
Definition: HexagonMCInstrInfo.cpp:712
llvm::HexagonMCInstrInfo::packetSizeSlots
unsigned packetSizeSlots(MCSubtargetInfo const &STI)
Definition: HexagonMCInstrInfo.cpp:909
llvm::HexagonMCInstrInfo::instruction
const MCInst & instruction(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:526
HEXAGON_PACKET_OUTER_SIZE
#define HEXAGON_PACKET_OUTER_SIZE
Definition: HexagonMCTargetDesc.h:40
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::HexagonII::TypeNCJ
@ TypeNCJ
Definition: HexagonDepITypes.h:57
llvm::HexagonII::NewValuePos
@ NewValuePos
Definition: HexagonBaseInfo.h:77
llvm::HexagonMCInstrInfo::isNewValueStore
bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI)
Return true if the operand is a new-value store insn.
Definition: HexagonMCInstrInfo.cpp:668
llvm::HexagonMCInstrInfo::isHVX
bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:637
llvm::HexagonMCInstrInfo::getMaxValue
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
Definition: HexagonMCInstrInfo.cpp:353
llvm::HexagonMCInstrInfo::bundleInstructionsOffset
constexpr size_t bundleInstructionsOffset
Definition: HexagonMCInstrInfo.h:85
SmallVector.h
llvm::HexagonII::isCVIMask
@ isCVIMask
Definition: HexagonBaseInfo.h:164
llvm::HexagonMCInstrInfo::padEndloop
void padEndloop(MCInst &MCI, MCContext &Context)
Definition: HexagonMCInstrInfo.cpp:921
N
#define N
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::HexagonMCInstrInfo::getExpr
const MCExpr & getExpr(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:310
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::HexagonII::ExtendableMask
@ ExtendableMask
Definition: HexagonBaseInfo.h:100
llvm::InstrItinerary::LastStage
uint16_t LastStage
Index of last + 1 stage in itinerary.
Definition: MCInstrItineraries.h:101
llvm::HexagonII::AccumulatorPos
@ AccumulatorPos
Definition: HexagonBaseInfo.h:150
llvm::HexagonMCInstrInfo::getMinValue
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
Definition: HexagonMCInstrInfo.cpp:364
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
llvm::HexagonII::TypeJ
@ TypeJ
Definition: HexagonDepITypes.h:53
llvm::HexagonII::ExtendableOpMask
@ ExtendableOpMask
Definition: HexagonBaseInfo.h:106
llvm::MCInstrDesc::isReturn
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:273
llvm::HexagonII::SoloAXPos
@ SoloAXPos
Definition: HexagonBaseInfo.h:60
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::HexagonMCInstrInfo::isExtended
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:626
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::HexagonMCInstrInfo::isSolo
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
Definition: HexagonMCInstrInfo.cpp:790
llvm::HexagonII::TypeCVI_LAST
const unsigned TypeCVI_LAST
Definition: HexagonBaseInfo.h:28
llvm::HexagonMCInstrInfo::isPredRegister
bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I)
Definition: HexagonMCInstrInfo.cpp:760
llvm::HexagonII::PredicatedMask
@ PredicatedMask
Definition: HexagonBaseInfo.h:68
llvm::HexagonII::FPPos
@ FPPos
Definition: HexagonBaseInfo.h:139
llvm::HexagonII::NewValueOpPos
@ NewValueOpPos
Definition: HexagonBaseInfo.h:83
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
llvm::HexagonII::TypePos
@ TypePos
Definition: HexagonBaseInfo.h:53
llvm::HexagonMCInstrInfo::GetVecRegPairIndices
std::pair< unsigned, unsigned > GetVecRegPairIndices(unsigned VecRegPair)
Returns an ordered pair of the constituent register ordinals for each of the elements of VecRegPair.
Definition: HexagonMCInstrInfo.cpp:700
llvm::Hexagon::PacketIterator::PacketIterator
PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
Definition: HexagonMCInstrInfo.cpp:39
llvm::HexagonMCInstrInfo::slotsConsumed
unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:977
MCExpr.h
llvm::HexagonMCInstrInfo::isPredicateLate
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:735
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSchedModel::InstrItineraries
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:311
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::HexagonMCExpr::setMustExtend
void setMustExtend(bool Val=true)
Definition: HexagonMCExpr.cpp:85
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::HexagonII::NewValueMask
@ NewValueMask
Definition: HexagonBaseInfo.h:78
llvm::HexagonII::NewValueOpMask2
@ NewValueOpMask2
Definition: HexagonBaseInfo.h:147
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1236
llvm::HexagonMCInstrInfo::isPredicatedNew
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
Definition: HexagonMCInstrInfo.cpp:742
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:620
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
llvm::HexagonMCInstrInfo::isInnerLoop
bool isInnerLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:646