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HexagonMCInstrInfo.cpp
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1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
10 //
11 //===----------------------------------------------------------------------===//
12 
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/Support/Casting.h"
29 #include <cassert>
30 #include <cstdint>
31 #include <limits>
32 
33 using namespace llvm;
34 
36  return Register != Hexagon::NoRegister;
37 }
38 
40  MCInst const &Inst)
41  : MCII(MCII), BundleCurrent(Inst.begin() +
42  HexagonMCInstrInfo::bundleInstructionsOffset),
43  BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
44 
46  MCInst const &Inst, std::nullptr_t)
47  : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
48  DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
49 
51  if (DuplexCurrent != DuplexEnd) {
52  ++DuplexCurrent;
53  if (DuplexCurrent == DuplexEnd) {
54  DuplexCurrent = BundleEnd;
55  DuplexEnd = BundleEnd;
56  ++BundleCurrent;
57  }
58  return *this;
59  }
60  ++BundleCurrent;
61  if (BundleCurrent != BundleEnd) {
62  MCInst const &Inst = *BundleCurrent->getInst();
63  if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
64  DuplexCurrent = Inst.begin();
65  DuplexEnd = Inst.end();
66  }
67  }
68  return *this;
69 }
70 
72  if (DuplexCurrent != DuplexEnd)
73  return *DuplexCurrent->getInst();
74  return *BundleCurrent->getInst();
75 }
76 
78  return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
79  DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
80 }
81 
83  MCContext &Context) {
85 }
86 
88  MCInstrInfo const &MCII, MCInst &MCB,
89  MCInst const &MCI) {
91  MCOperand const &exOp =
93 
94  // Create the extender.
95  MCInst *XMCI =
96  new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
97  XMCI->setLoc(MCI.getLoc());
98 
100 }
101 
104  MCInst const &MCI) {
105  assert(isBundle(MCI));
106  return make_range(Hexagon::PacketIterator(MCII, MCI),
107  Hexagon::PacketIterator(MCII, MCI, nullptr));
108 }
109 
112  assert(isBundle(MCI));
114 }
115 
118  return (MCI.size() - bundleInstructionsOffset);
119  else
120  return (1);
121 }
122 
123 namespace {
124 bool canonicalizePacketImpl(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
125  MCContext &Context, MCInst &MCB,
127  // Check the bundle for errors.
128  bool CheckOk = Check ? Check->check(false) : true;
129  if (!CheckOk)
130  return false;
131  // Examine the packet and convert pairs of instructions to compound
132  // instructions when possible.
134  HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
135  HexagonMCShuffle(Context, false, MCII, STI, MCB);
136 
137  // Examine the packet and convert pairs of instructions to duplex
138  // instructions when possible.
139  if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) {
140  SmallVector<DuplexCandidate, 8> possibleDuplexes;
141  possibleDuplexes =
143  HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
144  }
145  // Examines packet and pad the packet, if needed, when an
146  // end-loop is in the bundle.
148  // If compounding and duplexing didn't reduce the size below
149  // 4 or less we have a packet that is too big.
151  if (Check)
152  Check->reportError("invalid instruction packet: out of slots");
153  return false;
154  }
155  // Check the bundle for errors.
156  CheckOk = Check ? Check->check(true) : true;
157  if (!CheckOk)
158  return false;
159  HexagonMCShuffle(Context, true, MCII, STI, MCB);
160  return true;
161 }
162 } // namespace
163 
165  MCSubtargetInfo const &STI,
166  MCContext &Context, MCInst &MCB,
168  bool AttemptCompatibility) {
169  auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
170  if (!AttemptCompatibility || ArchSTI == nullptr)
171  return canonicalizePacketImpl(MCII, STI, Context, MCB, Check);
172 
173  const MCRegisterInfo *RI = Context.getRegisterInfo();
174  HexagonMCChecker DefaultCheck(Context, MCII, STI, MCB, *RI, false);
175  HexagonMCChecker *BaseCheck = (Check == nullptr) ? &DefaultCheck : Check;
176  HexagonMCChecker PerfCheck(*BaseCheck, STI, false);
177  if (canonicalizePacketImpl(MCII, STI, Context, MCB, &PerfCheck))
178  return true;
179 
180  HexagonMCChecker ArchCheck(*BaseCheck, *ArchSTI, true);
181  return canonicalizePacketImpl(MCII, *ArchSTI, Context, MCB, &ArchCheck);
182 }
183 
185  MCInst const &Inst,
186  MCOperand const &MO) {
188  HexagonMCInstrInfo::isExtended(MCII, Inst));
189 
190  MCInst XMI;
191  XMI.setOpcode(Hexagon::A4_ext);
192  if (MO.isImm())
193  XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
194  else if (MO.isExpr())
196  else
197  llvm_unreachable("invalid extendable operand");
198  return XMI;
199 }
200 
202  MCInst const &inst0,
203  MCInst const &inst1) {
204  assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
205  MCInst *duplexInst = new (Context) MCInst;
206  duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
207 
208  MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
209  MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
210  duplexInst->addOperand(MCOperand::createInst(SubInst0));
211  duplexInst->addOperand(MCOperand::createInst(SubInst1));
212  return duplexInst;
213 }
214 
216  size_t Index) {
217  assert(Index <= bundleSize(MCB));
218  if (Index == 0)
219  return nullptr;
220  MCInst const *Inst =
222  if (isImmext(*Inst))
223  return Inst;
224  return nullptr;
225 }
226 
228  MCInstrInfo const &MCII, MCInst &MCB,
229  MCInst const &MCI) {
230  if (isConstExtended(MCII, MCI))
231  addConstExtender(Context, MCII, MCB, MCI);
232 }
233 
235  MCInst const &MCI) {
239 }
240 
242  MCInst const &MCI) {
243  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
244  return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
246 }
247 
249  MCInst const &MCI) {
250  return MCII.get(MCI.getOpcode());
251 }
252 
254  using namespace Hexagon;
255 
256  switch (Reg) {
257  default:
258  llvm_unreachable("unknown duplex register");
259  // Rs Rss
260  case R0:
261  case D0:
262  return 0;
263  case R1:
264  case D1:
265  return 1;
266  case R2:
267  case D2:
268  return 2;
269  case R3:
270  case D3:
271  return 3;
272  case R4:
273  case D8:
274  return 4;
275  case R5:
276  case D9:
277  return 5;
278  case R6:
279  case D10:
280  return 6;
281  case R7:
282  case D11:
283  return 7;
284  case R16:
285  return 8;
286  case R17:
287  return 9;
288  case R18:
289  return 10;
290  case R19:
291  return 11;
292  case R20:
293  return 12;
294  case R21:
295  return 13;
296  case R22:
297  return 14;
298  case R23:
299  return 15;
300  }
301 }
302 
304  const auto &HExpr = cast<HexagonMCExpr>(Expr);
305  assert(HExpr.getExpr());
306  return *HExpr.getExpr();
307 }
308 
310  MCInst const &MCI) {
311  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
313 }
314 
315 MCOperand const &
317  MCInst const &MCI) {
318  unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
319  MCOperand const &MO = MCI.getOperand(O);
320 
322  HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
323  (MO.isImm() || MO.isExpr()));
324  return (MO);
325 }
326 
328  MCInst const &MCI) {
329  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
331 }
332 
334  MCInst const &MCI) {
335  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
337 }
338 
340  MCInst const &MCI) {
341  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
343 }
344 
345 /// Return the maximum value of an extendable operand.
347  MCInst const &MCI) {
349  HexagonMCInstrInfo::isExtended(MCII, MCI));
350 
351  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
352  return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
353  return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
354 }
355 
356 /// Return the minimum value of an extendable operand.
358  MCInst const &MCI) {
360  HexagonMCInstrInfo::isExtended(MCII, MCI));
361 
362  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
363  return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
364  return 0;
365 }
366 
368  MCInst const &MCI) {
369  return MCII.getName(MCI.getOpcode());
370 }
371 
373  MCInst const &MCI) {
374  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
376 }
377 
379  MCInst const &MCI) {
380  if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
381  // VTMP doesn't actually exist in the encodings for these 184
382  // 3 instructions so go ahead and create it here.
383  static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
384  return (MCO);
385  } else {
386  unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
387  MCOperand const &MCO = MCI.getOperand(O);
388 
390  HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
391  MCO.isReg());
392  return (MCO);
393  }
394 }
395 
396 /// Return the new value or the newly produced value.
398  MCInst const &MCI) {
399  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
401 }
402 
403 MCOperand const &
405  MCInst const &MCI) {
406  unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
407  MCOperand const &MCO = MCI.getOperand(O);
408 
410  HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
411  MCO.isReg());
412  return (MCO);
413 }
414 
415 /// Return the Hexagon ISA class for the insn.
417  MCInst const &MCI) {
418  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
419  return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
420 }
421 
422 /// Return the resources used by this instruction
424  MCSubtargetInfo const &STI,
425  MCInst const &MCI) {
426 
428  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
429  int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage;
430 
431  // HVX resources used are currenty located at the second to last stage.
432  // This could also be done with a linear search of the stages looking for:
433  // CVI_ALL, CVI_MPY01, CVI_XLSHF, CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE,
434  // CVI_ZW
435  unsigned Stage = II[SchedClass].LastStage - 1;
436 
437  if (Size < 2)
438  return 0;
439  return ((Stage + HexagonStages)->getUnits());
440 }
441 
442 /// Return the slots this instruction can execute out of
444  MCSubtargetInfo const &STI,
445  MCInst const &MCI) {
447  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
448  return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
449 }
450 
451 /// Return the slots this instruction consumes in addition to
452 /// the slot(s) it can execute out of
453 
455  MCSubtargetInfo const &STI,
456  MCInst const &MCI) {
458  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
459  unsigned Slots = 0;
460 
461  // FirstStage are slots that this instruction can execute in.
462  // FirstStage+1 are slots that are also consumed by this instruction.
463  // For example: vmemu can only execute in slot 0 but also consumes slot 1.
464  for (unsigned Stage = II[SchedClass].FirstStage + 1;
465  Stage < II[SchedClass].LastStage; ++Stage) {
466  unsigned Units = (Stage + HexagonStages)->getUnits();
467  if (Units > HexagonGetLastSlot())
468  break;
469  // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
470  Slots |= Units;
471  }
472 
473  // if 0 is returned, then no additional slots are consumed by this inst.
474  return Slots;
475 }
476 
477 bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
479  return false;
480 
481  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
482  if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
483  return true;
484  }
485 
486  return false;
487 }
488 
490  return extenderForIndex(MCB, Index) != nullptr;
491 }
492 
495  return false;
496 
497  for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
498  if (isImmext(*I.getInst()))
499  return true;
500  }
501 
502  return false;
503 }
504 
505 /// Return whether the insn produces a value.
507  MCInst const &MCI) {
508  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
510 }
511 
512 /// Return whether the insn produces a second value.
514  MCInst const &MCI) {
515  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
517 }
518 
520  assert(isBundle(MCB));
523 }
524 
525 /// Return where the instruction is an accumulator.
527  MCInst const &MCI) {
528  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
530 }
531 
533  auto Result = Hexagon::BUNDLE == MCI.getOpcode();
534  assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
535  return Result;
536 }
537 
539  MCInst const &MCI) {
540  if (HexagonMCInstrInfo::isExtended(MCII, MCI))
541  return true;
542  if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
543  return false;
545  if (isa<HexagonMCExpr>(MO.getExpr()) &&
547  return true;
548  // Branch insns are handled as necessary by relaxation.
549  if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
551  HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
554  return false;
555  // Otherwise loop instructions and other CR insts are handled by relaxation
556  else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
557  (MCI.getOpcode() != Hexagon::C4_addipc))
558  return false;
559 
560  assert(!MO.isImm());
561  if (isa<HexagonMCExpr>(MO.getExpr()) &&
563  return false;
564  int64_t Value;
565  if (!MO.getExpr()->evaluateAsAbsolute(Value))
566  return true;
567  int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
568  int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
569  return (MinValue > Value || Value > MaxValue);
570 }
571 
572 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
573  return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
574  !HexagonMCInstrInfo::isPrefix(MCII, MCI);
575 }
576 
577 bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
578  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
580 }
581 
583  MCInst const &MCI) {
584  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
586 }
587 
589  MCInst const &MCI) {
590  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
592 }
593 
595  MCInst const &MCI) {
596  return (getType(MCII, MCI) == HexagonII::TypeCJ);
597 }
598 
599 bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
600  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
602 }
603 
605  return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
606  (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
607 }
608 
609 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
611 }
612 
614  MCInst const &MCI) {
615  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
617 }
618 
620  MCInst const &MCI) {
621  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
623 }
624 
625 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
626  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
627  return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
628 }
629 
630 bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
631  const uint64_t V = getType(MCII, MCI);
633 }
634 
636  return MCI.getOpcode() == Hexagon::A4_ext;
637 }
638 
640  assert(isBundle(MCI));
641  int64_t Flags = MCI.getOperand(0).getImm();
642  return (Flags & innerLoopMask) != 0;
643 }
644 
646  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
647 }
648 
650  return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
651  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
652 }
653 
654 /// Return whether the insn expects newly produced value.
656  MCInst const &MCI) {
657  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
659 }
660 
662  MCInst const &MCI) {
663  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
665 }
666 
667 /// Return whether the operand is extendable.
669  MCInst const &MCI, unsigned short O) {
670  return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
671 }
672 
674  assert(isBundle(MCI));
675  int64_t Flags = MCI.getOperand(0).getImm();
676  return (Flags & outerLoopMask) != 0;
677 }
678 
679 bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) {
680  return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) ||
681  (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
682 }
683 
685  return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
686 }
687 
688 bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) {
689  return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31);
690 }
691 
692 std::pair<unsigned, unsigned>
694  assert(IsVecRegPair(VecRegPair) &&
695  "VecRegPair must be a vector register pair");
696 
697  const bool IsRev = IsReverseVecRegPair(VecRegPair);
698  const unsigned PairIndex =
699  2 * (IsRev ? VecRegPair - Hexagon::WR0 : VecRegPair - Hexagon::W0);
700 
701  return IsRev ? std::make_pair(PairIndex, PairIndex + 1)
702  : std::make_pair(PairIndex + 1, PairIndex);
703 }
704 
706  unsigned Consumer) {
707  if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) {
708  const unsigned ProdPairIndex = IsReverseVecRegPair(Producer)
709  ? Producer - Hexagon::WR0
710  : Producer - Hexagon::W0;
711  const unsigned ConsumerSingleIndex = (Consumer - Hexagon::V0) >> 1;
712 
713  return ConsumerSingleIndex == ProdPairIndex;
714  }
715  return false;
716 }
717 
719  MCInst const &MCI) {
720  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
722 }
723 
724 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
726 }
727 
729  MCInst const &MCI) {
730  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
732 }
733 
734 /// Return whether the insn is newly predicated.
736  MCInst const &MCI) {
737  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
739 }
740 
742  MCInst const &MCI) {
743  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
744  return (
746 }
747 
749  auto &PredRegClass = MRI.getRegClass(Hexagon::PredRegsRegClassID);
750  return PredRegClass.contains(Reg);
751 }
752 
754  MCInst const &Inst, unsigned I) {
755  MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);
756 
757  return Inst.getOperand(I).isReg() &&
758  Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID;
759 }
760 
761 /// Return whether the insn can be packaged only with A and X-type insns.
762 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
763  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
765 }
766 
767 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
769  MCInst const &MCI) {
770  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
771  return ((F >> HexagonII::RestrictSlot1AOKPos) &
773 }
774 
776  MCInst const &MCI) {
777  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
780 }
781 
782 /// Return whether the insn is solo, i.e., cannot be in a packet.
783 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
784  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
785  return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
786 }
787 
789  assert(isBundle(MCI));
790  auto Flags = MCI.getOperand(0).getImm();
791  return (Flags & memReorderDisabledMask) != 0;
792 }
793 
795  switch (MCI.getOpcode()) {
796  default:
797  return false;
798  case Hexagon::SA1_addi:
799  case Hexagon::SA1_addrx:
800  case Hexagon::SA1_addsp:
801  case Hexagon::SA1_and1:
802  case Hexagon::SA1_clrf:
803  case Hexagon::SA1_clrfnew:
804  case Hexagon::SA1_clrt:
805  case Hexagon::SA1_clrtnew:
806  case Hexagon::SA1_cmpeqi:
807  case Hexagon::SA1_combine0i:
808  case Hexagon::SA1_combine1i:
809  case Hexagon::SA1_combine2i:
810  case Hexagon::SA1_combine3i:
811  case Hexagon::SA1_combinerz:
812  case Hexagon::SA1_combinezr:
813  case Hexagon::SA1_dec:
814  case Hexagon::SA1_inc:
815  case Hexagon::SA1_seti:
816  case Hexagon::SA1_setin1:
817  case Hexagon::SA1_sxtb:
818  case Hexagon::SA1_sxth:
819  case Hexagon::SA1_tfr:
820  case Hexagon::SA1_zxtb:
821  case Hexagon::SA1_zxth:
822  case Hexagon::SL1_loadri_io:
823  case Hexagon::SL1_loadrub_io:
824  case Hexagon::SL2_deallocframe:
825  case Hexagon::SL2_jumpr31:
826  case Hexagon::SL2_jumpr31_f:
827  case Hexagon::SL2_jumpr31_fnew:
828  case Hexagon::SL2_jumpr31_t:
829  case Hexagon::SL2_jumpr31_tnew:
830  case Hexagon::SL2_loadrb_io:
831  case Hexagon::SL2_loadrd_sp:
832  case Hexagon::SL2_loadrh_io:
833  case Hexagon::SL2_loadri_sp:
834  case Hexagon::SL2_loadruh_io:
835  case Hexagon::SL2_return:
836  case Hexagon::SL2_return_f:
837  case Hexagon::SL2_return_fnew:
838  case Hexagon::SL2_return_t:
839  case Hexagon::SL2_return_tnew:
840  case Hexagon::SS1_storeb_io:
841  case Hexagon::SS1_storew_io:
842  case Hexagon::SS2_allocframe:
843  case Hexagon::SS2_storebi0:
844  case Hexagon::SS2_storebi1:
845  case Hexagon::SS2_stored_sp:
846  case Hexagon::SS2_storeh_io:
847  case Hexagon::SS2_storew_sp:
848  case Hexagon::SS2_storewi0:
849  case Hexagon::SS2_storewi1:
850  return true;
851  }
852 }
853 
854 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
855  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
857 }
858 
859 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
860  auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
861  << 8;
862  if (MCI.size() <= Index)
863  return Sentinal;
864  MCOperand const &MCO = MCI.getOperand(Index);
865  if (!MCO.isExpr())
866  return Sentinal;
867  int64_t Value;
868  if (!MCO.getExpr()->evaluateAsAbsolute(Value))
869  return Sentinal;
870  return Value;
871 }
872 
873 void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
874  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
875  HExpr.setMustExtend(Val);
876 }
877 
879  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
880  return HExpr.mustExtend();
881 }
882 void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
883  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
884  HExpr.setMustNotExtend(Val);
885 }
887  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
888  return HExpr.mustNotExtend();
889 }
890 void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
891  HexagonMCExpr &HExpr =
892  const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
893  HExpr.setS27_2_reloc(Val);
894 }
896  HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
897  if (!HExpr)
898  return false;
899  return HExpr->s27_2_reloc();
900 }
901 
903  const bool IsTiny = STI.getFeatureBits()[Hexagon::ProcTinyCore];
904 
905  return IsTiny ? (HEXAGON_PACKET_SIZE - 1) : HEXAGON_PACKET_SIZE;
906 }
907 
909  return llvm::StringSwitch<unsigned>(CPU)
910  .Case("hexagonv67t", 3)
911  .Default(4);
912 }
913 
915  MCInst Nop;
916  Nop.setOpcode(Hexagon::A2_nop);
917  assert(isBundle(MCB));
918  while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
923 }
924 
927  if (!isPredicated(MCII, MCI))
928  return {0, 0, false};
929  MCInstrDesc const &Desc = getDesc(MCII, MCI);
930  for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
931  if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
932  return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
933  return {0, 0, false};
934 }
935 
937  MCInst const &MCI) {
938  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
940 }
941 
942 /// return true if instruction has hasTmpDst attribute.
943 bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
944  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
946 }
947 
949  MCInst const &MCI) {
950  const unsigned OpCode = MCI.getOpcode();
951  const bool IsTiny = STI.getFeatureBits() [Hexagon::ProcTinyCore];
952  const bool NoSlotReqd = Hexagon::A4_ext == OpCode ||
953  (IsTiny && Hexagon::A2_nop == OpCode) ||
954  (IsTiny && Hexagon::J4_hintjumpr == OpCode);
955 
956  return !NoSlotReqd;
957 }
958 
960  MCSubtargetInfo const &STI,
961  MCInst const &MCI) {
962  unsigned slotsUsed = 0;
963  for (auto HMI : bundleInstructions(MCI)) {
964  MCInst const &MCI = *HMI.getInst();
965  if (!requiresSlot(STI, MCI))
966  continue;
967  if (isDuplex(MCII, MCI))
968  slotsUsed += 2;
969  else
970  ++slotsUsed;
971  }
972  return slotsUsed;
973 }
974 
976  DuplexCandidate Candidate) {
977  assert(Candidate.packetIndexI < MCB.size());
978  assert(Candidate.packetIndexJ < MCB.size());
979  assert(isBundle(MCB));
980  MCInst *Duplex =
981  deriveDuplex(Context, Candidate.iClass,
982  *MCB.getOperand(Candidate.packetIndexJ).getInst(),
983  *MCB.getOperand(Candidate.packetIndexI).getInst());
984  assert(Duplex != nullptr);
985  MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
986  MCB.erase(MCB.begin() + Candidate.packetIndexJ);
987 }
988 
990  assert(isBundle(MCI));
991  MCOperand &Operand = MCI.getOperand(0);
992  Operand.setImm(Operand.getImm() | innerLoopMask);
993 }
994 
996  assert(isBundle(MCI));
997  MCOperand &Operand = MCI.getOperand(0);
998  Operand.setImm(Operand.getImm() | memReorderDisabledMask);
1000 }
1001 
1003  assert(isBundle(MCI));
1004  MCOperand &Operand = MCI.getOperand(0);
1005  Operand.setImm(Operand.getImm() | outerLoopMask);
1006 }
1007 
1008 unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
1009  unsigned Producer,
1010  unsigned Producer2) {
1011  // If we're a single vector consumer of a double producer, set subreg bit
1012  // based on if we're accessing the lower or upper register component
1013  if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer))
1014  return (Consumer - Hexagon::V0) & 0x1;
1015  if (Producer2 != Hexagon::NoRegister)
1016  return Consumer == Producer;
1017  return 0;
1018 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
HexagonMCTargetDesc.h
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
llvm::HexagonII::NewValueOpMask
@ NewValueOpMask
Definition: HexagonBaseInfo.h:84
llvm::HexagonMCInstrInfo::mustNotExtend
bool mustNotExtend(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:886
llvm::HexagonMCInstrInfo::setMustExtend
void setMustExtend(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:873
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:248
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::DuplexCandidate
Definition: HexagonMCInstrInfo.h:34
llvm::HexagonMCInstrInfo::minConstant
int64_t minConstant(MCInst const &MCI, size_t Index)
Definition: HexagonMCInstrInfo.cpp:859
llvm::HexagonMCInstrInfo::isAccumulator
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
Definition: HexagonMCInstrInfo.cpp:526
llvm::HexagonII::AccumulatorMask
@ AccumulatorMask
Definition: HexagonBaseInfo.h:151
llvm::HexagonII::NVStoreMask
@ NVStoreMask
Definition: HexagonBaseInfo.h:90
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:266
llvm::HexagonMCInstrInfo::setMustNotExtend
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:882
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::WebAssembly::Nop
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
Definition: WebAssemblyMCTargetDesc.h:133
llvm::HexagonMCInstrInfo::isPredReg
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:748
llvm::HexagonII::FPMask
@ FPMask
Definition: HexagonBaseInfo.h:140
llvm::HexagonII::NewValueMask
@ NewValueMask
Definition: HexagonBaseInfo.h:78
llvm::HexagonII::PredicatedMask
@ PredicatedMask
Definition: HexagonBaseInfo.h:68
llvm::HexagonII::TypeCR
@ TypeCR
Definition: HexagonDepITypes.h:23
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::HexagonMCInstrInfo::isRestrictSlot1AOK
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
Definition: HexagonMCInstrInfo.cpp:768
llvm::HexagonDisableCompound
cl::opt< bool > HexagonDisableCompound
llvm::MCSubtargetInfo::getSchedModel
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Definition: MCSubtargetInfo.h:162
llvm::HexagonMCInstrInfo::getDuplexRegisterNumbering
unsigned getDuplexRegisterNumbering(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:253
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::HexagonMCInstrInfo::outerLoopMask
const int64_t outerLoopMask
Definition: HexagonMCInstrInfo.h:71
llvm::HexagonMCInstrInfo::innerLoopMask
const int64_t innerLoopMask
Definition: HexagonMCInstrInfo.h:68
llvm::MCInstrDesc::isPseudo
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MCInstrDesc.h:264
llvm::HexagonII::MemAccessSizePos
@ MemAccessSizePos
Definition: HexagonBaseInfo.h:131
llvm::HexagonII::RestrictSlot1AOKPos
@ RestrictSlot1AOKPos
Definition: HexagonBaseInfo.h:63
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
llvm::HexagonII::hasNewValueMask
@ hasNewValueMask
Definition: HexagonBaseInfo.h:81
llvm::HexagonMCInstrInfo::isCofMax1
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:577
llvm::HexagonMCInstrInfo::hasDuplex
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:477
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::HexagonMCInstrInfo::isCofRelax2
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:588
llvm::MCInstrDesc::getSchedClass
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:612
ErrorHandling.h
llvm::HexagonII::TypeEXTENDER
@ TypeEXTENDER
Definition: HexagonDepITypes.h:52
llvm::HexagonMCInstrInfo::getCVIResources
unsigned getCVIResources(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the resources used by this instruction.
Definition: HexagonMCInstrInfo.cpp:423
llvm::HexagonII::RestrictSlot1AOKMask
@ RestrictSlot1AOKMask
Definition: HexagonBaseInfo.h:64
llvm::HexagonII::SoloPos
@ SoloPos
Definition: HexagonBaseInfo.h:57
llvm::HexagonII::hasNewValuePos2
@ hasNewValuePos2
Definition: HexagonBaseInfo.h:143
llvm::HexagonMCExpr::mustExtend
bool mustExtend() const
Definition: HexagonMCExpr.cpp:89
llvm::Hexagon::PacketIterator::operator*
const MCInst & operator*() const
Definition: HexagonMCInstrInfo.cpp:71
llvm::HexagonMCInstrInfo::getNewValueOp
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:372
R4
#define R4(n)
llvm::HexagonII::ExtentBitsMask
@ ExtentBitsMask
Definition: HexagonBaseInfo.h:112
llvm::HexagonMCInstrInfo::hasTmpDst
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
return true if instruction has hasTmpDst attribute.
Definition: HexagonMCInstrInfo.cpp:943
llvm::HexagonMCInstrInfo::getMemAccessSize
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:234
llvm::HexagonII::CVINewMask
@ CVINewMask
Definition: HexagonBaseInfo.h:162
llvm::HexagonMCInstrInfo::getExtentAlignment
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:327
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
llvm::HexagonMCInstrInfo::addConstExtender
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:87
llvm::HexagonII::CofMax1Mask
@ CofMax1Mask
Definition: HexagonBaseInfo.h:118
llvm::HexagonMCInstrInfo::hasExtenderForIndex
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:489
llvm::HexagonMCInstrInfo::PredicateInfo::isPredicated
bool isPredicated() const
Definition: HexagonMCInstrInfo.cpp:35
llvm::HexagonMCInstrInfo::isImmext
bool isImmext(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:635
llvm::HexagonMCInstrInfo::extendIfNeeded
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:227
llvm::HexagonII::PredicateLatePos
@ PredicateLatePos
Definition: HexagonBaseInfo.h:73
llvm::HexagonII::AddrModeMask
@ AddrModeMask
Definition: HexagonBaseInfo.h:129
llvm::HexagonMCInstrInfo::isSubInstruction
bool isSubInstruction(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:794
llvm::HexagonII::getMemAccessSizeInBytes
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
Definition: HexagonBaseInfo.h:271
llvm::HexagonMCInstrInfo::extenderForIndex
const MCInst * extenderForIndex(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:215
llvm::HexagonMCInstrInfo::setInnerLoop
void setInnerLoop(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:989
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::HexagonMCInstrInfo::replaceDuplex
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
Definition: HexagonMCInstrInfo.cpp:975
llvm::HexagonMCInstrInfo::prefersSlot3
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:936
llvm::HexagonMCExpr
Definition: HexagonMCExpr.h:15
llvm::HexagonMCInstrInfo::isCofRelax1
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:582
llvm::HexagonII::hasNewValuePos
@ hasNewValuePos
Definition: HexagonBaseInfo.h:80
llvm::HexagonMCInstrInfo::bundleInstructionsOffset
const size_t bundleInstructionsOffset
Definition: HexagonMCInstrInfo.h:78
llvm::HexagonII::CofRelax2Pos
@ CofRelax2Pos
Definition: HexagonBaseInfo.h:121
llvm::Hexagon_MC::getArchSubtarget
const MCSubtargetInfo * getArchSubtarget(MCSubtargetInfo const *STI)
Definition: HexagonMCTargetDesc.cpp:411
HexagonBaseInfo.h
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::HexagonMCInstrInfo::getOtherReservedSlots
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of.
Definition: HexagonMCInstrInfo.cpp:454
llvm::HexagonII::RestrictNoSlot1StorePos
@ RestrictNoSlot1StorePos
Definition: HexagonBaseInfo.h:124
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::HexagonMCInstrInfo::isMemReorderDisabled
bool isMemReorderDisabled(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:788
llvm::HexagonII::CofRelax1Mask
@ CofRelax1Mask
Definition: HexagonBaseInfo.h:120
llvm::HexagonMCInstrInfo::isDblRegForSubInst
bool isDblRegForSubInst(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:604
llvm::HexagonMCInstrInfo::setS27_2_reloc
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:890
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1292
R2
#define R2(n)
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:91
llvm::HexagonII::MemAccessSize
MemAccessSize
Definition: HexagonBaseInfo.h:40
llvm::HexagonMCInstrInfo::PredicateInfo
Definition: HexagonMCInstrInfo.h:322
llvm::HexagonII::RestrictNoSlot1StoreMask
@ RestrictNoSlot1StoreMask
Definition: HexagonBaseInfo.h:125
HexagonMCShuffler.h
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::InstrItinerary
An itinerary represents the scheduling information for an instruction.
Definition: MCInstrItineraries.h:98
MCInstrItineraries.h
HEXAGON_PRESHUFFLE_PACKET_SIZE
#define HEXAGON_PRESHUFFLE_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:43
llvm::HexagonMCInstrInfo::isPredicatedTrue
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:741
llvm::HexagonII::ExtentSignedPos
@ ExtentSignedPos
Definition: HexagonBaseInfo.h:108
llvm::HexagonII::SoloMask
@ SoloMask
Definition: HexagonBaseInfo.h:58
llvm::ARM_MC::isPredicated
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
Definition: ARMMCTargetDesc.cpp:181
HexagonMCChecker.h
llvm::HexagonII::MemAccesSizeMask
@ MemAccesSizeMask
Definition: HexagonBaseInfo.h:132
llvm::HexagonMCInstrInfo::s27_2_reloc
bool s27_2_reloc(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:895
llvm::HexagonMCInstrInfo::hasImmExt
bool hasImmExt(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:493
llvm::HexagonMCInstrInfo::requiresSlot
bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:948
HexagonMCInstrInfo.h
llvm::HexagonMCInstrInfo::setMemReorderDisabled
void setMemReorderDisabled(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:995
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition: HexagonMCInstrInfo.cpp:513
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition: HexagonMCInstrInfo.cpp:655
llvm::HexagonMCInstrInfo::isPredicated
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:718
llvm::MCOperand::getInst
const MCInst * getInst() const
Definition: MCInst.h:124
llvm::HexagonMCExpr::s27_2_reloc
bool s27_2_reloc() const
Definition: HexagonMCExpr.cpp:96
MCContext.h
llvm::HexagonMCInstrInfo::isVector
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:854
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:532
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::HexagonMCInstrInfo::predicateInfo
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:926
MCInst.h
llvm::HexagonMCInstrInfo::getName
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:367
HexagonMCExpr.h
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::HexagonMCInstrInfo::isCanon
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:572
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:103
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::HexagonII::AccumulatorPos
@ AccumulatorPos
Definition: HexagonBaseInfo.h:150
llvm::HexagonII::FPPos
@ FPPos
Definition: HexagonBaseInfo.h:139
llvm::HexagonMCInstrInfo::getExtentBits
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:333
llvm::Hexagon::PacketIterator::operator==
bool operator==(PacketIterator const &Other) const
Definition: HexagonMCInstrInfo.cpp:77
llvm::HexagonMCInstrInfo::isRestrictNoSlot1Store
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:775
llvm::MCInst::end
iterator end()
Definition: MCInst.h:221
llvm::HexagonMCInstrInfo::isConstExtended
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:538
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:89
llvm::HexagonMCInstrInfo::hasNewValue
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
Definition: HexagonMCInstrInfo.cpp:506
llvm::HexagonMCInstrInfo::IsVecRegSingle
bool IsVecRegSingle(unsigned VecReg)
Definition: HexagonMCInstrInfo.cpp:688
llvm::DuplexCandidate::iClass
unsigned iClass
Definition: HexagonMCInstrInfo.h:36
llvm::HexagonMCInstrInfo::addConstant
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
Definition: HexagonMCInstrInfo.cpp:82
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::MCInst::erase
void erase(iterator I)
Definition: MCInst.h:216
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:169
llvm::HexagonII::PrefersSlot3Pos
@ PrefersSlot3Pos
Definition: HexagonBaseInfo.h:154
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MCOperand::setInst
void setInst(const MCInst *Val)
Definition: MCInst.h:129
llvm::HexagonII::NewValueOpPos
@ NewValueOpPos
Definition: HexagonBaseInfo.h:83
llvm::HexagonMCInstrInfo::getDuplexPossibilties
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
Definition: HexagonMCDuplexInfo.cpp:1033
llvm::HexagonMCInstrInfo::isIntRegForSubInst
bool isIntRegForSubInst(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:649
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::HexagonII::CofRelax1Pos
@ CofRelax1Pos
Definition: HexagonBaseInfo.h:119
llvm::HexagonMCInstrInfo::isOpExtendable
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
Definition: HexagonMCInstrInfo.cpp:668
llvm::HexagonMCInstrInfo::mustExtend
bool mustExtend(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:878
Check
static bool Check(DecodeStatus &Out, DecodeStatus In)
Definition: AArch64Disassembler.cpp:243
llvm::HexagonMCInstrInfo::deriveSubInst
MCInst deriveSubInst(MCInst const &Inst)
Definition: HexagonMCDuplexInfo.cpp:700
llvm::HexagonII::PredicatedPos
@ PredicatedPos
Definition: HexagonBaseInfo.h:67
llvm::HexagonII::ExtendableOpPos
@ ExtendableOpPos
Definition: HexagonBaseInfo.h:105
llvm::HexagonMCInstrInfo::isSoloAX
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
Definition: HexagonMCInstrInfo.cpp:762
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:179
llvm::HexagonMCInstrInfo::packetSize
unsigned packetSize(StringRef CPU)
Definition: HexagonMCInstrInfo.cpp:908
llvm::HexagonII::HasTmpDstPos
@ HasTmpDstPos
Definition: HexagonBaseInfo.h:158
llvm::HexagonII::CVINewPos
@ CVINewPos
Definition: HexagonBaseInfo.h:161
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::HexagonMCInstrInfo::isCVINew
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:599
llvm::HexagonII::ExtentSignedMask
@ ExtentSignedMask
Definition: HexagonBaseInfo.h:109
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
uint64_t
llvm::HexagonMCInstrInfo::isCompound
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:594
llvm::Hexagon::PacketIterator
Definition: HexagonMCInstrInfo.h:44
llvm::HexagonMCInstrInfo::tryCompound
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
Definition: HexagonMCCompound.cpp:399
llvm::HexagonMCShuffle
bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
Definition: HexagonMCShuffler.cpp:104
llvm::HexagonMCInstrInfo::SubregisterBit
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
Definition: HexagonMCInstrInfo.cpp:1008
llvm::HexagonMCInstrInfo::canonicalizePacket
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)
Definition: HexagonMCInstrInfo.cpp:164
llvm::HexagonII::ExtendableMask
@ ExtendableMask
Definition: HexagonBaseInfo.h:100
llvm::MCInst::begin
iterator begin()
Definition: MCInst.h:219
llvm::DuplexCandidate::packetIndexJ
unsigned packetIndexJ
Definition: HexagonMCInstrInfo.h:36
llvm::HexagonII::NewValuePos
@ NewValuePos
Definition: HexagonBaseInfo.h:77
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::InstrItinerary::FirstStage
uint16_t FirstStage
Index of first stage in itinerary.
Definition: MCInstrItineraries.h:100
llvm::HexagonMCExpr::setMustNotExtend
void setMustNotExtend(bool Val=true)
Definition: HexagonMCExpr.cpp:90
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:609
llvm::HexagonGetLastSlot
unsigned HexagonGetLastSlot()
Definition: HexagonMCTargetDesc.cpp:148
llvm::Hexagon::PacketIterator::operator++
PacketIterator & operator++()
Definition: HexagonMCInstrInfo.cpp:50
llvm::HexagonII::PredicatedFalsePos
@ PredicatedFalsePos
Definition: HexagonBaseInfo.h:69
llvm::HexagonMCInstrInfo::deriveExtender
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
Definition: HexagonMCInstrInfo.cpp:184
llvm::HexagonII::TypePos
@ TypePos
Definition: HexagonBaseInfo.h:53
llvm::HexagonII::ExtendablePos
@ ExtendablePos
Definition: HexagonBaseInfo.h:99
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::HexagonII::PredicatedNewMask
@ PredicatedNewMask
Definition: HexagonBaseInfo.h:72
llvm::HexagonMCInstrInfo::IsReverseVecRegPair
bool IsReverseVecRegPair(unsigned VecReg)
Definition: HexagonMCInstrInfo.cpp:684
llvm::HexagonMCInstrInfo::isIntReg
bool isIntReg(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:645
llvm::HexagonMCInstrInfo::IsVecRegPair
bool IsVecRegPair(unsigned VecReg)
Definition: HexagonMCInstrInfo.cpp:679
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::MCInst::size
size_t size() const
Definition: MCInst.h:218
llvm::MCOperand::setImm
void setImm(int64_t Val)
Definition: MCInst.h:85
llvm::HexagonMCInstrInfo::isFloat
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
Definition: HexagonMCInstrInfo.cpp:625
isBranch
static bool isBranch(unsigned Opcode)
Definition: R600InstrInfo.cpp:646
llvm::HexagonII::AddrModePos
@ AddrModePos
Definition: HexagonBaseInfo.h:128
R6
#define R6(n)
llvm::MCInstrInfo::getName
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:68
llvm::HexagonMCInstrInfo::getNewValueOp2
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
Definition: HexagonMCInstrInfo.cpp:397
llvm::HexagonMCInstrInfo::isOuterLoop
bool isOuterLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:673
llvm::HexagonMCInstrInfo::isPrefix
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:724
llvm::HexagonMCInstrInfo::isExtentSigned
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:339
llvm::HexagonII::CofMax1Pos
@ CofMax1Pos
Definition: HexagonBaseInfo.h:117
llvm::HexagonII::TypeDUPLEX
@ TypeDUPLEX
Definition: HexagonDepITypes.h:50
llvm::HexagonII::ExtentAlignMask
@ ExtentAlignMask
Definition: HexagonBaseInfo.h:115
llvm::HexagonII::SoloAXMask
@ SoloAXMask
Definition: HexagonBaseInfo.h:61
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::HexagonStages
const InstrStage HexagonStages[]
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::HexagonMCInstrInfo::getNewValueOperand
const MCOperand & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:378
llvm::HexagonII::TypeCJ
@ TypeCJ
Definition: HexagonDepITypes.h:22
llvm::HexagonMCExpr::setS27_2_reloc
void setS27_2_reloc(bool Val=true)
Definition: HexagonMCExpr.cpp:97
llvm::HexagonII::PrefersSlot3Mask
@ PrefersSlot3Mask
Definition: HexagonBaseInfo.h:155
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::HexagonMCInstrInfo::getExtendableOp
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:309
llvm::HexagonMCInstrInfo::setOuterLoop
void setOuterLoop(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:1002
llvm::HexagonII::hasNewValueMask2
@ hasNewValueMask2
Definition: HexagonBaseInfo.h:144
llvm::HexagonMCInstrInfo::getAddrMode
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:241
llvm::HexagonMCExpr::mustNotExtend
bool mustNotExtend() const
Definition: HexagonMCExpr.cpp:94
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::HexagonII::ExtendedPos
@ ExtendedPos
Definition: HexagonBaseInfo.h:102
HEXAGON_PACKET_INNER_SIZE
#define HEXAGON_PACKET_INNER_SIZE
Definition: HexagonMCTargetDesc.h:39
llvm::HexagonMCInstrInfo::getNewValueOperand2
const MCOperand & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:404
llvm::HexagonII::TypeCVI_FIRST
const unsigned TypeCVI_FIRST
Definition: HexagonBaseInfo.h:27
llvm::MCInst::getLoc
SMLoc getLoc() const
Definition: MCInst.h:204
llvm::HexagonMCInstrInfo::memReorderDisabledMask
const int64_t memReorderDisabledMask
Definition: HexagonMCInstrInfo.h:76
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::MCInst::setLoc
void setLoc(SMLoc loc)
Definition: MCInst.h:203
llvm::DuplexCandidate::packetIndexI
unsigned packetIndexI
Definition: HexagonMCInstrInfo.h:36
llvm::HexagonMCChecker
Check for a valid bundle.
Definition: HexagonMCChecker.h:34
llvm::HexagonMCInstrInfo::getType
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
Definition: HexagonMCInstrInfo.cpp:416
llvm::HexagonMCInstrInfo::deriveDuplex
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
Definition: HexagonMCInstrInfo.cpp:201
llvm::HexagonII::PredicatedFalseMask
@ PredicatedFalseMask
Definition: HexagonBaseInfo.h:70
Casting.h
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::HexagonII::CofRelax2Mask
@ CofRelax2Mask
Definition: HexagonBaseInfo.h:122
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::HexagonMCInstrInfo::getExtendableOperand
const MCOperand & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:316
StringSwitch.h
llvm::HexagonMCInstrInfo::getUnits
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
Definition: HexagonMCInstrInfo.cpp:443
llvm::HexagonMCInstrInfo::IsSingleConsumerRefPairProducer
bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer)
Definition: HexagonMCInstrInfo.cpp:705
llvm::HexagonMCInstrInfo::packetSizeSlots
unsigned packetSizeSlots(MCSubtargetInfo const &STI)
Definition: HexagonMCInstrInfo.cpp:902
llvm::HexagonII::ExtentBitsPos
@ ExtentBitsPos
Definition: HexagonBaseInfo.h:111
llvm::HexagonMCInstrInfo::instruction
const MCInst & instruction(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:519
HEXAGON_PACKET_OUTER_SIZE
#define HEXAGON_PACKET_OUTER_SIZE
Definition: HexagonMCTargetDesc.h:40
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::HexagonII::ExtentAlignPos
@ ExtentAlignPos
Definition: HexagonBaseInfo.h:114
llvm::HexagonII::TypeNCJ
@ TypeNCJ
Definition: HexagonDepITypes.h:57
llvm::HexagonMCInstrInfo::isNewValueStore
bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI)
Return true if the operand is a new-value store insn.
Definition: HexagonMCInstrInfo.cpp:661
llvm::HexagonII::NewValueOpPos2
@ NewValueOpPos2
Definition: HexagonBaseInfo.h:146
llvm::HexagonMCInstrInfo::isHVX
bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:630
llvm::HexagonII::isCVIPos
@ isCVIPos
Definition: HexagonBaseInfo.h:164
llvm::HexagonMCInstrInfo::getMaxValue
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
Definition: HexagonMCInstrInfo.cpp:346
llvm::HexagonII::PredicatedNewPos
@ PredicatedNewPos
Definition: HexagonBaseInfo.h:71
llvm::HexagonII::SoloAXPos
@ SoloAXPos
Definition: HexagonBaseInfo.h:60
SmallVector.h
llvm::HexagonII::TypeMask
@ TypeMask
Definition: HexagonBaseInfo.h:54
llvm::HexagonMCInstrInfo::padEndloop
void padEndloop(MCInst &MCI, MCContext &Context)
Definition: HexagonMCInstrInfo.cpp:914
N
#define N
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::HexagonMCInstrInfo::getExpr
const MCExpr & getExpr(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:303
llvm::HexagonII::isCVIMask
@ isCVIMask
Definition: HexagonBaseInfo.h:165
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::HexagonII::HasTmpDstMask
@ HasTmpDstMask
Definition: HexagonBaseInfo.h:159
llvm::InstrItinerary::LastStage
uint16_t LastStage
Index of last + 1 stage in itinerary.
Definition: MCInstrItineraries.h:101
llvm::HexagonMCInstrInfo::getMinValue
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
Definition: HexagonMCInstrInfo.cpp:357
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::HexagonII::TypeJ
@ TypeJ
Definition: HexagonDepITypes.h:53
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::HexagonMCInstrInfo::isExtended
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:619
llvm::HexagonII::ExtendableOpMask
@ ExtendableOpMask
Definition: HexagonBaseInfo.h:106
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::HexagonII::PredicateLateMask
@ PredicateLateMask
Definition: HexagonBaseInfo.h:74
llvm::HexagonMCInstrInfo::isSolo
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
Definition: HexagonMCInstrInfo.cpp:783
llvm::HexagonII::TypeCVI_LAST
const unsigned TypeCVI_LAST
Definition: HexagonBaseInfo.h:28
llvm::HexagonMCInstrInfo::isPredRegister
bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I)
Definition: HexagonMCInstrInfo.cpp:753
llvm::HexagonII::ExtendedMask
@ ExtendedMask
Definition: HexagonBaseInfo.h:103
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
llvm::HexagonMCInstrInfo::GetVecRegPairIndices
std::pair< unsigned, unsigned > GetVecRegPairIndices(unsigned VecRegPair)
Returns an ordered pair of the constituent register ordinals for each of the elements of VecRegPair.
Definition: HexagonMCInstrInfo.cpp:693
llvm::Hexagon::PacketIterator::PacketIterator
PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
Definition: HexagonMCInstrInfo.cpp:39
llvm::HexagonMCInstrInfo::slotsConsumed
unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:959
MCExpr.h
llvm::HexagonMCInstrInfo::isPredicateLate
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:728
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::MCSchedModel::InstrItineraries
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:312
llvm::HexagonII::NVStorePos
@ NVStorePos
Definition: HexagonBaseInfo.h:89
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::HexagonMCExpr::setMustExtend
void setMustExtend(bool Val=true)
Definition: HexagonMCExpr.cpp:84
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::HexagonII::NewValueOpMask2
@ NewValueOpMask2
Definition: HexagonBaseInfo.h:147
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1172
llvm::HexagonMCInstrInfo::isPredicatedNew
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
Definition: HexagonMCInstrInfo.cpp:735
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:613
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
llvm::HexagonMCInstrInfo::isInnerLoop
bool isInnerLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:639