LLVM 17.0.0git
HexagonMCInstrInfo.cpp
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1//===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
10//
11//===----------------------------------------------------------------------===//
12
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCExpr.h"
23#include "llvm/MC/MCInst.h"
24#include "llvm/MC/MCInstrInfo.h"
29#include <cassert>
30#include <cstdint>
31#include <limits>
32
33using namespace llvm;
34
36 return Register != Hexagon::NoRegister;
37}
38
40 MCInst const &Inst)
41 : MCII(MCII), BundleCurrent(Inst.begin() +
42 HexagonMCInstrInfo::bundleInstructionsOffset),
43 BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
44
46 MCInst const &Inst, std::nullptr_t)
47 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
48 DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
49
51 if (DuplexCurrent != DuplexEnd) {
52 ++DuplexCurrent;
53 if (DuplexCurrent == DuplexEnd) {
54 DuplexCurrent = BundleEnd;
55 DuplexEnd = BundleEnd;
56 ++BundleCurrent;
57 }
58 return *this;
59 }
60 ++BundleCurrent;
61 if (BundleCurrent != BundleEnd) {
62 MCInst const &Inst = *BundleCurrent->getInst();
63 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
64 DuplexCurrent = Inst.begin();
65 DuplexEnd = Inst.end();
66 }
67 }
68 return *this;
69}
70
72 if (DuplexCurrent != DuplexEnd)
73 return *DuplexCurrent->getInst();
74 return *BundleCurrent->getInst();
75}
76
78 return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
79 DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
80}
81
83 MCContext &Context) {
85}
86
88 MCInstrInfo const &MCII, MCInst &MCB,
89 MCInst const &MCI) {
91 MCOperand const &exOp =
93
94 // Create the extender.
95 MCInst *XMCI =
97 XMCI->setLoc(MCI.getLoc());
98
100}
101
104 MCInst const &MCI) {
105 assert(isBundle(MCI));
106 return make_range(Hexagon::PacketIterator(MCII, MCI),
107 Hexagon::PacketIterator(MCII, MCI, nullptr));
108}
109
112 assert(isBundle(MCI));
114}
115
118 return (MCI.size() - bundleInstructionsOffset);
119 else
120 return (1);
121}
122
123namespace {
124bool canonicalizePacketImpl(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
125 MCContext &Context, MCInst &MCB,
126 HexagonMCChecker *Check) {
127 // Check the bundle for errors.
128 bool CheckOk = Check ? Check->check(false) : true;
129 if (!CheckOk)
130 return false;
131
132 MCInst OrigMCB = MCB;
133
134 // Examine the packet and convert pairs of instructions to compound
135 // instructions when possible.
137 HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
138 HexagonMCShuffle(Context, false, MCII, STI, MCB);
139
140 const SmallVector<DuplexCandidate, 8> possibleDuplexes =
141 (STI.getFeatureBits()[Hexagon::FeatureDuplex])
144
145 // Examine the packet and convert pairs of instructions to duplex
146 // instructions when possible.
147 HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
148
149 // Examines packet and pad the packet, if needed, when an
150 // end-loop is in the bundle.
151 HexagonMCInstrInfo::padEndloop(MCB, Context);
152
153 // If compounding and duplexing didn't reduce the size below
154 // 4 or less we have a packet that is too big.
156 if (Check)
157 Check->reportError("invalid instruction packet: out of slots");
158 return false;
159 }
160 // Check the bundle for errors.
161 CheckOk = Check ? Check->check(true) : true;
162 if (!CheckOk)
163 return false;
164
165 HexagonMCShuffle(Context, true, MCII, STI, MCB);
166
167 return true;
168}
169} // namespace
170
172 MCSubtargetInfo const &STI,
173 MCContext &Context, MCInst &MCB,
174 HexagonMCChecker *Check,
175 bool AttemptCompatibility) {
176 auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
177 if (!AttemptCompatibility || ArchSTI == nullptr)
178 return canonicalizePacketImpl(MCII, STI, Context, MCB, Check);
179
180 const MCRegisterInfo *RI = Context.getRegisterInfo();
181 HexagonMCChecker DefaultCheck(Context, MCII, STI, MCB, *RI, false);
182 HexagonMCChecker *BaseCheck = (Check == nullptr) ? &DefaultCheck : Check;
183 HexagonMCChecker PerfCheck(*BaseCheck, STI, false);
184 if (canonicalizePacketImpl(MCII, STI, Context, MCB, &PerfCheck))
185 return true;
186
187 HexagonMCChecker ArchCheck(*BaseCheck, *ArchSTI, true);
188 return canonicalizePacketImpl(MCII, *ArchSTI, Context, MCB, &ArchCheck);
189}
190
192 MCInst const &Inst,
193 MCOperand const &MO) {
196
197 MCInst XMI;
198 XMI.setOpcode(Hexagon::A4_ext);
199 if (MO.isImm())
200 XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
201 else if (MO.isExpr())
203 else
204 llvm_unreachable("invalid extendable operand");
205 return XMI;
206}
207
209 MCInst const &inst0,
210 MCInst const &inst1) {
211 assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
212 MCInst *duplexInst = new (Context) MCInst;
213 duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
214
215 MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
216 MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
217 duplexInst->addOperand(MCOperand::createInst(SubInst0));
218 duplexInst->addOperand(MCOperand::createInst(SubInst1));
219 return duplexInst;
220}
221
223 size_t Index) {
224 assert(Index <= bundleSize(MCB));
225 if (Index == 0)
226 return nullptr;
227 MCInst const *Inst =
229 if (isImmext(*Inst))
230 return Inst;
231 return nullptr;
232}
233
235 MCInstrInfo const &MCII, MCInst &MCB,
236 MCInst const &MCI) {
237 if (isConstExtended(MCII, MCI))
238 addConstExtender(Context, MCII, MCB, MCI);
239}
240
242 MCInst const &MCI) {
246}
247
249 MCInst const &MCI) {
251 return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
253}
254
256 MCInst const &MCI) {
257 return MCII.get(MCI.getOpcode());
258}
259
261 using namespace Hexagon;
262
263 switch (Reg) {
264 default:
265 llvm_unreachable("unknown duplex register");
266 // Rs Rss
267 case R0:
268 case D0:
269 return 0;
270 case R1:
271 case D1:
272 return 1;
273 case R2:
274 case D2:
275 return 2;
276 case R3:
277 case D3:
278 return 3;
279 case R4:
280 case D8:
281 return 4;
282 case R5:
283 case D9:
284 return 5;
285 case R6:
286 case D10:
287 return 6;
288 case R7:
289 case D11:
290 return 7;
291 case R16:
292 return 8;
293 case R17:
294 return 9;
295 case R18:
296 return 10;
297 case R19:
298 return 11;
299 case R20:
300 return 12;
301 case R21:
302 return 13;
303 case R22:
304 return 14;
305 case R23:
306 return 15;
307 }
308}
309
311 const auto &HExpr = cast<HexagonMCExpr>(Expr);
312 assert(HExpr.getExpr());
313 return *HExpr.getExpr();
314}
315
317 MCInst const &MCI) {
320}
321
322MCOperand const &
324 MCInst const &MCI) {
325 unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
326 MCOperand const &MO = MCI.getOperand(O);
327
329 HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
330 (MO.isImm() || MO.isExpr()));
331 return (MO);
332}
333
335 MCInst const &MCI) {
338}
339
341 MCInst const &MCI) {
344}
345
347 MCInst const &MCI) {
350}
351
352/// Return the maximum value of an extendable operand.
354 MCInst const &MCI) {
357
358 if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
359 return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
360 return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
361}
362
363/// Return the minimum value of an extendable operand.
365 MCInst const &MCI) {
368
369 if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
370 return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
371 return 0;
372}
373
375 MCInst const &MCI) {
376 return MCII.getName(MCI.getOpcode());
377}
378
380 MCInst const &MCI) {
383}
384
386 MCInst const &MCI) {
387 if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
388 // VTMP doesn't actually exist in the encodings for these 184
389 // 3 instructions so go ahead and create it here.
390 static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
391 return (MCO);
392 } else {
393 unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
394 MCOperand const &MCO = MCI.getOperand(O);
395
398 MCO.isReg());
399 return (MCO);
400 }
401}
402
403/// Return the new value or the newly produced value.
405 MCInst const &MCI) {
408}
409
410MCOperand const &
412 MCInst const &MCI) {
413 unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
414 MCOperand const &MCO = MCI.getOperand(O);
415
418 MCO.isReg());
419 return (MCO);
420}
421
422/// Return the Hexagon ISA class for the insn.
424 MCInst const &MCI) {
425 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
427}
428
429/// Return the resources used by this instruction
431 MCSubtargetInfo const &STI,
432 MCInst const &MCI) {
433
435 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
436 int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage;
437
438 // HVX resources used are currenty located at the second to last stage.
439 // This could also be done with a linear search of the stages looking for:
440 // CVI_ALL, CVI_MPY01, CVI_XLSHF, CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE,
441 // CVI_ZW
442 unsigned Stage = II[SchedClass].LastStage - 1;
443
444 if (Size < 2)
445 return 0;
446 return ((Stage + HexagonStages)->getUnits());
447}
448
449/// Return the slots this instruction can execute out of
451 MCSubtargetInfo const &STI,
452 MCInst const &MCI) {
454 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
455 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
456}
457
458/// Return the slots this instruction consumes in addition to
459/// the slot(s) it can execute out of
460
462 MCSubtargetInfo const &STI,
463 MCInst const &MCI) {
465 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
466 unsigned Slots = 0;
467
468 // FirstStage are slots that this instruction can execute in.
469 // FirstStage+1 are slots that are also consumed by this instruction.
470 // For example: vmemu can only execute in slot 0 but also consumes slot 1.
471 for (unsigned Stage = II[SchedClass].FirstStage + 1;
472 Stage < II[SchedClass].LastStage; ++Stage) {
473 unsigned Units = (Stage + HexagonStages)->getUnits();
474 if (Units > HexagonGetLastSlot())
475 break;
476 // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
477 Slots |= Units;
478 }
479
480 // if 0 is returned, then no additional slots are consumed by this inst.
481 return Slots;
482}
483
484bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
486 return false;
487
488 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
489 if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
490 return true;
491 }
492
493 return false;
494}
495
497 return extenderForIndex(MCB, Index) != nullptr;
498}
499
502 return false;
503
504 for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
505 if (isImmext(*I.getInst()))
506 return true;
507 }
508
509 return false;
510}
511
512/// Return whether the insn produces a value.
514 MCInst const &MCI) {
517}
518
519/// Return whether the insn produces a second value.
521 MCInst const &MCI) {
524}
525
527 assert(isBundle(MCB));
530}
531
532/// Return where the instruction is an accumulator.
534 MCInst const &MCI) {
537}
538
540 auto Result = Hexagon::BUNDLE == MCI.getOpcode();
541 assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
542 return Result;
543}
544
546 MCInst const &MCI) {
547 if (HexagonMCInstrInfo::isExtended(MCII, MCI))
548 return true;
549 if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
550 return false;
552 if (isa<HexagonMCExpr>(MO.getExpr()) &&
554 return true;
555 // Branch insns are handled as necessary by relaxation.
556 if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
561 return false;
562 // Otherwise loop instructions and other CR insts are handled by relaxation
563 else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
564 (MCI.getOpcode() != Hexagon::C4_addipc))
565 return false;
566
567 assert(!MO.isImm());
568 if (isa<HexagonMCExpr>(MO.getExpr()) &&
570 return false;
571 int64_t Value;
572 if (!MO.getExpr()->evaluateAsAbsolute(Value))
573 return true;
574 int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
575 int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
576 return (MinValue > Value || Value > MaxValue);
577}
578
579bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
580 return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
582}
583
584bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
587}
588
590 MCInst const &MCI) {
593}
594
596 MCInst const &MCI) {
599}
600
602 MCInst const &MCI) {
603 return (getType(MCII, MCI) == HexagonII::TypeCJ);
604}
605
606bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
609}
610
612 return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
613 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
614}
615
616bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
618}
619
621 MCInst const &MCI) {
624}
625
627 MCInst const &MCI) {
630}
631
632bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
634 return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
635}
636
637bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
638 const uint64_t V = getType(MCII, MCI);
640}
641
643 return MCI.getOpcode() == Hexagon::A4_ext;
644}
645
647 assert(isBundle(MCI));
648 int64_t Flags = MCI.getOperand(0).getImm();
649 return (Flags & innerLoopMask) != 0;
650}
651
653 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
654}
655
657 return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
658 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
659}
660
661/// Return whether the insn expects newly produced value.
663 MCInst const &MCI) {
666}
667
669 MCInst const &MCI) {
672}
673
674/// Return whether the operand is extendable.
676 MCInst const &MCI, unsigned short O) {
677 return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
678}
679
681 assert(isBundle(MCI));
682 int64_t Flags = MCI.getOperand(0).getImm();
683 return (Flags & outerLoopMask) != 0;
684}
685
686bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) {
687 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) ||
688 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
689}
690
692 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
693}
694
696 return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31);
697}
698
699std::pair<unsigned, unsigned>
701 assert(IsVecRegPair(VecRegPair) &&
702 "VecRegPair must be a vector register pair");
703
704 const bool IsRev = IsReverseVecRegPair(VecRegPair);
705 const unsigned PairIndex =
706 2 * (IsRev ? VecRegPair - Hexagon::WR0 : VecRegPair - Hexagon::W0);
707
708 return IsRev ? std::make_pair(PairIndex, PairIndex + 1)
709 : std::make_pair(PairIndex + 1, PairIndex);
710}
711
713 unsigned Consumer) {
714 if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) {
715 const unsigned ProdPairIndex = IsReverseVecRegPair(Producer)
716 ? Producer - Hexagon::WR0
717 : Producer - Hexagon::W0;
718 const unsigned ConsumerSingleIndex = (Consumer - Hexagon::V0) >> 1;
719
720 return ConsumerSingleIndex == ProdPairIndex;
721 }
722 return false;
723}
724
726 MCInst const &MCI) {
729}
730
731bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
733}
734
736 MCInst const &MCI) {
739}
740
741/// Return whether the insn is newly predicated.
743 MCInst const &MCI) {
746}
747
749 MCInst const &MCI) {
751 return (
753}
754
756 auto &PredRegClass = MRI.getRegClass(Hexagon::PredRegsRegClassID);
757 return PredRegClass.contains(Reg);
758}
759
761 MCInst const &Inst, unsigned I) {
762 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);
763
764 return Inst.getOperand(I).isReg() &&
765 Desc.operands()[I].RegClass == Hexagon::PredRegsRegClassID;
766}
767
768/// Return whether the insn can be packaged only with A and X-type insns.
769bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
772}
773
774/// Return whether the insn can be packaged only with an A-type insn in slot #1.
776 MCInst const &MCI) {
778 return ((F >> HexagonII::RestrictSlot1AOKPos) &
780}
781
783 MCInst const &MCI) {
787}
788
789/// Return whether the insn is solo, i.e., cannot be in a packet.
790bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
791 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
793}
794
796 assert(isBundle(MCI));
797 auto Flags = MCI.getOperand(0).getImm();
798 return (Flags & memReorderDisabledMask) != 0;
799}
800
802 switch (MCI.getOpcode()) {
803 default:
804 return false;
805 case Hexagon::SA1_addi:
806 case Hexagon::SA1_addrx:
807 case Hexagon::SA1_addsp:
808 case Hexagon::SA1_and1:
809 case Hexagon::SA1_clrf:
810 case Hexagon::SA1_clrfnew:
811 case Hexagon::SA1_clrt:
812 case Hexagon::SA1_clrtnew:
813 case Hexagon::SA1_cmpeqi:
814 case Hexagon::SA1_combine0i:
815 case Hexagon::SA1_combine1i:
816 case Hexagon::SA1_combine2i:
817 case Hexagon::SA1_combine3i:
818 case Hexagon::SA1_combinerz:
819 case Hexagon::SA1_combinezr:
820 case Hexagon::SA1_dec:
821 case Hexagon::SA1_inc:
822 case Hexagon::SA1_seti:
823 case Hexagon::SA1_setin1:
824 case Hexagon::SA1_sxtb:
825 case Hexagon::SA1_sxth:
826 case Hexagon::SA1_tfr:
827 case Hexagon::SA1_zxtb:
828 case Hexagon::SA1_zxth:
829 case Hexagon::SL1_loadri_io:
830 case Hexagon::SL1_loadrub_io:
831 case Hexagon::SL2_deallocframe:
832 case Hexagon::SL2_jumpr31:
833 case Hexagon::SL2_jumpr31_f:
834 case Hexagon::SL2_jumpr31_fnew:
835 case Hexagon::SL2_jumpr31_t:
836 case Hexagon::SL2_jumpr31_tnew:
837 case Hexagon::SL2_loadrb_io:
838 case Hexagon::SL2_loadrd_sp:
839 case Hexagon::SL2_loadrh_io:
840 case Hexagon::SL2_loadri_sp:
841 case Hexagon::SL2_loadruh_io:
842 case Hexagon::SL2_return:
843 case Hexagon::SL2_return_f:
844 case Hexagon::SL2_return_fnew:
845 case Hexagon::SL2_return_t:
846 case Hexagon::SL2_return_tnew:
847 case Hexagon::SS1_storeb_io:
848 case Hexagon::SS1_storew_io:
849 case Hexagon::SS2_allocframe:
850 case Hexagon::SS2_storebi0:
851 case Hexagon::SS2_storebi1:
852 case Hexagon::SS2_stored_sp:
853 case Hexagon::SS2_storeh_io:
854 case Hexagon::SS2_storew_sp:
855 case Hexagon::SS2_storewi0:
856 case Hexagon::SS2_storewi1:
857 return true;
858 }
859}
860
861bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
864}
865
866int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
867 auto Sentinel = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
868 << 8;
869 if (MCI.size() <= Index)
870 return Sentinel;
871 MCOperand const &MCO = MCI.getOperand(Index);
872 if (!MCO.isExpr())
873 return Sentinel;
874 int64_t Value;
875 if (!MCO.getExpr()->evaluateAsAbsolute(Value))
876 return Sentinel;
877 return Value;
878}
879
880void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
881 HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
882 HExpr.setMustExtend(Val);
883}
884
886 HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
887 return HExpr.mustExtend();
888}
889void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
890 HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
891 HExpr.setMustNotExtend(Val);
892}
894 HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
895 return HExpr.mustNotExtend();
896}
897void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
898 HexagonMCExpr &HExpr =
899 const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
900 HExpr.setS27_2_reloc(Val);
901}
903 HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
904 if (!HExpr)
905 return false;
906 return HExpr->s27_2_reloc();
907}
908
910 const bool IsTiny = STI.getFeatureBits()[Hexagon::ProcTinyCore];
911
912 return IsTiny ? (HEXAGON_PACKET_SIZE - 1) : HEXAGON_PACKET_SIZE;
913}
914
917 .Case("hexagonv67t", 3)
918 .Default(4);
919}
920
922 MCInst Nop;
923 Nop.setOpcode(Hexagon::A2_nop);
924 assert(isBundle(MCB));
925 while (LoopNeedsPadding(MCB))
927}
928
931 if (!isPredicated(MCII, MCI))
932 return {0, 0, false};
933 MCInstrDesc const &Desc = getDesc(MCII, MCI);
934 for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
935 if (Desc.operands()[I].RegClass == Hexagon::PredRegsRegClassID)
936 return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
937 return {0, 0, false};
938}
939
941 MCInst const &MCI) {
944}
945
946bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
947 switch (MCI.getOpcode()) {
948 default:
949 return false;
950 case Hexagon::V6_vgathermh:
951 case Hexagon::V6_vgathermhq:
952 case Hexagon::V6_vgathermhw:
953 case Hexagon::V6_vgathermhwq:
954 case Hexagon::V6_vgathermw:
955 case Hexagon::V6_vgathermwq:
956 return true;
957 }
958 return false;
959}
960
961bool HexagonMCInstrInfo::hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI) {
964}
965
967 MCInst const &MCI) {
968 const unsigned OpCode = MCI.getOpcode();
969 const bool IsTiny = STI.getFeatureBits() [Hexagon::ProcTinyCore];
970 const bool NoSlotReqd = Hexagon::A4_ext == OpCode ||
971 (IsTiny && Hexagon::A2_nop == OpCode) ||
972 (IsTiny && Hexagon::J4_hintjumpr == OpCode);
973
974 return !NoSlotReqd;
975}
976
978 MCSubtargetInfo const &STI,
979 MCInst const &MCI) {
980 unsigned slotsUsed = 0;
981 for (auto HMI : bundleInstructions(MCI)) {
982 MCInst const &MCI = *HMI.getInst();
983 if (!requiresSlot(STI, MCI))
984 continue;
985 if (isDuplex(MCII, MCI))
986 slotsUsed += 2;
987 else
988 ++slotsUsed;
989 }
990 return slotsUsed;
991}
992
994 DuplexCandidate Candidate) {
995 assert(Candidate.packetIndexI < MCB.size());
996 assert(Candidate.packetIndexJ < MCB.size());
997 assert(isBundle(MCB));
998 MCInst *Duplex =
999 deriveDuplex(Context, Candidate.iClass,
1000 *MCB.getOperand(Candidate.packetIndexJ).getInst(),
1001 *MCB.getOperand(Candidate.packetIndexI).getInst());
1002 assert(Duplex != nullptr);
1003 MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
1004 MCB.erase(MCB.begin() + Candidate.packetIndexJ);
1005}
1006
1008 assert(isBundle(MCI));
1009 MCOperand &Operand = MCI.getOperand(0);
1010 Operand.setImm(Operand.getImm() | innerLoopMask);
1011}
1012
1014 assert(isBundle(MCI));
1015 MCOperand &Operand = MCI.getOperand(0);
1016 Operand.setImm(Operand.getImm() | memReorderDisabledMask);
1018}
1019
1021 assert(isBundle(MCI));
1022 MCOperand &Operand = MCI.getOperand(0);
1023 Operand.setImm(Operand.getImm() | outerLoopMask);
1024}
1025
1026unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
1027 unsigned Producer,
1028 unsigned Producer2) {
1029 // If we're a single vector consumer of a double producer, set subreg bit
1030 // based on if we're accessing the lower or upper register component
1031 if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer))
1032 return (Consumer - Hexagon::V0) & 0x1;
1033 if (Producer2 != Hexagon::NoRegister)
1034 return Consumer == Producer;
1035 return 0;
1036}
1037
1039 return (
1044}
1045
1047 MCSubtargetInfo const &STI,
1048 MCInst const &I) {
1050 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
1051 return (Desc.isBranch() || Desc.isCall() || Desc.isReturn());
1052}
unsigned const MachineRegisterInfo * MRI
uint64_t Size
#define HEXAGON_PACKET_OUTER_SIZE
#define HEXAGON_PACKET_INNER_SIZE
#define HEXAGON_PACKET_SIZE
#define HEXAGON_PRESHUFFLE_PACKET_SIZE
IRTranslator LLVM IR MI
#define Check(C,...)
Definition: Lint.cpp:170
static M68kRelType getType(unsigned Kind, MCSymbolRefExpr::VariantKind &Modifier, bool &IsPCRel)
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define R4(n)
#define R2(n)
#define R6(n)
LLVMContext & Context
static bool isBranch(unsigned Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Check for a valid bundle.
void setMustNotExtend(bool Val=true)
bool mustNotExtend() const
bool mustExtend() const
bool s27_2_reloc() const
void setMustExtend(bool Val=true)
void setS27_2_reloc(bool Val=true)
bool operator==(PacketIterator const &Other) const
MCInst const & operator*() const
PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void erase(iterator I)
Definition: MCInst.h:216
SMLoc getLoc() const
Definition: MCInst.h:204
void setLoc(SMLoc loc)
Definition: MCInst.h:203
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
iterator begin()
Definition: MCInst.h:219
iterator end()
Definition: MCInst.h:221
size_t size() const
Definition: MCInst.h:218
void setOpcode(unsigned Op)
Definition: MCInst.h:197
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:596
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:247
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:306
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:287
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:275
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MCInstrDesc.h:268
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:70
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
void setImm(int64_t Val)
Definition: MCInst.h:85
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
int64_t getImm() const
Definition: MCInst.h:80
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
void setInst(const MCInst *Val)
Definition: MCInst.h:129
const MCInst * getInst() const
Definition: MCInst.h:124
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:169
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
LLVM Value Representation.
Definition: Value.h:74
A range adaptor for a pair of iterators.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned const TypeCVI_LAST
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
unsigned const TypeCVI_FIRST
bool IsReverseVecRegPair(unsigned VecReg)
bool isDblRegForSubInst(unsigned Reg)
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst deriveSubInst(MCInst const &Inst)
bool hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI)
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
bool isOuterLoop(MCInst const &MCI)
bool isIntRegForSubInst(unsigned Reg)
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &I)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
bool IsVecRegPair(unsigned VecReg)
unsigned getCVIResources(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the resources used by this instruction.
void padEndloop(MCInst &MCI, MCContext &Context)
constexpr int64_t memReorderDisabledMask
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg)
bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
bool isMemReorderDisabled(MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
std::pair< unsigned, unsigned > GetVecRegPairIndices(unsigned VecRegPair)
Returns an ordered pair of the constituent register ordinals for each of the elements of VecRegPair.
bool mustNotExtend(MCExpr const &Expr)
bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI)
Return true if the operand is a new-value store insn.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool LoopNeedsPadding(MCInst const &MCB)
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
void setMemReorderDisabled(MCInst &MCI)
bool isBundle(MCInst const &MCI)
int64_t minConstant(MCInst const &MCI, size_t Index)
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
MCExpr const & getExpr(MCExpr const &Expr)
bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer)
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
bool isImmext(MCInst const &MCI)
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I)
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
constexpr int64_t innerLoopMask
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
constexpr size_t bundleInstructionsOffset
bool s27_2_reloc(MCExpr const &Expr)
bool hasImmExt(MCInst const &MCI)
bool isInnerLoop(MCInst const &MCI)
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned packetSizeSlots(MCSubtargetInfo const &STI)
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
constexpr int64_t outerLoopMask
MCInst const & instruction(MCInst const &MCB, size_t Index)
bool IsVecRegSingle(unsigned VecReg)
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
bool mustExtend(MCExpr const &Expr)
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getDuplexRegisterNumbering(unsigned Reg)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isSubInstruction(MCInst const &MCI)
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
void setMustExtend(MCExpr const &Expr, bool Val=true)
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned packetSize(StringRef CPU)
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:386
cl::opt< bool > HexagonDisableCompound
bool HexagonMCShuffle(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
unsigned HexagonGetLastSlot()
const InstrStage HexagonStages[]
#define N
An itinerary represents the scheduling information for an instruction.
uint16_t FirstStage
Index of first stage in itinerary.
uint16_t LastStage
Index of last + 1 stage in itinerary.
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:311