LLVM  15.0.0git
X86CustomBehaviour.cpp
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1 //===------------------- X86CustomBehaviour.cpp -----------------*-C++ -* -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file implements methods from the X86CustomBehaviour class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86CustomBehaviour.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/MC/TargetRegistry.h"
18 #include "llvm/Support/WithColor.h"
19 
20 namespace llvm {
21 namespace mca {
22 
23 void X86InstrPostProcess::setMemBarriers(std::unique_ptr<Instruction> &Inst,
24  const MCInst &MCI) {
25  switch (MCI.getOpcode()) {
26  case X86::MFENCE:
27  Inst->setLoadBarrier(true);
28  Inst->setStoreBarrier(true);
29  break;
30  case X86::LFENCE:
31  Inst->setLoadBarrier(true);
32  break;
33  case X86::SFENCE:
34  Inst->setStoreBarrier(true);
35  break;
36  }
37 }
38 
40  std::unique_ptr<Instruction> &Inst, const MCInst &MCI) {
41  // Currently, we only modify certain instructions' IsALoadBarrier and
42  // IsAStoreBarrier flags.
43  setMemBarriers(Inst, MCI);
44 }
45 
46 } // namespace mca
47 } // namespace llvm
48 
49 using namespace llvm;
50 using namespace mca;
51 
53  const MCInstrInfo &MCII) {
54  return new X86InstrPostProcess(STI, MCII);
55 }
56 
57 /// Extern function to initialize the targets for the X86 backend
58 
64 }
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::mca::X86InstrPostProcess
Definition: X86CustomBehaviour.h:27
llvm::getTheX86_64Target
Target & getTheX86_64Target()
Definition: X86TargetInfo.cpp:17
createX86InstrPostProcess
static InstrPostProcess * createX86InstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)
Definition: X86CustomBehaviour.cpp:52
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::X86ISD::MFENCE
@ MFENCE
Definition: X86ISelLowering.h:664
llvm::TargetRegistry::RegisterInstrPostProcess
static void RegisterInstrPostProcess(Target &T, Target::InstrPostProcessCtorTy Fn)
RegisterInstrPostProcess - Register an InstrPostProcess implementation for the given target.
Definition: TargetRegistry.h:1076
llvm::getTheX86_32Target
Target & getTheX86_32Target()
Definition: X86TargetInfo.cpp:13
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
LLVMInitializeX86TargetMCA
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86TargetMCA()
Extern function to initialize the targets for the X86 backend.
Definition: X86CustomBehaviour.cpp:59
llvm::mca::InstrPostProcess
Class which can be overriden by targets to modify the mca::Instruction objects before the pipeline st...
Definition: CustomBehaviour.h:35
WithColor.h
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::mca::X86InstrPostProcess::postProcessInstruction
void postProcessInstruction(std::unique_ptr< Instruction > &Inst, const MCInst &MCI) override
This method can be overriden by targets to modify the mca::Instruction object after it has been lower...
Definition: X86CustomBehaviour.cpp:39
X86CustomBehaviour.h
X86InstrInfo.h
X86TargetInfo.h
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76