LLVM  10.0.0svn
InstructionSelect.cpp
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the InstructionSelect class.
10 //===----------------------------------------------------------------------===//
11 
14 #include "llvm/ADT/Twine.h"
24 #include "llvm/Config/config.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/Function.h"
28 #include "llvm/Support/Debug.h"
30 
31 #define DEBUG_TYPE "instruction-select"
32 
33 using namespace llvm;
34 
35 #ifdef LLVM_GISEL_COV_PREFIX
37  CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
38  cl::desc("Record GlobalISel rule coverage files of this "
39  "prefix if instrumentation was generated"));
40 #else
41 static const std::string CoveragePrefix = "";
42 #endif
43 
44 char InstructionSelect::ID = 0;
46  "Select target instructions out of generic instructions",
47  false, false)
51  "Select target instructions out of generic instructions",
52  false, false)
53 
54 InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) { }
55 
62 }
63 
65  // If the ISel pipeline failed, do not bother running that pass.
66  if (MF.getProperties().hasProperty(
68  return false;
69 
70  LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
71  GISelKnownBits &KB = getAnalysis<GISelKnownBitsAnalysis>().get(MF);
72 
73  const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
75  CodeGenCoverage CoverageInfo;
76  assert(ISel && "Cannot work without InstructionSelector");
77  ISel->setupMF(MF, KB, CoverageInfo);
78 
79  // An optimization remark emitter. Used to report failures.
80  MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
81 
82  // FIXME: There are many other MF/MFI fields we need to initialize.
83 
85 #ifndef NDEBUG
86  // Check that our input is fully legal: we require the function to have the
87  // Legalized property, so it should be.
88  // FIXME: This should be in the MachineVerifier, as the RegBankSelected
89  // property check already is.
91  if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
92  reportGISelFailure(MF, TPC, MORE, "gisel-select",
93  "instruction is not legal", *MI);
94  return false;
95  }
96  // FIXME: We could introduce new blocks and will need to fix the outer loop.
97  // Until then, keep track of the number of blocks to assert that we don't.
98  const size_t NumBlocks = MF.size();
99 #endif
100 
101  for (MachineBasicBlock *MBB : post_order(&MF)) {
102  if (MBB->empty())
103  continue;
104 
105  // Select instructions in reverse block order. We permit erasing so have
106  // to resort to manually iterating and recognizing the begin (rend) case.
107  bool ReachedBegin = false;
108  for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
109  !ReachedBegin;) {
110 #ifndef NDEBUG
111  // Keep track of the insertion range for debug printing.
112  const auto AfterIt = std::next(MII);
113 #endif
114  // Select this instruction.
115  MachineInstr &MI = *MII;
116 
117  // And have our iterator point to the next instruction, if there is one.
118  if (MII == Begin)
119  ReachedBegin = true;
120  else
121  --MII;
122 
123  LLVM_DEBUG(dbgs() << "Selecting: \n " << MI);
124 
125  // We could have folded this instruction away already, making it dead.
126  // If so, erase it.
127  if (isTriviallyDead(MI, MRI)) {
128  LLVM_DEBUG(dbgs() << "Is dead; erasing.\n");
130  continue;
131  }
132 
133  if (!ISel->select(MI)) {
134  // FIXME: It would be nice to dump all inserted instructions. It's
135  // not obvious how, esp. considering select() can insert after MI.
136  reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
137  return false;
138  }
139 
140  // Dump the range of instructions that MI expanded into.
141  LLVM_DEBUG({
142  auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
143  dbgs() << "Into:\n";
144  for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
145  dbgs() << " " << InsertedMI;
146  dbgs() << '\n';
147  });
148  }
149  }
150 
151  for (MachineBasicBlock &MBB : MF) {
152  if (MBB.empty())
153  continue;
154 
155  // Try to find redundant copies b/w vregs of the same register class.
156  bool ReachedBegin = false;
157  for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
158  // Select this instruction.
159  MachineInstr &MI = *MII;
160 
161  // And have our iterator point to the next instruction, if there is one.
162  if (MII == Begin)
163  ReachedBegin = true;
164  else
165  --MII;
166  if (MI.getOpcode() != TargetOpcode::COPY)
167  continue;
168  Register SrcReg = MI.getOperand(1).getReg();
169  Register DstReg = MI.getOperand(0).getReg();
170  if (Register::isVirtualRegister(SrcReg) &&
171  Register::isVirtualRegister(DstReg)) {
172  auto SrcRC = MRI.getRegClass(SrcReg);
173  auto DstRC = MRI.getRegClass(DstReg);
174  if (SrcRC == DstRC) {
175  MRI.replaceRegWith(DstReg, SrcReg);
177  }
178  }
179  }
180  }
181 
182 #ifndef NDEBUG
183  const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
184  // Now that selection is complete, there are no more generic vregs. Verify
185  // that the size of the now-constrained vreg is unchanged and that it has a
186  // register class.
187  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
188  unsigned VReg = Register::index2VirtReg(I);
189 
190  MachineInstr *MI = nullptr;
191  if (!MRI.def_empty(VReg))
192  MI = &*MRI.def_instr_begin(VReg);
193  else if (!MRI.use_empty(VReg))
194  MI = &*MRI.use_instr_begin(VReg);
195  if (!MI)
196  continue;
197 
198  const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
199  if (!RC) {
200  reportGISelFailure(MF, TPC, MORE, "gisel-select",
201  "VReg has no regclass after selection", *MI);
202  return false;
203  }
204 
205  const LLT Ty = MRI.getType(VReg);
206  if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
208  MF, TPC, MORE, "gisel-select",
209  "VReg's low-level type and register class have different sizes", *MI);
210  return false;
211  }
212  }
213 
214  if (MF.size() != NumBlocks) {
215  MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
216  MF.getFunction().getSubprogram(),
217  /*MBB=*/nullptr);
218  R << "inserting blocks is not supported yet";
219  reportGISelFailure(MF, TPC, MORE, R);
220  return false;
221  }
222 #endif
223  auto &TLI = *MF.getSubtarget().getTargetLowering();
224  TLI.finalizeLowering(MF);
225 
226  LLVM_DEBUG({
227  dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
228  for (auto RuleID : CoverageInfo.covered())
229  dbgs() << " id" << RuleID;
230  dbgs() << "\n\n";
231  });
232  CoverageInfo.emit(CoveragePrefix,
233  MF.getSubtarget()
234  .getTargetLowering()
235  ->getTargetMachine()
236  .getTarget()
237  .getBackendName());
238 
239  // If we successfully selected the function nothing is going to use the vreg
240  // types after us (otherwise MIRPrinter would need them). Make sure the types
241  // disappear.
242  MRI.clearVirtRegTypes();
243 
244  // FIXME: Should we accurately track changes?
245  return true;
246 }
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:412
const MachineFunctionProperties & getProperties() const
Get the function properties.
unsigned size() const
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
unsigned const TargetRegisterInfo * TRI
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:83
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
bool emit(StringRef FilePrefix, StringRef BackendName) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
Target-Independent Code Generator Pass Configuration Options.
INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE, "Select target instructions out of generic instructions", false, false) INITIALIZE_PASS_END(InstructionSelect
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelKnownBitsInfoAnalysis...
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Represent the analysis usage information of a pass.
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool isValid() const
virtual InstructionSelector * getInstructionSelector() const
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
iterator_range< po_iterator< T > > post_order(const T &G)
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static const std::string CoveragePrefix
cl::opt< bool > DisableGISelLegalityCheck
#define DEBUG_TYPE
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)
Checks that MIR is fully legal, returns an illegal instruction if it&#39;s not, nullptr otherwise...
The optimization diagnostic interface.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
#define MORE()
Definition: regcomp.c:252
This pass is responsible for selecting generic machine instructions to target-specific instructions...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
def_instr_iterator def_instr_begin(unsigned RegNo) const
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides the logic to select generic machine instructions.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:158
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
iterator_range< const_covered_iterator > covered() const
#define I(x, y, z)
Definition: MD5.cpp:58
Diagnostic information for missed-optimization remarks.
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
IRTranslator LLVM IR MI
inst_range instructions(Function *F)
Definition: InstIterator.h:133
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:178
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This file describes how to lower LLVM code to machine code.