LLVM  9.0.0svn
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the TargetLoweringBase class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/CodeGen/Analysis.h"
32 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalValue.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/IRBuilder.h"
45 #include "llvm/IR/Module.h"
46 #include "llvm/IR/Type.h"
48 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/Compiler.h"
55 #include <algorithm>
56 #include <cassert>
57 #include <cstddef>
58 #include <cstdint>
59 #include <cstring>
60 #include <iterator>
61 #include <string>
62 #include <tuple>
63 #include <utility>
64 
65 using namespace llvm;
66 
68  "jump-is-expensive", cl::init(false),
69  cl::desc("Do not create extra branches to split comparison logic."),
70  cl::Hidden);
71 
73  ("min-jump-table-entries", cl::init(4), cl::Hidden,
74  cl::desc("Set minimum number of entries to use a jump table."));
75 
77  ("max-jump-table-size", cl::init(0), cl::Hidden,
78  cl::desc("Set maximum size of jump tables; zero for no limit."));
79 
80 /// Minimum jump table density for normal functions.
81 static cl::opt<unsigned>
82  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
83  cl::desc("Minimum density for building a jump table in "
84  "a normal function"));
85 
86 /// Minimum jump table density for -Os or -Oz functions.
88  "optsize-jump-table-density", cl::init(40), cl::Hidden,
89  cl::desc("Minimum density for building a jump table in "
90  "an optsize function"));
91 
92 static bool darwinHasSinCos(const Triple &TT) {
93  assert(TT.isOSDarwin() && "should be called with darwin triple");
94  // Don't bother with 32 bit x86.
95  if (TT.getArch() == Triple::x86)
96  return false;
97  // Macos < 10.9 has no sincos_stret.
98  if (TT.isMacOSX())
99  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
100  // iOS < 7.0 has no sincos_stret.
101  if (TT.isiOS())
102  return !TT.isOSVersionLT(7, 0);
103  // Any other darwin such as WatchOS/TvOS is new enough.
104  return true;
105 }
106 
107 // Although this default value is arbitrary, it is not random. It is assumed
108 // that a condition that evaluates the same way by a higher percentage than this
109 // is best represented as control flow. Therefore, the default value N should be
110 // set such that the win from N% correct executions is greater than the loss
111 // from (100 - N)% mispredicted executions for the majority of intended targets.
113  "min-predictable-branch", cl::init(99),
114  cl::desc("Minimum percentage (0-100) that a condition must be either true "
115  "or false to assume that the condition is predictable"),
116  cl::Hidden);
117 
118 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
119 #define HANDLE_LIBCALL(code, name) \
120  setLibcallName(RTLIB::code, name);
121 #include "llvm/IR/RuntimeLibcalls.def"
122 #undef HANDLE_LIBCALL
123  // Initialize calling conventions to their default.
124  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
126 
127  // A few names are different on particular architectures or environments.
128  if (TT.isOSDarwin()) {
129  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
130  // of the gnueabi-style __gnu_*_ieee.
131  // FIXME: What about other targets?
132  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
133  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
134 
135  // Some darwins have an optimized __bzero/bzero function.
136  switch (TT.getArch()) {
137  case Triple::x86:
138  case Triple::x86_64:
139  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
140  setLibcallName(RTLIB::BZERO, "__bzero");
141  break;
142  case Triple::aarch64:
143  setLibcallName(RTLIB::BZERO, "bzero");
144  break;
145  default:
146  break;
147  }
148 
149  if (darwinHasSinCos(TT)) {
150  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
151  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
152  if (TT.isWatchABI()) {
153  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
155  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
157  }
158  }
159  } else {
160  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
161  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
162  }
163 
164  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
165  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
166  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
167  setLibcallName(RTLIB::SINCOS_F64, "sincos");
168  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
169  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
170  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
171  }
172 
173  if (TT.isOSOpenBSD()) {
174  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
175  }
176 }
177 
178 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
179 /// UNKNOWN_LIBCALL if there is none.
181  if (OpVT == MVT::f16) {
182  if (RetVT == MVT::f32)
183  return FPEXT_F16_F32;
184  } else if (OpVT == MVT::f32) {
185  if (RetVT == MVT::f64)
186  return FPEXT_F32_F64;
187  if (RetVT == MVT::f128)
188  return FPEXT_F32_F128;
189  if (RetVT == MVT::ppcf128)
190  return FPEXT_F32_PPCF128;
191  } else if (OpVT == MVT::f64) {
192  if (RetVT == MVT::f128)
193  return FPEXT_F64_F128;
194  else if (RetVT == MVT::ppcf128)
195  return FPEXT_F64_PPCF128;
196  } else if (OpVT == MVT::f80) {
197  if (RetVT == MVT::f128)
198  return FPEXT_F80_F128;
199  }
200 
201  return UNKNOWN_LIBCALL;
202 }
203 
204 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
205 /// UNKNOWN_LIBCALL if there is none.
207  if (RetVT == MVT::f16) {
208  if (OpVT == MVT::f32)
209  return FPROUND_F32_F16;
210  if (OpVT == MVT::f64)
211  return FPROUND_F64_F16;
212  if (OpVT == MVT::f80)
213  return FPROUND_F80_F16;
214  if (OpVT == MVT::f128)
215  return FPROUND_F128_F16;
216  if (OpVT == MVT::ppcf128)
217  return FPROUND_PPCF128_F16;
218  } else if (RetVT == MVT::f32) {
219  if (OpVT == MVT::f64)
220  return FPROUND_F64_F32;
221  if (OpVT == MVT::f80)
222  return FPROUND_F80_F32;
223  if (OpVT == MVT::f128)
224  return FPROUND_F128_F32;
225  if (OpVT == MVT::ppcf128)
226  return FPROUND_PPCF128_F32;
227  } else if (RetVT == MVT::f64) {
228  if (OpVT == MVT::f80)
229  return FPROUND_F80_F64;
230  if (OpVT == MVT::f128)
231  return FPROUND_F128_F64;
232  if (OpVT == MVT::ppcf128)
233  return FPROUND_PPCF128_F64;
234  } else if (RetVT == MVT::f80) {
235  if (OpVT == MVT::f128)
236  return FPROUND_F128_F80;
237  }
238 
239  return UNKNOWN_LIBCALL;
240 }
241 
242 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
243 /// UNKNOWN_LIBCALL if there is none.
245  if (OpVT == MVT::f32) {
246  if (RetVT == MVT::i32)
247  return FPTOSINT_F32_I32;
248  if (RetVT == MVT::i64)
249  return FPTOSINT_F32_I64;
250  if (RetVT == MVT::i128)
251  return FPTOSINT_F32_I128;
252  } else if (OpVT == MVT::f64) {
253  if (RetVT == MVT::i32)
254  return FPTOSINT_F64_I32;
255  if (RetVT == MVT::i64)
256  return FPTOSINT_F64_I64;
257  if (RetVT == MVT::i128)
258  return FPTOSINT_F64_I128;
259  } else if (OpVT == MVT::f80) {
260  if (RetVT == MVT::i32)
261  return FPTOSINT_F80_I32;
262  if (RetVT == MVT::i64)
263  return FPTOSINT_F80_I64;
264  if (RetVT == MVT::i128)
265  return FPTOSINT_F80_I128;
266  } else if (OpVT == MVT::f128) {
267  if (RetVT == MVT::i32)
268  return FPTOSINT_F128_I32;
269  if (RetVT == MVT::i64)
270  return FPTOSINT_F128_I64;
271  if (RetVT == MVT::i128)
272  return FPTOSINT_F128_I128;
273  } else if (OpVT == MVT::ppcf128) {
274  if (RetVT == MVT::i32)
275  return FPTOSINT_PPCF128_I32;
276  if (RetVT == MVT::i64)
277  return FPTOSINT_PPCF128_I64;
278  if (RetVT == MVT::i128)
279  return FPTOSINT_PPCF128_I128;
280  }
281  return UNKNOWN_LIBCALL;
282 }
283 
284 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
285 /// UNKNOWN_LIBCALL if there is none.
287  if (OpVT == MVT::f32) {
288  if (RetVT == MVT::i32)
289  return FPTOUINT_F32_I32;
290  if (RetVT == MVT::i64)
291  return FPTOUINT_F32_I64;
292  if (RetVT == MVT::i128)
293  return FPTOUINT_F32_I128;
294  } else if (OpVT == MVT::f64) {
295  if (RetVT == MVT::i32)
296  return FPTOUINT_F64_I32;
297  if (RetVT == MVT::i64)
298  return FPTOUINT_F64_I64;
299  if (RetVT == MVT::i128)
300  return FPTOUINT_F64_I128;
301  } else if (OpVT == MVT::f80) {
302  if (RetVT == MVT::i32)
303  return FPTOUINT_F80_I32;
304  if (RetVT == MVT::i64)
305  return FPTOUINT_F80_I64;
306  if (RetVT == MVT::i128)
307  return FPTOUINT_F80_I128;
308  } else if (OpVT == MVT::f128) {
309  if (RetVT == MVT::i32)
310  return FPTOUINT_F128_I32;
311  if (RetVT == MVT::i64)
312  return FPTOUINT_F128_I64;
313  if (RetVT == MVT::i128)
314  return FPTOUINT_F128_I128;
315  } else if (OpVT == MVT::ppcf128) {
316  if (RetVT == MVT::i32)
317  return FPTOUINT_PPCF128_I32;
318  if (RetVT == MVT::i64)
319  return FPTOUINT_PPCF128_I64;
320  if (RetVT == MVT::i128)
321  return FPTOUINT_PPCF128_I128;
322  }
323  return UNKNOWN_LIBCALL;
324 }
325 
326 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
327 /// UNKNOWN_LIBCALL if there is none.
329  if (OpVT == MVT::i32) {
330  if (RetVT == MVT::f32)
331  return SINTTOFP_I32_F32;
332  if (RetVT == MVT::f64)
333  return SINTTOFP_I32_F64;
334  if (RetVT == MVT::f80)
335  return SINTTOFP_I32_F80;
336  if (RetVT == MVT::f128)
337  return SINTTOFP_I32_F128;
338  if (RetVT == MVT::ppcf128)
339  return SINTTOFP_I32_PPCF128;
340  } else if (OpVT == MVT::i64) {
341  if (RetVT == MVT::f32)
342  return SINTTOFP_I64_F32;
343  if (RetVT == MVT::f64)
344  return SINTTOFP_I64_F64;
345  if (RetVT == MVT::f80)
346  return SINTTOFP_I64_F80;
347  if (RetVT == MVT::f128)
348  return SINTTOFP_I64_F128;
349  if (RetVT == MVT::ppcf128)
350  return SINTTOFP_I64_PPCF128;
351  } else if (OpVT == MVT::i128) {
352  if (RetVT == MVT::f32)
353  return SINTTOFP_I128_F32;
354  if (RetVT == MVT::f64)
355  return SINTTOFP_I128_F64;
356  if (RetVT == MVT::f80)
357  return SINTTOFP_I128_F80;
358  if (RetVT == MVT::f128)
359  return SINTTOFP_I128_F128;
360  if (RetVT == MVT::ppcf128)
361  return SINTTOFP_I128_PPCF128;
362  }
363  return UNKNOWN_LIBCALL;
364 }
365 
366 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
367 /// UNKNOWN_LIBCALL if there is none.
369  if (OpVT == MVT::i32) {
370  if (RetVT == MVT::f32)
371  return UINTTOFP_I32_F32;
372  if (RetVT == MVT::f64)
373  return UINTTOFP_I32_F64;
374  if (RetVT == MVT::f80)
375  return UINTTOFP_I32_F80;
376  if (RetVT == MVT::f128)
377  return UINTTOFP_I32_F128;
378  if (RetVT == MVT::ppcf128)
379  return UINTTOFP_I32_PPCF128;
380  } else if (OpVT == MVT::i64) {
381  if (RetVT == MVT::f32)
382  return UINTTOFP_I64_F32;
383  if (RetVT == MVT::f64)
384  return UINTTOFP_I64_F64;
385  if (RetVT == MVT::f80)
386  return UINTTOFP_I64_F80;
387  if (RetVT == MVT::f128)
388  return UINTTOFP_I64_F128;
389  if (RetVT == MVT::ppcf128)
390  return UINTTOFP_I64_PPCF128;
391  } else if (OpVT == MVT::i128) {
392  if (RetVT == MVT::f32)
393  return UINTTOFP_I128_F32;
394  if (RetVT == MVT::f64)
395  return UINTTOFP_I128_F64;
396  if (RetVT == MVT::f80)
397  return UINTTOFP_I128_F80;
398  if (RetVT == MVT::f128)
399  return UINTTOFP_I128_F128;
400  if (RetVT == MVT::ppcf128)
401  return UINTTOFP_I128_PPCF128;
402  }
403  return UNKNOWN_LIBCALL;
404 }
405 
406 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
407 #define OP_TO_LIBCALL(Name, Enum) \
408  case Name: \
409  switch (VT.SimpleTy) { \
410  default: \
411  return UNKNOWN_LIBCALL; \
412  case MVT::i8: \
413  return Enum##_1; \
414  case MVT::i16: \
415  return Enum##_2; \
416  case MVT::i32: \
417  return Enum##_4; \
418  case MVT::i64: \
419  return Enum##_8; \
420  case MVT::i128: \
421  return Enum##_16; \
422  }
423 
424  switch (Opc) {
425  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
426  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
427  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
428  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
429  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
430  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
431  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
432  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
433  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
434  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
435  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
436  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
437  }
438 
439 #undef OP_TO_LIBCALL
440 
441  return UNKNOWN_LIBCALL;
442 }
443 
445  switch (ElementSize) {
446  case 1:
447  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
448  case 2:
449  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
450  case 4:
451  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
452  case 8:
453  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
454  case 16:
455  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
456  default:
457  return UNKNOWN_LIBCALL;
458  }
459 }
460 
462  switch (ElementSize) {
463  case 1:
464  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
465  case 2:
466  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
467  case 4:
468  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
469  case 8:
470  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
471  case 16:
472  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
473  default:
474  return UNKNOWN_LIBCALL;
475  }
476 }
477 
479  switch (ElementSize) {
480  case 1:
481  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
482  case 2:
483  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
484  case 4:
485  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
486  case 8:
487  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
488  case 16:
489  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
490  default:
491  return UNKNOWN_LIBCALL;
492  }
493 }
494 
495 /// InitCmpLibcallCCs - Set default comparison libcall CC.
496 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
497  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
498  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
499  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
500  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
501  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
502  CCs[RTLIB::UNE_F32] = ISD::SETNE;
503  CCs[RTLIB::UNE_F64] = ISD::SETNE;
504  CCs[RTLIB::UNE_F128] = ISD::SETNE;
505  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
506  CCs[RTLIB::OGE_F32] = ISD::SETGE;
507  CCs[RTLIB::OGE_F64] = ISD::SETGE;
508  CCs[RTLIB::OGE_F128] = ISD::SETGE;
509  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
510  CCs[RTLIB::OLT_F32] = ISD::SETLT;
511  CCs[RTLIB::OLT_F64] = ISD::SETLT;
512  CCs[RTLIB::OLT_F128] = ISD::SETLT;
513  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
514  CCs[RTLIB::OLE_F32] = ISD::SETLE;
515  CCs[RTLIB::OLE_F64] = ISD::SETLE;
516  CCs[RTLIB::OLE_F128] = ISD::SETLE;
517  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
518  CCs[RTLIB::OGT_F32] = ISD::SETGT;
519  CCs[RTLIB::OGT_F64] = ISD::SETGT;
520  CCs[RTLIB::OGT_F128] = ISD::SETGT;
521  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
522  CCs[RTLIB::UO_F32] = ISD::SETNE;
523  CCs[RTLIB::UO_F64] = ISD::SETNE;
524  CCs[RTLIB::UO_F128] = ISD::SETNE;
525  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
526  CCs[RTLIB::O_F32] = ISD::SETEQ;
527  CCs[RTLIB::O_F64] = ISD::SETEQ;
528  CCs[RTLIB::O_F128] = ISD::SETEQ;
529  CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
530 }
531 
532 /// NOTE: The TargetMachine owns TLOF.
534  initActions();
535 
536  // Perform these initializations only once.
538  MaxLoadsPerMemcmp = 8;
542  UseUnderscoreSetJmp = false;
543  UseUnderscoreLongJmp = false;
544  HasMultipleConditionRegisters = false;
545  HasExtractBitsInsn = false;
546  JumpIsExpensive = JumpIsExpensiveOverride;
548  EnableExtLdPromotion = false;
549  HasFloatingPointExceptions = true;
550  StackPointerRegisterToSaveRestore = 0;
551  BooleanContents = UndefinedBooleanContent;
552  BooleanFloatContents = UndefinedBooleanContent;
553  BooleanVectorContents = UndefinedBooleanContent;
554  SchedPreferenceInfo = Sched::ILP;
555  JumpBufSize = 0;
556  JumpBufAlignment = 0;
557  MinFunctionAlignment = 0;
558  PrefFunctionAlignment = 0;
559  PrefLoopAlignment = 0;
561  MinStackArgumentAlignment = 1;
562  // TODO: the default will be switched to 0 in the next commit, along
563  // with the Target-specific changes necessary.
564  MaxAtomicSizeInBitsSupported = 1024;
565 
566  MinCmpXchgSizeInBits = 0;
567  SupportsUnalignedAtomics = false;
568 
569  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
570 
571  InitLibcalls(TM.getTargetTriple());
572  InitCmpLibcallCCs(CmpLibcallCCs);
573 }
574 
576  // All operations default to being supported.
577  memset(OpActions, 0, sizeof(OpActions));
578  memset(LoadExtActions, 0, sizeof(LoadExtActions));
579  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
580  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
581  memset(CondCodeActions, 0, sizeof(CondCodeActions));
582  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
583  std::fill(std::begin(TargetDAGCombineArray),
584  std::end(TargetDAGCombineArray), 0);
585 
586  for (MVT VT : MVT::fp_valuetypes()) {
587  MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
588  if (IntVT.isValid()) {
591  }
592  }
593 
594  // Set default actions for various operations.
595  for (MVT VT : MVT::all_valuetypes()) {
596  // Default all indexed load / store to expand.
597  for (unsigned IM = (unsigned)ISD::PRE_INC;
598  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
599  setIndexedLoadAction(IM, VT, Expand);
600  setIndexedStoreAction(IM, VT, Expand);
601  }
602 
603  // Most backends expect to see the node which just returns the value loaded.
605 
606  // These operations default to expand.
628 
629  // Overflow operations default to expand
636 
637  // ADDCARRY operations default to expand
641 
642  // ADDC/ADDE/SUBC/SUBE default to expand.
647 
648  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
651 
653 
654  // These library functions default to expand.
657 
658  // These operations default to expand for vector types.
659  if (VT.isVector()) {
664  }
665 
666  // For most targets @llvm.get.dynamic.area.offset just returns 0.
668  }
669 
670  // Most targets ignore the @llvm.prefetch intrinsic.
672 
673  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
675 
676  // ConstantFP nodes default to expand. Targets can either change this to
677  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
678  // to optimize expansions for certain constants.
684 
685  // These library functions default to expand.
686  for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
699  }
700 
701  // Default ISD::TRAP to expand (which turns it into abort).
703 
704  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
705  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
707 }
708 
710  EVT) const {
711  return MVT::getIntegerVT(8 * DL.getPointerSize(0));
712 }
713 
715  bool LegalTypes) const {
716  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
717  if (LHSTy.isVector())
718  return LHSTy;
719  return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
720  : getPointerTy(DL);
721 }
722 
723 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
724  assert(isTypeLegal(VT));
725  switch (Op) {
726  default:
727  return false;
728  case ISD::SDIV:
729  case ISD::UDIV:
730  case ISD::SREM:
731  case ISD::UREM:
732  return true;
733  }
734 }
735 
737  // If the command-line option was specified, ignore this request.
738  if (!JumpIsExpensiveOverride.getNumOccurrences())
739  JumpIsExpensive = isExpensive;
740 }
741 
743 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
744  // If this is a simple type, use the ComputeRegisterProp mechanism.
745  if (VT.isSimple()) {
746  MVT SVT = VT.getSimpleVT();
747  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
748  MVT NVT = TransformToType[SVT.SimpleTy];
750 
751  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
753  "Promote may not follow Expand or Promote");
754 
755  if (LA == TypeSplitVector)
756  return LegalizeKind(LA,
757  EVT::getVectorVT(Context, SVT.getVectorElementType(),
758  SVT.getVectorNumElements() / 2));
759  if (LA == TypeScalarizeVector)
760  return LegalizeKind(LA, SVT.getVectorElementType());
761  return LegalizeKind(LA, NVT);
762  }
763 
764  // Handle Extended Scalar Types.
765  if (!VT.isVector()) {
766  assert(VT.isInteger() && "Float types must be simple");
767  unsigned BitSize = VT.getSizeInBits();
768  // First promote to a power-of-two size, then expand if necessary.
769  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
770  EVT NVT = VT.getRoundIntegerType(Context);
771  assert(NVT != VT && "Unable to round integer VT");
772  LegalizeKind NextStep = getTypeConversion(Context, NVT);
773  // Avoid multi-step promotion.
774  if (NextStep.first == TypePromoteInteger)
775  return NextStep;
776  // Return rounded integer type.
777  return LegalizeKind(TypePromoteInteger, NVT);
778  }
779 
781  EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
782  }
783 
784  // Handle vector types.
785  unsigned NumElts = VT.getVectorNumElements();
786  EVT EltVT = VT.getVectorElementType();
787 
788  // Vectors with only one element are always scalarized.
789  if (NumElts == 1)
790  return LegalizeKind(TypeScalarizeVector, EltVT);
791 
792  // Try to widen vector elements until the element type is a power of two and
793  // promote it to a legal type later on, for example:
794  // <3 x i8> -> <4 x i8> -> <4 x i32>
795  if (EltVT.isInteger()) {
796  // Vectors with a number of elements that is not a power of two are always
797  // widened, for example <3 x i8> -> <4 x i8>.
798  if (!VT.isPow2VectorType()) {
799  NumElts = (unsigned)NextPowerOf2(NumElts);
800  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
801  return LegalizeKind(TypeWidenVector, NVT);
802  }
803 
804  // Examine the element type.
805  LegalizeKind LK = getTypeConversion(Context, EltVT);
806 
807  // If type is to be expanded, split the vector.
808  // <4 x i140> -> <2 x i140>
809  if (LK.first == TypeExpandInteger)
811  EVT::getVectorVT(Context, EltVT, NumElts / 2));
812 
813  // Promote the integer element types until a legal vector type is found
814  // or until the element integer type is too big. If a legal type was not
815  // found, fallback to the usual mechanism of widening/splitting the
816  // vector.
817  EVT OldEltVT = EltVT;
818  while (true) {
819  // Increase the bitwidth of the element to the next pow-of-two
820  // (which is greater than 8 bits).
821  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
822  .getRoundIntegerType(Context);
823 
824  // Stop trying when getting a non-simple element type.
825  // Note that vector elements may be greater than legal vector element
826  // types. Example: X86 XMM registers hold 64bit element on 32bit
827  // systems.
828  if (!EltVT.isSimple())
829  break;
830 
831  // Build a new vector type and check if it is legal.
832  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
833  // Found a legal promoted vector type.
834  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
836  EVT::getVectorVT(Context, EltVT, NumElts));
837  }
838 
839  // Reset the type to the unexpanded type if we did not find a legal vector
840  // type with a promoted vector element type.
841  EltVT = OldEltVT;
842  }
843 
844  // Try to widen the vector until a legal type is found.
845  // If there is no wider legal type, split the vector.
846  while (true) {
847  // Round up to the next power of 2.
848  NumElts = (unsigned)NextPowerOf2(NumElts);
849 
850  // If there is no simple vector type with this many elements then there
851  // cannot be a larger legal vector type. Note that this assumes that
852  // there are no skipped intermediate vector types in the simple types.
853  if (!EltVT.isSimple())
854  break;
855  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
856  if (LargerVector == MVT())
857  break;
858 
859  // If this type is legal then widen the vector.
860  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
861  return LegalizeKind(TypeWidenVector, LargerVector);
862  }
863 
864  // Widen odd vectors to next power of two.
865  if (!VT.isPow2VectorType()) {
866  EVT NVT = VT.getPow2VectorType(Context);
867  return LegalizeKind(TypeWidenVector, NVT);
868  }
869 
870  // Vectors with illegal element types are expanded.
871  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
872  return LegalizeKind(TypeSplitVector, NVT);
873 }
874 
875 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
876  unsigned &NumIntermediates,
877  MVT &RegisterVT,
878  TargetLoweringBase *TLI) {
879  // Figure out the right, legal destination reg to copy into.
880  unsigned NumElts = VT.getVectorNumElements();
881  MVT EltTy = VT.getVectorElementType();
882 
883  unsigned NumVectorRegs = 1;
884 
885  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
886  // could break down into LHS/RHS like LegalizeDAG does.
887  if (!isPowerOf2_32(NumElts)) {
888  NumVectorRegs = NumElts;
889  NumElts = 1;
890  }
891 
892  // Divide the input until we get to a supported size. This will always
893  // end with a scalar if the target doesn't support vectors.
894  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
895  NumElts >>= 1;
896  NumVectorRegs <<= 1;
897  }
898 
899  NumIntermediates = NumVectorRegs;
900 
901  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
902  if (!TLI->isTypeLegal(NewVT))
903  NewVT = EltTy;
904  IntermediateVT = NewVT;
905 
906  unsigned NewVTSize = NewVT.getSizeInBits();
907 
908  // Convert sizes such as i33 to i64.
909  if (!isPowerOf2_32(NewVTSize))
910  NewVTSize = NextPowerOf2(NewVTSize);
911 
912  MVT DestVT = TLI->getRegisterType(NewVT);
913  RegisterVT = DestVT;
914  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
915  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
916 
917  // Otherwise, promotion or legal types use the same number of registers as
918  // the vector decimated to the appropriate level.
919  return NumVectorRegs;
920 }
921 
922 /// isLegalRC - Return true if the value types that can be represented by the
923 /// specified register class are all legal.
925  const TargetRegisterClass &RC) const {
926  for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
927  if (isTypeLegal(*I))
928  return true;
929  return false;
930 }
931 
932 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
933 /// sequence of memory operands that is recognized by PrologEpilogInserter.
936  MachineBasicBlock *MBB) const {
937  MachineInstr *MI = &InitialMI;
938  MachineFunction &MF = *MI->getMF();
939  MachineFrameInfo &MFI = MF.getFrameInfo();
940 
941  // We're handling multiple types of operands here:
942  // PATCHPOINT MetaArgs - live-in, read only, direct
943  // STATEPOINT Deopt Spill - live-through, read only, indirect
944  // STATEPOINT Deopt Alloca - live-through, read only, direct
945  // (We're currently conservative and mark the deopt slots read/write in
946  // practice.)
947  // STATEPOINT GC Spill - live-through, read/write, indirect
948  // STATEPOINT GC Alloca - live-through, read/write, direct
949  // The live-in vs live-through is handled already (the live through ones are
950  // all stack slots), but we need to handle the different type of stackmap
951  // operands and memory effects here.
952 
953  // MI changes inside this loop as we grow operands.
954  for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
955  MachineOperand &MO = MI->getOperand(OperIdx);
956  if (!MO.isFI())
957  continue;
958 
959  // foldMemoryOperand builds a new MI after replacing a single FI operand
960  // with the canonical set of five x86 addressing-mode operands.
961  int FI = MO.getIndex();
962  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
963 
964  // Copy operands before the frame-index.
965  for (unsigned i = 0; i < OperIdx; ++i)
966  MIB.add(MI->getOperand(i));
967  // Add frame index operands recognized by stackmaps.cpp
968  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
969  // indirect-mem-ref tag, size, #FI, offset.
970  // Used for spills inserted by StatepointLowering. This codepath is not
971  // used for patchpoints/stackmaps at all, for these spilling is done via
972  // foldMemoryOperand callback only.
973  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
974  MIB.addImm(StackMaps::IndirectMemRefOp);
975  MIB.addImm(MFI.getObjectSize(FI));
976  MIB.add(MI->getOperand(OperIdx));
977  MIB.addImm(0);
978  } else {
979  // direct-mem-ref tag, #FI, offset.
980  // Used by patchpoint, and direct alloca arguments to statepoints
981  MIB.addImm(StackMaps::DirectMemRefOp);
982  MIB.add(MI->getOperand(OperIdx));
983  MIB.addImm(0);
984  }
985  // Copy the operands after the frame index.
986  for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
987  MIB.add(MI->getOperand(i));
988 
989  // Inherit previous memory operands.
990  MIB.cloneMemRefs(*MI);
991  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
992 
993  // Add a new memory operand for this FI.
994  assert(MFI.getObjectOffset(FI) != -1);
995 
996  auto Flags = MachineMemOperand::MOLoad;
997  if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
1000  }
1002  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1004  MIB->addMemOperand(MF, MMO);
1005 
1006  // Replace the instruction and update the operand index.
1007  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1008  OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1009  MI->eraseFromParent();
1010  MI = MIB;
1011  }
1012  return MBB;
1013 }
1014 
1017  MachineBasicBlock *MBB) const {
1018  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL &&
1019  "Called emitXRayCustomEvent on the wrong MI!");
1020  auto &MF = *MI.getMF();
1021  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1022  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1023  MIB.add(MI.getOperand(OpIdx));
1024 
1025  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1026  MI.eraseFromParent();
1027  return MBB;
1028 }
1029 
1032  MachineBasicBlock *MBB) const {
1033  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL &&
1034  "Called emitXRayTypedEvent on the wrong MI!");
1035  auto &MF = *MI.getMF();
1036  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1037  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1038  MIB.add(MI.getOperand(OpIdx));
1039 
1040  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1041  MI.eraseFromParent();
1042  return MBB;
1043 }
1044 
1045 /// findRepresentativeClass - Return the largest legal super-reg register class
1046 /// of the register class for the specified type and its associated "cost".
1047 // This function is in TargetLowering because it uses RegClassForVT which would
1048 // need to be moved to TargetRegisterInfo and would necessitate moving
1049 // isTypeLegal over as well - a massive change that would just require
1050 // TargetLowering having a TargetRegisterInfo class member that it would use.
1051 std::pair<const TargetRegisterClass *, uint8_t>
1053  MVT VT) const {
1054  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1055  if (!RC)
1056  return std::make_pair(RC, 0);
1057 
1058  // Compute the set of all super-register classes.
1059  BitVector SuperRegRC(TRI->getNumRegClasses());
1060  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1061  SuperRegRC.setBitsInMask(RCI.getMask());
1062 
1063  // Find the first legal register class with the largest spill size.
1064  const TargetRegisterClass *BestRC = RC;
1065  for (unsigned i : SuperRegRC.set_bits()) {
1066  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1067  // We want the largest possible spill size.
1068  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1069  continue;
1070  if (!isLegalRC(*TRI, *SuperRC))
1071  continue;
1072  BestRC = SuperRC;
1073  }
1074  return std::make_pair(BestRC, 1);
1075 }
1076 
1077 /// computeRegisterProperties - Once all of the register classes are added,
1078 /// this allows us to compute derived properties we expose.
1080  const TargetRegisterInfo *TRI) {
1082  "Too many value types for ValueTypeActions to hold!");
1083 
1084  // Everything defaults to needing one register.
1085  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1086  NumRegistersForVT[i] = 1;
1087  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1088  }
1089  // ...except isVoid, which doesn't need any registers.
1090  NumRegistersForVT[MVT::isVoid] = 0;
1091 
1092  // Find the largest integer register class.
1093  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1094  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1095  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1096 
1097  // Every integer value type larger than this largest register takes twice as
1098  // many registers to represent as the previous ValueType.
1099  for (unsigned ExpandedReg = LargestIntReg + 1;
1100  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1101  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1102  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1103  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1106  }
1107 
1108  // Inspect all of the ValueType's smaller than the largest integer
1109  // register to see which ones need promotion.
1110  unsigned LegalIntReg = LargestIntReg;
1111  for (unsigned IntReg = LargestIntReg - 1;
1112  IntReg >= (unsigned)MVT::i1; --IntReg) {
1113  MVT IVT = (MVT::SimpleValueType)IntReg;
1114  if (isTypeLegal(IVT)) {
1115  LegalIntReg = IntReg;
1116  } else {
1117  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1118  (MVT::SimpleValueType)LegalIntReg;
1120  }
1121  }
1122 
1123  // ppcf128 type is really two f64's.
1124  if (!isTypeLegal(MVT::ppcf128)) {
1125  if (isTypeLegal(MVT::f64)) {
1126  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1127  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1128  TransformToType[MVT::ppcf128] = MVT::f64;
1130  } else {
1131  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1132  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1133  TransformToType[MVT::ppcf128] = MVT::i128;
1135  }
1136  }
1137 
1138  // Decide how to handle f128. If the target does not have native f128 support,
1139  // expand it to i128 and we will be generating soft float library calls.
1140  if (!isTypeLegal(MVT::f128)) {
1141  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1142  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1143  TransformToType[MVT::f128] = MVT::i128;
1145  }
1146 
1147  // Decide how to handle f64. If the target does not have native f64 support,
1148  // expand it to i64 and we will be generating soft float library calls.
1149  if (!isTypeLegal(MVT::f64)) {
1150  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1151  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1152  TransformToType[MVT::f64] = MVT::i64;
1154  }
1155 
1156  // Decide how to handle f32. If the target does not have native f32 support,
1157  // expand it to i32 and we will be generating soft float library calls.
1158  if (!isTypeLegal(MVT::f32)) {
1159  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1160  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1161  TransformToType[MVT::f32] = MVT::i32;
1163  }
1164 
1165  // Decide how to handle f16. If the target does not have native f16 support,
1166  // promote it to f32, because there are no f16 library calls (except for
1167  // conversions).
1168  if (!isTypeLegal(MVT::f16)) {
1169  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1170  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1171  TransformToType[MVT::f16] = MVT::f32;
1173  }
1174 
1175  // Loop over all of the vector value types to see which need transformations.
1176  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1177  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1178  MVT VT = (MVT::SimpleValueType) i;
1179  if (isTypeLegal(VT))
1180  continue;
1181 
1182  MVT EltVT = VT.getVectorElementType();
1183  unsigned NElts = VT.getVectorNumElements();
1184  bool IsLegalWiderType = false;
1185  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1186  switch (PreferredAction) {
1187  case TypePromoteInteger:
1188  // Try to promote the elements of integer vectors. If no legal
1189  // promotion was found, fall through to the widen-vector method.
1190  for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
1191  MVT SVT = (MVT::SimpleValueType) nVT;
1192  // Promote vectors of integers to vectors with the same number
1193  // of elements, with a wider element type.
1194  if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1195  SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
1196  TransformToType[i] = SVT;
1197  RegisterTypeForVT[i] = SVT;
1198  NumRegistersForVT[i] = 1;
1200  IsLegalWiderType = true;
1201  break;
1202  }
1203  }
1204  if (IsLegalWiderType)
1205  break;
1207 
1208  case TypeWidenVector:
1209  // Try to widen the vector.
1210  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1211  MVT SVT = (MVT::SimpleValueType) nVT;
1212  if (SVT.getVectorElementType() == EltVT
1213  && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1214  TransformToType[i] = SVT;
1215  RegisterTypeForVT[i] = SVT;
1216  NumRegistersForVT[i] = 1;
1218  IsLegalWiderType = true;
1219  break;
1220  }
1221  }
1222  if (IsLegalWiderType)
1223  break;
1225 
1226  case TypeSplitVector:
1227  case TypeScalarizeVector: {
1228  MVT IntermediateVT;
1229  MVT RegisterVT;
1230  unsigned NumIntermediates;
1231  NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1232  NumIntermediates, RegisterVT, this);
1233  RegisterTypeForVT[i] = RegisterVT;
1234 
1235  MVT NVT = VT.getPow2VectorType();
1236  if (NVT == VT) {
1237  // Type is already a power of 2. The default action is to split.
1238  TransformToType[i] = MVT::Other;
1239  if (PreferredAction == TypeScalarizeVector)
1241  else if (PreferredAction == TypeSplitVector)
1243  else
1244  // Set type action according to the number of elements.
1246  : TypeSplitVector);
1247  } else {
1248  TransformToType[i] = NVT;
1250  }
1251  break;
1252  }
1253  default:
1254  llvm_unreachable("Unknown vector legalization action!");
1255  }
1256  }
1257 
1258  // Determine the 'representative' register class for each value type.
1259  // An representative register class is the largest (meaning one which is
1260  // not a sub-register class / subreg register class) legal register class for
1261  // a group of value types. For example, on i386, i8, i16, and i32
1262  // representative would be GR32; while on x86_64 it's GR64.
1263  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1264  const TargetRegisterClass* RRC;
1265  uint8_t Cost;
1266  std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1267  RepRegClassForVT[i] = RRC;
1268  RepRegClassCostForVT[i] = Cost;
1269  }
1270 }
1271 
1273  EVT VT) const {
1274  assert(!VT.isVector() && "No default SetCC type for vectors!");
1275  return getPointerTy(DL).SimpleTy;
1276 }
1277 
1279  return MVT::i32; // return the default value
1280 }
1281 
1282 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1283 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1284 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1285 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1286 ///
1287 /// This method returns the number of registers needed, and the VT for each
1288 /// register. It also returns the VT and quantity of the intermediate values
1289 /// before they are promoted/expanded.
1291  EVT &IntermediateVT,
1292  unsigned &NumIntermediates,
1293  MVT &RegisterVT) const {
1294  unsigned NumElts = VT.getVectorNumElements();
1295 
1296  // If there is a wider vector type with the same element type as this one,
1297  // or a promoted vector type that has the same number of elements which
1298  // are wider, then we should convert to that legal vector type.
1299  // This handles things like <2 x float> -> <4 x float> and
1300  // <4 x i1> -> <4 x i32>.
1301  LegalizeTypeAction TA = getTypeAction(Context, VT);
1302  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1303  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1304  if (isTypeLegal(RegisterEVT)) {
1305  IntermediateVT = RegisterEVT;
1306  RegisterVT = RegisterEVT.getSimpleVT();
1307  NumIntermediates = 1;
1308  return 1;
1309  }
1310  }
1311 
1312  // Figure out the right, legal destination reg to copy into.
1313  EVT EltTy = VT.getVectorElementType();
1314 
1315  unsigned NumVectorRegs = 1;
1316 
1317  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1318  // could break down into LHS/RHS like LegalizeDAG does.
1319  if (!isPowerOf2_32(NumElts)) {
1320  NumVectorRegs = NumElts;
1321  NumElts = 1;
1322  }
1323 
1324  // Divide the input until we get to a supported size. This will always
1325  // end with a scalar if the target doesn't support vectors.
1326  while (NumElts > 1 && !isTypeLegal(
1327  EVT::getVectorVT(Context, EltTy, NumElts))) {
1328  NumElts >>= 1;
1329  NumVectorRegs <<= 1;
1330  }
1331 
1332  NumIntermediates = NumVectorRegs;
1333 
1334  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1335  if (!isTypeLegal(NewVT))
1336  NewVT = EltTy;
1337  IntermediateVT = NewVT;
1338 
1339  MVT DestVT = getRegisterType(Context, NewVT);
1340  RegisterVT = DestVT;
1341  unsigned NewVTSize = NewVT.getSizeInBits();
1342 
1343  // Convert sizes such as i33 to i64.
1344  if (!isPowerOf2_32(NewVTSize))
1345  NewVTSize = NextPowerOf2(NewVTSize);
1346 
1347  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1348  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1349 
1350  // Otherwise, promotion or legal types use the same number of registers as
1351  // the vector decimated to the appropriate level.
1352  return NumVectorRegs;
1353 }
1354 
1355 /// Get the EVTs and ArgFlags collections that represent the legalized return
1356 /// type of the given function. This does not require a DAG or a return value,
1357 /// and is suitable for use before any DAGs for the function are constructed.
1358 /// TODO: Move this out of TargetLowering.cpp.
1360  AttributeList attr,
1362  const TargetLowering &TLI, const DataLayout &DL) {
1363  SmallVector<EVT, 4> ValueVTs;
1364  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1365  unsigned NumValues = ValueVTs.size();
1366  if (NumValues == 0) return;
1367 
1368  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1369  EVT VT = ValueVTs[j];
1370  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1371 
1372  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1373  ExtendKind = ISD::SIGN_EXTEND;
1374  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1375  ExtendKind = ISD::ZERO_EXTEND;
1376 
1377  // FIXME: C calling convention requires the return type to be promoted to
1378  // at least 32-bit. But this is not necessary for non-C calling
1379  // conventions. The frontend should mark functions whose return values
1380  // require promoting with signext or zeroext attributes.
1381  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1382  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1383  if (VT.bitsLT(MinVT))
1384  VT = MinVT;
1385  }
1386 
1387  unsigned NumParts =
1388  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1389  MVT PartVT =
1390  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1391 
1392  // 'inreg' on function refers to return value
1393  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1394  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1395  Flags.setInReg();
1396 
1397  // Propagate extension type if any
1398  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1399  Flags.setSExt();
1400  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1401  Flags.setZExt();
1402 
1403  for (unsigned i = 0; i < NumParts; ++i)
1404  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
1405  }
1406 }
1407 
1408 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1409 /// function arguments in the caller parameter area. This is the actual
1410 /// alignment, not its logarithm.
1412  const DataLayout &DL) const {
1413  return DL.getABITypeAlignment(Ty);
1414 }
1415 
1417  const DataLayout &DL, EVT VT,
1418  unsigned AddrSpace,
1419  unsigned Alignment,
1420  bool *Fast) const {
1421  // Check if the specified alignment is sufficient based on the data layout.
1422  // TODO: While using the data layout works in practice, a better solution
1423  // would be to implement this check directly (make this a virtual function).
1424  // For example, the ABI alignment may change based on software platform while
1425  // this function should only be affected by hardware implementation.
1426  Type *Ty = VT.getTypeForEVT(Context);
1427  if (Alignment >= DL.getABITypeAlignment(Ty)) {
1428  // Assume that an access that meets the ABI-specified alignment is fast.
1429  if (Fast != nullptr)
1430  *Fast = true;
1431  return true;
1432  }
1433 
1434  // This is a misaligned access.
1435  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast);
1436 }
1437 
1439  return BranchProbability(MinPercentageForPredictableBranch, 100);
1440 }
1441 
1442 //===----------------------------------------------------------------------===//
1443 // TargetTransformInfo Helpers
1444 //===----------------------------------------------------------------------===//
1445 
1447  enum InstructionOpcodes {
1448 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1449 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1450 #include "llvm/IR/Instruction.def"
1451  };
1452  switch (static_cast<InstructionOpcodes>(Opcode)) {
1453  case Ret: return 0;
1454  case Br: return 0;
1455  case Switch: return 0;
1456  case IndirectBr: return 0;
1457  case Invoke: return 0;
1458  case Resume: return 0;
1459  case Unreachable: return 0;
1460  case CleanupRet: return 0;
1461  case CatchRet: return 0;
1462  case CatchPad: return 0;
1463  case CatchSwitch: return 0;
1464  case CleanupPad: return 0;
1465  case FNeg: return ISD::FNEG;
1466  case Add: return ISD::ADD;
1467  case FAdd: return ISD::FADD;
1468  case Sub: return ISD::SUB;
1469  case FSub: return ISD::FSUB;
1470  case Mul: return ISD::MUL;
1471  case FMul: return ISD::FMUL;
1472  case UDiv: return ISD::UDIV;
1473  case SDiv: return ISD::SDIV;
1474  case FDiv: return ISD::FDIV;
1475  case URem: return ISD::UREM;
1476  case SRem: return ISD::SREM;
1477  case FRem: return ISD::FREM;
1478  case Shl: return ISD::SHL;
1479  case LShr: return ISD::SRL;
1480  case AShr: return ISD::SRA;
1481  case And: return ISD::AND;
1482  case Or: return ISD::OR;
1483  case Xor: return ISD::XOR;
1484  case Alloca: return 0;
1485  case Load: return ISD::LOAD;
1486  case Store: return ISD::STORE;
1487  case GetElementPtr: return 0;
1488  case Fence: return 0;
1489  case AtomicCmpXchg: return 0;
1490  case AtomicRMW: return 0;
1491  case Trunc: return ISD::TRUNCATE;
1492  case ZExt: return ISD::ZERO_EXTEND;
1493  case SExt: return ISD::SIGN_EXTEND;
1494  case FPToUI: return ISD::FP_TO_UINT;
1495  case FPToSI: return ISD::FP_TO_SINT;
1496  case UIToFP: return ISD::UINT_TO_FP;
1497  case SIToFP: return ISD::SINT_TO_FP;
1498  case FPTrunc: return ISD::FP_ROUND;
1499  case FPExt: return ISD::FP_EXTEND;
1500  case PtrToInt: return ISD::BITCAST;
1501  case IntToPtr: return ISD::BITCAST;
1502  case BitCast: return ISD::BITCAST;
1503  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1504  case ICmp: return ISD::SETCC;
1505  case FCmp: return ISD::SETCC;
1506  case PHI: return 0;
1507  case Call: return 0;
1508  case Select: return ISD::SELECT;
1509  case UserOp1: return 0;
1510  case UserOp2: return 0;
1511  case VAArg: return 0;
1512  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1513  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1514  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1515  case ExtractValue: return ISD::MERGE_VALUES;
1516  case InsertValue: return ISD::MERGE_VALUES;
1517  case LandingPad: return 0;
1518  }
1519 
1520  llvm_unreachable("Unknown instruction type encountered!");
1521 }
1522 
1523 std::pair<int, MVT>
1525  Type *Ty) const {
1526  LLVMContext &C = Ty->getContext();
1527  EVT MTy = getValueType(DL, Ty);
1528 
1529  int Cost = 1;
1530  // We keep legalizing the type until we find a legal kind. We assume that
1531  // the only operation that costs anything is the split. After splitting
1532  // we need to handle two types.
1533  while (true) {
1534  LegalizeKind LK = getTypeConversion(C, MTy);
1535 
1536  if (LK.first == TypeLegal)
1537  return std::make_pair(Cost, MTy.getSimpleVT());
1538 
1539  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1540  Cost *= 2;
1541 
1542  // Do not loop with f128 type.
1543  if (MTy == LK.second)
1544  return std::make_pair(Cost, MTy.getSimpleVT());
1545 
1546  // Keep legalizing the type.
1547  MTy = LK.second;
1548  }
1549 }
1550 
1552  bool UseTLS) const {
1553  // compiler-rt provides a variable with a magic name. Targets that do not
1554  // link with compiler-rt may also provide such a variable.
1555  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1556  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1557  auto UnsafeStackPtr =
1558  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1559 
1560  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1561 
1562  if (!UnsafeStackPtr) {
1563  auto TLSModel = UseTLS ?
1566  // The global variable is not defined yet, define it ourselves.
1567  // We use the initial-exec TLS model because we do not support the
1568  // variable living anywhere other than in the main executable.
1569  UnsafeStackPtr = new GlobalVariable(
1570  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1571  UnsafeStackPtrVar, nullptr, TLSModel);
1572  } else {
1573  // The variable exists, check its type and attributes.
1574  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1575  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1576  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1577  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1578  (UseTLS ? "" : "not ") + "be thread-local");
1579  }
1580  return UnsafeStackPtr;
1581 }
1582 
1584  if (!TM.getTargetTriple().isAndroid())
1585  return getDefaultSafeStackPointerLocation(IRB, true);
1586 
1587  // Android provides a libc function to retrieve the address of the current
1588  // thread's unsafe stack pointer.
1589  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1590  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1591  Value *Fn = M->getOrInsertFunction("__safestack_pointer_address",
1592  StackPtrTy->getPointerTo(0));
1593  return IRB.CreateCall(Fn);
1594 }
1595 
1596 //===----------------------------------------------------------------------===//
1597 // Loop Strength Reduction hooks
1598 //===----------------------------------------------------------------------===//
1599 
1600 /// isLegalAddressingMode - Return true if the addressing mode represented
1601 /// by AM is legal for this target, for a load/store of the specified type.
1603  const AddrMode &AM, Type *Ty,
1604  unsigned AS, Instruction *I) const {
1605  // The default implementation of this implements a conservative RISCy, r+r and
1606  // r+i addr mode.
1607 
1608  // Allows a sign-extended 16-bit immediate field.
1609  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1610  return false;
1611 
1612  // No global is ever allowed as a base.
1613  if (AM.BaseGV)
1614  return false;
1615 
1616  // Only support r+r,
1617  switch (AM.Scale) {
1618  case 0: // "r+i" or just "i", depending on HasBaseReg.
1619  break;
1620  case 1:
1621  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1622  return false;
1623  // Otherwise we have r+r or r+i.
1624  break;
1625  case 2:
1626  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1627  return false;
1628  // Allow 2*r as r+r.
1629  break;
1630  default: // Don't allow n * r
1631  return false;
1632  }
1633 
1634  return true;
1635 }
1636 
1637 //===----------------------------------------------------------------------===//
1638 // Stack Protector
1639 //===----------------------------------------------------------------------===//
1640 
1641 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1642 // so that SelectionDAG handle SSP.
1644  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1645  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1647  return M.getOrInsertGlobal("__guard_local", PtrTy);
1648  }
1649  return nullptr;
1650 }
1651 
1652 // Currently only support "standard" __stack_chk_guard.
1653 // TODO: add LOAD_STACK_GUARD support.
1655  if (!M.getNamedValue("__stack_chk_guard"))
1656  new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1658  nullptr, "__stack_chk_guard");
1659 }
1660 
1661 // Currently only support "standard" __stack_chk_guard.
1662 // TODO: add LOAD_STACK_GUARD support.
1664  return M.getNamedValue("__stack_chk_guard");
1665 }
1666 
1668  return nullptr;
1669 }
1670 
1672  return MinimumJumpTableEntries;
1673 }
1674 
1677 }
1678 
1679 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1680  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1681 }
1682 
1684  return MaximumJumpTableSize;
1685 }
1686 
1688  MaximumJumpTableSize = Val;
1689 }
1690 
1691 //===----------------------------------------------------------------------===//
1692 // Reciprocal Estimates
1693 //===----------------------------------------------------------------------===//
1694 
1695 /// Get the reciprocal estimate attribute string for a function that will
1696 /// override the target defaults.
1698  const Function &F = MF.getFunction();
1699  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1700 }
1701 
1702 /// Construct a string for the given reciprocal operation of the given type.
1703 /// This string should match the corresponding option to the front-end's
1704 /// "-mrecip" flag assuming those strings have been passed through in an
1705 /// attribute string. For example, "vec-divf" for a division of a vXf32.
1706 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1707  std::string Name = VT.isVector() ? "vec-" : "";
1708 
1709  Name += IsSqrt ? "sqrt" : "div";
1710 
1711  // TODO: Handle "half" or other float types?
1712  if (VT.getScalarType() == MVT::f64) {
1713  Name += "d";
1714  } else {
1715  assert(VT.getScalarType() == MVT::f32 &&
1716  "Unexpected FP type for reciprocal estimate");
1717  Name += "f";
1718  }
1719 
1720  return Name;
1721 }
1722 
1723 /// Return the character position and value (a single numeric character) of a
1724 /// customized refinement operation in the input string if it exists. Return
1725 /// false if there is no customized refinement step count.
1727  uint8_t &Value) {
1728  const char RefStepToken = ':';
1729  Position = In.find(RefStepToken);
1730  if (Position == StringRef::npos)
1731  return false;
1732 
1733  StringRef RefStepString = In.substr(Position + 1);
1734  // Allow exactly one numeric character for the additional refinement
1735  // step parameter.
1736  if (RefStepString.size() == 1) {
1737  char RefStepChar = RefStepString[0];
1738  if (RefStepChar >= '0' && RefStepChar <= '9') {
1739  Value = RefStepChar - '0';
1740  return true;
1741  }
1742  }
1743  report_fatal_error("Invalid refinement step for -recip.");
1744 }
1745 
1746 /// For the input attribute string, return one of the ReciprocalEstimate enum
1747 /// status values (enabled, disabled, or not specified) for this operation on
1748 /// the specified data type.
1749 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1750  if (Override.empty())
1751  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1752 
1753  SmallVector<StringRef, 4> OverrideVector;
1754  Override.split(OverrideVector, ',');
1755  unsigned NumArgs = OverrideVector.size();
1756 
1757  // Check if "all", "none", or "default" was specified.
1758  if (NumArgs == 1) {
1759  // Look for an optional setting of the number of refinement steps needed
1760  // for this type of reciprocal operation.
1761  size_t RefPos;
1762  uint8_t RefSteps;
1763  if (parseRefinementStep(Override, RefPos, RefSteps)) {
1764  // Split the string for further processing.
1765  Override = Override.substr(0, RefPos);
1766  }
1767 
1768  // All reciprocal types are enabled.
1769  if (Override == "all")
1771 
1772  // All reciprocal types are disabled.
1773  if (Override == "none")
1774  return TargetLoweringBase::ReciprocalEstimate::Disabled;
1775 
1776  // Target defaults for enablement are used.
1777  if (Override == "default")
1778  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1779  }
1780 
1781  // The attribute string may omit the size suffix ('f'/'d').
1782  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1783  std::string VTNameNoSize = VTName;
1784  VTNameNoSize.pop_back();
1785  static const char DisabledPrefix = '!';
1786 
1787  for (StringRef RecipType : OverrideVector) {
1788  size_t RefPos;
1789  uint8_t RefSteps;
1790  if (parseRefinementStep(RecipType, RefPos, RefSteps))
1791  RecipType = RecipType.substr(0, RefPos);
1792 
1793  // Ignore the disablement token for string matching.
1794  bool IsDisabled = RecipType[0] == DisabledPrefix;
1795  if (IsDisabled)
1796  RecipType = RecipType.substr(1);
1797 
1798  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1799  return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
1801  }
1802 
1803  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1804 }
1805 
1806 /// For the input attribute string, return the customized refinement step count
1807 /// for this operation on the specified data type. If the step count does not
1808 /// exist, return the ReciprocalEstimate enum value for unspecified.
1809 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
1810  if (Override.empty())
1811  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1812 
1813  SmallVector<StringRef, 4> OverrideVector;
1814  Override.split(OverrideVector, ',');
1815  unsigned NumArgs = OverrideVector.size();
1816 
1817  // Check if "all", "default", or "none" was specified.
1818  if (NumArgs == 1) {
1819  // Look for an optional setting of the number of refinement steps needed
1820  // for this type of reciprocal operation.
1821  size_t RefPos;
1822  uint8_t RefSteps;
1823  if (!parseRefinementStep(Override, RefPos, RefSteps))
1824  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1825 
1826  // Split the string for further processing.
1827  Override = Override.substr(0, RefPos);
1828  assert(Override != "none" &&
1829  "Disabled reciprocals, but specifed refinement steps?");
1830 
1831  // If this is a general override, return the specified number of steps.
1832  if (Override == "all" || Override == "default")
1833  return RefSteps;
1834  }
1835 
1836  // The attribute string may omit the size suffix ('f'/'d').
1837  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1838  std::string VTNameNoSize = VTName;
1839  VTNameNoSize.pop_back();
1840 
1841  for (StringRef RecipType : OverrideVector) {
1842  size_t RefPos;
1843  uint8_t RefSteps;
1844  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
1845  continue;
1846 
1847  RecipType = RecipType.substr(0, RefPos);
1848  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1849  return RefSteps;
1850  }
1851 
1852  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1853 }
1854 
1856  MachineFunction &MF) const {
1857  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
1858 }
1859 
1861  MachineFunction &MF) const {
1862  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
1863 }
1864 
1866  MachineFunction &MF) const {
1867  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
1868 }
1869 
1871  MachineFunction &MF) const {
1872  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
1873 }
1874 
1876  MF.getRegInfo().freezeReservedRegs(MF);
1877 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
static bool darwinHasSinCos(const Triple &TT)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:571
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:538
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:475
static MVT getIntegerVT(unsigned BitWidth)
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:259
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:594
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
LLVMContext & Context
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:359
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:250
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
This class represents lattice values for constants.
Definition: AllocatorList.h:24
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:447
static MVT getVectorVT(MVT VT, unsigned NumElements)
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:605
Constant * getOrInsertFunction(StringRef Name, FunctionType *T, AttributeList AttributeList)
Look up the specified function in the module symbol table.
Definition: Module.cpp:144
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:367
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:260
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:519
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
Y = RRC X, rotate right via carry.
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:251
static cl::opt< int > MinPercentageForPredictableBranch("min-predictable-branch", cl::init(99), cl::desc("Minimum percentage (0-100) that a condition must be either true " "or false to assume that the condition is predictable"), cl::Hidden)
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled...
unsigned getVectorNumElements() const
Externally visible function.
Definition: GlobalValue.h:49
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:802
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
F(f)
bool isOSFuchsia() const
Definition: Triple.h:495
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:508
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:384
Same for subtraction.
Definition: ISDOpcodes.h:254
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:316
bool isValid() const
Return true if this is a valid simple valuetype.
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type...
Definition: ValueTypes.h:366
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function&#39;s at...
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
A description of a memory reference used in the backend.
amdgpu Simplify well known AMD library false Value Value const Twine & Name
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
Shift and rotation operations.
Definition: ISDOpcodes.h:410
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:244
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:393
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:652
RESULT = SMULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same wi...
Definition: ISDOpcodes.h:280
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:743
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:810
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Position
Position to insert a new instruction relative to an existing instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
unsigned getNumRegClasses() const
unsigned getSizeInBits() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:478
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:290
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:121
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
GlobalValue * getNamedValue(StringRef Name) const
Return the global value in the module with the specified name, of arbitrary type. ...
Definition: Module.cpp:114
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:456
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:959
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:598
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:747
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:497
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:84
MVT getVectorElementType() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function&#39;s attri...
Class to represent pointers.
Definition: DerivedTypes.h:467
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:103
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:524
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
The memory access is volatile.
virtual Value * getIRStackGuard(IRBuilder<> &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:423
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:429
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
Simple binary floating point operators.
Definition: ISDOpcodes.h:283
bool isOSOpenBSD() const
Definition: Triple.h:487
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
unsigned getScalarSizeInBits() const
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:629
bool isWatchABI() const
Definition: Triple.h:470
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:332
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:232
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
static mvt_range fp_valuetypes()
bool isAndroidVersionLT(unsigned Major) const
Definition: Triple.h:639
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:767
const Triple & getTargetTriple() const
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:770
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(0), cl::Hidden, cl::desc("Set maximum size of jump tables; zero for no limit."))
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:416
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:796
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:556
virtual Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Extended Value Type.
Definition: ValueTypes.h:34
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:640
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
size_t size() const
Definition: SmallVector.h:53
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:220
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function&#39;s attributes...
const TargetMachine & getTargetMachine() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Value * getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) const
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
The memory access writes data.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
void initActions()
Initialize all of the actions to default values.
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:265
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal...
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight)...
Definition: ValueTypes.h:317
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:339
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:265
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:451
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:575
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
Module.h This file contains the declarations for the Module class.
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:727
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1044
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:730
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values, following the IEEE-754 2008 definition.
Definition: ISDOpcodes.h:600
static bool Enabled
Definition: Statistic.cpp:51
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:73
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:420
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:241
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:468
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:471
ValueTypeActionImpl ValueTypeActions
#define OP_TO_LIBCALL(Name, Enum)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:312
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
virtual Value * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function&#39;s attribut...
The memory access reads data.
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca...
Definition: ISDOpcodes.h:859
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static mvt_range all_valuetypes()
SimpleValueType Iteration.
Representation of each machine instruction.
Definition: MachineInstr.h:64
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Constant * getOrInsertGlobal(StringRef Name, Type *Ty, function_ref< GlobalVariable *()> CreateGlobalCallback)
Look up the specified global in the module symbol table.
Definition: Module.cpp:206
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:387
static const size_t npos
Definition: StringRef.h:51
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineBasicBlock * emitXRayCustomEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay custom event operands with target-dependent details.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1269
void setTypeAction(MVT VT, LegalizeTypeAction Action)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:614
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return &#39;Legal&#39;) or we ...
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:107
MachineBasicBlock * emitXRayTypedEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay typed event operands with target-dependent details.
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
bool isGNUEnvironment() const
Definition: Triple.h:511
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:273
Same for multiplication.
Definition: ISDOpcodes.h:257
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:922
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value *> Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:1974
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that&#39;s previously inserted by insertSSPDeclarations, if any, otherwise return nul...
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool isMacOSXVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isMacOSXVersionLT - Comparison function for checking OS X version compatibility, which handles suppor...
Definition: Triple.h:432
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:345
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:807
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:566
LLVM Value Representation.
Definition: Value.h:73
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:251
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:776
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:637
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:331
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
Definition: ISDOpcodes.h:306
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:443
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isOSVersionLT - Helper function for doing comparisons against version numbers included in the target ...
Definition: Triple.h:408
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:198
Conversion operators.
Definition: ISDOpcodes.h:465
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:474
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:126
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:298
virtual BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:584
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:64
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add &#39;1&#39; bits from Mask to this vector.
Definition: BitVector.h:776
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:242
LegalizeTypeAction getTypeAction(MVT VT) const
This file describes how to lower LLVM code to machine code.
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class...
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...