LLVM  10.0.0svn
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/CodeGen/Analysis.h"
31 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalValue.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/IRBuilder.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
47 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/Compiler.h"
54 #include <algorithm>
55 #include <cassert>
56 #include <cstddef>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <tuple>
62 #include <utility>
63 
64 using namespace llvm;
65 
67  "jump-is-expensive", cl::init(false),
68  cl::desc("Do not create extra branches to split comparison logic."),
69  cl::Hidden);
70 
72  ("min-jump-table-entries", cl::init(4), cl::Hidden,
73  cl::desc("Set minimum number of entries to use a jump table."));
74 
76  ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
77  cl::desc("Set maximum size of jump tables."));
78 
79 /// Minimum jump table density for normal functions.
80 static cl::opt<unsigned>
81  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
82  cl::desc("Minimum density for building a jump table in "
83  "a normal function"));
84 
85 /// Minimum jump table density for -Os or -Oz functions.
87  "optsize-jump-table-density", cl::init(40), cl::Hidden,
88  cl::desc("Minimum density for building a jump table in "
89  "an optsize function"));
90 
91 static bool darwinHasSinCos(const Triple &TT) {
92  assert(TT.isOSDarwin() && "should be called with darwin triple");
93  // Don't bother with 32 bit x86.
94  if (TT.getArch() == Triple::x86)
95  return false;
96  // Macos < 10.9 has no sincos_stret.
97  if (TT.isMacOSX())
98  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
99  // iOS < 7.0 has no sincos_stret.
100  if (TT.isiOS())
101  return !TT.isOSVersionLT(7, 0);
102  // Any other darwin such as WatchOS/TvOS is new enough.
103  return true;
104 }
105 
106 // Although this default value is arbitrary, it is not random. It is assumed
107 // that a condition that evaluates the same way by a higher percentage than this
108 // is best represented as control flow. Therefore, the default value N should be
109 // set such that the win from N% correct executions is greater than the loss
110 // from (100 - N)% mispredicted executions for the majority of intended targets.
112  "min-predictable-branch", cl::init(99),
113  cl::desc("Minimum percentage (0-100) that a condition must be either true "
114  "or false to assume that the condition is predictable"),
115  cl::Hidden);
116 
117 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
118 #define HANDLE_LIBCALL(code, name) \
119  setLibcallName(RTLIB::code, name);
120 #include "llvm/IR/RuntimeLibcalls.def"
121 #undef HANDLE_LIBCALL
122  // Initialize calling conventions to their default.
123  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
125 
126  // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
127  if (TT.getArch() == Triple::ppc || TT.isPPC64()) {
128  setLibcallName(RTLIB::ADD_F128, "__addkf3");
129  setLibcallName(RTLIB::SUB_F128, "__subkf3");
130  setLibcallName(RTLIB::MUL_F128, "__mulkf3");
131  setLibcallName(RTLIB::DIV_F128, "__divkf3");
132  setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
133  setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
134  setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
135  setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
136  setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
137  setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
138  setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
139  setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
140  setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
141  setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
142  setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
143  setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
144  setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
145  setLibcallName(RTLIB::UNE_F128, "__nekf2");
146  setLibcallName(RTLIB::OGE_F128, "__gekf2");
147  setLibcallName(RTLIB::OLT_F128, "__ltkf2");
148  setLibcallName(RTLIB::OLE_F128, "__lekf2");
149  setLibcallName(RTLIB::OGT_F128, "__gtkf2");
150  setLibcallName(RTLIB::UO_F128, "__unordkf2");
151  setLibcallName(RTLIB::O_F128, "__unordkf2");
152  }
153 
154  // A few names are different on particular architectures or environments.
155  if (TT.isOSDarwin()) {
156  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
157  // of the gnueabi-style __gnu_*_ieee.
158  // FIXME: What about other targets?
159  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
160  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
161 
162  // Some darwins have an optimized __bzero/bzero function.
163  switch (TT.getArch()) {
164  case Triple::x86:
165  case Triple::x86_64:
166  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
167  setLibcallName(RTLIB::BZERO, "__bzero");
168  break;
169  case Triple::aarch64:
170  case Triple::aarch64_32:
171  setLibcallName(RTLIB::BZERO, "bzero");
172  break;
173  default:
174  break;
175  }
176 
177  if (darwinHasSinCos(TT)) {
178  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
179  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
180  if (TT.isWatchABI()) {
181  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
183  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
185  }
186  }
187  } else {
188  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
189  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
190  }
191 
192  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
193  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
194  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
195  setLibcallName(RTLIB::SINCOS_F64, "sincos");
196  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
197  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
198  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
199  }
200 
201  if (TT.isPS4CPU()) {
202  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
203  setLibcallName(RTLIB::SINCOS_F64, "sincos");
204  }
205 
206  if (TT.isOSOpenBSD()) {
207  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
208  }
209 }
210 
211 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
212 /// UNKNOWN_LIBCALL if there is none.
214  if (OpVT == MVT::f16) {
215  if (RetVT == MVT::f32)
216  return FPEXT_F16_F32;
217  } else if (OpVT == MVT::f32) {
218  if (RetVT == MVT::f64)
219  return FPEXT_F32_F64;
220  if (RetVT == MVT::f128)
221  return FPEXT_F32_F128;
222  if (RetVT == MVT::ppcf128)
223  return FPEXT_F32_PPCF128;
224  } else if (OpVT == MVT::f64) {
225  if (RetVT == MVT::f128)
226  return FPEXT_F64_F128;
227  else if (RetVT == MVT::ppcf128)
228  return FPEXT_F64_PPCF128;
229  } else if (OpVT == MVT::f80) {
230  if (RetVT == MVT::f128)
231  return FPEXT_F80_F128;
232  }
233 
234  return UNKNOWN_LIBCALL;
235 }
236 
237 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
238 /// UNKNOWN_LIBCALL if there is none.
240  if (RetVT == MVT::f16) {
241  if (OpVT == MVT::f32)
242  return FPROUND_F32_F16;
243  if (OpVT == MVT::f64)
244  return FPROUND_F64_F16;
245  if (OpVT == MVT::f80)
246  return FPROUND_F80_F16;
247  if (OpVT == MVT::f128)
248  return FPROUND_F128_F16;
249  if (OpVT == MVT::ppcf128)
250  return FPROUND_PPCF128_F16;
251  } else if (RetVT == MVT::f32) {
252  if (OpVT == MVT::f64)
253  return FPROUND_F64_F32;
254  if (OpVT == MVT::f80)
255  return FPROUND_F80_F32;
256  if (OpVT == MVT::f128)
257  return FPROUND_F128_F32;
258  if (OpVT == MVT::ppcf128)
259  return FPROUND_PPCF128_F32;
260  } else if (RetVT == MVT::f64) {
261  if (OpVT == MVT::f80)
262  return FPROUND_F80_F64;
263  if (OpVT == MVT::f128)
264  return FPROUND_F128_F64;
265  if (OpVT == MVT::ppcf128)
266  return FPROUND_PPCF128_F64;
267  } else if (RetVT == MVT::f80) {
268  if (OpVT == MVT::f128)
269  return FPROUND_F128_F80;
270  }
271 
272  return UNKNOWN_LIBCALL;
273 }
274 
275 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
276 /// UNKNOWN_LIBCALL if there is none.
278  if (OpVT == MVT::f32) {
279  if (RetVT == MVT::i32)
280  return FPTOSINT_F32_I32;
281  if (RetVT == MVT::i64)
282  return FPTOSINT_F32_I64;
283  if (RetVT == MVT::i128)
284  return FPTOSINT_F32_I128;
285  } else if (OpVT == MVT::f64) {
286  if (RetVT == MVT::i32)
287  return FPTOSINT_F64_I32;
288  if (RetVT == MVT::i64)
289  return FPTOSINT_F64_I64;
290  if (RetVT == MVT::i128)
291  return FPTOSINT_F64_I128;
292  } else if (OpVT == MVT::f80) {
293  if (RetVT == MVT::i32)
294  return FPTOSINT_F80_I32;
295  if (RetVT == MVT::i64)
296  return FPTOSINT_F80_I64;
297  if (RetVT == MVT::i128)
298  return FPTOSINT_F80_I128;
299  } else if (OpVT == MVT::f128) {
300  if (RetVT == MVT::i32)
301  return FPTOSINT_F128_I32;
302  if (RetVT == MVT::i64)
303  return FPTOSINT_F128_I64;
304  if (RetVT == MVT::i128)
305  return FPTOSINT_F128_I128;
306  } else if (OpVT == MVT::ppcf128) {
307  if (RetVT == MVT::i32)
308  return FPTOSINT_PPCF128_I32;
309  if (RetVT == MVT::i64)
310  return FPTOSINT_PPCF128_I64;
311  if (RetVT == MVT::i128)
312  return FPTOSINT_PPCF128_I128;
313  }
314  return UNKNOWN_LIBCALL;
315 }
316 
317 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
318 /// UNKNOWN_LIBCALL if there is none.
320  if (OpVT == MVT::f32) {
321  if (RetVT == MVT::i32)
322  return FPTOUINT_F32_I32;
323  if (RetVT == MVT::i64)
324  return FPTOUINT_F32_I64;
325  if (RetVT == MVT::i128)
326  return FPTOUINT_F32_I128;
327  } else if (OpVT == MVT::f64) {
328  if (RetVT == MVT::i32)
329  return FPTOUINT_F64_I32;
330  if (RetVT == MVT::i64)
331  return FPTOUINT_F64_I64;
332  if (RetVT == MVT::i128)
333  return FPTOUINT_F64_I128;
334  } else if (OpVT == MVT::f80) {
335  if (RetVT == MVT::i32)
336  return FPTOUINT_F80_I32;
337  if (RetVT == MVT::i64)
338  return FPTOUINT_F80_I64;
339  if (RetVT == MVT::i128)
340  return FPTOUINT_F80_I128;
341  } else if (OpVT == MVT::f128) {
342  if (RetVT == MVT::i32)
343  return FPTOUINT_F128_I32;
344  if (RetVT == MVT::i64)
345  return FPTOUINT_F128_I64;
346  if (RetVT == MVT::i128)
347  return FPTOUINT_F128_I128;
348  } else if (OpVT == MVT::ppcf128) {
349  if (RetVT == MVT::i32)
350  return FPTOUINT_PPCF128_I32;
351  if (RetVT == MVT::i64)
352  return FPTOUINT_PPCF128_I64;
353  if (RetVT == MVT::i128)
354  return FPTOUINT_PPCF128_I128;
355  }
356  return UNKNOWN_LIBCALL;
357 }
358 
359 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
360 /// UNKNOWN_LIBCALL if there is none.
362  if (OpVT == MVT::i32) {
363  if (RetVT == MVT::f32)
364  return SINTTOFP_I32_F32;
365  if (RetVT == MVT::f64)
366  return SINTTOFP_I32_F64;
367  if (RetVT == MVT::f80)
368  return SINTTOFP_I32_F80;
369  if (RetVT == MVT::f128)
370  return SINTTOFP_I32_F128;
371  if (RetVT == MVT::ppcf128)
372  return SINTTOFP_I32_PPCF128;
373  } else if (OpVT == MVT::i64) {
374  if (RetVT == MVT::f32)
375  return SINTTOFP_I64_F32;
376  if (RetVT == MVT::f64)
377  return SINTTOFP_I64_F64;
378  if (RetVT == MVT::f80)
379  return SINTTOFP_I64_F80;
380  if (RetVT == MVT::f128)
381  return SINTTOFP_I64_F128;
382  if (RetVT == MVT::ppcf128)
383  return SINTTOFP_I64_PPCF128;
384  } else if (OpVT == MVT::i128) {
385  if (RetVT == MVT::f32)
386  return SINTTOFP_I128_F32;
387  if (RetVT == MVT::f64)
388  return SINTTOFP_I128_F64;
389  if (RetVT == MVT::f80)
390  return SINTTOFP_I128_F80;
391  if (RetVT == MVT::f128)
392  return SINTTOFP_I128_F128;
393  if (RetVT == MVT::ppcf128)
394  return SINTTOFP_I128_PPCF128;
395  }
396  return UNKNOWN_LIBCALL;
397 }
398 
399 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
400 /// UNKNOWN_LIBCALL if there is none.
402  if (OpVT == MVT::i32) {
403  if (RetVT == MVT::f32)
404  return UINTTOFP_I32_F32;
405  if (RetVT == MVT::f64)
406  return UINTTOFP_I32_F64;
407  if (RetVT == MVT::f80)
408  return UINTTOFP_I32_F80;
409  if (RetVT == MVT::f128)
410  return UINTTOFP_I32_F128;
411  if (RetVT == MVT::ppcf128)
412  return UINTTOFP_I32_PPCF128;
413  } else if (OpVT == MVT::i64) {
414  if (RetVT == MVT::f32)
415  return UINTTOFP_I64_F32;
416  if (RetVT == MVT::f64)
417  return UINTTOFP_I64_F64;
418  if (RetVT == MVT::f80)
419  return UINTTOFP_I64_F80;
420  if (RetVT == MVT::f128)
421  return UINTTOFP_I64_F128;
422  if (RetVT == MVT::ppcf128)
423  return UINTTOFP_I64_PPCF128;
424  } else if (OpVT == MVT::i128) {
425  if (RetVT == MVT::f32)
426  return UINTTOFP_I128_F32;
427  if (RetVT == MVT::f64)
428  return UINTTOFP_I128_F64;
429  if (RetVT == MVT::f80)
430  return UINTTOFP_I128_F80;
431  if (RetVT == MVT::f128)
432  return UINTTOFP_I128_F128;
433  if (RetVT == MVT::ppcf128)
434  return UINTTOFP_I128_PPCF128;
435  }
436  return UNKNOWN_LIBCALL;
437 }
438 
439 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
440 #define OP_TO_LIBCALL(Name, Enum) \
441  case Name: \
442  switch (VT.SimpleTy) { \
443  default: \
444  return UNKNOWN_LIBCALL; \
445  case MVT::i8: \
446  return Enum##_1; \
447  case MVT::i16: \
448  return Enum##_2; \
449  case MVT::i32: \
450  return Enum##_4; \
451  case MVT::i64: \
452  return Enum##_8; \
453  case MVT::i128: \
454  return Enum##_16; \
455  }
456 
457  switch (Opc) {
458  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
459  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
460  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
461  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
462  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
463  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
464  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
465  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
466  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
467  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
468  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
469  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
470  }
471 
472 #undef OP_TO_LIBCALL
473 
474  return UNKNOWN_LIBCALL;
475 }
476 
478  switch (ElementSize) {
479  case 1:
480  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
481  case 2:
482  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
483  case 4:
484  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
485  case 8:
486  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
487  case 16:
488  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
489  default:
490  return UNKNOWN_LIBCALL;
491  }
492 }
493 
495  switch (ElementSize) {
496  case 1:
497  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
498  case 2:
499  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
500  case 4:
501  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
502  case 8:
503  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
504  case 16:
505  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
506  default:
507  return UNKNOWN_LIBCALL;
508  }
509 }
510 
512  switch (ElementSize) {
513  case 1:
514  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
515  case 2:
516  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
517  case 4:
518  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
519  case 8:
520  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
521  case 16:
522  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
523  default:
524  return UNKNOWN_LIBCALL;
525  }
526 }
527 
528 /// InitCmpLibcallCCs - Set default comparison libcall CC.
529 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
530  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
531  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
532  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
533  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
534  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
535  CCs[RTLIB::UNE_F32] = ISD::SETNE;
536  CCs[RTLIB::UNE_F64] = ISD::SETNE;
537  CCs[RTLIB::UNE_F128] = ISD::SETNE;
538  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
539  CCs[RTLIB::OGE_F32] = ISD::SETGE;
540  CCs[RTLIB::OGE_F64] = ISD::SETGE;
541  CCs[RTLIB::OGE_F128] = ISD::SETGE;
542  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
543  CCs[RTLIB::OLT_F32] = ISD::SETLT;
544  CCs[RTLIB::OLT_F64] = ISD::SETLT;
545  CCs[RTLIB::OLT_F128] = ISD::SETLT;
546  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
547  CCs[RTLIB::OLE_F32] = ISD::SETLE;
548  CCs[RTLIB::OLE_F64] = ISD::SETLE;
549  CCs[RTLIB::OLE_F128] = ISD::SETLE;
550  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
551  CCs[RTLIB::OGT_F32] = ISD::SETGT;
552  CCs[RTLIB::OGT_F64] = ISD::SETGT;
553  CCs[RTLIB::OGT_F128] = ISD::SETGT;
554  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
555  CCs[RTLIB::UO_F32] = ISD::SETNE;
556  CCs[RTLIB::UO_F64] = ISD::SETNE;
557  CCs[RTLIB::UO_F128] = ISD::SETNE;
558  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
559  CCs[RTLIB::O_F32] = ISD::SETEQ;
560  CCs[RTLIB::O_F64] = ISD::SETEQ;
561  CCs[RTLIB::O_F128] = ISD::SETEQ;
562  CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
563 }
564 
565 /// NOTE: The TargetMachine owns TLOF.
567  initActions();
568 
569  // Perform these initializations only once.
571  MaxLoadsPerMemcmp = 8;
575  UseUnderscoreSetJmp = false;
576  UseUnderscoreLongJmp = false;
577  HasMultipleConditionRegisters = false;
578  HasExtractBitsInsn = false;
579  JumpIsExpensive = JumpIsExpensiveOverride;
581  EnableExtLdPromotion = false;
582  StackPointerRegisterToSaveRestore = 0;
583  BooleanContents = UndefinedBooleanContent;
584  BooleanFloatContents = UndefinedBooleanContent;
585  BooleanVectorContents = UndefinedBooleanContent;
586  SchedPreferenceInfo = Sched::ILP;
588  // TODO: the default will be switched to 0 in the next commit, along
589  // with the Target-specific changes necessary.
590  MaxAtomicSizeInBitsSupported = 1024;
591 
592  MinCmpXchgSizeInBits = 0;
593  SupportsUnalignedAtomics = false;
594 
595  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
596 
597  InitLibcalls(TM.getTargetTriple());
598  InitCmpLibcallCCs(CmpLibcallCCs);
599 }
600 
602  // All operations default to being supported.
603  memset(OpActions, 0, sizeof(OpActions));
604  memset(LoadExtActions, 0, sizeof(LoadExtActions));
605  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
606  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
607  memset(CondCodeActions, 0, sizeof(CondCodeActions));
608  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
609  std::fill(std::begin(TargetDAGCombineArray),
610  std::end(TargetDAGCombineArray), 0);
611 
612  for (MVT VT : MVT::fp_valuetypes()) {
613  MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
614  if (IntVT.isValid()) {
617  }
618  }
619 
620  // Set default actions for various operations.
621  for (MVT VT : MVT::all_valuetypes()) {
622  // Default all indexed load / store to expand.
623  for (unsigned IM = (unsigned)ISD::PRE_INC;
624  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
625  setIndexedLoadAction(IM, VT, Expand);
626  setIndexedStoreAction(IM, VT, Expand);
627  }
628 
629  // Most backends expect to see the node which just returns the value loaded.
631 
632  // These operations default to expand.
657 
658  // Overflow operations default to expand
665 
666  // ADDCARRY operations default to expand
670 
671  // ADDC/ADDE/SUBC/SUBE default to expand.
676 
677  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
680 
682 
683  // These library functions default to expand.
686 
687  // These operations default to expand for vector types.
688  if (VT.isVector()) {
694  }
695 
696  // Constrained floating-point operations default to expand.
729 
730  // For most targets @llvm.get.dynamic.area.offset just returns 0.
732 
733  // Vector reduction default to expand.
747  }
748 
749  // Most targets ignore the @llvm.prefetch intrinsic.
751 
752  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
754 
755  // ConstantFP nodes default to expand. Targets can either change this to
756  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
757  // to optimize expansions for certain constants.
763 
764  // These library functions default to expand.
765  for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
782  }
783 
784  // Default ISD::TRAP to expand (which turns it into abort).
786 
787  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
788  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
790 }
791 
793  EVT) const {
795 }
796 
798  bool LegalTypes) const {
799  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
800  if (LHSTy.isVector())
801  return LHSTy;
802  return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
803  : getPointerTy(DL);
804 }
805 
806 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
807  assert(isTypeLegal(VT));
808  switch (Op) {
809  default:
810  return false;
811  case ISD::SDIV:
812  case ISD::UDIV:
813  case ISD::SREM:
814  case ISD::UREM:
815  return true;
816  }
817 }
818 
820  // If the command-line option was specified, ignore this request.
821  if (!JumpIsExpensiveOverride.getNumOccurrences())
822  JumpIsExpensive = isExpensive;
823 }
824 
826 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
827  // If this is a simple type, use the ComputeRegisterProp mechanism.
828  if (VT.isSimple()) {
829  MVT SVT = VT.getSimpleVT();
830  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
831  MVT NVT = TransformToType[SVT.SimpleTy];
832  LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
833 
834  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
835  (NVT.isVector() ||
836  ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
837  "Promote may not follow Expand or Promote");
838 
839  if (LA == TypeSplitVector)
840  return LegalizeKind(LA,
841  EVT::getVectorVT(Context, SVT.getVectorElementType(),
842  SVT.getVectorNumElements() / 2));
843  if (LA == TypeScalarizeVector)
844  return LegalizeKind(LA, SVT.getVectorElementType());
845  return LegalizeKind(LA, NVT);
846  }
847 
848  // Handle Extended Scalar Types.
849  if (!VT.isVector()) {
850  assert(VT.isInteger() && "Float types must be simple");
851  unsigned BitSize = VT.getSizeInBits();
852  // First promote to a power-of-two size, then expand if necessary.
853  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
854  EVT NVT = VT.getRoundIntegerType(Context);
855  assert(NVT != VT && "Unable to round integer VT");
856  LegalizeKind NextStep = getTypeConversion(Context, NVT);
857  // Avoid multi-step promotion.
858  if (NextStep.first == TypePromoteInteger)
859  return NextStep;
860  // Return rounded integer type.
861  return LegalizeKind(TypePromoteInteger, NVT);
862  }
863 
865  EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
866  }
867 
868  // Handle vector types.
869  unsigned NumElts = VT.getVectorNumElements();
870  EVT EltVT = VT.getVectorElementType();
871 
872  // Vectors with only one element are always scalarized.
873  if (NumElts == 1)
874  return LegalizeKind(TypeScalarizeVector, EltVT);
875 
876  // Try to widen vector elements until the element type is a power of two and
877  // promote it to a legal type later on, for example:
878  // <3 x i8> -> <4 x i8> -> <4 x i32>
879  if (EltVT.isInteger()) {
880  // Vectors with a number of elements that is not a power of two are always
881  // widened, for example <3 x i8> -> <4 x i8>.
882  if (!VT.isPow2VectorType()) {
883  NumElts = (unsigned)NextPowerOf2(NumElts);
884  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
885  return LegalizeKind(TypeWidenVector, NVT);
886  }
887 
888  // Examine the element type.
889  LegalizeKind LK = getTypeConversion(Context, EltVT);
890 
891  // If type is to be expanded, split the vector.
892  // <4 x i140> -> <2 x i140>
893  if (LK.first == TypeExpandInteger)
895  EVT::getVectorVT(Context, EltVT, NumElts / 2));
896 
897  // Promote the integer element types until a legal vector type is found
898  // or until the element integer type is too big. If a legal type was not
899  // found, fallback to the usual mechanism of widening/splitting the
900  // vector.
901  EVT OldEltVT = EltVT;
902  while (true) {
903  // Increase the bitwidth of the element to the next pow-of-two
904  // (which is greater than 8 bits).
905  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
906  .getRoundIntegerType(Context);
907 
908  // Stop trying when getting a non-simple element type.
909  // Note that vector elements may be greater than legal vector element
910  // types. Example: X86 XMM registers hold 64bit element on 32bit
911  // systems.
912  if (!EltVT.isSimple())
913  break;
914 
915  // Build a new vector type and check if it is legal.
916  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
917  // Found a legal promoted vector type.
918  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
920  EVT::getVectorVT(Context, EltVT, NumElts));
921  }
922 
923  // Reset the type to the unexpanded type if we did not find a legal vector
924  // type with a promoted vector element type.
925  EltVT = OldEltVT;
926  }
927 
928  // Try to widen the vector until a legal type is found.
929  // If there is no wider legal type, split the vector.
930  while (true) {
931  // Round up to the next power of 2.
932  NumElts = (unsigned)NextPowerOf2(NumElts);
933 
934  // If there is no simple vector type with this many elements then there
935  // cannot be a larger legal vector type. Note that this assumes that
936  // there are no skipped intermediate vector types in the simple types.
937  if (!EltVT.isSimple())
938  break;
939  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
940  if (LargerVector == MVT())
941  break;
942 
943  // If this type is legal then widen the vector.
944  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
945  return LegalizeKind(TypeWidenVector, LargerVector);
946  }
947 
948  // Widen odd vectors to next power of two.
949  if (!VT.isPow2VectorType()) {
950  EVT NVT = VT.getPow2VectorType(Context);
951  return LegalizeKind(TypeWidenVector, NVT);
952  }
953 
954  // Vectors with illegal element types are expanded.
955  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
956  return LegalizeKind(TypeSplitVector, NVT);
957 }
958 
959 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
960  unsigned &NumIntermediates,
961  MVT &RegisterVT,
962  TargetLoweringBase *TLI) {
963  // Figure out the right, legal destination reg to copy into.
964  unsigned NumElts = VT.getVectorNumElements();
965  MVT EltTy = VT.getVectorElementType();
966 
967  unsigned NumVectorRegs = 1;
968 
969  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
970  // could break down into LHS/RHS like LegalizeDAG does.
971  if (!isPowerOf2_32(NumElts)) {
972  NumVectorRegs = NumElts;
973  NumElts = 1;
974  }
975 
976  // Divide the input until we get to a supported size. This will always
977  // end with a scalar if the target doesn't support vectors.
978  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
979  NumElts >>= 1;
980  NumVectorRegs <<= 1;
981  }
982 
983  NumIntermediates = NumVectorRegs;
984 
985  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
986  if (!TLI->isTypeLegal(NewVT))
987  NewVT = EltTy;
988  IntermediateVT = NewVT;
989 
990  unsigned NewVTSize = NewVT.getSizeInBits();
991 
992  // Convert sizes such as i33 to i64.
993  if (!isPowerOf2_32(NewVTSize))
994  NewVTSize = NextPowerOf2(NewVTSize);
995 
996  MVT DestVT = TLI->getRegisterType(NewVT);
997  RegisterVT = DestVT;
998  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
999  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1000 
1001  // Otherwise, promotion or legal types use the same number of registers as
1002  // the vector decimated to the appropriate level.
1003  return NumVectorRegs;
1004 }
1005 
1006 /// isLegalRC - Return true if the value types that can be represented by the
1007 /// specified register class are all legal.
1009  const TargetRegisterClass &RC) const {
1010  for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1011  if (isTypeLegal(*I))
1012  return true;
1013  return false;
1014 }
1015 
1016 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1017 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1020  MachineBasicBlock *MBB) const {
1021  MachineInstr *MI = &InitialMI;
1022  MachineFunction &MF = *MI->getMF();
1023  MachineFrameInfo &MFI = MF.getFrameInfo();
1024 
1025  // We're handling multiple types of operands here:
1026  // PATCHPOINT MetaArgs - live-in, read only, direct
1027  // STATEPOINT Deopt Spill - live-through, read only, indirect
1028  // STATEPOINT Deopt Alloca - live-through, read only, direct
1029  // (We're currently conservative and mark the deopt slots read/write in
1030  // practice.)
1031  // STATEPOINT GC Spill - live-through, read/write, indirect
1032  // STATEPOINT GC Alloca - live-through, read/write, direct
1033  // The live-in vs live-through is handled already (the live through ones are
1034  // all stack slots), but we need to handle the different type of stackmap
1035  // operands and memory effects here.
1036 
1037  // MI changes inside this loop as we grow operands.
1038  for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1039  MachineOperand &MO = MI->getOperand(OperIdx);
1040  if (!MO.isFI())
1041  continue;
1042 
1043  // foldMemoryOperand builds a new MI after replacing a single FI operand
1044  // with the canonical set of five x86 addressing-mode operands.
1045  int FI = MO.getIndex();
1046  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1047 
1048  // Copy operands before the frame-index.
1049  for (unsigned i = 0; i < OperIdx; ++i)
1050  MIB.add(MI->getOperand(i));
1051  // Add frame index operands recognized by stackmaps.cpp
1052  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1053  // indirect-mem-ref tag, size, #FI, offset.
1054  // Used for spills inserted by StatepointLowering. This codepath is not
1055  // used for patchpoints/stackmaps at all, for these spilling is done via
1056  // foldMemoryOperand callback only.
1057  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1058  MIB.addImm(StackMaps::IndirectMemRefOp);
1059  MIB.addImm(MFI.getObjectSize(FI));
1060  MIB.add(MI->getOperand(OperIdx));
1061  MIB.addImm(0);
1062  } else {
1063  // direct-mem-ref tag, #FI, offset.
1064  // Used by patchpoint, and direct alloca arguments to statepoints
1065  MIB.addImm(StackMaps::DirectMemRefOp);
1066  MIB.add(MI->getOperand(OperIdx));
1067  MIB.addImm(0);
1068  }
1069  // Copy the operands after the frame index.
1070  for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1071  MIB.add(MI->getOperand(i));
1072 
1073  // Inherit previous memory operands.
1074  MIB.cloneMemRefs(*MI);
1075  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1076 
1077  // Add a new memory operand for this FI.
1078  assert(MFI.getObjectOffset(FI) != -1);
1079 
1080  // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1081  // PATCHPOINT should be updated to do the same. (TODO)
1082  if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1083  auto Flags = MachineMemOperand::MOLoad;
1085  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1087  MIB->addMemOperand(MF, MMO);
1088  }
1089 
1090  // Replace the instruction and update the operand index.
1091  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1092  OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1093  MI->eraseFromParent();
1094  MI = MIB;
1095  }
1096  return MBB;
1097 }
1098 
1101  MachineBasicBlock *MBB) const {
1102  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL &&
1103  "Called emitXRayCustomEvent on the wrong MI!");
1104  auto &MF = *MI.getMF();
1105  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1106  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1107  MIB.add(MI.getOperand(OpIdx));
1108 
1109  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1110  MI.eraseFromParent();
1111  return MBB;
1112 }
1113 
1116  MachineBasicBlock *MBB) const {
1117  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL &&
1118  "Called emitXRayTypedEvent on the wrong MI!");
1119  auto &MF = *MI.getMF();
1120  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1121  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1122  MIB.add(MI.getOperand(OpIdx));
1123 
1124  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1125  MI.eraseFromParent();
1126  return MBB;
1127 }
1128 
1129 /// findRepresentativeClass - Return the largest legal super-reg register class
1130 /// of the register class for the specified type and its associated "cost".
1131 // This function is in TargetLowering because it uses RegClassForVT which would
1132 // need to be moved to TargetRegisterInfo and would necessitate moving
1133 // isTypeLegal over as well - a massive change that would just require
1134 // TargetLowering having a TargetRegisterInfo class member that it would use.
1135 std::pair<const TargetRegisterClass *, uint8_t>
1137  MVT VT) const {
1138  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1139  if (!RC)
1140  return std::make_pair(RC, 0);
1141 
1142  // Compute the set of all super-register classes.
1143  BitVector SuperRegRC(TRI->getNumRegClasses());
1144  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1145  SuperRegRC.setBitsInMask(RCI.getMask());
1146 
1147  // Find the first legal register class with the largest spill size.
1148  const TargetRegisterClass *BestRC = RC;
1149  for (unsigned i : SuperRegRC.set_bits()) {
1150  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1151  // We want the largest possible spill size.
1152  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1153  continue;
1154  if (!isLegalRC(*TRI, *SuperRC))
1155  continue;
1156  BestRC = SuperRC;
1157  }
1158  return std::make_pair(BestRC, 1);
1159 }
1160 
1161 /// computeRegisterProperties - Once all of the register classes are added,
1162 /// this allows us to compute derived properties we expose.
1164  const TargetRegisterInfo *TRI) {
1166  "Too many value types for ValueTypeActions to hold!");
1167 
1168  // Everything defaults to needing one register.
1169  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1170  NumRegistersForVT[i] = 1;
1171  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1172  }
1173  // ...except isVoid, which doesn't need any registers.
1174  NumRegistersForVT[MVT::isVoid] = 0;
1175 
1176  // Find the largest integer register class.
1177  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1178  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1179  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1180 
1181  // Every integer value type larger than this largest register takes twice as
1182  // many registers to represent as the previous ValueType.
1183  for (unsigned ExpandedReg = LargestIntReg + 1;
1184  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1185  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1186  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1187  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1188  ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1190  }
1191 
1192  // Inspect all of the ValueType's smaller than the largest integer
1193  // register to see which ones need promotion.
1194  unsigned LegalIntReg = LargestIntReg;
1195  for (unsigned IntReg = LargestIntReg - 1;
1196  IntReg >= (unsigned)MVT::i1; --IntReg) {
1197  MVT IVT = (MVT::SimpleValueType)IntReg;
1198  if (isTypeLegal(IVT)) {
1199  LegalIntReg = IntReg;
1200  } else {
1201  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1202  (MVT::SimpleValueType)LegalIntReg;
1203  ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1204  }
1205  }
1206 
1207  // ppcf128 type is really two f64's.
1208  if (!isTypeLegal(MVT::ppcf128)) {
1209  if (isTypeLegal(MVT::f64)) {
1210  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1211  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1212  TransformToType[MVT::ppcf128] = MVT::f64;
1213  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1214  } else {
1215  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1216  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1217  TransformToType[MVT::ppcf128] = MVT::i128;
1218  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1219  }
1220  }
1221 
1222  // Decide how to handle f128. If the target does not have native f128 support,
1223  // expand it to i128 and we will be generating soft float library calls.
1224  if (!isTypeLegal(MVT::f128)) {
1225  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1226  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1227  TransformToType[MVT::f128] = MVT::i128;
1228  ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1229  }
1230 
1231  // Decide how to handle f64. If the target does not have native f64 support,
1232  // expand it to i64 and we will be generating soft float library calls.
1233  if (!isTypeLegal(MVT::f64)) {
1234  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1235  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1236  TransformToType[MVT::f64] = MVT::i64;
1237  ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1238  }
1239 
1240  // Decide how to handle f32. If the target does not have native f32 support,
1241  // expand it to i32 and we will be generating soft float library calls.
1242  if (!isTypeLegal(MVT::f32)) {
1243  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1244  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1245  TransformToType[MVT::f32] = MVT::i32;
1246  ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1247  }
1248 
1249  // Decide how to handle f16. If the target does not have native f16 support,
1250  // promote it to f32, because there are no f16 library calls (except for
1251  // conversions).
1252  if (!isTypeLegal(MVT::f16)) {
1253  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1254  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1255  TransformToType[MVT::f16] = MVT::f32;
1256  ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1257  }
1258 
1259  // Loop over all of the vector value types to see which need transformations.
1260  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1261  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1262  MVT VT = (MVT::SimpleValueType) i;
1263  if (isTypeLegal(VT))
1264  continue;
1265 
1266  MVT EltVT = VT.getVectorElementType();
1267  unsigned NElts = VT.getVectorNumElements();
1268  bool IsLegalWiderType = false;
1269  bool IsScalable = VT.isScalableVector();
1270  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1271  switch (PreferredAction) {
1272  case TypePromoteInteger: {
1273  MVT::SimpleValueType EndVT = IsScalable ?
1276  // Try to promote the elements of integer vectors. If no legal
1277  // promotion was found, fall through to the widen-vector method.
1278  for (unsigned nVT = i + 1;
1279  (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1280  MVT SVT = (MVT::SimpleValueType) nVT;
1281  // Promote vectors of integers to vectors with the same number
1282  // of elements, with a wider element type.
1283  if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1284  SVT.getVectorNumElements() == NElts &&
1285  SVT.isScalableVector() == IsScalable && isTypeLegal(SVT)) {
1286  TransformToType[i] = SVT;
1287  RegisterTypeForVT[i] = SVT;
1288  NumRegistersForVT[i] = 1;
1289  ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1290  IsLegalWiderType = true;
1291  break;
1292  }
1293  }
1294  if (IsLegalWiderType)
1295  break;
1297  }
1298 
1299  case TypeWidenVector:
1300  if (isPowerOf2_32(NElts)) {
1301  // Try to widen the vector.
1302  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1303  MVT SVT = (MVT::SimpleValueType) nVT;
1304  if (SVT.getVectorElementType() == EltVT
1305  && SVT.getVectorNumElements() > NElts
1306  && SVT.isScalableVector() == IsScalable && isTypeLegal(SVT)) {
1307  TransformToType[i] = SVT;
1308  RegisterTypeForVT[i] = SVT;
1309  NumRegistersForVT[i] = 1;
1310  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1311  IsLegalWiderType = true;
1312  break;
1313  }
1314  }
1315  if (IsLegalWiderType)
1316  break;
1317  } else {
1318  // Only widen to the next power of 2 to keep consistency with EVT.
1319  MVT NVT = VT.getPow2VectorType();
1320  if (isTypeLegal(NVT)) {
1321  TransformToType[i] = NVT;
1322  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1323  RegisterTypeForVT[i] = NVT;
1324  NumRegistersForVT[i] = 1;
1325  break;
1326  }
1327  }
1329 
1330  case TypeSplitVector:
1331  case TypeScalarizeVector: {
1332  MVT IntermediateVT;
1333  MVT RegisterVT;
1334  unsigned NumIntermediates;
1335  NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1336  NumIntermediates, RegisterVT, this);
1337  RegisterTypeForVT[i] = RegisterVT;
1338 
1339  MVT NVT = VT.getPow2VectorType();
1340  if (NVT == VT) {
1341  // Type is already a power of 2. The default action is to split.
1342  TransformToType[i] = MVT::Other;
1343  if (PreferredAction == TypeScalarizeVector)
1344  ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1345  else if (PreferredAction == TypeSplitVector)
1346  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1347  else
1348  // Set type action according to the number of elements.
1349  ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1350  : TypeSplitVector);
1351  } else {
1352  TransformToType[i] = NVT;
1353  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1354  }
1355  break;
1356  }
1357  default:
1358  llvm_unreachable("Unknown vector legalization action!");
1359  }
1360  }
1361 
1362  // Determine the 'representative' register class for each value type.
1363  // An representative register class is the largest (meaning one which is
1364  // not a sub-register class / subreg register class) legal register class for
1365  // a group of value types. For example, on i386, i8, i16, and i32
1366  // representative would be GR32; while on x86_64 it's GR64.
1367  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1368  const TargetRegisterClass* RRC;
1369  uint8_t Cost;
1370  std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1371  RepRegClassForVT[i] = RRC;
1372  RepRegClassCostForVT[i] = Cost;
1373  }
1374 }
1375 
1377  EVT VT) const {
1378  assert(!VT.isVector() && "No default SetCC type for vectors!");
1379  return getPointerTy(DL).SimpleTy;
1380 }
1381 
1383  return MVT::i32; // return the default value
1384 }
1385 
1386 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1387 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1388 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1389 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1390 ///
1391 /// This method returns the number of registers needed, and the VT for each
1392 /// register. It also returns the VT and quantity of the intermediate values
1393 /// before they are promoted/expanded.
1395  EVT &IntermediateVT,
1396  unsigned &NumIntermediates,
1397  MVT &RegisterVT) const {
1398  unsigned NumElts = VT.getVectorNumElements();
1399 
1400  // If there is a wider vector type with the same element type as this one,
1401  // or a promoted vector type that has the same number of elements which
1402  // are wider, then we should convert to that legal vector type.
1403  // This handles things like <2 x float> -> <4 x float> and
1404  // <4 x i1> -> <4 x i32>.
1405  LegalizeTypeAction TA = getTypeAction(Context, VT);
1406  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1407  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1408  if (isTypeLegal(RegisterEVT)) {
1409  IntermediateVT = RegisterEVT;
1410  RegisterVT = RegisterEVT.getSimpleVT();
1411  NumIntermediates = 1;
1412  return 1;
1413  }
1414  }
1415 
1416  // Figure out the right, legal destination reg to copy into.
1417  EVT EltTy = VT.getVectorElementType();
1418 
1419  unsigned NumVectorRegs = 1;
1420 
1421  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1422  // could break down into LHS/RHS like LegalizeDAG does.
1423  if (!isPowerOf2_32(NumElts)) {
1424  NumVectorRegs = NumElts;
1425  NumElts = 1;
1426  }
1427 
1428  // Divide the input until we get to a supported size. This will always
1429  // end with a scalar if the target doesn't support vectors.
1430  while (NumElts > 1 && !isTypeLegal(
1431  EVT::getVectorVT(Context, EltTy, NumElts))) {
1432  NumElts >>= 1;
1433  NumVectorRegs <<= 1;
1434  }
1435 
1436  NumIntermediates = NumVectorRegs;
1437 
1438  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1439  if (!isTypeLegal(NewVT))
1440  NewVT = EltTy;
1441  IntermediateVT = NewVT;
1442 
1443  MVT DestVT = getRegisterType(Context, NewVT);
1444  RegisterVT = DestVT;
1445  unsigned NewVTSize = NewVT.getSizeInBits();
1446 
1447  // Convert sizes such as i33 to i64.
1448  if (!isPowerOf2_32(NewVTSize))
1449  NewVTSize = NextPowerOf2(NewVTSize);
1450 
1451  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1452  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1453 
1454  // Otherwise, promotion or legal types use the same number of registers as
1455  // the vector decimated to the appropriate level.
1456  return NumVectorRegs;
1457 }
1458 
1459 /// Get the EVTs and ArgFlags collections that represent the legalized return
1460 /// type of the given function. This does not require a DAG or a return value,
1461 /// and is suitable for use before any DAGs for the function are constructed.
1462 /// TODO: Move this out of TargetLowering.cpp.
1464  AttributeList attr,
1466  const TargetLowering &TLI, const DataLayout &DL) {
1467  SmallVector<EVT, 4> ValueVTs;
1468  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1469  unsigned NumValues = ValueVTs.size();
1470  if (NumValues == 0) return;
1471 
1472  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1473  EVT VT = ValueVTs[j];
1474  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1475 
1476  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1477  ExtendKind = ISD::SIGN_EXTEND;
1478  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1479  ExtendKind = ISD::ZERO_EXTEND;
1480 
1481  // FIXME: C calling convention requires the return type to be promoted to
1482  // at least 32-bit. But this is not necessary for non-C calling
1483  // conventions. The frontend should mark functions whose return values
1484  // require promoting with signext or zeroext attributes.
1485  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1486  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1487  if (VT.bitsLT(MinVT))
1488  VT = MinVT;
1489  }
1490 
1491  unsigned NumParts =
1492  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1493  MVT PartVT =
1494  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1495 
1496  // 'inreg' on function refers to return value
1497  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1498  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1499  Flags.setInReg();
1500 
1501  // Propagate extension type if any
1502  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1503  Flags.setSExt();
1504  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1505  Flags.setZExt();
1506 
1507  for (unsigned i = 0; i < NumParts; ++i)
1508  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1509  }
1510 }
1511 
1512 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1513 /// function arguments in the caller parameter area. This is the actual
1514 /// alignment, not its logarithm.
1516  const DataLayout &DL) const {
1517  return DL.getABITypeAlignment(Ty);
1518 }
1519 
1521  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1522  unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
1523  // Check if the specified alignment is sufficient based on the data layout.
1524  // TODO: While using the data layout works in practice, a better solution
1525  // would be to implement this check directly (make this a virtual function).
1526  // For example, the ABI alignment may change based on software platform while
1527  // this function should only be affected by hardware implementation.
1528  Type *Ty = VT.getTypeForEVT(Context);
1529  if (Alignment >= DL.getABITypeAlignment(Ty)) {
1530  // Assume that an access that meets the ABI-specified alignment is fast.
1531  if (Fast != nullptr)
1532  *Fast = true;
1533  return true;
1534  }
1535 
1536  // This is a misaligned access.
1537  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1538 }
1539 
1541  LLVMContext &Context, const DataLayout &DL, EVT VT,
1542  const MachineMemOperand &MMO, bool *Fast) const {
1543  return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(),
1544  MMO.getAlignment(), MMO.getFlags(),
1545  Fast);
1546 }
1547 
1549  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1550  unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
1551  return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1552  Flags, Fast);
1553 }
1554 
1556  const DataLayout &DL, EVT VT,
1557  const MachineMemOperand &MMO,
1558  bool *Fast) const {
1559  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(),
1560  MMO.getAlignment(), MMO.getFlags(), Fast);
1561 }
1562 
1564  return BranchProbability(MinPercentageForPredictableBranch, 100);
1565 }
1566 
1567 //===----------------------------------------------------------------------===//
1568 // TargetTransformInfo Helpers
1569 //===----------------------------------------------------------------------===//
1570 
1572  enum InstructionOpcodes {
1573 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1574 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1575 #include "llvm/IR/Instruction.def"
1576  };
1577  switch (static_cast<InstructionOpcodes>(Opcode)) {
1578  case Ret: return 0;
1579  case Br: return 0;
1580  case Switch: return 0;
1581  case IndirectBr: return 0;
1582  case Invoke: return 0;
1583  case CallBr: return 0;
1584  case Resume: return 0;
1585  case Unreachable: return 0;
1586  case CleanupRet: return 0;
1587  case CatchRet: return 0;
1588  case CatchPad: return 0;
1589  case CatchSwitch: return 0;
1590  case CleanupPad: return 0;
1591  case FNeg: return ISD::FNEG;
1592  case Add: return ISD::ADD;
1593  case FAdd: return ISD::FADD;
1594  case Sub: return ISD::SUB;
1595  case FSub: return ISD::FSUB;
1596  case Mul: return ISD::MUL;
1597  case FMul: return ISD::FMUL;
1598  case UDiv: return ISD::UDIV;
1599  case SDiv: return ISD::SDIV;
1600  case FDiv: return ISD::FDIV;
1601  case URem: return ISD::UREM;
1602  case SRem: return ISD::SREM;
1603  case FRem: return ISD::FREM;
1604  case Shl: return ISD::SHL;
1605  case LShr: return ISD::SRL;
1606  case AShr: return ISD::SRA;
1607  case And: return ISD::AND;
1608  case Or: return ISD::OR;
1609  case Xor: return ISD::XOR;
1610  case Alloca: return 0;
1611  case Load: return ISD::LOAD;
1612  case Store: return ISD::STORE;
1613  case GetElementPtr: return 0;
1614  case Fence: return 0;
1615  case AtomicCmpXchg: return 0;
1616  case AtomicRMW: return 0;
1617  case Trunc: return ISD::TRUNCATE;
1618  case ZExt: return ISD::ZERO_EXTEND;
1619  case SExt: return ISD::SIGN_EXTEND;
1620  case FPToUI: return ISD::FP_TO_UINT;
1621  case FPToSI: return ISD::FP_TO_SINT;
1622  case UIToFP: return ISD::UINT_TO_FP;
1623  case SIToFP: return ISD::SINT_TO_FP;
1624  case FPTrunc: return ISD::FP_ROUND;
1625  case FPExt: return ISD::FP_EXTEND;
1626  case PtrToInt: return ISD::BITCAST;
1627  case IntToPtr: return ISD::BITCAST;
1628  case BitCast: return ISD::BITCAST;
1629  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1630  case ICmp: return ISD::SETCC;
1631  case FCmp: return ISD::SETCC;
1632  case PHI: return 0;
1633  case Call: return 0;
1634  case Select: return ISD::SELECT;
1635  case UserOp1: return 0;
1636  case UserOp2: return 0;
1637  case VAArg: return 0;
1638  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1639  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1640  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1641  case ExtractValue: return ISD::MERGE_VALUES;
1642  case InsertValue: return ISD::MERGE_VALUES;
1643  case LandingPad: return 0;
1644  }
1645 
1646  llvm_unreachable("Unknown instruction type encountered!");
1647 }
1648 
1649 std::pair<int, MVT>
1651  Type *Ty) const {
1652  LLVMContext &C = Ty->getContext();
1653  EVT MTy = getValueType(DL, Ty);
1654 
1655  int Cost = 1;
1656  // We keep legalizing the type until we find a legal kind. We assume that
1657  // the only operation that costs anything is the split. After splitting
1658  // we need to handle two types.
1659  while (true) {
1660  LegalizeKind LK = getTypeConversion(C, MTy);
1661 
1662  if (LK.first == TypeLegal)
1663  return std::make_pair(Cost, MTy.getSimpleVT());
1664 
1665  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1666  Cost *= 2;
1667 
1668  // Do not loop with f128 type.
1669  if (MTy == LK.second)
1670  return std::make_pair(Cost, MTy.getSimpleVT());
1671 
1672  // Keep legalizing the type.
1673  MTy = LK.second;
1674  }
1675 }
1676 
1678  bool UseTLS) const {
1679  // compiler-rt provides a variable with a magic name. Targets that do not
1680  // link with compiler-rt may also provide such a variable.
1681  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1682  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1683  auto UnsafeStackPtr =
1684  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1685 
1686  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1687 
1688  if (!UnsafeStackPtr) {
1689  auto TLSModel = UseTLS ?
1692  // The global variable is not defined yet, define it ourselves.
1693  // We use the initial-exec TLS model because we do not support the
1694  // variable living anywhere other than in the main executable.
1695  UnsafeStackPtr = new GlobalVariable(
1696  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1697  UnsafeStackPtrVar, nullptr, TLSModel);
1698  } else {
1699  // The variable exists, check its type and attributes.
1700  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1701  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1702  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1703  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1704  (UseTLS ? "" : "not ") + "be thread-local");
1705  }
1706  return UnsafeStackPtr;
1707 }
1708 
1710  if (!TM.getTargetTriple().isAndroid())
1711  return getDefaultSafeStackPointerLocation(IRB, true);
1712 
1713  // Android provides a libc function to retrieve the address of the current
1714  // thread's unsafe stack pointer.
1715  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1716  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1717  FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1718  StackPtrTy->getPointerTo(0));
1719  return IRB.CreateCall(Fn);
1720 }
1721 
1722 //===----------------------------------------------------------------------===//
1723 // Loop Strength Reduction hooks
1724 //===----------------------------------------------------------------------===//
1725 
1726 /// isLegalAddressingMode - Return true if the addressing mode represented
1727 /// by AM is legal for this target, for a load/store of the specified type.
1729  const AddrMode &AM, Type *Ty,
1730  unsigned AS, Instruction *I) const {
1731  // The default implementation of this implements a conservative RISCy, r+r and
1732  // r+i addr mode.
1733 
1734  // Allows a sign-extended 16-bit immediate field.
1735  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1736  return false;
1737 
1738  // No global is ever allowed as a base.
1739  if (AM.BaseGV)
1740  return false;
1741 
1742  // Only support r+r,
1743  switch (AM.Scale) {
1744  case 0: // "r+i" or just "i", depending on HasBaseReg.
1745  break;
1746  case 1:
1747  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1748  return false;
1749  // Otherwise we have r+r or r+i.
1750  break;
1751  case 2:
1752  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1753  return false;
1754  // Allow 2*r as r+r.
1755  break;
1756  default: // Don't allow n * r
1757  return false;
1758  }
1759 
1760  return true;
1761 }
1762 
1763 //===----------------------------------------------------------------------===//
1764 // Stack Protector
1765 //===----------------------------------------------------------------------===//
1766 
1767 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1768 // so that SelectionDAG handle SSP.
1770  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1771  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1773  return M.getOrInsertGlobal("__guard_local", PtrTy);
1774  }
1775  return nullptr;
1776 }
1777 
1778 // Currently only support "standard" __stack_chk_guard.
1779 // TODO: add LOAD_STACK_GUARD support.
1781  if (!M.getNamedValue("__stack_chk_guard"))
1782  new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1784  nullptr, "__stack_chk_guard");
1785 }
1786 
1787 // Currently only support "standard" __stack_chk_guard.
1788 // TODO: add LOAD_STACK_GUARD support.
1790  return M.getNamedValue("__stack_chk_guard");
1791 }
1792 
1794  return nullptr;
1795 }
1796 
1798  return MinimumJumpTableEntries;
1799 }
1800 
1803 }
1804 
1805 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1806  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1807 }
1808 
1810  return MaximumJumpTableSize;
1811 }
1812 
1814  MaximumJumpTableSize = Val;
1815 }
1816 
1817 //===----------------------------------------------------------------------===//
1818 // Reciprocal Estimates
1819 //===----------------------------------------------------------------------===//
1820 
1821 /// Get the reciprocal estimate attribute string for a function that will
1822 /// override the target defaults.
1824  const Function &F = MF.getFunction();
1825  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1826 }
1827 
1828 /// Construct a string for the given reciprocal operation of the given type.
1829 /// This string should match the corresponding option to the front-end's
1830 /// "-mrecip" flag assuming those strings have been passed through in an
1831 /// attribute string. For example, "vec-divf" for a division of a vXf32.
1832 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1833  std::string Name = VT.isVector() ? "vec-" : "";
1834 
1835  Name += IsSqrt ? "sqrt" : "div";
1836 
1837  // TODO: Handle "half" or other float types?
1838  if (VT.getScalarType() == MVT::f64) {
1839  Name += "d";
1840  } else {
1841  assert(VT.getScalarType() == MVT::f32 &&
1842  "Unexpected FP type for reciprocal estimate");
1843  Name += "f";
1844  }
1845 
1846  return Name;
1847 }
1848 
1849 /// Return the character position and value (a single numeric character) of a
1850 /// customized refinement operation in the input string if it exists. Return
1851 /// false if there is no customized refinement step count.
1853  uint8_t &Value) {
1854  const char RefStepToken = ':';
1855  Position = In.find(RefStepToken);
1856  if (Position == StringRef::npos)
1857  return false;
1858 
1859  StringRef RefStepString = In.substr(Position + 1);
1860  // Allow exactly one numeric character for the additional refinement
1861  // step parameter.
1862  if (RefStepString.size() == 1) {
1863  char RefStepChar = RefStepString[0];
1864  if (RefStepChar >= '0' && RefStepChar <= '9') {
1865  Value = RefStepChar - '0';
1866  return true;
1867  }
1868  }
1869  report_fatal_error("Invalid refinement step for -recip.");
1870 }
1871 
1872 /// For the input attribute string, return one of the ReciprocalEstimate enum
1873 /// status values (enabled, disabled, or not specified) for this operation on
1874 /// the specified data type.
1875 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1876  if (Override.empty())
1877  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1878 
1879  SmallVector<StringRef, 4> OverrideVector;
1880  Override.split(OverrideVector, ',');
1881  unsigned NumArgs = OverrideVector.size();
1882 
1883  // Check if "all", "none", or "default" was specified.
1884  if (NumArgs == 1) {
1885  // Look for an optional setting of the number of refinement steps needed
1886  // for this type of reciprocal operation.
1887  size_t RefPos;
1888  uint8_t RefSteps;
1889  if (parseRefinementStep(Override, RefPos, RefSteps)) {
1890  // Split the string for further processing.
1891  Override = Override.substr(0, RefPos);
1892  }
1893 
1894  // All reciprocal types are enabled.
1895  if (Override == "all")
1897 
1898  // All reciprocal types are disabled.
1899  if (Override == "none")
1900  return TargetLoweringBase::ReciprocalEstimate::Disabled;
1901 
1902  // Target defaults for enablement are used.
1903  if (Override == "default")
1904  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1905  }
1906 
1907  // The attribute string may omit the size suffix ('f'/'d').
1908  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1909  std::string VTNameNoSize = VTName;
1910  VTNameNoSize.pop_back();
1911  static const char DisabledPrefix = '!';
1912 
1913  for (StringRef RecipType : OverrideVector) {
1914  size_t RefPos;
1915  uint8_t RefSteps;
1916  if (parseRefinementStep(RecipType, RefPos, RefSteps))
1917  RecipType = RecipType.substr(0, RefPos);
1918 
1919  // Ignore the disablement token for string matching.
1920  bool IsDisabled = RecipType[0] == DisabledPrefix;
1921  if (IsDisabled)
1922  RecipType = RecipType.substr(1);
1923 
1924  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1925  return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
1927  }
1928 
1929  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1930 }
1931 
1932 /// For the input attribute string, return the customized refinement step count
1933 /// for this operation on the specified data type. If the step count does not
1934 /// exist, return the ReciprocalEstimate enum value for unspecified.
1935 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
1936  if (Override.empty())
1937  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1938 
1939  SmallVector<StringRef, 4> OverrideVector;
1940  Override.split(OverrideVector, ',');
1941  unsigned NumArgs = OverrideVector.size();
1942 
1943  // Check if "all", "default", or "none" was specified.
1944  if (NumArgs == 1) {
1945  // Look for an optional setting of the number of refinement steps needed
1946  // for this type of reciprocal operation.
1947  size_t RefPos;
1948  uint8_t RefSteps;
1949  if (!parseRefinementStep(Override, RefPos, RefSteps))
1950  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1951 
1952  // Split the string for further processing.
1953  Override = Override.substr(0, RefPos);
1954  assert(Override != "none" &&
1955  "Disabled reciprocals, but specifed refinement steps?");
1956 
1957  // If this is a general override, return the specified number of steps.
1958  if (Override == "all" || Override == "default")
1959  return RefSteps;
1960  }
1961 
1962  // The attribute string may omit the size suffix ('f'/'d').
1963  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1964  std::string VTNameNoSize = VTName;
1965  VTNameNoSize.pop_back();
1966 
1967  for (StringRef RecipType : OverrideVector) {
1968  size_t RefPos;
1969  uint8_t RefSteps;
1970  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
1971  continue;
1972 
1973  RecipType = RecipType.substr(0, RefPos);
1974  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1975  return RefSteps;
1976  }
1977 
1978  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1979 }
1980 
1982  MachineFunction &MF) const {
1983  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
1984 }
1985 
1987  MachineFunction &MF) const {
1988  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
1989 }
1990 
1992  MachineFunction &MF) const {
1993  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
1994 }
1995 
1997  MachineFunction &MF) const {
1998  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
1999 }
2000 
2002  MF.getRegInfo().freezeReservedRegs(MF);
2003 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
static bool darwinHasSinCos(const Triple &TT)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:603
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:577
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
static MVT getIntegerVT(unsigned BitWidth)
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:630
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:300
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
LLVMContext & Context
unsigned getAddrSpace() const
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:358
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:453
static MVT getVectorVT(MVT VT, unsigned NumElements)
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:641
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:399
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:66
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:284
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:558
bool isVector() const
Return true if this is a vector value type.
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:170
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
Y = RRC X, rotate right via carry.
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
static cl::opt< int > MinPercentageForPredictableBranch("min-predictable-branch", cl::init(99), cl::desc("Minimum percentage (0-100) that a condition must be either true " "or false to assume that the condition is predictable"), cl::Hidden)
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled...
unsigned getVectorNumElements() const
Externally visible function.
Definition: GlobalValue.h:48
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:414
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:841
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:392
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:293
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
bool isOSFuchsia() const
Definition: Triple.h:505
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:547
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:423
Same for subtraction.
Definition: ISDOpcodes.h:253
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:348
bool isValid() const
Return true if this is a valid simple valuetype.
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type...
Definition: ValueTypes.h:365
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function&#39;s at...
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
A description of a memory reference used in the backend.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
Shift and rotation operations.
Definition: ISDOpcodes.h:449
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:264
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:245
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:432
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:659
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:779
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:849
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:592
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:140
Position
Position to insert a new instruction relative to an existing instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
unsigned getNumRegClasses() const
unsigned getSizeInBits() const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:517
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:296
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:126
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
GlobalValue * getNamedValue(StringRef Name) const
Return the global value in the module with the specified name, of arbitrary type. ...
Definition: Module.cpp:113
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:144
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:462
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:1020
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:331
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:786
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:536
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
MVT getVectorElementType() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function&#39;s attri...
Class to represent pointers.
Definition: DerivedTypes.h:579
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:563
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
virtual Value * getIRStackGuard(IRBuilder<> &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
These reductions are non-strict, and have a single vector operand.
Definition: ISDOpcodes.h:909
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:465
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
bool isOSOpenBSD() const
Definition: Triple.h:497
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
unsigned getScalarSizeInBits() const
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:654
bool isWatchABI() const
Definition: Triple.h:476
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:364
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:299
static mvt_range fp_valuetypes()
bool isAndroidVersionLT(unsigned Major) const
Definition: Triple.h:663
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
bool isPS4CPU() const
Tests whether the target is the PS4 CPU.
Definition: Triple.h:648
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:806
const Triple & getTargetTriple() const
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:809
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
bool isPPC64() const
Tests whether the target is 64-bit PowerPC (little and big endian).
Definition: Triple.h:724
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:455
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:835
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:588
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Extended Value Type.
Definition: ValueTypes.h:33
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:672
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
size_t size() const
Definition: SmallVector.h:52
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:224
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function&#39;s attributes...
const TargetMachine & getTargetMachine() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
Value * getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) const
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
void initActions()
Initialize all of the actions to default values.
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:264
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal...
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight)...
Definition: ValueTypes.h:316
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:371
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:490
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:607
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
Module.h This file contains the declarations for the Module class.
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:710
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1023
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:755
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values, following the IEEE-754 2008 definition.
Definition: ISDOpcodes.h:636
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
FunctionCallee getOrInsertFunction(StringRef Name, FunctionType *T, AttributeList AttributeList)
Look up the specified function in the module symbol table.
Definition: Module.cpp:143
static bool Enabled
Definition: Statistic.cpp:50
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:72
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:459
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:240
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:507
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:510
#define OP_TO_LIBCALL(Name, Enum)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:344
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Flags
Flags values. These may be or&#39;d together.
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function&#39;s attribut...
The memory access reads data.
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca...
Definition: ISDOpcodes.h:900
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static mvt_range all_valuetypes()
SimpleValueType Iteration.
Representation of each machine instruction.
Definition: MachineInstr.h:63
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Constant * getOrInsertGlobal(StringRef Name, Type *Ty, function_ref< GlobalVariable *()> CreateGlobalCallback)
Look up the specified global in the module symbol table.
Definition: Module.cpp:204
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:426
static const size_t npos
Definition: StringRef.h:50
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineBasicBlock * emitXRayCustomEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay custom event operands with target-dependent details.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:220
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1292
void setTypeAction(MVT VT, LegalizeTypeAction Action)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:650
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return &#39;Legal&#39;) or we ...
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
MachineBasicBlock * emitXRayTypedEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay typed event operands with target-dependent details.
#define I(x, y, z)
Definition: MD5.cpp:58
Flags getFlags() const
Return the raw flags of the source value,.
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
bool isGNUEnvironment() const
Definition: Triple.h:521
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:272
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision ...
Definition: ISDOpcodes.h:326
Same for multiplication.
Definition: ISDOpcodes.h:256
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:966
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value *> Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2239
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that&#39;s previously inserted by insertSSPDeclarations, if any, otherwise return nul...
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
bool isMacOSXVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isMacOSXVersionLT - Comparison function for checking OS X version compatibility, which handles suppor...
Definition: Triple.h:438
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:377
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:830
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:74
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:915
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:911
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:107
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:815
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:661
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
Definition: ISDOpcodes.h:338
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:482
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isOSVersionLT - Helper function for doing comparisons against version numbers included in the target ...
Definition: Triple.h:414
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
Conversion operators.
Definition: ISDOpcodes.h:504
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:513
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
virtual BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:618
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:63
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:310
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add &#39;1&#39; bits from Mask to this vector.
Definition: BitVector.h:775
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:241
LegalizeTypeAction getTypeAction(MVT VT) const
This file describes how to lower LLVM code to machine code.
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class...
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...