LLVM  10.0.0svn
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/CodeGen/Analysis.h"
31 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalValue.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/IRBuilder.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
47 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/Compiler.h"
54 #include <algorithm>
55 #include <cassert>
56 #include <cstddef>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <tuple>
62 #include <utility>
63 
64 using namespace llvm;
65 
67  "jump-is-expensive", cl::init(false),
68  cl::desc("Do not create extra branches to split comparison logic."),
69  cl::Hidden);
70 
72  ("min-jump-table-entries", cl::init(4), cl::Hidden,
73  cl::desc("Set minimum number of entries to use a jump table."));
74 
76  ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
77  cl::desc("Set maximum size of jump tables."));
78 
79 /// Minimum jump table density for normal functions.
80 static cl::opt<unsigned>
81  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
82  cl::desc("Minimum density for building a jump table in "
83  "a normal function"));
84 
85 /// Minimum jump table density for -Os or -Oz functions.
87  "optsize-jump-table-density", cl::init(40), cl::Hidden,
88  cl::desc("Minimum density for building a jump table in "
89  "an optsize function"));
90 
91 static bool darwinHasSinCos(const Triple &TT) {
92  assert(TT.isOSDarwin() && "should be called with darwin triple");
93  // Don't bother with 32 bit x86.
94  if (TT.getArch() == Triple::x86)
95  return false;
96  // Macos < 10.9 has no sincos_stret.
97  if (TT.isMacOSX())
98  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
99  // iOS < 7.0 has no sincos_stret.
100  if (TT.isiOS())
101  return !TT.isOSVersionLT(7, 0);
102  // Any other darwin such as WatchOS/TvOS is new enough.
103  return true;
104 }
105 
106 // Although this default value is arbitrary, it is not random. It is assumed
107 // that a condition that evaluates the same way by a higher percentage than this
108 // is best represented as control flow. Therefore, the default value N should be
109 // set such that the win from N% correct executions is greater than the loss
110 // from (100 - N)% mispredicted executions for the majority of intended targets.
112  "min-predictable-branch", cl::init(99),
113  cl::desc("Minimum percentage (0-100) that a condition must be either true "
114  "or false to assume that the condition is predictable"),
115  cl::Hidden);
116 
117 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
118 #define HANDLE_LIBCALL(code, name) \
119  setLibcallName(RTLIB::code, name);
120 #include "llvm/IR/RuntimeLibcalls.def"
121 #undef HANDLE_LIBCALL
122  // Initialize calling conventions to their default.
123  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
125 
126  // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
127  if (TT.getArch() == Triple::ppc || TT.isPPC64()) {
128  setLibcallName(RTLIB::ADD_F128, "__addkf3");
129  setLibcallName(RTLIB::SUB_F128, "__subkf3");
130  setLibcallName(RTLIB::MUL_F128, "__mulkf3");
131  setLibcallName(RTLIB::DIV_F128, "__divkf3");
132  setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
133  setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
134  setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
135  setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
136  setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
137  setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
138  setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
139  setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
140  setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
141  setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
142  setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
143  setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
144  setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
145  setLibcallName(RTLIB::UNE_F128, "__nekf2");
146  setLibcallName(RTLIB::OGE_F128, "__gekf2");
147  setLibcallName(RTLIB::OLT_F128, "__ltkf2");
148  setLibcallName(RTLIB::OLE_F128, "__lekf2");
149  setLibcallName(RTLIB::OGT_F128, "__gtkf2");
150  setLibcallName(RTLIB::UO_F128, "__unordkf2");
151  setLibcallName(RTLIB::O_F128, "__unordkf2");
152  }
153 
154  // A few names are different on particular architectures or environments.
155  if (TT.isOSDarwin()) {
156  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
157  // of the gnueabi-style __gnu_*_ieee.
158  // FIXME: What about other targets?
159  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
160  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
161 
162  // Some darwins have an optimized __bzero/bzero function.
163  switch (TT.getArch()) {
164  case Triple::x86:
165  case Triple::x86_64:
166  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
167  setLibcallName(RTLIB::BZERO, "__bzero");
168  break;
169  case Triple::aarch64:
170  setLibcallName(RTLIB::BZERO, "bzero");
171  break;
172  default:
173  break;
174  }
175 
176  if (darwinHasSinCos(TT)) {
177  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
178  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
179  if (TT.isWatchABI()) {
180  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
182  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
184  }
185  }
186  } else {
187  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
188  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
189  }
190 
191  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
192  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
193  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
194  setLibcallName(RTLIB::SINCOS_F64, "sincos");
195  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
196  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
197  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
198  }
199 
200  if (TT.isOSOpenBSD()) {
201  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
202  }
203 }
204 
205 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
206 /// UNKNOWN_LIBCALL if there is none.
208  if (OpVT == MVT::f16) {
209  if (RetVT == MVT::f32)
210  return FPEXT_F16_F32;
211  } else if (OpVT == MVT::f32) {
212  if (RetVT == MVT::f64)
213  return FPEXT_F32_F64;
214  if (RetVT == MVT::f128)
215  return FPEXT_F32_F128;
216  if (RetVT == MVT::ppcf128)
217  return FPEXT_F32_PPCF128;
218  } else if (OpVT == MVT::f64) {
219  if (RetVT == MVT::f128)
220  return FPEXT_F64_F128;
221  else if (RetVT == MVT::ppcf128)
222  return FPEXT_F64_PPCF128;
223  } else if (OpVT == MVT::f80) {
224  if (RetVT == MVT::f128)
225  return FPEXT_F80_F128;
226  }
227 
228  return UNKNOWN_LIBCALL;
229 }
230 
231 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
232 /// UNKNOWN_LIBCALL if there is none.
234  if (RetVT == MVT::f16) {
235  if (OpVT == MVT::f32)
236  return FPROUND_F32_F16;
237  if (OpVT == MVT::f64)
238  return FPROUND_F64_F16;
239  if (OpVT == MVT::f80)
240  return FPROUND_F80_F16;
241  if (OpVT == MVT::f128)
242  return FPROUND_F128_F16;
243  if (OpVT == MVT::ppcf128)
244  return FPROUND_PPCF128_F16;
245  } else if (RetVT == MVT::f32) {
246  if (OpVT == MVT::f64)
247  return FPROUND_F64_F32;
248  if (OpVT == MVT::f80)
249  return FPROUND_F80_F32;
250  if (OpVT == MVT::f128)
251  return FPROUND_F128_F32;
252  if (OpVT == MVT::ppcf128)
253  return FPROUND_PPCF128_F32;
254  } else if (RetVT == MVT::f64) {
255  if (OpVT == MVT::f80)
256  return FPROUND_F80_F64;
257  if (OpVT == MVT::f128)
258  return FPROUND_F128_F64;
259  if (OpVT == MVT::ppcf128)
260  return FPROUND_PPCF128_F64;
261  } else if (RetVT == MVT::f80) {
262  if (OpVT == MVT::f128)
263  return FPROUND_F128_F80;
264  }
265 
266  return UNKNOWN_LIBCALL;
267 }
268 
269 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
270 /// UNKNOWN_LIBCALL if there is none.
272  if (OpVT == MVT::f32) {
273  if (RetVT == MVT::i32)
274  return FPTOSINT_F32_I32;
275  if (RetVT == MVT::i64)
276  return FPTOSINT_F32_I64;
277  if (RetVT == MVT::i128)
278  return FPTOSINT_F32_I128;
279  } else if (OpVT == MVT::f64) {
280  if (RetVT == MVT::i32)
281  return FPTOSINT_F64_I32;
282  if (RetVT == MVT::i64)
283  return FPTOSINT_F64_I64;
284  if (RetVT == MVT::i128)
285  return FPTOSINT_F64_I128;
286  } else if (OpVT == MVT::f80) {
287  if (RetVT == MVT::i32)
288  return FPTOSINT_F80_I32;
289  if (RetVT == MVT::i64)
290  return FPTOSINT_F80_I64;
291  if (RetVT == MVT::i128)
292  return FPTOSINT_F80_I128;
293  } else if (OpVT == MVT::f128) {
294  if (RetVT == MVT::i32)
295  return FPTOSINT_F128_I32;
296  if (RetVT == MVT::i64)
297  return FPTOSINT_F128_I64;
298  if (RetVT == MVT::i128)
299  return FPTOSINT_F128_I128;
300  } else if (OpVT == MVT::ppcf128) {
301  if (RetVT == MVT::i32)
302  return FPTOSINT_PPCF128_I32;
303  if (RetVT == MVT::i64)
304  return FPTOSINT_PPCF128_I64;
305  if (RetVT == MVT::i128)
306  return FPTOSINT_PPCF128_I128;
307  }
308  return UNKNOWN_LIBCALL;
309 }
310 
311 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
312 /// UNKNOWN_LIBCALL if there is none.
314  if (OpVT == MVT::f32) {
315  if (RetVT == MVT::i32)
316  return FPTOUINT_F32_I32;
317  if (RetVT == MVT::i64)
318  return FPTOUINT_F32_I64;
319  if (RetVT == MVT::i128)
320  return FPTOUINT_F32_I128;
321  } else if (OpVT == MVT::f64) {
322  if (RetVT == MVT::i32)
323  return FPTOUINT_F64_I32;
324  if (RetVT == MVT::i64)
325  return FPTOUINT_F64_I64;
326  if (RetVT == MVT::i128)
327  return FPTOUINT_F64_I128;
328  } else if (OpVT == MVT::f80) {
329  if (RetVT == MVT::i32)
330  return FPTOUINT_F80_I32;
331  if (RetVT == MVT::i64)
332  return FPTOUINT_F80_I64;
333  if (RetVT == MVT::i128)
334  return FPTOUINT_F80_I128;
335  } else if (OpVT == MVT::f128) {
336  if (RetVT == MVT::i32)
337  return FPTOUINT_F128_I32;
338  if (RetVT == MVT::i64)
339  return FPTOUINT_F128_I64;
340  if (RetVT == MVT::i128)
341  return FPTOUINT_F128_I128;
342  } else if (OpVT == MVT::ppcf128) {
343  if (RetVT == MVT::i32)
344  return FPTOUINT_PPCF128_I32;
345  if (RetVT == MVT::i64)
346  return FPTOUINT_PPCF128_I64;
347  if (RetVT == MVT::i128)
348  return FPTOUINT_PPCF128_I128;
349  }
350  return UNKNOWN_LIBCALL;
351 }
352 
353 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
354 /// UNKNOWN_LIBCALL if there is none.
356  if (OpVT == MVT::i32) {
357  if (RetVT == MVT::f32)
358  return SINTTOFP_I32_F32;
359  if (RetVT == MVT::f64)
360  return SINTTOFP_I32_F64;
361  if (RetVT == MVT::f80)
362  return SINTTOFP_I32_F80;
363  if (RetVT == MVT::f128)
364  return SINTTOFP_I32_F128;
365  if (RetVT == MVT::ppcf128)
366  return SINTTOFP_I32_PPCF128;
367  } else if (OpVT == MVT::i64) {
368  if (RetVT == MVT::f32)
369  return SINTTOFP_I64_F32;
370  if (RetVT == MVT::f64)
371  return SINTTOFP_I64_F64;
372  if (RetVT == MVT::f80)
373  return SINTTOFP_I64_F80;
374  if (RetVT == MVT::f128)
375  return SINTTOFP_I64_F128;
376  if (RetVT == MVT::ppcf128)
377  return SINTTOFP_I64_PPCF128;
378  } else if (OpVT == MVT::i128) {
379  if (RetVT == MVT::f32)
380  return SINTTOFP_I128_F32;
381  if (RetVT == MVT::f64)
382  return SINTTOFP_I128_F64;
383  if (RetVT == MVT::f80)
384  return SINTTOFP_I128_F80;
385  if (RetVT == MVT::f128)
386  return SINTTOFP_I128_F128;
387  if (RetVT == MVT::ppcf128)
388  return SINTTOFP_I128_PPCF128;
389  }
390  return UNKNOWN_LIBCALL;
391 }
392 
393 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
394 /// UNKNOWN_LIBCALL if there is none.
396  if (OpVT == MVT::i32) {
397  if (RetVT == MVT::f32)
398  return UINTTOFP_I32_F32;
399  if (RetVT == MVT::f64)
400  return UINTTOFP_I32_F64;
401  if (RetVT == MVT::f80)
402  return UINTTOFP_I32_F80;
403  if (RetVT == MVT::f128)
404  return UINTTOFP_I32_F128;
405  if (RetVT == MVT::ppcf128)
406  return UINTTOFP_I32_PPCF128;
407  } else if (OpVT == MVT::i64) {
408  if (RetVT == MVT::f32)
409  return UINTTOFP_I64_F32;
410  if (RetVT == MVT::f64)
411  return UINTTOFP_I64_F64;
412  if (RetVT == MVT::f80)
413  return UINTTOFP_I64_F80;
414  if (RetVT == MVT::f128)
415  return UINTTOFP_I64_F128;
416  if (RetVT == MVT::ppcf128)
417  return UINTTOFP_I64_PPCF128;
418  } else if (OpVT == MVT::i128) {
419  if (RetVT == MVT::f32)
420  return UINTTOFP_I128_F32;
421  if (RetVT == MVT::f64)
422  return UINTTOFP_I128_F64;
423  if (RetVT == MVT::f80)
424  return UINTTOFP_I128_F80;
425  if (RetVT == MVT::f128)
426  return UINTTOFP_I128_F128;
427  if (RetVT == MVT::ppcf128)
428  return UINTTOFP_I128_PPCF128;
429  }
430  return UNKNOWN_LIBCALL;
431 }
432 
433 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
434 #define OP_TO_LIBCALL(Name, Enum) \
435  case Name: \
436  switch (VT.SimpleTy) { \
437  default: \
438  return UNKNOWN_LIBCALL; \
439  case MVT::i8: \
440  return Enum##_1; \
441  case MVT::i16: \
442  return Enum##_2; \
443  case MVT::i32: \
444  return Enum##_4; \
445  case MVT::i64: \
446  return Enum##_8; \
447  case MVT::i128: \
448  return Enum##_16; \
449  }
450 
451  switch (Opc) {
452  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
453  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
454  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
455  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
456  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
457  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
458  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
459  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
460  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
461  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
462  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
463  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
464  }
465 
466 #undef OP_TO_LIBCALL
467 
468  return UNKNOWN_LIBCALL;
469 }
470 
472  switch (ElementSize) {
473  case 1:
474  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
475  case 2:
476  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
477  case 4:
478  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
479  case 8:
480  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
481  case 16:
482  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
483  default:
484  return UNKNOWN_LIBCALL;
485  }
486 }
487 
489  switch (ElementSize) {
490  case 1:
491  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
492  case 2:
493  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
494  case 4:
495  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
496  case 8:
497  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
498  case 16:
499  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
500  default:
501  return UNKNOWN_LIBCALL;
502  }
503 }
504 
506  switch (ElementSize) {
507  case 1:
508  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
509  case 2:
510  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
511  case 4:
512  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
513  case 8:
514  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
515  case 16:
516  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
517  default:
518  return UNKNOWN_LIBCALL;
519  }
520 }
521 
522 /// InitCmpLibcallCCs - Set default comparison libcall CC.
523 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
524  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
525  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
526  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
527  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
528  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
529  CCs[RTLIB::UNE_F32] = ISD::SETNE;
530  CCs[RTLIB::UNE_F64] = ISD::SETNE;
531  CCs[RTLIB::UNE_F128] = ISD::SETNE;
532  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
533  CCs[RTLIB::OGE_F32] = ISD::SETGE;
534  CCs[RTLIB::OGE_F64] = ISD::SETGE;
535  CCs[RTLIB::OGE_F128] = ISD::SETGE;
536  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
537  CCs[RTLIB::OLT_F32] = ISD::SETLT;
538  CCs[RTLIB::OLT_F64] = ISD::SETLT;
539  CCs[RTLIB::OLT_F128] = ISD::SETLT;
540  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
541  CCs[RTLIB::OLE_F32] = ISD::SETLE;
542  CCs[RTLIB::OLE_F64] = ISD::SETLE;
543  CCs[RTLIB::OLE_F128] = ISD::SETLE;
544  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
545  CCs[RTLIB::OGT_F32] = ISD::SETGT;
546  CCs[RTLIB::OGT_F64] = ISD::SETGT;
547  CCs[RTLIB::OGT_F128] = ISD::SETGT;
548  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
549  CCs[RTLIB::UO_F32] = ISD::SETNE;
550  CCs[RTLIB::UO_F64] = ISD::SETNE;
551  CCs[RTLIB::UO_F128] = ISD::SETNE;
552  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
553  CCs[RTLIB::O_F32] = ISD::SETEQ;
554  CCs[RTLIB::O_F64] = ISD::SETEQ;
555  CCs[RTLIB::O_F128] = ISD::SETEQ;
556  CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
557 }
558 
559 /// NOTE: The TargetMachine owns TLOF.
561  initActions();
562 
563  // Perform these initializations only once.
565  MaxLoadsPerMemcmp = 8;
569  UseUnderscoreSetJmp = false;
570  UseUnderscoreLongJmp = false;
571  HasMultipleConditionRegisters = false;
572  HasExtractBitsInsn = false;
573  JumpIsExpensive = JumpIsExpensiveOverride;
575  EnableExtLdPromotion = false;
576  StackPointerRegisterToSaveRestore = 0;
577  BooleanContents = UndefinedBooleanContent;
578  BooleanFloatContents = UndefinedBooleanContent;
579  BooleanVectorContents = UndefinedBooleanContent;
580  SchedPreferenceInfo = Sched::ILP;
581  JumpBufSize = 0;
582  JumpBufAlignment = 0;
583  MinFunctionAlignment = 0;
584  PrefFunctionAlignment = 0;
585  PrefLoopAlignment = 0;
587  MinStackArgumentAlignment = 1;
588  // TODO: the default will be switched to 0 in the next commit, along
589  // with the Target-specific changes necessary.
590  MaxAtomicSizeInBitsSupported = 1024;
591 
592  MinCmpXchgSizeInBits = 0;
593  SupportsUnalignedAtomics = false;
594 
595  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
596 
597  InitLibcalls(TM.getTargetTriple());
598  InitCmpLibcallCCs(CmpLibcallCCs);
599 }
600 
602  // All operations default to being supported.
603  memset(OpActions, 0, sizeof(OpActions));
604  memset(LoadExtActions, 0, sizeof(LoadExtActions));
605  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
606  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
607  memset(CondCodeActions, 0, sizeof(CondCodeActions));
608  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
609  std::fill(std::begin(TargetDAGCombineArray),
610  std::end(TargetDAGCombineArray), 0);
611 
612  for (MVT VT : MVT::fp_valuetypes()) {
613  MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
614  if (IntVT.isValid()) {
617  }
618  }
619 
620  // Set default actions for various operations.
621  for (MVT VT : MVT::all_valuetypes()) {
622  // Default all indexed load / store to expand.
623  for (unsigned IM = (unsigned)ISD::PRE_INC;
624  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
625  setIndexedLoadAction(IM, VT, Expand);
626  setIndexedStoreAction(IM, VT, Expand);
627  }
628 
629  // Most backends expect to see the node which just returns the value loaded.
631 
632  // These operations default to expand.
656 
657  // Overflow operations default to expand
664 
665  // ADDCARRY operations default to expand
669 
670  // ADDC/ADDE/SUBC/SUBE default to expand.
675 
676  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
679 
681 
682  // These library functions default to expand.
685 
686  // These operations default to expand for vector types.
687  if (VT.isVector()) {
692  }
693 
694  // Constrained floating-point operations default to expand.
721 
722  // For most targets @llvm.get.dynamic.area.offset just returns 0.
724 
725  // Vector reduction default to expand.
739  }
740 
741  // Most targets ignore the @llvm.prefetch intrinsic.
743 
744  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
746 
747  // ConstantFP nodes default to expand. Targets can either change this to
748  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
749  // to optimize expansions for certain constants.
755 
756  // These library functions default to expand.
757  for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
774  }
775 
776  // Default ISD::TRAP to expand (which turns it into abort).
778 
779  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
780  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
782 }
783 
785  EVT) const {
787 }
788 
790  bool LegalTypes) const {
791  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
792  if (LHSTy.isVector())
793  return LHSTy;
794  return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
795  : getPointerTy(DL);
796 }
797 
798 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
799  assert(isTypeLegal(VT));
800  switch (Op) {
801  default:
802  return false;
803  case ISD::SDIV:
804  case ISD::UDIV:
805  case ISD::SREM:
806  case ISD::UREM:
807  return true;
808  }
809 }
810 
812  // If the command-line option was specified, ignore this request.
813  if (!JumpIsExpensiveOverride.getNumOccurrences())
814  JumpIsExpensive = isExpensive;
815 }
816 
818 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
819  // If this is a simple type, use the ComputeRegisterProp mechanism.
820  if (VT.isSimple()) {
821  MVT SVT = VT.getSimpleVT();
822  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
823  MVT NVT = TransformToType[SVT.SimpleTy];
825 
826  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
828  "Promote may not follow Expand or Promote");
829 
830  if (LA == TypeSplitVector)
831  return LegalizeKind(LA,
832  EVT::getVectorVT(Context, SVT.getVectorElementType(),
833  SVT.getVectorNumElements() / 2));
834  if (LA == TypeScalarizeVector)
835  return LegalizeKind(LA, SVT.getVectorElementType());
836  return LegalizeKind(LA, NVT);
837  }
838 
839  // Handle Extended Scalar Types.
840  if (!VT.isVector()) {
841  assert(VT.isInteger() && "Float types must be simple");
842  unsigned BitSize = VT.getSizeInBits();
843  // First promote to a power-of-two size, then expand if necessary.
844  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
845  EVT NVT = VT.getRoundIntegerType(Context);
846  assert(NVT != VT && "Unable to round integer VT");
847  LegalizeKind NextStep = getTypeConversion(Context, NVT);
848  // Avoid multi-step promotion.
849  if (NextStep.first == TypePromoteInteger)
850  return NextStep;
851  // Return rounded integer type.
852  return LegalizeKind(TypePromoteInteger, NVT);
853  }
854 
856  EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
857  }
858 
859  // Handle vector types.
860  unsigned NumElts = VT.getVectorNumElements();
861  EVT EltVT = VT.getVectorElementType();
862 
863  // Vectors with only one element are always scalarized.
864  if (NumElts == 1)
865  return LegalizeKind(TypeScalarizeVector, EltVT);
866 
867  // Try to widen vector elements until the element type is a power of two and
868  // promote it to a legal type later on, for example:
869  // <3 x i8> -> <4 x i8> -> <4 x i32>
870  if (EltVT.isInteger()) {
871  // Vectors with a number of elements that is not a power of two are always
872  // widened, for example <3 x i8> -> <4 x i8>.
873  if (!VT.isPow2VectorType()) {
874  NumElts = (unsigned)NextPowerOf2(NumElts);
875  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
876  return LegalizeKind(TypeWidenVector, NVT);
877  }
878 
879  // Examine the element type.
880  LegalizeKind LK = getTypeConversion(Context, EltVT);
881 
882  // If type is to be expanded, split the vector.
883  // <4 x i140> -> <2 x i140>
884  if (LK.first == TypeExpandInteger)
886  EVT::getVectorVT(Context, EltVT, NumElts / 2));
887 
888  // Promote the integer element types until a legal vector type is found
889  // or until the element integer type is too big. If a legal type was not
890  // found, fallback to the usual mechanism of widening/splitting the
891  // vector.
892  EVT OldEltVT = EltVT;
893  while (true) {
894  // Increase the bitwidth of the element to the next pow-of-two
895  // (which is greater than 8 bits).
896  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
897  .getRoundIntegerType(Context);
898 
899  // Stop trying when getting a non-simple element type.
900  // Note that vector elements may be greater than legal vector element
901  // types. Example: X86 XMM registers hold 64bit element on 32bit
902  // systems.
903  if (!EltVT.isSimple())
904  break;
905 
906  // Build a new vector type and check if it is legal.
907  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
908  // Found a legal promoted vector type.
909  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
911  EVT::getVectorVT(Context, EltVT, NumElts));
912  }
913 
914  // Reset the type to the unexpanded type if we did not find a legal vector
915  // type with a promoted vector element type.
916  EltVT = OldEltVT;
917  }
918 
919  // Try to widen the vector until a legal type is found.
920  // If there is no wider legal type, split the vector.
921  while (true) {
922  // Round up to the next power of 2.
923  NumElts = (unsigned)NextPowerOf2(NumElts);
924 
925  // If there is no simple vector type with this many elements then there
926  // cannot be a larger legal vector type. Note that this assumes that
927  // there are no skipped intermediate vector types in the simple types.
928  if (!EltVT.isSimple())
929  break;
930  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
931  if (LargerVector == MVT())
932  break;
933 
934  // If this type is legal then widen the vector.
935  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
936  return LegalizeKind(TypeWidenVector, LargerVector);
937  }
938 
939  // Widen odd vectors to next power of two.
940  if (!VT.isPow2VectorType()) {
941  EVT NVT = VT.getPow2VectorType(Context);
942  return LegalizeKind(TypeWidenVector, NVT);
943  }
944 
945  // Vectors with illegal element types are expanded.
946  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
947  return LegalizeKind(TypeSplitVector, NVT);
948 }
949 
950 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
951  unsigned &NumIntermediates,
952  MVT &RegisterVT,
953  TargetLoweringBase *TLI) {
954  // Figure out the right, legal destination reg to copy into.
955  unsigned NumElts = VT.getVectorNumElements();
956  MVT EltTy = VT.getVectorElementType();
957 
958  unsigned NumVectorRegs = 1;
959 
960  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
961  // could break down into LHS/RHS like LegalizeDAG does.
962  if (!isPowerOf2_32(NumElts)) {
963  NumVectorRegs = NumElts;
964  NumElts = 1;
965  }
966 
967  // Divide the input until we get to a supported size. This will always
968  // end with a scalar if the target doesn't support vectors.
969  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
970  NumElts >>= 1;
971  NumVectorRegs <<= 1;
972  }
973 
974  NumIntermediates = NumVectorRegs;
975 
976  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
977  if (!TLI->isTypeLegal(NewVT))
978  NewVT = EltTy;
979  IntermediateVT = NewVT;
980 
981  unsigned NewVTSize = NewVT.getSizeInBits();
982 
983  // Convert sizes such as i33 to i64.
984  if (!isPowerOf2_32(NewVTSize))
985  NewVTSize = NextPowerOf2(NewVTSize);
986 
987  MVT DestVT = TLI->getRegisterType(NewVT);
988  RegisterVT = DestVT;
989  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
990  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
991 
992  // Otherwise, promotion or legal types use the same number of registers as
993  // the vector decimated to the appropriate level.
994  return NumVectorRegs;
995 }
996 
997 /// isLegalRC - Return true if the value types that can be represented by the
998 /// specified register class are all legal.
1000  const TargetRegisterClass &RC) const {
1001  for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1002  if (isTypeLegal(*I))
1003  return true;
1004  return false;
1005 }
1006 
1007 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1008 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1011  MachineBasicBlock *MBB) const {
1012  MachineInstr *MI = &InitialMI;
1013  MachineFunction &MF = *MI->getMF();
1014  MachineFrameInfo &MFI = MF.getFrameInfo();
1015 
1016  // We're handling multiple types of operands here:
1017  // PATCHPOINT MetaArgs - live-in, read only, direct
1018  // STATEPOINT Deopt Spill - live-through, read only, indirect
1019  // STATEPOINT Deopt Alloca - live-through, read only, direct
1020  // (We're currently conservative and mark the deopt slots read/write in
1021  // practice.)
1022  // STATEPOINT GC Spill - live-through, read/write, indirect
1023  // STATEPOINT GC Alloca - live-through, read/write, direct
1024  // The live-in vs live-through is handled already (the live through ones are
1025  // all stack slots), but we need to handle the different type of stackmap
1026  // operands and memory effects here.
1027 
1028  // MI changes inside this loop as we grow operands.
1029  for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1030  MachineOperand &MO = MI->getOperand(OperIdx);
1031  if (!MO.isFI())
1032  continue;
1033 
1034  // foldMemoryOperand builds a new MI after replacing a single FI operand
1035  // with the canonical set of five x86 addressing-mode operands.
1036  int FI = MO.getIndex();
1037  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1038 
1039  // Copy operands before the frame-index.
1040  for (unsigned i = 0; i < OperIdx; ++i)
1041  MIB.add(MI->getOperand(i));
1042  // Add frame index operands recognized by stackmaps.cpp
1043  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1044  // indirect-mem-ref tag, size, #FI, offset.
1045  // Used for spills inserted by StatepointLowering. This codepath is not
1046  // used for patchpoints/stackmaps at all, for these spilling is done via
1047  // foldMemoryOperand callback only.
1048  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1049  MIB.addImm(StackMaps::IndirectMemRefOp);
1050  MIB.addImm(MFI.getObjectSize(FI));
1051  MIB.add(MI->getOperand(OperIdx));
1052  MIB.addImm(0);
1053  } else {
1054  // direct-mem-ref tag, #FI, offset.
1055  // Used by patchpoint, and direct alloca arguments to statepoints
1056  MIB.addImm(StackMaps::DirectMemRefOp);
1057  MIB.add(MI->getOperand(OperIdx));
1058  MIB.addImm(0);
1059  }
1060  // Copy the operands after the frame index.
1061  for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1062  MIB.add(MI->getOperand(i));
1063 
1064  // Inherit previous memory operands.
1065  MIB.cloneMemRefs(*MI);
1066  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1067 
1068  // Add a new memory operand for this FI.
1069  assert(MFI.getObjectOffset(FI) != -1);
1070 
1071  // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1072  // PATCHPOINT should be updated to do the same. (TODO)
1073  if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1074  auto Flags = MachineMemOperand::MOLoad;
1076  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1078  MIB->addMemOperand(MF, MMO);
1079  }
1080 
1081  // Replace the instruction and update the operand index.
1082  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1083  OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1084  MI->eraseFromParent();
1085  MI = MIB;
1086  }
1087  return MBB;
1088 }
1089 
1092  MachineBasicBlock *MBB) const {
1093  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL &&
1094  "Called emitXRayCustomEvent on the wrong MI!");
1095  auto &MF = *MI.getMF();
1096  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1097  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1098  MIB.add(MI.getOperand(OpIdx));
1099 
1100  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1101  MI.eraseFromParent();
1102  return MBB;
1103 }
1104 
1107  MachineBasicBlock *MBB) const {
1108  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL &&
1109  "Called emitXRayTypedEvent on the wrong MI!");
1110  auto &MF = *MI.getMF();
1111  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1112  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1113  MIB.add(MI.getOperand(OpIdx));
1114 
1115  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1116  MI.eraseFromParent();
1117  return MBB;
1118 }
1119 
1120 /// findRepresentativeClass - Return the largest legal super-reg register class
1121 /// of the register class for the specified type and its associated "cost".
1122 // This function is in TargetLowering because it uses RegClassForVT which would
1123 // need to be moved to TargetRegisterInfo and would necessitate moving
1124 // isTypeLegal over as well - a massive change that would just require
1125 // TargetLowering having a TargetRegisterInfo class member that it would use.
1126 std::pair<const TargetRegisterClass *, uint8_t>
1128  MVT VT) const {
1129  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1130  if (!RC)
1131  return std::make_pair(RC, 0);
1132 
1133  // Compute the set of all super-register classes.
1134  BitVector SuperRegRC(TRI->getNumRegClasses());
1135  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1136  SuperRegRC.setBitsInMask(RCI.getMask());
1137 
1138  // Find the first legal register class with the largest spill size.
1139  const TargetRegisterClass *BestRC = RC;
1140  for (unsigned i : SuperRegRC.set_bits()) {
1141  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1142  // We want the largest possible spill size.
1143  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1144  continue;
1145  if (!isLegalRC(*TRI, *SuperRC))
1146  continue;
1147  BestRC = SuperRC;
1148  }
1149  return std::make_pair(BestRC, 1);
1150 }
1151 
1152 /// computeRegisterProperties - Once all of the register classes are added,
1153 /// this allows us to compute derived properties we expose.
1155  const TargetRegisterInfo *TRI) {
1157  "Too many value types for ValueTypeActions to hold!");
1158 
1159  // Everything defaults to needing one register.
1160  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1161  NumRegistersForVT[i] = 1;
1162  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1163  }
1164  // ...except isVoid, which doesn't need any registers.
1165  NumRegistersForVT[MVT::isVoid] = 0;
1166 
1167  // Find the largest integer register class.
1168  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1169  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1170  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1171 
1172  // Every integer value type larger than this largest register takes twice as
1173  // many registers to represent as the previous ValueType.
1174  for (unsigned ExpandedReg = LargestIntReg + 1;
1175  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1176  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1177  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1178  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1181  }
1182 
1183  // Inspect all of the ValueType's smaller than the largest integer
1184  // register to see which ones need promotion.
1185  unsigned LegalIntReg = LargestIntReg;
1186  for (unsigned IntReg = LargestIntReg - 1;
1187  IntReg >= (unsigned)MVT::i1; --IntReg) {
1188  MVT IVT = (MVT::SimpleValueType)IntReg;
1189  if (isTypeLegal(IVT)) {
1190  LegalIntReg = IntReg;
1191  } else {
1192  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1193  (MVT::SimpleValueType)LegalIntReg;
1195  }
1196  }
1197 
1198  // ppcf128 type is really two f64's.
1199  if (!isTypeLegal(MVT::ppcf128)) {
1200  if (isTypeLegal(MVT::f64)) {
1201  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1202  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1203  TransformToType[MVT::ppcf128] = MVT::f64;
1205  } else {
1206  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1207  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1208  TransformToType[MVT::ppcf128] = MVT::i128;
1210  }
1211  }
1212 
1213  // Decide how to handle f128. If the target does not have native f128 support,
1214  // expand it to i128 and we will be generating soft float library calls.
1215  if (!isTypeLegal(MVT::f128)) {
1216  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1217  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1218  TransformToType[MVT::f128] = MVT::i128;
1220  }
1221 
1222  // Decide how to handle f64. If the target does not have native f64 support,
1223  // expand it to i64 and we will be generating soft float library calls.
1224  if (!isTypeLegal(MVT::f64)) {
1225  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1226  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1227  TransformToType[MVT::f64] = MVT::i64;
1229  }
1230 
1231  // Decide how to handle f32. If the target does not have native f32 support,
1232  // expand it to i32 and we will be generating soft float library calls.
1233  if (!isTypeLegal(MVT::f32)) {
1234  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1235  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1236  TransformToType[MVT::f32] = MVT::i32;
1238  }
1239 
1240  // Decide how to handle f16. If the target does not have native f16 support,
1241  // promote it to f32, because there are no f16 library calls (except for
1242  // conversions).
1243  if (!isTypeLegal(MVT::f16)) {
1244  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1245  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1246  TransformToType[MVT::f16] = MVT::f32;
1248  }
1249 
1250  // Loop over all of the vector value types to see which need transformations.
1251  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1252  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1253  MVT VT = (MVT::SimpleValueType) i;
1254  if (isTypeLegal(VT))
1255  continue;
1256 
1257  MVT EltVT = VT.getVectorElementType();
1258  unsigned NElts = VT.getVectorNumElements();
1259  bool IsLegalWiderType = false;
1260  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1261  switch (PreferredAction) {
1262  case TypePromoteInteger:
1263  // Try to promote the elements of integer vectors. If no legal
1264  // promotion was found, fall through to the widen-vector method.
1265  for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
1266  MVT SVT = (MVT::SimpleValueType) nVT;
1267  // Promote vectors of integers to vectors with the same number
1268  // of elements, with a wider element type.
1269  if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1270  SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
1271  TransformToType[i] = SVT;
1272  RegisterTypeForVT[i] = SVT;
1273  NumRegistersForVT[i] = 1;
1275  IsLegalWiderType = true;
1276  break;
1277  }
1278  }
1279  if (IsLegalWiderType)
1280  break;
1282 
1283  case TypeWidenVector:
1284  // Try to widen the vector.
1285  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1286  MVT SVT = (MVT::SimpleValueType) nVT;
1287  if (SVT.getVectorElementType() == EltVT
1288  && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1289  TransformToType[i] = SVT;
1290  RegisterTypeForVT[i] = SVT;
1291  NumRegistersForVT[i] = 1;
1293  IsLegalWiderType = true;
1294  break;
1295  }
1296  }
1297  if (IsLegalWiderType)
1298  break;
1300 
1301  case TypeSplitVector:
1302  case TypeScalarizeVector: {
1303  MVT IntermediateVT;
1304  MVT RegisterVT;
1305  unsigned NumIntermediates;
1306  NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1307  NumIntermediates, RegisterVT, this);
1308  RegisterTypeForVT[i] = RegisterVT;
1309 
1310  MVT NVT = VT.getPow2VectorType();
1311  if (NVT == VT) {
1312  // Type is already a power of 2. The default action is to split.
1313  TransformToType[i] = MVT::Other;
1314  if (PreferredAction == TypeScalarizeVector)
1316  else if (PreferredAction == TypeSplitVector)
1318  else
1319  // Set type action according to the number of elements.
1321  : TypeSplitVector);
1322  } else {
1323  TransformToType[i] = NVT;
1325  }
1326  break;
1327  }
1328  default:
1329  llvm_unreachable("Unknown vector legalization action!");
1330  }
1331  }
1332 
1333  // Determine the 'representative' register class for each value type.
1334  // An representative register class is the largest (meaning one which is
1335  // not a sub-register class / subreg register class) legal register class for
1336  // a group of value types. For example, on i386, i8, i16, and i32
1337  // representative would be GR32; while on x86_64 it's GR64.
1338  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1339  const TargetRegisterClass* RRC;
1340  uint8_t Cost;
1341  std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1342  RepRegClassForVT[i] = RRC;
1343  RepRegClassCostForVT[i] = Cost;
1344  }
1345 }
1346 
1348  EVT VT) const {
1349  assert(!VT.isVector() && "No default SetCC type for vectors!");
1350  return getPointerTy(DL).SimpleTy;
1351 }
1352 
1354  return MVT::i32; // return the default value
1355 }
1356 
1357 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1358 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1359 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1360 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1361 ///
1362 /// This method returns the number of registers needed, and the VT for each
1363 /// register. It also returns the VT and quantity of the intermediate values
1364 /// before they are promoted/expanded.
1366  EVT &IntermediateVT,
1367  unsigned &NumIntermediates,
1368  MVT &RegisterVT) const {
1369  unsigned NumElts = VT.getVectorNumElements();
1370 
1371  // If there is a wider vector type with the same element type as this one,
1372  // or a promoted vector type that has the same number of elements which
1373  // are wider, then we should convert to that legal vector type.
1374  // This handles things like <2 x float> -> <4 x float> and
1375  // <4 x i1> -> <4 x i32>.
1376  LegalizeTypeAction TA = getTypeAction(Context, VT);
1377  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1378  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1379  if (isTypeLegal(RegisterEVT)) {
1380  IntermediateVT = RegisterEVT;
1381  RegisterVT = RegisterEVT.getSimpleVT();
1382  NumIntermediates = 1;
1383  return 1;
1384  }
1385  }
1386 
1387  // Figure out the right, legal destination reg to copy into.
1388  EVT EltTy = VT.getVectorElementType();
1389 
1390  unsigned NumVectorRegs = 1;
1391 
1392  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1393  // could break down into LHS/RHS like LegalizeDAG does.
1394  if (!isPowerOf2_32(NumElts)) {
1395  NumVectorRegs = NumElts;
1396  NumElts = 1;
1397  }
1398 
1399  // Divide the input until we get to a supported size. This will always
1400  // end with a scalar if the target doesn't support vectors.
1401  while (NumElts > 1 && !isTypeLegal(
1402  EVT::getVectorVT(Context, EltTy, NumElts))) {
1403  NumElts >>= 1;
1404  NumVectorRegs <<= 1;
1405  }
1406 
1407  NumIntermediates = NumVectorRegs;
1408 
1409  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1410  if (!isTypeLegal(NewVT))
1411  NewVT = EltTy;
1412  IntermediateVT = NewVT;
1413 
1414  MVT DestVT = getRegisterType(Context, NewVT);
1415  RegisterVT = DestVT;
1416  unsigned NewVTSize = NewVT.getSizeInBits();
1417 
1418  // Convert sizes such as i33 to i64.
1419  if (!isPowerOf2_32(NewVTSize))
1420  NewVTSize = NextPowerOf2(NewVTSize);
1421 
1422  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1423  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1424 
1425  // Otherwise, promotion or legal types use the same number of registers as
1426  // the vector decimated to the appropriate level.
1427  return NumVectorRegs;
1428 }
1429 
1430 /// Get the EVTs and ArgFlags collections that represent the legalized return
1431 /// type of the given function. This does not require a DAG or a return value,
1432 /// and is suitable for use before any DAGs for the function are constructed.
1433 /// TODO: Move this out of TargetLowering.cpp.
1435  AttributeList attr,
1437  const TargetLowering &TLI, const DataLayout &DL) {
1438  SmallVector<EVT, 4> ValueVTs;
1439  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1440  unsigned NumValues = ValueVTs.size();
1441  if (NumValues == 0) return;
1442 
1443  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1444  EVT VT = ValueVTs[j];
1445  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1446 
1447  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1448  ExtendKind = ISD::SIGN_EXTEND;
1449  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1450  ExtendKind = ISD::ZERO_EXTEND;
1451 
1452  // FIXME: C calling convention requires the return type to be promoted to
1453  // at least 32-bit. But this is not necessary for non-C calling
1454  // conventions. The frontend should mark functions whose return values
1455  // require promoting with signext or zeroext attributes.
1456  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1457  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1458  if (VT.bitsLT(MinVT))
1459  VT = MinVT;
1460  }
1461 
1462  unsigned NumParts =
1463  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1464  MVT PartVT =
1465  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1466 
1467  // 'inreg' on function refers to return value
1468  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1469  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1470  Flags.setInReg();
1471 
1472  // Propagate extension type if any
1473  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1474  Flags.setSExt();
1475  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1476  Flags.setZExt();
1477 
1478  for (unsigned i = 0; i < NumParts; ++i)
1479  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1480  }
1481 }
1482 
1483 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1484 /// function arguments in the caller parameter area. This is the actual
1485 /// alignment, not its logarithm.
1487  const DataLayout &DL) const {
1488  return DL.getABITypeAlignment(Ty);
1489 }
1490 
1492  const DataLayout &DL, EVT VT,
1493  unsigned AddrSpace,
1494  unsigned Alignment,
1496  bool *Fast) const {
1497  // Check if the specified alignment is sufficient based on the data layout.
1498  // TODO: While using the data layout works in practice, a better solution
1499  // would be to implement this check directly (make this a virtual function).
1500  // For example, the ABI alignment may change based on software platform while
1501  // this function should only be affected by hardware implementation.
1502  Type *Ty = VT.getTypeForEVT(Context);
1503  if (Alignment >= DL.getABITypeAlignment(Ty)) {
1504  // Assume that an access that meets the ABI-specified alignment is fast.
1505  if (Fast != nullptr)
1506  *Fast = true;
1507  return true;
1508  }
1509 
1510  // This is a misaligned access.
1511  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1512 }
1513 
1515  const DataLayout &DL, EVT VT,
1516  const MachineMemOperand &MMO,
1517  bool *Fast) const {
1518  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(),
1519  MMO.getAlignment(), MMO.getFlags(), Fast);
1520 }
1521 
1523  return BranchProbability(MinPercentageForPredictableBranch, 100);
1524 }
1525 
1526 //===----------------------------------------------------------------------===//
1527 // TargetTransformInfo Helpers
1528 //===----------------------------------------------------------------------===//
1529 
1531  enum InstructionOpcodes {
1532 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1533 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1534 #include "llvm/IR/Instruction.def"
1535  };
1536  switch (static_cast<InstructionOpcodes>(Opcode)) {
1537  case Ret: return 0;
1538  case Br: return 0;
1539  case Switch: return 0;
1540  case IndirectBr: return 0;
1541  case Invoke: return 0;
1542  case CallBr: return 0;
1543  case Resume: return 0;
1544  case Unreachable: return 0;
1545  case CleanupRet: return 0;
1546  case CatchRet: return 0;
1547  case CatchPad: return 0;
1548  case CatchSwitch: return 0;
1549  case CleanupPad: return 0;
1550  case FNeg: return ISD::FNEG;
1551  case Add: return ISD::ADD;
1552  case FAdd: return ISD::FADD;
1553  case Sub: return ISD::SUB;
1554  case FSub: return ISD::FSUB;
1555  case Mul: return ISD::MUL;
1556  case FMul: return ISD::FMUL;
1557  case UDiv: return ISD::UDIV;
1558  case SDiv: return ISD::SDIV;
1559  case FDiv: return ISD::FDIV;
1560  case URem: return ISD::UREM;
1561  case SRem: return ISD::SREM;
1562  case FRem: return ISD::FREM;
1563  case Shl: return ISD::SHL;
1564  case LShr: return ISD::SRL;
1565  case AShr: return ISD::SRA;
1566  case And: return ISD::AND;
1567  case Or: return ISD::OR;
1568  case Xor: return ISD::XOR;
1569  case Alloca: return 0;
1570  case Load: return ISD::LOAD;
1571  case Store: return ISD::STORE;
1572  case GetElementPtr: return 0;
1573  case Fence: return 0;
1574  case AtomicCmpXchg: return 0;
1575  case AtomicRMW: return 0;
1576  case Trunc: return ISD::TRUNCATE;
1577  case ZExt: return ISD::ZERO_EXTEND;
1578  case SExt: return ISD::SIGN_EXTEND;
1579  case FPToUI: return ISD::FP_TO_UINT;
1580  case FPToSI: return ISD::FP_TO_SINT;
1581  case UIToFP: return ISD::UINT_TO_FP;
1582  case SIToFP: return ISD::SINT_TO_FP;
1583  case FPTrunc: return ISD::FP_ROUND;
1584  case FPExt: return ISD::FP_EXTEND;
1585  case PtrToInt: return ISD::BITCAST;
1586  case IntToPtr: return ISD::BITCAST;
1587  case BitCast: return ISD::BITCAST;
1588  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1589  case ICmp: return ISD::SETCC;
1590  case FCmp: return ISD::SETCC;
1591  case PHI: return 0;
1592  case Call: return 0;
1593  case Select: return ISD::SELECT;
1594  case UserOp1: return 0;
1595  case UserOp2: return 0;
1596  case VAArg: return 0;
1597  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1598  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1599  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1600  case ExtractValue: return ISD::MERGE_VALUES;
1601  case InsertValue: return ISD::MERGE_VALUES;
1602  case LandingPad: return 0;
1603  }
1604 
1605  llvm_unreachable("Unknown instruction type encountered!");
1606 }
1607 
1608 std::pair<int, MVT>
1610  Type *Ty) const {
1611  LLVMContext &C = Ty->getContext();
1612  EVT MTy = getValueType(DL, Ty);
1613 
1614  int Cost = 1;
1615  // We keep legalizing the type until we find a legal kind. We assume that
1616  // the only operation that costs anything is the split. After splitting
1617  // we need to handle two types.
1618  while (true) {
1619  LegalizeKind LK = getTypeConversion(C, MTy);
1620 
1621  if (LK.first == TypeLegal)
1622  return std::make_pair(Cost, MTy.getSimpleVT());
1623 
1624  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1625  Cost *= 2;
1626 
1627  // Do not loop with f128 type.
1628  if (MTy == LK.second)
1629  return std::make_pair(Cost, MTy.getSimpleVT());
1630 
1631  // Keep legalizing the type.
1632  MTy = LK.second;
1633  }
1634 }
1635 
1637  bool UseTLS) const {
1638  // compiler-rt provides a variable with a magic name. Targets that do not
1639  // link with compiler-rt may also provide such a variable.
1640  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1641  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1642  auto UnsafeStackPtr =
1643  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1644 
1645  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1646 
1647  if (!UnsafeStackPtr) {
1648  auto TLSModel = UseTLS ?
1651  // The global variable is not defined yet, define it ourselves.
1652  // We use the initial-exec TLS model because we do not support the
1653  // variable living anywhere other than in the main executable.
1654  UnsafeStackPtr = new GlobalVariable(
1655  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1656  UnsafeStackPtrVar, nullptr, TLSModel);
1657  } else {
1658  // The variable exists, check its type and attributes.
1659  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1660  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1661  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1662  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1663  (UseTLS ? "" : "not ") + "be thread-local");
1664  }
1665  return UnsafeStackPtr;
1666 }
1667 
1669  if (!TM.getTargetTriple().isAndroid())
1670  return getDefaultSafeStackPointerLocation(IRB, true);
1671 
1672  // Android provides a libc function to retrieve the address of the current
1673  // thread's unsafe stack pointer.
1674  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1675  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1676  FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1677  StackPtrTy->getPointerTo(0));
1678  return IRB.CreateCall(Fn);
1679 }
1680 
1681 //===----------------------------------------------------------------------===//
1682 // Loop Strength Reduction hooks
1683 //===----------------------------------------------------------------------===//
1684 
1685 /// isLegalAddressingMode - Return true if the addressing mode represented
1686 /// by AM is legal for this target, for a load/store of the specified type.
1688  const AddrMode &AM, Type *Ty,
1689  unsigned AS, Instruction *I) const {
1690  // The default implementation of this implements a conservative RISCy, r+r and
1691  // r+i addr mode.
1692 
1693  // Allows a sign-extended 16-bit immediate field.
1694  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1695  return false;
1696 
1697  // No global is ever allowed as a base.
1698  if (AM.BaseGV)
1699  return false;
1700 
1701  // Only support r+r,
1702  switch (AM.Scale) {
1703  case 0: // "r+i" or just "i", depending on HasBaseReg.
1704  break;
1705  case 1:
1706  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1707  return false;
1708  // Otherwise we have r+r or r+i.
1709  break;
1710  case 2:
1711  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1712  return false;
1713  // Allow 2*r as r+r.
1714  break;
1715  default: // Don't allow n * r
1716  return false;
1717  }
1718 
1719  return true;
1720 }
1721 
1722 //===----------------------------------------------------------------------===//
1723 // Stack Protector
1724 //===----------------------------------------------------------------------===//
1725 
1726 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1727 // so that SelectionDAG handle SSP.
1729  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1730  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1732  return M.getOrInsertGlobal("__guard_local", PtrTy);
1733  }
1734  return nullptr;
1735 }
1736 
1737 // Currently only support "standard" __stack_chk_guard.
1738 // TODO: add LOAD_STACK_GUARD support.
1740  if (!M.getNamedValue("__stack_chk_guard"))
1741  new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1743  nullptr, "__stack_chk_guard");
1744 }
1745 
1746 // Currently only support "standard" __stack_chk_guard.
1747 // TODO: add LOAD_STACK_GUARD support.
1749  return M.getNamedValue("__stack_chk_guard");
1750 }
1751 
1753  return nullptr;
1754 }
1755 
1757  return MinimumJumpTableEntries;
1758 }
1759 
1762 }
1763 
1764 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1765  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1766 }
1767 
1769  return MaximumJumpTableSize;
1770 }
1771 
1773  MaximumJumpTableSize = Val;
1774 }
1775 
1776 //===----------------------------------------------------------------------===//
1777 // Reciprocal Estimates
1778 //===----------------------------------------------------------------------===//
1779 
1780 /// Get the reciprocal estimate attribute string for a function that will
1781 /// override the target defaults.
1783  const Function &F = MF.getFunction();
1784  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1785 }
1786 
1787 /// Construct a string for the given reciprocal operation of the given type.
1788 /// This string should match the corresponding option to the front-end's
1789 /// "-mrecip" flag assuming those strings have been passed through in an
1790 /// attribute string. For example, "vec-divf" for a division of a vXf32.
1791 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1792  std::string Name = VT.isVector() ? "vec-" : "";
1793 
1794  Name += IsSqrt ? "sqrt" : "div";
1795 
1796  // TODO: Handle "half" or other float types?
1797  if (VT.getScalarType() == MVT::f64) {
1798  Name += "d";
1799  } else {
1800  assert(VT.getScalarType() == MVT::f32 &&
1801  "Unexpected FP type for reciprocal estimate");
1802  Name += "f";
1803  }
1804 
1805  return Name;
1806 }
1807 
1808 /// Return the character position and value (a single numeric character) of a
1809 /// customized refinement operation in the input string if it exists. Return
1810 /// false if there is no customized refinement step count.
1812  uint8_t &Value) {
1813  const char RefStepToken = ':';
1814  Position = In.find(RefStepToken);
1815  if (Position == StringRef::npos)
1816  return false;
1817 
1818  StringRef RefStepString = In.substr(Position + 1);
1819  // Allow exactly one numeric character for the additional refinement
1820  // step parameter.
1821  if (RefStepString.size() == 1) {
1822  char RefStepChar = RefStepString[0];
1823  if (RefStepChar >= '0' && RefStepChar <= '9') {
1824  Value = RefStepChar - '0';
1825  return true;
1826  }
1827  }
1828  report_fatal_error("Invalid refinement step for -recip.");
1829 }
1830 
1831 /// For the input attribute string, return one of the ReciprocalEstimate enum
1832 /// status values (enabled, disabled, or not specified) for this operation on
1833 /// the specified data type.
1834 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1835  if (Override.empty())
1836  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1837 
1838  SmallVector<StringRef, 4> OverrideVector;
1839  Override.split(OverrideVector, ',');
1840  unsigned NumArgs = OverrideVector.size();
1841 
1842  // Check if "all", "none", or "default" was specified.
1843  if (NumArgs == 1) {
1844  // Look for an optional setting of the number of refinement steps needed
1845  // for this type of reciprocal operation.
1846  size_t RefPos;
1847  uint8_t RefSteps;
1848  if (parseRefinementStep(Override, RefPos, RefSteps)) {
1849  // Split the string for further processing.
1850  Override = Override.substr(0, RefPos);
1851  }
1852 
1853  // All reciprocal types are enabled.
1854  if (Override == "all")
1856 
1857  // All reciprocal types are disabled.
1858  if (Override == "none")
1859  return TargetLoweringBase::ReciprocalEstimate::Disabled;
1860 
1861  // Target defaults for enablement are used.
1862  if (Override == "default")
1863  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1864  }
1865 
1866  // The attribute string may omit the size suffix ('f'/'d').
1867  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1868  std::string VTNameNoSize = VTName;
1869  VTNameNoSize.pop_back();
1870  static const char DisabledPrefix = '!';
1871 
1872  for (StringRef RecipType : OverrideVector) {
1873  size_t RefPos;
1874  uint8_t RefSteps;
1875  if (parseRefinementStep(RecipType, RefPos, RefSteps))
1876  RecipType = RecipType.substr(0, RefPos);
1877 
1878  // Ignore the disablement token for string matching.
1879  bool IsDisabled = RecipType[0] == DisabledPrefix;
1880  if (IsDisabled)
1881  RecipType = RecipType.substr(1);
1882 
1883  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1884  return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
1886  }
1887 
1888  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1889 }
1890 
1891 /// For the input attribute string, return the customized refinement step count
1892 /// for this operation on the specified data type. If the step count does not
1893 /// exist, return the ReciprocalEstimate enum value for unspecified.
1894 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
1895  if (Override.empty())
1896  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1897 
1898  SmallVector<StringRef, 4> OverrideVector;
1899  Override.split(OverrideVector, ',');
1900  unsigned NumArgs = OverrideVector.size();
1901 
1902  // Check if "all", "default", or "none" was specified.
1903  if (NumArgs == 1) {
1904  // Look for an optional setting of the number of refinement steps needed
1905  // for this type of reciprocal operation.
1906  size_t RefPos;
1907  uint8_t RefSteps;
1908  if (!parseRefinementStep(Override, RefPos, RefSteps))
1909  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1910 
1911  // Split the string for further processing.
1912  Override = Override.substr(0, RefPos);
1913  assert(Override != "none" &&
1914  "Disabled reciprocals, but specifed refinement steps?");
1915 
1916  // If this is a general override, return the specified number of steps.
1917  if (Override == "all" || Override == "default")
1918  return RefSteps;
1919  }
1920 
1921  // The attribute string may omit the size suffix ('f'/'d').
1922  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1923  std::string VTNameNoSize = VTName;
1924  VTNameNoSize.pop_back();
1925 
1926  for (StringRef RecipType : OverrideVector) {
1927  size_t RefPos;
1928  uint8_t RefSteps;
1929  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
1930  continue;
1931 
1932  RecipType = RecipType.substr(0, RefPos);
1933  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1934  return RefSteps;
1935  }
1936 
1937  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1938 }
1939 
1941  MachineFunction &MF) const {
1942  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
1943 }
1944 
1946  MachineFunction &MF) const {
1947  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
1948 }
1949 
1951  MachineFunction &MF) const {
1952  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
1953 }
1954 
1956  MachineFunction &MF) const {
1957  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
1958 }
1959 
1961  MF.getRegInfo().freezeReservedRegs(MF);
1962 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
static bool darwinHasSinCos(const Triple &TT)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:562
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
static MVT getIntegerVT(unsigned BitWidth)
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:300
LLVMContext & Context
unsigned getAddrSpace() const
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:358
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:453
static MVT getVectorVT(MVT VT, unsigned NumElements)
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:633
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:391
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:284
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:543
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:165
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
Y = RRC X, rotate right via carry.
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
static cl::opt< int > MinPercentageForPredictableBranch("min-predictable-branch", cl::init(99), cl::desc("Minimum percentage (0-100) that a condition must be either true " "or false to assume that the condition is predictable"), cl::Hidden)
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled...
unsigned getVectorNumElements() const
Externally visible function.
Definition: GlobalValue.h:48
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:833
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:388
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:293
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
bool isOSFuchsia() const
Definition: Triple.h:505
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:532
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:408
Same for subtraction.
Definition: ISDOpcodes.h:253
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:340
bool isValid() const
Return true if this is a valid simple valuetype.
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type...
Definition: ValueTypes.h:365
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function&#39;s at...
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
A description of a memory reference used in the backend.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
Shift and rotation operations.
Definition: ISDOpcodes.h:434
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:217
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:244
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:417
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:654
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:779
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:841
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:578
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Position
Position to insert a new instruction relative to an existing instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
unsigned getNumRegClasses() const
unsigned getSizeInBits() const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:502
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:296
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:126
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
GlobalValue * getNamedValue(StringRef Name) const
Return the global value in the module with the specified name, of arbitrary type. ...
Definition: Module.cpp:113
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:462
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:323
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:778
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:521
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
MVT getVectorElementType() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function&#39;s attri...
Class to represent pointers.
Definition: DerivedTypes.h:544
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:548
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
virtual Value * getIRStackGuard(IRBuilder<> &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
These reductions are non-strict, and have a single vector operand.
Definition: ISDOpcodes.h:901
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
bool isOSOpenBSD() const
Definition: Triple.h:497
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
unsigned getScalarSizeInBits() const
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:645
bool isWatchABI() const
Definition: Triple.h:476
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:356
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:285
static mvt_range fp_valuetypes()
bool isAndroidVersionLT(unsigned Major) const
Definition: Triple.h:663
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:798
const Triple & getTargetTriple() const
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:801
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
bool isPPC64() const
Tests whether the target is 64-bit PowerPC (little and big endian).
Definition: Triple.h:724
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:440
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:827
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:580
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Extended Value Type.
Definition: ValueTypes.h:33
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:644
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
size_t size() const
Definition: SmallVector.h:52
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:219
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function&#39;s attributes...
const TargetMachine & getTargetMachine() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
Value * getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) const
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
void initActions()
Initialize all of the actions to default values.
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:264
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal...
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight)...
Definition: ValueTypes.h:316
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:102
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:363
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:475
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:599
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
Module.h This file contains the declarations for the Module class.
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1050
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:746
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values, following the IEEE-754 2008 definition.
Definition: ISDOpcodes.h:628
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
FunctionCallee getOrInsertFunction(StringRef Name, FunctionType *T, AttributeList AttributeList)
Look up the specified function in the module symbol table.
Definition: Module.cpp:143
static bool Enabled
Definition: Statistic.cpp:50
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:72
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:444
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:240
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:492
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:495
ValueTypeActionImpl ValueTypeActions
#define OP_TO_LIBCALL(Name, Enum)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:336
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Flags
Flags values. These may be or&#39;d together.
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function&#39;s attribut...
The memory access reads data.
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca...
Definition: ISDOpcodes.h:892
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static mvt_range all_valuetypes()
SimpleValueType Iteration.
Representation of each machine instruction.
Definition: MachineInstr.h:64
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Constant * getOrInsertGlobal(StringRef Name, Type *Ty, function_ref< GlobalVariable *()> CreateGlobalCallback)
Look up the specified global in the module symbol table.
Definition: Module.cpp:204
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:411
static const size_t npos
Definition: StringRef.h:50
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineBasicBlock * emitXRayCustomEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay custom event operands with target-dependent details.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:223
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1292
void setTypeAction(MVT VT, LegalizeTypeAction Action)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:642
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return &#39;Legal&#39;) or we ...
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
MachineBasicBlock * emitXRayTypedEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay typed event operands with target-dependent details.
#define I(x, y, z)
Definition: MD5.cpp:58
Flags getFlags() const
Return the raw flags of the source value,.
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
bool isGNUEnvironment() const
Definition: Triple.h:521
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:272
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision ...
Definition: ISDOpcodes.h:318
Same for multiplication.
Definition: ISDOpcodes.h:256
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:958
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value *> Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2223
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that&#39;s previously inserted by insertSSPDeclarations, if any, otherwise return nul...
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool isMacOSXVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isMacOSXVersionLT - Comparison function for checking OS X version compatibility, which handles suppor...
Definition: Triple.h:438
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:369
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:809
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:72
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:907
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:903
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:807
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:661
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
Definition: ISDOpcodes.h:330
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:467
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isOSVersionLT - Helper function for doing comparisons against version numbers included in the target ...
Definition: Triple.h:414
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
Conversion operators.
Definition: ISDOpcodes.h:489
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:498
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
virtual BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:610
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:63
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add &#39;1&#39; bits from Mask to this vector.
Definition: BitVector.h:775
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:241
LegalizeTypeAction getTypeAction(MVT VT) const
This file describes how to lower LLVM code to machine code.
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class...
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...