LLVM  9.0.0svn
MachineInstr.cpp
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1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Methods common to all machine instructions.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/APFloat.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/FoldingSet.h"
18 #include "llvm/ADT/Hashing.h"
19 #include "llvm/ADT/None.h"
20 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/Analysis/Loads.h"
40 #include "llvm/Config/llvm-config.h"
41 #include "llvm/IR/Constants.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Metadata.h"
51 #include "llvm/IR/Module.h"
53 #include "llvm/IR/Type.h"
54 #include "llvm/IR/Value.h"
55 #include "llvm/IR/Operator.h"
56 #include "llvm/MC/MCInstrDesc.h"
57 #include "llvm/MC/MCRegisterInfo.h"
58 #include "llvm/MC/MCSymbol.h"
59 #include "llvm/Support/Casting.h"
61 #include "llvm/Support/Compiler.h"
62 #include "llvm/Support/Debug.h"
69 #include <algorithm>
70 #include <cassert>
71 #include <cstddef>
72 #include <cstdint>
73 #include <cstring>
74 #include <iterator>
75 #include <utility>
76 
77 using namespace llvm;
78 
80  if (const MachineBasicBlock *MBB = MI.getParent())
81  if (const MachineFunction *MF = MBB->getParent())
82  return MF;
83  return nullptr;
84 }
85 
86 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
87 // it.
88 static void tryToGetTargetInfo(const MachineInstr &MI,
89  const TargetRegisterInfo *&TRI,
90  const MachineRegisterInfo *&MRI,
91  const TargetIntrinsicInfo *&IntrinsicInfo,
92  const TargetInstrInfo *&TII) {
93 
94  if (const MachineFunction *MF = getMFIfAvailable(MI)) {
95  TRI = MF->getSubtarget().getRegisterInfo();
96  MRI = &MF->getRegInfo();
97  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
98  TII = MF->getSubtarget().getInstrInfo();
99  }
100 }
101 
103  if (MCID->ImplicitDefs)
104  for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
105  ++ImpDefs)
106  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
107  if (MCID->ImplicitUses)
108  for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
109  ++ImpUses)
110  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
111 }
112 
113 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
114 /// implicit operands. It reserves space for the number of operands specified by
115 /// the MCInstrDesc.
116 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
117  DebugLoc dl, bool NoImp)
118  : MCID(&tid), debugLoc(std::move(dl)) {
119  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
120 
121  // Reserve space for the expected number of operands.
122  if (unsigned NumOps = MCID->getNumOperands() +
123  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
124  CapOperands = OperandCapacity::get(NumOps);
125  Operands = MF.allocateOperandArray(CapOperands);
126  }
127 
128  if (!NoImp)
130 }
131 
132 /// MachineInstr ctor - Copies MachineInstr arg exactly
133 ///
134 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
135  : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) {
136  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
137 
138  CapOperands = OperandCapacity::get(MI.getNumOperands());
139  Operands = MF.allocateOperandArray(CapOperands);
140 
141  // Copy operands.
142  for (const MachineOperand &MO : MI.operands())
143  addOperand(MF, MO);
144 
145  // Copy all the sensible flags.
146  setFlags(MI.Flags);
147 }
148 
149 /// getRegInfo - If this instruction is embedded into a MachineFunction,
150 /// return the MachineRegisterInfo object for the current function, otherwise
151 /// return null.
152 MachineRegisterInfo *MachineInstr::getRegInfo() {
153  if (MachineBasicBlock *MBB = getParent())
154  return &MBB->getParent()->getRegInfo();
155  return nullptr;
156 }
157 
158 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
159 /// this instruction from their respective use lists. This requires that the
160 /// operands already be on their use lists.
161 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
162  for (MachineOperand &MO : operands())
163  if (MO.isReg())
165 }
166 
167 /// AddRegOperandsToUseLists - Add all of the register operands in
168 /// this instruction from their respective use lists. This requires that the
169 /// operands not be on their use lists yet.
170 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
171  for (MachineOperand &MO : operands())
172  if (MO.isReg())
173  MRI.addRegOperandToUseList(&MO);
174 }
175 
177  MachineBasicBlock *MBB = getParent();
178  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
179  MachineFunction *MF = MBB->getParent();
180  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
181  addOperand(*MF, Op);
182 }
183 
184 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
185 /// ranges. If MRI is non-null also update use-def chains.
187  unsigned NumOps, MachineRegisterInfo *MRI) {
188  if (MRI)
189  return MRI->moveOperands(Dst, Src, NumOps);
190 
191  // MachineOperand is a trivially copyable type so we can just use memmove.
192  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
193 }
194 
195 /// addOperand - Add the specified operand to the instruction. If it is an
196 /// implicit operand, it is added to the end of the operand list. If it is
197 /// an explicit operand it is added at the end of the explicit operand list
198 /// (before the first implicit operand).
200  assert(MCID && "Cannot add operands before providing an instr descriptor");
201 
202  // Check if we're adding one of our existing operands.
203  if (&Op >= Operands && &Op < Operands + NumOperands) {
204  // This is unusual: MI->addOperand(MI->getOperand(i)).
205  // If adding Op requires reallocating or moving existing operands around,
206  // the Op reference could go stale. Support it by copying Op.
207  MachineOperand CopyOp(Op);
208  return addOperand(MF, CopyOp);
209  }
210 
211  // Find the insert location for the new operand. Implicit registers go at
212  // the end, everything else goes before the implicit regs.
213  //
214  // FIXME: Allow mixed explicit and implicit operands on inline asm.
215  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
216  // implicit-defs, but they must not be moved around. See the FIXME in
217  // InstrEmitter.cpp.
218  unsigned OpNo = getNumOperands();
219  bool isImpReg = Op.isReg() && Op.isImplicit();
220  if (!isImpReg && !isInlineAsm()) {
221  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
222  --OpNo;
223  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
224  }
225  }
226 
227 #ifndef NDEBUG
228  bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
230  // OpNo now points as the desired insertion point. Unless this is a variadic
231  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
232  // RegMask operands go between the explicit and implicit operands.
233  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
234  OpNo < MCID->getNumOperands() || isDebugOp) &&
235  "Trying to add an operand to a machine instr that is already done!");
236 #endif
237 
238  MachineRegisterInfo *MRI = getRegInfo();
239 
240  // Determine if the Operands array needs to be reallocated.
241  // Save the old capacity and operand array.
242  OperandCapacity OldCap = CapOperands;
243  MachineOperand *OldOperands = Operands;
244  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
245  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
246  Operands = MF.allocateOperandArray(CapOperands);
247  // Move the operands before the insertion point.
248  if (OpNo)
249  moveOperands(Operands, OldOperands, OpNo, MRI);
250  }
251 
252  // Move the operands following the insertion point.
253  if (OpNo != NumOperands)
254  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
255  MRI);
256  ++NumOperands;
257 
258  // Deallocate the old operand array.
259  if (OldOperands != Operands && OldOperands)
260  MF.deallocateOperandArray(OldCap, OldOperands);
261 
262  // Copy Op into place. It still needs to be inserted into the MRI use lists.
263  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
264  NewMO->ParentMI = this;
265 
266  // When adding a register operand, tell MRI about it.
267  if (NewMO->isReg()) {
268  // Ensure isOnRegUseList() returns false, regardless of Op's status.
269  NewMO->Contents.Reg.Prev = nullptr;
270  // Ignore existing ties. This is not a property that can be copied.
271  NewMO->TiedTo = 0;
272  // Add the new operand to MRI, but only for instructions in an MBB.
273  if (MRI)
274  MRI->addRegOperandToUseList(NewMO);
275  // The MCID operand information isn't accurate until we start adding
276  // explicit operands. The implicit operands are added first, then the
277  // explicits are inserted before them.
278  if (!isImpReg) {
279  // Tie uses to defs as indicated in MCInstrDesc.
280  if (NewMO->isUse()) {
281  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
282  if (DefIdx != -1)
283  tieOperands(DefIdx, OpNo);
284  }
285  // If the register operand is flagged as early, mark the operand as such.
286  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
287  NewMO->setIsEarlyClobber(true);
288  }
289  }
290 }
291 
292 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
293 /// fewer operand than it started with.
294 ///
295 void MachineInstr::RemoveOperand(unsigned OpNo) {
296  assert(OpNo < getNumOperands() && "Invalid operand number");
297  untieRegOperand(OpNo);
298 
299 #ifndef NDEBUG
300  // Moving tied operands would break the ties.
301  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
302  if (Operands[i].isReg())
303  assert(!Operands[i].isTied() && "Cannot move tied operands");
304 #endif
305 
306  MachineRegisterInfo *MRI = getRegInfo();
307  if (MRI && Operands[OpNo].isReg())
308  MRI->removeRegOperandFromUseList(Operands + OpNo);
309 
310  // Don't call the MachineOperand destructor. A lot of this code depends on
311  // MachineOperand having a trivial destructor anyway, and adding a call here
312  // wouldn't make it 'destructor-correct'.
313 
314  if (unsigned N = NumOperands - 1 - OpNo)
315  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
316  --NumOperands;
317 }
318 
320  if (memoperands_empty())
321  return;
322 
323  // See if we can just drop all of our extra info.
324  if (!getPreInstrSymbol() && !getPostInstrSymbol()) {
325  Info.clear();
326  return;
327  }
328  if (!getPostInstrSymbol()) {
329  Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
330  return;
331  }
332  if (!getPreInstrSymbol()) {
333  Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
334  return;
335  }
336 
337  // Otherwise allocate a fresh extra info with just these symbols.
338  Info.set<EIIK_OutOfLine>(
340 }
341 
344  if (MMOs.empty()) {
345  dropMemRefs(MF);
346  return;
347  }
348 
349  // Try to store a single MMO inline.
350  if (MMOs.size() == 1 && !getPreInstrSymbol() && !getPostInstrSymbol()) {
351  Info.set<EIIK_MMO>(MMOs[0]);
352  return;
353  }
354 
355  // Otherwise create an extra info struct with all of our info.
356  Info.set<EIIK_OutOfLine>(
358 }
359 
361  MachineMemOperand *MO) {
364  MMOs.push_back(MO);
365  setMemRefs(MF, MMOs);
366 }
367 
369  if (this == &MI)
370  // Nothing to do for a self-clone!
371  return;
372 
373  assert(&MF == MI.getMF() &&
374  "Invalid machine functions when cloning memory refrences!");
375  // See if we can just steal the extra info already allocated for the
376  // instruction. We can do this whenever the pre- and post-instruction symbols
377  // are the same (including null).
378  if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
380  Info = MI.Info;
381  return;
382  }
383 
384  // Otherwise, fall back on a copy-based clone.
385  setMemRefs(MF, MI.memoperands());
386 }
387 
388 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
389 /// identical.
392  if (LHS.size() != RHS.size())
393  return false;
394 
395  auto LHSPointees = make_pointee_range(LHS);
396  auto RHSPointees = make_pointee_range(RHS);
397  return std::equal(LHSPointees.begin(), LHSPointees.end(),
398  RHSPointees.begin());
399 }
400 
403  // Try handling easy numbers of MIs with simpler mechanisms.
404  if (MIs.empty()) {
405  dropMemRefs(MF);
406  return;
407  }
408  if (MIs.size() == 1) {
409  cloneMemRefs(MF, *MIs[0]);
410  return;
411  }
412  // Because an empty memoperands list provides *no* information and must be
413  // handled conservatively (assuming the instruction can do anything), the only
414  // way to merge with it is to drop all other memoperands.
415  if (MIs[0]->memoperands_empty()) {
416  dropMemRefs(MF);
417  return;
418  }
419 
420  // Handle the general case.
422  // Start with the first instruction.
423  assert(&MF == MIs[0]->getMF() &&
424  "Invalid machine functions when cloning memory references!");
425  MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
426  // Now walk all the other instructions and accumulate any different MMOs.
427  for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
428  assert(&MF == MI.getMF() &&
429  "Invalid machine functions when cloning memory references!");
430 
431  // Skip MIs with identical operands to the first. This is a somewhat
432  // arbitrary hack but will catch common cases without being quadratic.
433  // TODO: We could fully implement merge semantics here if needed.
434  if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
435  continue;
436 
437  // Because an empty memoperands list provides *no* information and must be
438  // handled conservatively (assuming the instruction can do anything), the
439  // only way to merge with it is to drop all other memoperands.
440  if (MI.memoperands_empty()) {
441  dropMemRefs(MF);
442  return;
443  }
444 
445  // Otherwise accumulate these into our temporary buffer of the merged state.
446  MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
447  }
448 
449  setMemRefs(MF, MergedMMOs);
450 }
451 
453  MCSymbol *OldSymbol = getPreInstrSymbol();
454  if (OldSymbol == Symbol)
455  return;
456  if (OldSymbol && !Symbol) {
457  // We're removing a symbol rather than adding one. Try to clean up any
458  // extra info carried around.
459  if (Info.is<EIIK_PreInstrSymbol>()) {
460  Info.clear();
461  return;
462  }
463 
464  if (memoperands_empty()) {
466  "Should never have only a single symbol allocated out-of-line!");
467  Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
468  return;
469  }
470 
471  // Otherwise fallback on the generic update.
472  } else if (!Info || Info.is<EIIK_PreInstrSymbol>()) {
473  // If we don't have any other extra info, we can store this inline.
474  Info.set<EIIK_PreInstrSymbol>(Symbol);
475  return;
476  }
477 
478  // Otherwise, allocate a full new set of extra info.
479  // FIXME: Maybe we should make the symbols in the extra info mutable?
480  Info.set<EIIK_OutOfLine>(
482 }
483 
485  MCSymbol *OldSymbol = getPostInstrSymbol();
486  if (OldSymbol == Symbol)
487  return;
488  if (OldSymbol && !Symbol) {
489  // We're removing a symbol rather than adding one. Try to clean up any
490  // extra info carried around.
491  if (Info.is<EIIK_PostInstrSymbol>()) {
492  Info.clear();
493  return;
494  }
495 
496  if (memoperands_empty()) {
498  "Should never have only a single symbol allocated out-of-line!");
499  Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
500  return;
501  }
502 
503  // Otherwise fallback on the generic update.
504  } else if (!Info || Info.is<EIIK_PostInstrSymbol>()) {
505  // If we don't have any other extra info, we can store this inline.
506  Info.set<EIIK_PostInstrSymbol>(Symbol);
507  return;
508  }
509 
510  // Otherwise, allocate a full new set of extra info.
511  // FIXME: Maybe we should make the symbols in the extra info mutable?
512  Info.set<EIIK_OutOfLine>(
514 }
515 
516 uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
517  // For now, the just return the union of the flags. If the flags get more
518  // complicated over time, we might need more logic here.
519  return getFlags() | Other.getFlags();
520 }
521 
523  // Copy the wrapping flags.
524  if (const OverflowingBinaryOperator *OB =
525  dyn_cast<OverflowingBinaryOperator>(&I)) {
526  if (OB->hasNoSignedWrap())
527  setFlag(MachineInstr::MIFlag::NoSWrap);
528  if (OB->hasNoUnsignedWrap())
529  setFlag(MachineInstr::MIFlag::NoUWrap);
530  }
531 
532  // Copy the exact flag.
533  if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
534  if (PE->isExact())
535  setFlag(MachineInstr::MIFlag::IsExact);
536 
537  // Copy the fast-math flags.
538  if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
539  const FastMathFlags Flags = FP->getFastMathFlags();
540  if (Flags.noNaNs())
541  setFlag(MachineInstr::MIFlag::FmNoNans);
542  if (Flags.noInfs())
543  setFlag(MachineInstr::MIFlag::FmNoInfs);
544  if (Flags.noSignedZeros())
545  setFlag(MachineInstr::MIFlag::FmNsz);
546  if (Flags.allowReciprocal())
547  setFlag(MachineInstr::MIFlag::FmArcp);
548  if (Flags.allowContract())
549  setFlag(MachineInstr::MIFlag::FmContract);
550  if (Flags.approxFunc())
551  setFlag(MachineInstr::MIFlag::FmAfn);
552  if (Flags.allowReassoc())
553  setFlag(MachineInstr::MIFlag::FmReassoc);
554  }
555 }
556 
557 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
558  assert(!isBundledWithPred() && "Must be called on bundle header");
560  if (MII->getDesc().getFlags() & Mask) {
561  if (Type == AnyInBundle)
562  return true;
563  } else {
564  if (Type == AllInBundle && !MII->isBundle())
565  return false;
566  }
567  // This was the last instruction in the bundle.
568  if (!MII->isBundledWithSucc())
569  return Type == AllInBundle;
570  }
571 }
572 
574  MICheckType Check) const {
575  // If opcodes or number of operands are not the same then the two
576  // instructions are obviously not identical.
577  if (Other.getOpcode() != getOpcode() ||
578  Other.getNumOperands() != getNumOperands())
579  return false;
580 
581  if (isBundle()) {
582  // We have passed the test above that both instructions have the same
583  // opcode, so we know that both instructions are bundles here. Let's compare
584  // MIs inside the bundle.
585  assert(Other.isBundle() && "Expected that both instructions are bundles.");
588  // Loop until we analysed the last intruction inside at least one of the
589  // bundles.
590  while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
591  ++I1;
592  ++I2;
593  if (!I1->isIdenticalTo(*I2, Check))
594  return false;
595  }
596  // If we've reached the end of just one of the two bundles, but not both,
597  // the instructions are not identical.
598  if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
599  return false;
600  }
601 
602  // Check operands to make sure they match.
603  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
604  const MachineOperand &MO = getOperand(i);
605  const MachineOperand &OMO = Other.getOperand(i);
606  if (!MO.isReg()) {
607  if (!MO.isIdenticalTo(OMO))
608  return false;
609  continue;
610  }
611 
612  // Clients may or may not want to ignore defs when testing for equality.
613  // For example, machine CSE pass only cares about finding common
614  // subexpressions, so it's safe to ignore virtual register defs.
615  if (MO.isDef()) {
616  if (Check == IgnoreDefs)
617  continue;
618  else if (Check == IgnoreVRegDefs) {
621  if (!MO.isIdenticalTo(OMO))
622  return false;
623  } else {
624  if (!MO.isIdenticalTo(OMO))
625  return false;
626  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
627  return false;
628  }
629  } else {
630  if (!MO.isIdenticalTo(OMO))
631  return false;
632  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
633  return false;
634  }
635  }
636  // If DebugLoc does not match then two debug instructions are not identical.
637  if (isDebugInstr())
638  if (getDebugLoc() && Other.getDebugLoc() &&
639  getDebugLoc() != Other.getDebugLoc())
640  return false;
641  return true;
642 }
643 
645  return getParent()->getParent();
646 }
647 
649  assert(getParent() && "Not embedded in a basic block!");
650  return getParent()->remove(this);
651 }
652 
654  assert(getParent() && "Not embedded in a basic block!");
655  return getParent()->remove_instr(this);
656 }
657 
659  assert(getParent() && "Not embedded in a basic block!");
660  getParent()->erase(this);
661 }
662 
664  assert(getParent() && "Not embedded in a basic block!");
665  MachineBasicBlock *MBB = getParent();
666  MachineFunction *MF = MBB->getParent();
667  assert(MF && "Not embedded in a function!");
668 
669  MachineInstr *MI = (MachineInstr *)this;
670  MachineRegisterInfo &MRI = MF->getRegInfo();
671 
672  for (const MachineOperand &MO : MI->operands()) {
673  if (!MO.isReg() || !MO.isDef())
674  continue;
675  unsigned Reg = MO.getReg();
677  continue;
679  }
680  MI->eraseFromParent();
681 }
682 
684  assert(getParent() && "Not embedded in a basic block!");
685  getParent()->erase_instr(this);
686 }
687 
689  unsigned NumOperands = MCID->getNumOperands();
690  if (!MCID->isVariadic())
691  return NumOperands;
692 
693  for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
694  const MachineOperand &MO = getOperand(I);
695  // The operands must always be in the following order:
696  // - explicit reg defs,
697  // - other explicit operands (reg uses, immediates, etc.),
698  // - implicit reg defs
699  // - implicit reg uses
700  if (MO.isReg() && MO.isImplicit())
701  break;
702  ++NumOperands;
703  }
704  return NumOperands;
705 }
706 
708  unsigned NumDefs = MCID->getNumDefs();
709  if (!MCID->isVariadic())
710  return NumDefs;
711 
712  for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
713  const MachineOperand &MO = getOperand(I);
714  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
715  break;
716  ++NumDefs;
717  }
718  return NumDefs;
719 }
720 
722  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
725  --Pred;
726  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
727  Pred->setFlag(BundledSucc);
728 }
729 
731  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
734  ++Succ;
735  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
736  Succ->setFlag(BundledPred);
737 }
738 
740  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
743  --Pred;
744  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
745  Pred->clearFlag(BundledSucc);
746 }
747 
749  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
752  ++Succ;
753  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
754  Succ->clearFlag(BundledPred);
755 }
756 
758  if (isInlineAsm()) {
759  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
760  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
761  return true;
762  }
763  return false;
764 }
765 
767  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
768  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
769  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
770 }
771 
773  unsigned *GroupNo) const {
774  assert(isInlineAsm() && "Expected an inline asm instruction");
775  assert(OpIdx < getNumOperands() && "OpIdx out of range");
776 
777  // Ignore queries about the initial operands.
778  if (OpIdx < InlineAsm::MIOp_FirstOperand)
779  return -1;
780 
781  unsigned Group = 0;
782  unsigned NumOps;
783  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
784  i += NumOps) {
785  const MachineOperand &FlagMO = getOperand(i);
786  // If we reach the implicit register operands, stop looking.
787  if (!FlagMO.isImm())
788  return -1;
789  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
790  if (i + NumOps > OpIdx) {
791  if (GroupNo)
792  *GroupNo = Group;
793  return i;
794  }
795  ++Group;
796  }
797  return -1;
798 }
799 
801  assert(isDebugLabel() && "not a DBG_LABEL");
802  return cast<DILabel>(getOperand(0).getMetadata());
803 }
804 
806  assert(isDebugValue() && "not a DBG_VALUE");
807  return cast<DILocalVariable>(getOperand(2).getMetadata());
808 }
809 
811  assert(isDebugValue() && "not a DBG_VALUE");
812  return cast<DIExpression>(getOperand(3).getMetadata());
813 }
814 
815 const TargetRegisterClass*
817  const TargetInstrInfo *TII,
818  const TargetRegisterInfo *TRI) const {
819  assert(getParent() && "Can't have an MBB reference here!");
820  assert(getMF() && "Can't have an MF reference here!");
821  const MachineFunction &MF = *getMF();
822 
823  // Most opcodes have fixed constraints in their MCInstrDesc.
824  if (!isInlineAsm())
825  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
826 
827  if (!getOperand(OpIdx).isReg())
828  return nullptr;
829 
830  // For tied uses on inline asm, get the constraint from the def.
831  unsigned DefIdx;
832  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
833  OpIdx = DefIdx;
834 
835  // Inline asm stores register class constraints in the flag word.
836  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
837  if (FlagIdx < 0)
838  return nullptr;
839 
840  unsigned Flag = getOperand(FlagIdx).getImm();
841  unsigned RCID;
846  return TRI->getRegClass(RCID);
847 
848  // Assume that all registers in a memory operand are pointers.
850  return TRI->getPointerRegClass(MF);
851 
852  return nullptr;
853 }
854 
856  unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
857  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
858  // Check every operands inside the bundle if we have
859  // been asked to.
860  if (ExploreBundle)
861  for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
862  ++OpndIt)
863  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
864  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
865  else
866  // Otherwise, just check the current operands.
867  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
868  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
869  return CurRC;
870 }
871 
872 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
873  unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
874  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
875  assert(CurRC && "Invalid initial register class");
876  // Check if Reg is constrained by some of its use/def from MI.
877  const MachineOperand &MO = getOperand(OpIdx);
878  if (!MO.isReg() || MO.getReg() != Reg)
879  return CurRC;
880  // If yes, accumulate the constraints through the operand.
881  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
882 }
883 
885  unsigned OpIdx, const TargetRegisterClass *CurRC,
886  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
887  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
888  const MachineOperand &MO = getOperand(OpIdx);
889  assert(MO.isReg() &&
890  "Cannot get register constraints for non-register operand");
891  assert(CurRC && "Invalid initial register class");
892  if (unsigned SubIdx = MO.getSubReg()) {
893  if (OpRC)
894  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
895  else
896  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
897  } else if (OpRC)
898  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
899  return CurRC;
900 }
901 
902 /// Return the number of instructions inside the MI bundle, not counting the
903 /// header instruction.
904 unsigned MachineInstr::getBundleSize() const {
906  unsigned Size = 0;
907  while (I->isBundledWithSucc()) {
908  ++Size;
909  ++I;
910  }
911  return Size;
912 }
913 
914 /// Returns true if the MachineInstr has an implicit-use operand of exactly
915 /// the given register (not considering sub/super-registers).
917  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
918  const MachineOperand &MO = getOperand(i);
919  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
920  return true;
921  }
922  return false;
923 }
924 
925 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
926 /// the specific register or -1 if it is not found. It further tightens
927 /// the search criteria to a use that kills the register if isKill is true.
929  unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
930  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
931  const MachineOperand &MO = getOperand(i);
932  if (!MO.isReg() || !MO.isUse())
933  continue;
934  unsigned MOReg = MO.getReg();
935  if (!MOReg)
936  continue;
937  if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
938  if (!isKill || MO.isKill())
939  return i;
940  }
941  return -1;
942 }
943 
944 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
945 /// indicating if this instruction reads or writes Reg. This also considers
946 /// partial defines.
947 std::pair<bool,bool>
949  SmallVectorImpl<unsigned> *Ops) const {
950  bool PartDef = false; // Partial redefine.
951  bool FullDef = false; // Full define.
952  bool Use = false;
953 
954  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
955  const MachineOperand &MO = getOperand(i);
956  if (!MO.isReg() || MO.getReg() != Reg)
957  continue;
958  if (Ops)
959  Ops->push_back(i);
960  if (MO.isUse())
961  Use |= !MO.isUndef();
962  else if (MO.getSubReg() && !MO.isUndef())
963  // A partial def undef doesn't count as reading the register.
964  PartDef = true;
965  else
966  FullDef = true;
967  }
968  // A partial redefine uses Reg unless there is also a full define.
969  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
970 }
971 
972 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
973 /// the specified register or -1 if it is not found. If isDead is true, defs
974 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
975 /// also checks if there is a def of a super-register.
976 int
977 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
978  const TargetRegisterInfo *TRI) const {
979  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
980  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
981  const MachineOperand &MO = getOperand(i);
982  // Accept regmask operands when Overlap is set.
983  // Ignore them when looking for a specific def operand (Overlap == false).
984  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
985  return i;
986  if (!MO.isReg() || !MO.isDef())
987  continue;
988  unsigned MOReg = MO.getReg();
989  bool Found = (MOReg == Reg);
990  if (!Found && TRI && isPhys &&
992  if (Overlap)
993  Found = TRI->regsOverlap(MOReg, Reg);
994  else
995  Found = TRI->isSubRegister(MOReg, Reg);
996  }
997  if (Found && (!isDead || MO.isDead()))
998  return i;
999  }
1000  return -1;
1001 }
1002 
1003 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1004 /// operand list that is used to represent the predicate. It returns -1 if
1005 /// none is found.
1007  // Don't call MCID.findFirstPredOperandIdx() because this variant
1008  // is sometimes called on an instruction that's not yet complete, and
1009  // so the number of operands is less than the MCID indicates. In
1010  // particular, the PTX target does this.
1011  const MCInstrDesc &MCID = getDesc();
1012  if (MCID.isPredicable()) {
1013  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1014  if (MCID.OpInfo[i].isPredicate())
1015  return i;
1016  }
1017 
1018  return -1;
1019 }
1020 
1021 // MachineOperand::TiedTo is 4 bits wide.
1022 const unsigned TiedMax = 15;
1023 
1024 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1025 ///
1026 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1027 /// field. TiedTo can have these values:
1028 ///
1029 /// 0: Operand is not tied to anything.
1030 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1031 /// TiedMax: Tied to an operand >= TiedMax-1.
1032 ///
1033 /// The tied def must be one of the first TiedMax operands on a normal
1034 /// instruction. INLINEASM instructions allow more tied defs.
1035 ///
1036 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1037  MachineOperand &DefMO = getOperand(DefIdx);
1038  MachineOperand &UseMO = getOperand(UseIdx);
1039  assert(DefMO.isDef() && "DefIdx must be a def operand");
1040  assert(UseMO.isUse() && "UseIdx must be a use operand");
1041  assert(!DefMO.isTied() && "Def is already tied to another use");
1042  assert(!UseMO.isTied() && "Use is already tied to another def");
1043 
1044  if (DefIdx < TiedMax)
1045  UseMO.TiedTo = DefIdx + 1;
1046  else {
1047  // Inline asm can use the group descriptors to find tied operands, but on
1048  // normal instruction, the tied def must be within the first TiedMax
1049  // operands.
1050  assert(isInlineAsm() && "DefIdx out of range");
1051  UseMO.TiedTo = TiedMax;
1052  }
1053 
1054  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1055  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1056 }
1057 
1058 /// Given the index of a tied register operand, find the operand it is tied to.
1059 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1060 /// which must exist.
1061 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1062  const MachineOperand &MO = getOperand(OpIdx);
1063  assert(MO.isTied() && "Operand isn't tied");
1064 
1065  // Normally TiedTo is in range.
1066  if (MO.TiedTo < TiedMax)
1067  return MO.TiedTo - 1;
1068 
1069  // Uses on normal instructions can be out of range.
1070  if (!isInlineAsm()) {
1071  // Normal tied defs must be in the 0..TiedMax-1 range.
1072  if (MO.isUse())
1073  return TiedMax - 1;
1074  // MO is a def. Search for the tied use.
1075  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1076  const MachineOperand &UseMO = getOperand(i);
1077  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1078  return i;
1079  }
1080  llvm_unreachable("Can't find tied use");
1081  }
1082 
1083  // Now deal with inline asm by parsing the operand group descriptor flags.
1084  // Find the beginning of each operand group.
1085  SmallVector<unsigned, 8> GroupIdx;
1086  unsigned OpIdxGroup = ~0u;
1087  unsigned NumOps;
1088  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1089  i += NumOps) {
1090  const MachineOperand &FlagMO = getOperand(i);
1091  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1092  unsigned CurGroup = GroupIdx.size();
1093  GroupIdx.push_back(i);
1094  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1095  // OpIdx belongs to this operand group.
1096  if (OpIdx > i && OpIdx < i + NumOps)
1097  OpIdxGroup = CurGroup;
1098  unsigned TiedGroup;
1099  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1100  continue;
1101  // Operands in this group are tied to operands in TiedGroup which must be
1102  // earlier. Find the number of operands between the two groups.
1103  unsigned Delta = i - GroupIdx[TiedGroup];
1104 
1105  // OpIdx is a use tied to TiedGroup.
1106  if (OpIdxGroup == CurGroup)
1107  return OpIdx - Delta;
1108 
1109  // OpIdx is a def tied to this use group.
1110  if (OpIdxGroup == TiedGroup)
1111  return OpIdx + Delta;
1112  }
1113  llvm_unreachable("Invalid tied operand on inline asm");
1114 }
1115 
1116 /// clearKillInfo - Clears kill flags on all operands.
1117 ///
1119  for (MachineOperand &MO : operands()) {
1120  if (MO.isReg() && MO.isUse())
1121  MO.setIsKill(false);
1122  }
1123 }
1124 
1125 void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
1126  unsigned SubIdx,
1127  const TargetRegisterInfo &RegInfo) {
1129  if (SubIdx)
1130  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1131  for (MachineOperand &MO : operands()) {
1132  if (!MO.isReg() || MO.getReg() != FromReg)
1133  continue;
1134  MO.substPhysReg(ToReg, RegInfo);
1135  }
1136  } else {
1137  for (MachineOperand &MO : operands()) {
1138  if (!MO.isReg() || MO.getReg() != FromReg)
1139  continue;
1140  MO.substVirtReg(ToReg, SubIdx, RegInfo);
1141  }
1142  }
1143 }
1144 
1145 /// isSafeToMove - Return true if it is safe to move this instruction. If
1146 /// SawStore is set to true, it means that there is a store (or call) between
1147 /// the instruction's location and its intended destination.
1148 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1149  // Ignore stuff that we obviously can't move.
1150  //
1151  // Treat volatile loads as stores. This is not strictly necessary for
1152  // volatiles, but it is required for atomic loads. It is not allowed to move
1153  // a load across an atomic load with Ordering > Monotonic.
1154  if (mayStore() || isCall() || isPHI() ||
1155  (mayLoad() && hasOrderedMemoryRef())) {
1156  SawStore = true;
1157  return false;
1158  }
1159 
1160  if (isPosition() || isDebugInstr() || isTerminator() ||
1162  return false;
1163 
1164  // See if this instruction does a load. If so, we have to guarantee that the
1165  // loaded value doesn't change between the load and the its intended
1166  // destination. The check for isInvariantLoad gives the targe the chance to
1167  // classify the load as always returning a constant, e.g. a constant pool
1168  // load.
1170  // Otherwise, this is a real load. If there is a store between the load and
1171  // end of block, we can't move it.
1172  return !SawStore;
1173 
1174  return true;
1175 }
1176 
1178  bool UseTBAA) {
1179  const MachineFunction *MF = getMF();
1180  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1181  const MachineFrameInfo &MFI = MF->getFrameInfo();
1182 
1183  // If neither instruction stores to memory, they can't alias in any
1184  // meaningful way, even if they read from the same address.
1185  if (!mayStore() && !Other.mayStore())
1186  return false;
1187 
1188  // Let the target decide if memory accesses cannot possibly overlap.
1189  if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
1190  return false;
1191 
1192  // FIXME: Need to handle multiple memory operands to support all targets.
1193  if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1194  return true;
1195 
1197  MachineMemOperand *MMOb = *Other.memoperands_begin();
1198 
1199  // The following interface to AA is fashioned after DAGCombiner::isAlias
1200  // and operates with MachineMemOperand offset with some important
1201  // assumptions:
1202  // - LLVM fundamentally assumes flat address spaces.
1203  // - MachineOperand offset can *only* result from legalization and
1204  // cannot affect queries other than the trivial case of overlap
1205  // checking.
1206  // - These offsets never wrap and never step outside
1207  // of allocated objects.
1208  // - There should never be any negative offsets here.
1209  //
1210  // FIXME: Modify API to hide this math from "user"
1211  // Even before we go to AA we can reason locally about some
1212  // memory objects. It can save compile time, and possibly catch some
1213  // corner cases not currently covered.
1214 
1215  int64_t OffsetA = MMOa->getOffset();
1216  int64_t OffsetB = MMOb->getOffset();
1217  int64_t MinOffset = std::min(OffsetA, OffsetB);
1218 
1219  uint64_t WidthA = MMOa->getSize();
1220  uint64_t WidthB = MMOb->getSize();
1221  bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1222  bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1223 
1224  const Value *ValA = MMOa->getValue();
1225  const Value *ValB = MMOb->getValue();
1226  bool SameVal = (ValA && ValB && (ValA == ValB));
1227  if (!SameVal) {
1228  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1229  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1230  if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1231  return false;
1232  if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1233  return false;
1234  if (PSVa && PSVb && (PSVa == PSVb))
1235  SameVal = true;
1236  }
1237 
1238  if (SameVal) {
1239  if (!KnownWidthA || !KnownWidthB)
1240  return true;
1241  int64_t MaxOffset = std::max(OffsetA, OffsetB);
1242  int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1243  return (MinOffset + LowWidth > MaxOffset);
1244  }
1245 
1246  if (!AA)
1247  return true;
1248 
1249  if (!ValA || !ValB)
1250  return true;
1251 
1252  assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1253  assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1254 
1255  int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
1257  int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
1259 
1260  AliasResult AAResult = AA->alias(
1261  MemoryLocation(ValA, OverlapA,
1262  UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1263  MemoryLocation(ValB, OverlapB,
1264  UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1265 
1266  return (AAResult != NoAlias);
1267 }
1268 
1269 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1270 /// or volatile memory reference, or if the information describing the memory
1271 /// reference is not available. Return false if it is known to have no ordered
1272 /// memory references.
1274  // An instruction known never to access memory won't have a volatile access.
1275  if (!mayStore() &&
1276  !mayLoad() &&
1277  !isCall() &&
1279  return false;
1280 
1281  // Otherwise, if the instruction has no memory reference information,
1282  // conservatively assume it wasn't preserved.
1283  if (memoperands_empty())
1284  return true;
1285 
1286  // Check if any of our memory operands are ordered.
1287  return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1288  return !MMO->isUnordered();
1289  });
1290 }
1291 
1292 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1293 /// trap and is loading from a location whose value is invariant across a run of
1294 /// this function.
1296  // If the instruction doesn't load at all, it isn't an invariant load.
1297  if (!mayLoad())
1298  return false;
1299 
1300  // If the instruction has lost its memoperands, conservatively assume that
1301  // it may not be an invariant load.
1302  if (memoperands_empty())
1303  return false;
1304 
1305  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1306 
1307  for (MachineMemOperand *MMO : memoperands()) {
1308  if (MMO->isVolatile()) return false;
1309  if (MMO->isStore()) return false;
1310  if (MMO->isInvariant() && MMO->isDereferenceable())
1311  continue;
1312 
1313  // A load from a constant PseudoSourceValue is invariant.
1314  if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1315  if (PSV->isConstant(&MFI))
1316  continue;
1317 
1318  if (const Value *V = MMO->getValue()) {
1319  // If we have an AliasAnalysis, ask it whether the memory is constant.
1320  if (AA &&
1322  MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1323  continue;
1324  }
1325 
1326  // Otherwise assume conservatively.
1327  return false;
1328  }
1329 
1330  // Everything checks out.
1331  return true;
1332 }
1333 
1334 /// isConstantValuePHI - If the specified instruction is a PHI that always
1335 /// merges together the same virtual register, return the register, otherwise
1336 /// return 0.
1338  if (!isPHI())
1339  return 0;
1340  assert(getNumOperands() >= 3 &&
1341  "It's illegal to have a PHI without source operands");
1342 
1343  unsigned Reg = getOperand(1).getReg();
1344  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1345  if (getOperand(i).getReg() != Reg)
1346  return 0;
1347  return Reg;
1348 }
1349 
1352  return true;
1353  if (isInlineAsm()) {
1354  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1355  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1356  return true;
1357  }
1358 
1359  return false;
1360 }
1361 
1363  return mayStore() || isCall() || hasUnmodeledSideEffects();
1364 }
1365 
1366 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1367 ///
1369  for (const MachineOperand &MO : operands()) {
1370  if (!MO.isReg() || MO.isUse())
1371  continue;
1372  if (!MO.isDead())
1373  return false;
1374  }
1375  return true;
1376 }
1377 
1378 /// copyImplicitOps - Copy implicit register operands from specified
1379 /// instruction to this instruction.
1381  const MachineInstr &MI) {
1382  for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1383  i != e; ++i) {
1384  const MachineOperand &MO = MI.getOperand(i);
1385  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1386  addOperand(MF, MO);
1387  }
1388 }
1389 
1391  const MCInstrDesc &MCID = getDesc();
1392  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1393  const auto &Operand = getOperand(I);
1394  if (!Operand.isReg() || Operand.isDef())
1395  // Ignore the defined registers as MCID marks only the uses as tied.
1396  continue;
1397  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1398  int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1399  if (ExpectedTiedIdx != TiedIdx)
1400  return true;
1401  }
1402  return false;
1403 }
1404 
1405 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1406  const MachineRegisterInfo &MRI) const {
1407  const MachineOperand &Op = getOperand(OpIdx);
1408  if (!Op.isReg())
1409  return LLT{};
1410 
1411  if (isVariadic() || OpIdx >= getNumExplicitOperands())
1412  return MRI.getType(Op.getReg());
1413 
1414  auto &OpInfo = getDesc().OpInfo[OpIdx];
1415  if (!OpInfo.isGenericType())
1416  return MRI.getType(Op.getReg());
1417 
1418  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1419  return LLT{};
1420 
1421  LLT TypeToPrint = MRI.getType(Op.getReg());
1422  // Don't mark the type index printed if it wasn't actually printed: maybe
1423  // another operand with the same type index has an actual type attached:
1424  if (TypeToPrint.isValid())
1425  PrintedTypes.set(OpInfo.getGenericTypeIndex());
1426  return TypeToPrint;
1427 }
1428 
1429 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1431  dbgs() << " ";
1432  print(dbgs());
1433 }
1434 #endif
1435 
1436 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1437  bool SkipDebugLoc, bool AddNewLine,
1438  const TargetInstrInfo *TII) const {
1439  const Module *M = nullptr;
1440  const Function *F = nullptr;
1441  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1442  F = &MF->getFunction();
1443  M = F->getParent();
1444  if (!TII)
1445  TII = MF->getSubtarget().getInstrInfo();
1446  }
1447 
1448  ModuleSlotTracker MST(M);
1449  if (F)
1450  MST.incorporateFunction(*F);
1451  print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, TII);
1452 }
1453 
1455  bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1456  bool AddNewLine, const TargetInstrInfo *TII) const {
1457  // We can be a bit tidier if we know the MachineFunction.
1458  const MachineFunction *MF = nullptr;
1459  const TargetRegisterInfo *TRI = nullptr;
1460  const MachineRegisterInfo *MRI = nullptr;
1461  const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1462  tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1463 
1464  if (isCFIInstruction())
1465  assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1466 
1467  SmallBitVector PrintedTypes(8);
1468  bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1469  auto getTiedOperandIdx = [&](unsigned OpIdx) {
1470  if (!ShouldPrintRegisterTies)
1471  return 0U;
1472  const MachineOperand &MO = getOperand(OpIdx);
1473  if (MO.isReg() && MO.isTied() && !MO.isDef())
1474  return findTiedOperandIdx(OpIdx);
1475  return 0U;
1476  };
1477  unsigned StartOp = 0;
1478  unsigned e = getNumOperands();
1479 
1480  // Print explicitly defined operands on the left of an assignment syntax.
1481  while (StartOp < e) {
1482  const MachineOperand &MO = getOperand(StartOp);
1483  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1484  break;
1485 
1486  if (StartOp != 0)
1487  OS << ", ";
1488 
1489  LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1490  unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1491  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
1492  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1493  ++StartOp;
1494  }
1495 
1496  if (StartOp != 0)
1497  OS << " = ";
1498 
1500  OS << "frame-setup ";
1502  OS << "frame-destroy ";
1504  OS << "nnan ";
1506  OS << "ninf ";
1508  OS << "nsz ";
1510  OS << "arcp ";
1512  OS << "contract ";
1514  OS << "afn ";
1516  OS << "reassoc ";
1518  OS << "nuw ";
1520  OS << "nsw ";
1522  OS << "exact ";
1523 
1524  // Print the opcode name.
1525  if (TII)
1526  OS << TII->getName(getOpcode());
1527  else
1528  OS << "UNKNOWN";
1529 
1530  if (SkipOpers)
1531  return;
1532 
1533  // Print the rest of the operands.
1534  bool FirstOp = true;
1535  unsigned AsmDescOp = ~0u;
1536  unsigned AsmOpCount = 0;
1537 
1538  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1539  // Print asm string.
1540  OS << " ";
1541  const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1542  LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1543  unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1544  getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1545  ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1546  IntrinsicInfo);
1547 
1548  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1549  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1550  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1551  OS << " [sideeffect]";
1552  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1553  OS << " [mayload]";
1554  if (ExtraInfo & InlineAsm::Extra_MayStore)
1555  OS << " [maystore]";
1556  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1557  OS << " [isconvergent]";
1558  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1559  OS << " [alignstack]";
1561  OS << " [attdialect]";
1563  OS << " [inteldialect]";
1564 
1565  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1566  FirstOp = false;
1567  }
1568 
1569  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1570  const MachineOperand &MO = getOperand(i);
1571 
1572  if (FirstOp) FirstOp = false; else OS << ",";
1573  OS << " ";
1574 
1575  if (isDebugValue() && MO.isMetadata()) {
1576  // Pretty print DBG_VALUE instructions.
1577  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1578  if (DIV && !DIV->getName().empty())
1579  OS << "!\"" << DIV->getName() << '\"';
1580  else {
1581  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1582  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1583  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1584  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1585  }
1586  } else if (isDebugLabel() && MO.isMetadata()) {
1587  // Pretty print DBG_LABEL instructions.
1588  auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1589  if (DIL && !DIL->getName().empty())
1590  OS << "\"" << DIL->getName() << '\"';
1591  else {
1592  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1593  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1594  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1595  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1596  }
1597  } else if (i == AsmDescOp && MO.isImm()) {
1598  // Pretty print the inline asm operand descriptor.
1599  OS << '$' << AsmOpCount++;
1600  unsigned Flag = MO.getImm();
1601  switch (InlineAsm::getKind(Flag)) {
1602  case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1603  case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1604  case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1605  case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1606  case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1607  case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1608  default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1609  }
1610 
1611  unsigned RCID = 0;
1612  if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1613  InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1614  if (TRI) {
1615  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1616  } else
1617  OS << ":RC" << RCID;
1618  }
1619 
1620  if (InlineAsm::isMemKind(Flag)) {
1621  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1622  switch (MCID) {
1623  case InlineAsm::Constraint_es: OS << ":es"; break;
1624  case InlineAsm::Constraint_i: OS << ":i"; break;
1625  case InlineAsm::Constraint_m: OS << ":m"; break;
1626  case InlineAsm::Constraint_o: OS << ":o"; break;
1627  case InlineAsm::Constraint_v: OS << ":v"; break;
1628  case InlineAsm::Constraint_Q: OS << ":Q"; break;
1629  case InlineAsm::Constraint_R: OS << ":R"; break;
1630  case InlineAsm::Constraint_S: OS << ":S"; break;
1631  case InlineAsm::Constraint_T: OS << ":T"; break;
1632  case InlineAsm::Constraint_Um: OS << ":Um"; break;
1633  case InlineAsm::Constraint_Un: OS << ":Un"; break;
1634  case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1635  case InlineAsm::Constraint_Us: OS << ":Us"; break;
1636  case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1637  case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1638  case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1639  case InlineAsm::Constraint_X: OS << ":X"; break;
1640  case InlineAsm::Constraint_Z: OS << ":Z"; break;
1641  case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1642  case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1643  default: OS << ":?"; break;
1644  }
1645  }
1646 
1647  unsigned TiedTo = 0;
1648  if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1649  OS << " tiedto:$" << TiedTo;
1650 
1651  OS << ']';
1652 
1653  // Compute the index of the next operand descriptor.
1654  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1655  } else {
1656  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1657  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1658  if (MO.isImm() && isOperandSubregIdx(i))
1660  else
1661  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1662  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1663  }
1664  }
1665 
1666  // Print any optional symbols attached to this instruction as-if they were
1667  // operands.
1668  if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1669  if (!FirstOp) {
1670  FirstOp = false;
1671  OS << ',';
1672  }
1673  OS << " pre-instr-symbol ";
1674  MachineOperand::printSymbol(OS, *PreInstrSymbol);
1675  }
1676  if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1677  if (!FirstOp) {
1678  FirstOp = false;
1679  OS << ',';
1680  }
1681  OS << " post-instr-symbol ";
1682  MachineOperand::printSymbol(OS, *PostInstrSymbol);
1683  }
1684 
1685  if (!SkipDebugLoc) {
1686  if (const DebugLoc &DL = getDebugLoc()) {
1687  if (!FirstOp)
1688  OS << ',';
1689  OS << " debug-location ";
1690  DL->printAsOperand(OS, MST);
1691  }
1692  }
1693 
1694  if (!memoperands_empty()) {
1696  const LLVMContext *Context = nullptr;
1697  std::unique_ptr<LLVMContext> CtxPtr;
1698  const MachineFrameInfo *MFI = nullptr;
1699  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1700  MFI = &MF->getFrameInfo();
1701  Context = &MF->getFunction().getContext();
1702  } else {
1703  CtxPtr = llvm::make_unique<LLVMContext>();
1704  Context = CtxPtr.get();
1705  }
1706 
1707  OS << " :: ";
1708  bool NeedComma = false;
1709  for (const MachineMemOperand *Op : memoperands()) {
1710  if (NeedComma)
1711  OS << ", ";
1712  Op->print(OS, MST, SSNs, *Context, MFI, TII);
1713  NeedComma = true;
1714  }
1715  }
1716 
1717  if (SkipDebugLoc)
1718  return;
1719 
1720  bool HaveSemi = false;
1721 
1722  // Print debug location information.
1723  if (const DebugLoc &DL = getDebugLoc()) {
1724  if (!HaveSemi) {
1725  OS << ';';
1726  HaveSemi = true;
1727  }
1728  OS << ' ';
1729  DL.print(OS);
1730  }
1731 
1732  // Print extra comments for DEBUG_VALUE.
1733  if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1734  if (!HaveSemi) {
1735  OS << ";";
1736  HaveSemi = true;
1737  }
1738  auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1739  OS << " line no:" << DV->getLine();
1740  if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1741  DebugLoc InlinedAtDL(InlinedAt);
1742  if (InlinedAtDL && MF) {
1743  OS << " inlined @[ ";
1744  InlinedAtDL.print(OS);
1745  OS << " ]";
1746  }
1747  }
1748  if (isIndirectDebugValue())
1749  OS << " indirect";
1750  }
1751  // TODO: DBG_LABEL
1752 
1753  if (AddNewLine)
1754  OS << '\n';
1755 }
1756 
1757 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1758  const TargetRegisterInfo *RegInfo,
1759  bool AddIfNotFound) {
1760  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1761  bool hasAliases = isPhysReg &&
1762  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1763  bool Found = false;
1764  SmallVector<unsigned,4> DeadOps;
1765  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1766  MachineOperand &MO = getOperand(i);
1767  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1768  continue;
1769 
1770  // DEBUG_VALUE nodes do not contribute to code generation and should
1771  // always be ignored. Failure to do so may result in trying to modify
1772  // KILL flags on DEBUG_VALUE nodes.
1773  if (MO.isDebug())
1774  continue;
1775 
1776  unsigned Reg = MO.getReg();
1777  if (!Reg)
1778  continue;
1779 
1780  if (Reg == IncomingReg) {
1781  if (!Found) {
1782  if (MO.isKill())
1783  // The register is already marked kill.
1784  return true;
1785  if (isPhysReg && isRegTiedToDefOperand(i))
1786  // Two-address uses of physregs must not be marked kill.
1787  return true;
1788  MO.setIsKill();
1789  Found = true;
1790  }
1791  } else if (hasAliases && MO.isKill() &&
1793  // A super-register kill already exists.
1794  if (RegInfo->isSuperRegister(IncomingReg, Reg))
1795  return true;
1796  if (RegInfo->isSubRegister(IncomingReg, Reg))
1797  DeadOps.push_back(i);
1798  }
1799  }
1800 
1801  // Trim unneeded kill operands.
1802  while (!DeadOps.empty()) {
1803  unsigned OpIdx = DeadOps.back();
1804  if (getOperand(OpIdx).isImplicit() &&
1805  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1806  RemoveOperand(OpIdx);
1807  else
1808  getOperand(OpIdx).setIsKill(false);
1809  DeadOps.pop_back();
1810  }
1811 
1812  // If not found, this means an alias of one of the operands is killed. Add a
1813  // new implicit operand if required.
1814  if (!Found && AddIfNotFound) {
1816  false /*IsDef*/,
1817  true /*IsImp*/,
1818  true /*IsKill*/));
1819  return true;
1820  }
1821  return Found;
1822 }
1823 
1825  const TargetRegisterInfo *RegInfo) {
1827  RegInfo = nullptr;
1828  for (MachineOperand &MO : operands()) {
1829  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1830  continue;
1831  unsigned OpReg = MO.getReg();
1832  if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1833  MO.setIsKill(false);
1834  }
1835 }
1836 
1838  const TargetRegisterInfo *RegInfo,
1839  bool AddIfNotFound) {
1840  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1841  bool hasAliases = isPhysReg &&
1842  MCRegAliasIterator(Reg, RegInfo, false).isValid();
1843  bool Found = false;
1844  SmallVector<unsigned,4> DeadOps;
1845  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1846  MachineOperand &MO = getOperand(i);
1847  if (!MO.isReg() || !MO.isDef())
1848  continue;
1849  unsigned MOReg = MO.getReg();
1850  if (!MOReg)
1851  continue;
1852 
1853  if (MOReg == Reg) {
1854  MO.setIsDead();
1855  Found = true;
1856  } else if (hasAliases && MO.isDead() &&
1858  // There exists a super-register that's marked dead.
1859  if (RegInfo->isSuperRegister(Reg, MOReg))
1860  return true;
1861  if (RegInfo->isSubRegister(Reg, MOReg))
1862  DeadOps.push_back(i);
1863  }
1864  }
1865 
1866  // Trim unneeded dead operands.
1867  while (!DeadOps.empty()) {
1868  unsigned OpIdx = DeadOps.back();
1869  if (getOperand(OpIdx).isImplicit() &&
1870  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1871  RemoveOperand(OpIdx);
1872  else
1873  getOperand(OpIdx).setIsDead(false);
1874  DeadOps.pop_back();
1875  }
1876 
1877  // If not found, this means an alias of one of the operands is dead. Add a
1878  // new implicit operand if required.
1879  if (Found || !AddIfNotFound)
1880  return Found;
1881 
1883  true /*IsDef*/,
1884  true /*IsImp*/,
1885  false /*IsKill*/,
1886  true /*IsDead*/));
1887  return true;
1888 }
1889 
1891  for (MachineOperand &MO : operands()) {
1892  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1893  continue;
1894  MO.setIsDead(false);
1895  }
1896 }
1897 
1898 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
1899  for (MachineOperand &MO : operands()) {
1900  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1901  continue;
1902  MO.setIsUndef(IsUndef);
1903  }
1904 }
1905 
1907  const TargetRegisterInfo *RegInfo) {
1909  MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1910  if (MO)
1911  return;
1912  } else {
1913  for (const MachineOperand &MO : operands()) {
1914  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1915  MO.getSubReg() == 0)
1916  return;
1917  }
1918  }
1920  true /*IsDef*/,
1921  true /*IsImp*/));
1922 }
1923 
1925  const TargetRegisterInfo &TRI) {
1926  bool HasRegMask = false;
1927  for (MachineOperand &MO : operands()) {
1928  if (MO.isRegMask()) {
1929  HasRegMask = true;
1930  continue;
1931  }
1932  if (!MO.isReg() || !MO.isDef()) continue;
1933  unsigned Reg = MO.getReg();
1934  if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1935  // If there are no uses, including partial uses, the def is dead.
1936  if (llvm::none_of(UsedRegs,
1937  [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1938  MO.setIsDead();
1939  }
1940 
1941  // This is a call with a register mask operand.
1942  // Mask clobbers are always dead, so add defs for the non-dead defines.
1943  if (HasRegMask)
1944  for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1945  I != E; ++I)
1946  addRegisterDefined(*I, &TRI);
1947 }
1948 
1949 unsigned
1951  // Build up a buffer of hash code components.
1952  SmallVector<size_t, 8> HashComponents;
1953  HashComponents.reserve(MI->getNumOperands() + 1);
1954  HashComponents.push_back(MI->getOpcode());
1955  for (const MachineOperand &MO : MI->operands()) {
1956  if (MO.isReg() && MO.isDef() &&
1958  continue; // Skip virtual register defs.
1959 
1960  HashComponents.push_back(hash_value(MO));
1961  }
1962  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1963 }
1964 
1966  // Find the source location cookie.
1967  unsigned LocCookie = 0;
1968  const MDNode *LocMD = nullptr;
1969  for (unsigned i = getNumOperands(); i != 0; --i) {
1970  if (getOperand(i-1).isMetadata() &&
1971  (LocMD = getOperand(i-1).getMetadata()) &&
1972  LocMD->getNumOperands() != 0) {
1973  if (const ConstantInt *CI =
1974  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1975  LocCookie = CI->getZExtValue();
1976  break;
1977  }
1978  }
1979  }
1980 
1981  if (const MachineBasicBlock *MBB = getParent())
1982  if (const MachineFunction *MF = MBB->getParent())
1983  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1984  report_fatal_error(Msg);
1985 }
1986 
1988  const MCInstrDesc &MCID, bool IsIndirect,
1989  unsigned Reg, const MDNode *Variable,
1990  const MDNode *Expr) {
1991  assert(isa<DILocalVariable>(Variable) && "not a variable");
1992  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
1993  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
1994  "Expected inlined-at fields to agree");
1995  auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
1996  if (IsIndirect)
1997  MIB.addImm(0U);
1998  else
1999  MIB.addReg(0U, RegState::Debug);
2000  return MIB.addMetadata(Variable).addMetadata(Expr);
2001 }
2002 
2004  const MCInstrDesc &MCID, bool IsIndirect,
2005  MachineOperand &MO, const MDNode *Variable,
2006  const MDNode *Expr) {
2007  assert(isa<DILocalVariable>(Variable) && "not a variable");
2008  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2009  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2010  "Expected inlined-at fields to agree");
2011  if (MO.isReg())
2012  return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2013 
2014  auto MIB = BuildMI(MF, DL, MCID).add(MO);
2015  if (IsIndirect)
2016  MIB.addImm(0U);
2017  else
2018  MIB.addReg(0U, RegState::Debug);
2019  return MIB.addMetadata(Variable).addMetadata(Expr);
2020  }
2021 
2024  const DebugLoc &DL, const MCInstrDesc &MCID,
2025  bool IsIndirect, unsigned Reg,
2026  const MDNode *Variable, const MDNode *Expr) {
2027  MachineFunction &MF = *BB.getParent();
2028  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2029  BB.insert(I, MI);
2030  return MachineInstrBuilder(MF, MI);
2031 }
2032 
2035  const DebugLoc &DL, const MCInstrDesc &MCID,
2036  bool IsIndirect, MachineOperand &MO,
2037  const MDNode *Variable, const MDNode *Expr) {
2038  MachineFunction &MF = *BB.getParent();
2039  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2040  BB.insert(I, MI);
2041  return MachineInstrBuilder(MF, *MI);
2042 }
2043 
2044 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2045 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2047  assert(MI.getOperand(0).isReg() && "can't spill non-register");
2049  "Expected inlined-at fields to agree");
2050 
2051  const DIExpression *Expr = MI.getDebugExpression();
2052  if (MI.isIndirectDebugValue()) {
2053  assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
2055  }
2056  return Expr;
2057 }
2058 
2061  const MachineInstr &Orig,
2062  int FrameIndex) {
2063  const DIExpression *Expr = computeExprForSpill(Orig);
2064  return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2065  .addFrameIndex(FrameIndex)
2066  .addImm(0U)
2067  .addMetadata(Orig.getDebugVariable())
2068  .addMetadata(Expr);
2069 }
2070 
2072  const DIExpression *Expr = computeExprForSpill(Orig);
2073  Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
2074  Orig.getOperand(1).ChangeToImmediate(0U);
2075  Orig.getOperand(3).setMetadata(Expr);
2076 }
2077 
2079  SmallVectorImpl<MachineInstr *> &DbgValues) {
2080  MachineInstr &MI = *this;
2081  if (!MI.getOperand(0).isReg())
2082  return;
2083 
2084  MachineBasicBlock::iterator DI = MI; ++DI;
2085  for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2086  DI != DE; ++DI) {
2087  if (!DI->isDebugValue())
2088  return;
2089  if (DI->getOperand(0).isReg() &&
2090  DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2091  DbgValues.push_back(&*DI);
2092  }
2093 }
2094 
2096  // Collect matching debug values.
2098  collectDebugValues(DbgValues);
2099 
2100  // Propagate Reg to debug value instructions.
2101  for (auto *DBI : DbgValues)
2102  DBI->getOperand(0).setReg(Reg);
2103 }
static bool isReg(const MCInst &MI, unsigned OpNo)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
static bool Check(DecodeStatus &Out, DecodeStatus In)
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:527
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void bundleWithPred()
Bundle this instruction with its predecessor.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
bool isUnordered() const
Returns true if this memory operation doesn&#39;t have any ordering constraints other than normal aliasin...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs...
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool hasRegisterImplicitUseOperand(unsigned Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool isDebugLabel() const
Definition: MachineInstr.h:998
void collectDebugValues(SmallVectorImpl< MachineInstr *> &DbgValues)
Scan instructions following MI and collect any matching DBG_VALUEs.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:633
bool noNaNs() const
Definition: Operator.h:200
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:549
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
This class represents lattice values for constants.
Definition: AllocatorList.h:24
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:465
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
iterator begin() const
Definition: ArrayRef.h:137
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static const DIExpression * computeExprForSpill(const MachineInstr &MI)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value...
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
bool isCFIInstruction() const
Definition: MachineInstr.h:990
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:362
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:524
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
This file contains the declarations for metadata subclasses.
unsigned getSubReg() const
bool isInlineAsm() const
The two locations do not alias at all.
Definition: AliasAnalysis.h:84
bool noInfs() const
Definition: Operator.h:201
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:864
void setIsDead(bool Val=true)
F(f)
MachineModuleInfo & getMMI() const
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1069
Manage lifetime of a slot tracker for printing IR.
void reserve(size_type N)
Definition: SmallVector.h:376
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:459
bool isPHI() const
void print(raw_ostream &OS) const
prints source location /path/to/file.exe:line:col @[inlined at]
Definition: DebugLoc.cpp:119
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:276
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:342
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static DIExpression * prepend(const DIExpression *Expr, bool DerefBefore, int64_t Offset=0, bool DerefAfter=false, bool StackValue=false)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
void clearKillInfo()
Clears kill flags on all operands.
AliasResult alias(const MemoryLocation &LocA, const MemoryLocation &LocB)
The main low level interface to the alias analysis implementation.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
A description of a memory reference used in the backend.
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:211
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:366
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:244
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1200
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:649
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
void bundleWithSucc()
Bundle this instruction with its successor.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand *> MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr)
Allocate and construct an extra info structure for a MachineInstr.
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
void setIsEarlyClobber(bool Val=true)
void unbundleFromPred()
Break bundle above this instruction.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
bool isValid() const
isValid - Returns true until all the operands have been visited.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool isBundle() const
void changeDebugValuesDefReg(unsigned Reg)
Find all DBG_VALUEs immediately following this instruction that point to a register def in this instr...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4431
bool allowContract() const
Definition: Operator.h:204
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
virtual const TargetInstrInfo * getInstrInfo() const
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:93
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA)
Returns true if this instruction&#39;s memory access aliases the memory access of Other.
virtual bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn&#39;t ...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:555
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr&#39;s memory reference descriptor list.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
TargetInstrInfo - Interface to description of machine instruction set.
AliasResult
The possible results of an alias query.
Definition: AliasAnalysis.h:78
const Value * getValue() const
Return the base address of the memory access.
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
struct llvm::MachineOperand::@164::@166 Reg
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:820
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:546
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
unsigned const MachineRegisterInfo * MRI
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:516
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:235
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:129
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:429
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:174
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed...
Definition: Operator.h:120
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:300
MCRegAliasIterator enumerates all registers aliasing Reg.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:311
This file declares a class to represent arbitrary precision floating point values and provide a varie...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:549
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1193
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:329
bool isValid() const
const PseudoSourceValue * getPseudoValue() const
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl...
Definition: Operator.h:67
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:325
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool allowReciprocal() const
Definition: Operator.h:203
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:308
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can&#39;t be determined by the instruction&#39;s descr...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:193
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:841
bool isStackAligningInlineAsm() const
static unsigned getHashValue(const MachineInstr *const &MI)
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:277
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
size_t size() const
Definition: SmallVector.h:53
bool isDebugInstr() const
Definition: MachineInstr.h:999
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:567
void eraseFromBundle()
Unlink &#39;this&#39; form its basic block and delete it.
void setIsKill(bool Val=true)
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
TargetIntrinsicInfo - Interface to description of machine instruction set.
SmallBitVector & set()
Representation for a specific memory location.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:188
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr&#39;s memory reference descriptor list and replace ours with it...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Iterator for intrusive lists based on ilist_node.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
InlineAsm::AsmDialect getInlineAsmDialect() const
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:534
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
void setFlags(unsigned flags)
Definition: MachineInstr.h:304
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
bool isDebugValue() const
Definition: MachineInstr.h:997
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
Utility class for floating point operations which can have information about relaxed accuracy require...
Definition: Operator.h:240
Module.h This file contains the declarations for the Module class.
iterator end() const
Definition: ArrayRef.h:138
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:644
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:226
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:607
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
int64_t getImm() const
void setMetadata(const MDNode *MD)
DWARF expression.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
MCSymbol reference (for debug/eh info)
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:592
Special value supplied for machine level alias analysis.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:479
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
Definition: ArrayRef.h:179
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:394
const unsigned TiedMax
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:581
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:351
Representation of each machine instruction.
Definition: MachineInstr.h:64
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:133
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges. ...
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
This file provides utility analysis objects describing memory locations.
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr *> MIs)
Clone the merge of multiple MachineInstrs&#39; memory reference descriptors list and replace ours with it...
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
Definition: iterator.h:303
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand *> LHS, ArrayRef< MachineMemOperand *> RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
uint32_t Size
Definition: Profile.cpp:47
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isKill() const
const Module * getModule() const
MachineInstr * removeFromParent()
Unlink &#39;this&#39; from the containing basic block, and return it without deleting it. ...
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:290
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:807
bool memoperands_empty() const
Return true if we don&#39;t have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:546
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand *> MemRefs)
Assign this MachineInstr&#39;s memory reference descriptor list.
void unbundleFromSucc()
Break bundle below this instruction.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:566
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:73
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
bool isPosition() const
Definition: MachineInstr.h:995
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:175
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
bool allowReassoc() const
Flag queries.
Definition: Operator.h:199
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:160
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool approxFunc() const
Definition: Operator.h:205
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1075
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:295
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
const MDNode * getMetadata() const
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:173
bool noSignedZeros() const
Definition: Operator.h:202
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:541
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
bool isImplicit() const
Metadata reference (for debug info)
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:70
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.