LLVM  9.0.0svn
MachineInstr.cpp
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1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Methods common to all machine instructions.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/FoldingSet.h"
17 #include "llvm/ADT/Hashing.h"
18 #include "llvm/ADT/None.h"
19 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/Analysis/Loads.h"
40 #include "llvm/Config/llvm-config.h"
41 #include "llvm/IR/Constants.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Metadata.h"
51 #include "llvm/IR/Module.h"
53 #include "llvm/IR/Operator.h"
54 #include "llvm/IR/Type.h"
55 #include "llvm/IR/Value.h"
56 #include "llvm/MC/MCInstrDesc.h"
57 #include "llvm/MC/MCRegisterInfo.h"
58 #include "llvm/MC/MCSymbol.h"
59 #include "llvm/Support/Casting.h"
61 #include "llvm/Support/Compiler.h"
62 #include "llvm/Support/Debug.h"
69 #include <algorithm>
70 #include <cassert>
71 #include <cstddef>
72 #include <cstdint>
73 #include <cstring>
74 #include <iterator>
75 #include <utility>
76 
77 using namespace llvm;
78 
80  if (const MachineBasicBlock *MBB = MI.getParent())
81  if (const MachineFunction *MF = MBB->getParent())
82  return MF;
83  return nullptr;
84 }
85 
86 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
87 // it.
88 static void tryToGetTargetInfo(const MachineInstr &MI,
89  const TargetRegisterInfo *&TRI,
90  const MachineRegisterInfo *&MRI,
91  const TargetIntrinsicInfo *&IntrinsicInfo,
92  const TargetInstrInfo *&TII) {
93 
94  if (const MachineFunction *MF = getMFIfAvailable(MI)) {
95  TRI = MF->getSubtarget().getRegisterInfo();
96  MRI = &MF->getRegInfo();
97  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
98  TII = MF->getSubtarget().getInstrInfo();
99  }
100 }
101 
103  if (MCID->ImplicitDefs)
104  for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
105  ++ImpDefs)
106  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
107  if (MCID->ImplicitUses)
108  for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
109  ++ImpUses)
110  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
111 }
112 
113 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
114 /// implicit operands. It reserves space for the number of operands specified by
115 /// the MCInstrDesc.
116 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
117  DebugLoc dl, bool NoImp)
118  : MCID(&tid), debugLoc(std::move(dl)) {
119  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
120 
121  // Reserve space for the expected number of operands.
122  if (unsigned NumOps = MCID->getNumOperands() +
123  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
124  CapOperands = OperandCapacity::get(NumOps);
125  Operands = MF.allocateOperandArray(CapOperands);
126  }
127 
128  if (!NoImp)
130 }
131 
132 /// MachineInstr ctor - Copies MachineInstr arg exactly
133 ///
134 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
135  : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) {
136  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
137 
138  CapOperands = OperandCapacity::get(MI.getNumOperands());
139  Operands = MF.allocateOperandArray(CapOperands);
140 
141  // Copy operands.
142  for (const MachineOperand &MO : MI.operands())
143  addOperand(MF, MO);
144 
145  // Copy all the sensible flags.
146  setFlags(MI.Flags);
147 }
148 
149 /// getRegInfo - If this instruction is embedded into a MachineFunction,
150 /// return the MachineRegisterInfo object for the current function, otherwise
151 /// return null.
152 MachineRegisterInfo *MachineInstr::getRegInfo() {
153  if (MachineBasicBlock *MBB = getParent())
154  return &MBB->getParent()->getRegInfo();
155  return nullptr;
156 }
157 
158 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
159 /// this instruction from their respective use lists. This requires that the
160 /// operands already be on their use lists.
161 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
162  for (MachineOperand &MO : operands())
163  if (MO.isReg())
165 }
166 
167 /// AddRegOperandsToUseLists - Add all of the register operands in
168 /// this instruction from their respective use lists. This requires that the
169 /// operands not be on their use lists yet.
170 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
171  for (MachineOperand &MO : operands())
172  if (MO.isReg())
173  MRI.addRegOperandToUseList(&MO);
174 }
175 
177  MachineBasicBlock *MBB = getParent();
178  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
179  MachineFunction *MF = MBB->getParent();
180  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
181  addOperand(*MF, Op);
182 }
183 
184 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
185 /// ranges. If MRI is non-null also update use-def chains.
187  unsigned NumOps, MachineRegisterInfo *MRI) {
188  if (MRI)
189  return MRI->moveOperands(Dst, Src, NumOps);
190 
191  // MachineOperand is a trivially copyable type so we can just use memmove.
192  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
193 }
194 
195 /// addOperand - Add the specified operand to the instruction. If it is an
196 /// implicit operand, it is added to the end of the operand list. If it is
197 /// an explicit operand it is added at the end of the explicit operand list
198 /// (before the first implicit operand).
200  assert(MCID && "Cannot add operands before providing an instr descriptor");
201 
202  // Check if we're adding one of our existing operands.
203  if (&Op >= Operands && &Op < Operands + NumOperands) {
204  // This is unusual: MI->addOperand(MI->getOperand(i)).
205  // If adding Op requires reallocating or moving existing operands around,
206  // the Op reference could go stale. Support it by copying Op.
207  MachineOperand CopyOp(Op);
208  return addOperand(MF, CopyOp);
209  }
210 
211  // Find the insert location for the new operand. Implicit registers go at
212  // the end, everything else goes before the implicit regs.
213  //
214  // FIXME: Allow mixed explicit and implicit operands on inline asm.
215  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
216  // implicit-defs, but they must not be moved around. See the FIXME in
217  // InstrEmitter.cpp.
218  unsigned OpNo = getNumOperands();
219  bool isImpReg = Op.isReg() && Op.isImplicit();
220  if (!isImpReg && !isInlineAsm()) {
221  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
222  --OpNo;
223  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
224  }
225  }
226 
227 #ifndef NDEBUG
228  bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
230  // OpNo now points as the desired insertion point. Unless this is a variadic
231  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
232  // RegMask operands go between the explicit and implicit operands.
233  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
234  OpNo < MCID->getNumOperands() || isDebugOp) &&
235  "Trying to add an operand to a machine instr that is already done!");
236 #endif
237 
238  MachineRegisterInfo *MRI = getRegInfo();
239 
240  // Determine if the Operands array needs to be reallocated.
241  // Save the old capacity and operand array.
242  OperandCapacity OldCap = CapOperands;
243  MachineOperand *OldOperands = Operands;
244  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
245  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
246  Operands = MF.allocateOperandArray(CapOperands);
247  // Move the operands before the insertion point.
248  if (OpNo)
249  moveOperands(Operands, OldOperands, OpNo, MRI);
250  }
251 
252  // Move the operands following the insertion point.
253  if (OpNo != NumOperands)
254  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
255  MRI);
256  ++NumOperands;
257 
258  // Deallocate the old operand array.
259  if (OldOperands != Operands && OldOperands)
260  MF.deallocateOperandArray(OldCap, OldOperands);
261 
262  // Copy Op into place. It still needs to be inserted into the MRI use lists.
263  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
264  NewMO->ParentMI = this;
265 
266  // When adding a register operand, tell MRI about it.
267  if (NewMO->isReg()) {
268  // Ensure isOnRegUseList() returns false, regardless of Op's status.
269  NewMO->Contents.Reg.Prev = nullptr;
270  // Ignore existing ties. This is not a property that can be copied.
271  NewMO->TiedTo = 0;
272  // Add the new operand to MRI, but only for instructions in an MBB.
273  if (MRI)
274  MRI->addRegOperandToUseList(NewMO);
275  // The MCID operand information isn't accurate until we start adding
276  // explicit operands. The implicit operands are added first, then the
277  // explicits are inserted before them.
278  if (!isImpReg) {
279  // Tie uses to defs as indicated in MCInstrDesc.
280  if (NewMO->isUse()) {
281  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
282  if (DefIdx != -1)
283  tieOperands(DefIdx, OpNo);
284  }
285  // If the register operand is flagged as early, mark the operand as such.
286  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
287  NewMO->setIsEarlyClobber(true);
288  }
289  }
290 }
291 
292 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
293 /// fewer operand than it started with.
294 ///
295 void MachineInstr::RemoveOperand(unsigned OpNo) {
296  assert(OpNo < getNumOperands() && "Invalid operand number");
297  untieRegOperand(OpNo);
298 
299 #ifndef NDEBUG
300  // Moving tied operands would break the ties.
301  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
302  if (Operands[i].isReg())
303  assert(!Operands[i].isTied() && "Cannot move tied operands");
304 #endif
305 
306  MachineRegisterInfo *MRI = getRegInfo();
307  if (MRI && Operands[OpNo].isReg())
308  MRI->removeRegOperandFromUseList(Operands + OpNo);
309 
310  // Don't call the MachineOperand destructor. A lot of this code depends on
311  // MachineOperand having a trivial destructor anyway, and adding a call here
312  // wouldn't make it 'destructor-correct'.
313 
314  if (unsigned N = NumOperands - 1 - OpNo)
315  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
316  --NumOperands;
317 }
318 
320  if (memoperands_empty())
321  return;
322 
323  // See if we can just drop all of our extra info.
324  if (!getPreInstrSymbol() && !getPostInstrSymbol()) {
325  Info.clear();
326  return;
327  }
328  if (!getPostInstrSymbol()) {
329  Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
330  return;
331  }
332  if (!getPreInstrSymbol()) {
333  Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
334  return;
335  }
336 
337  // Otherwise allocate a fresh extra info with just these symbols.
338  Info.set<EIIK_OutOfLine>(
340 }
341 
344  if (MMOs.empty()) {
345  dropMemRefs(MF);
346  return;
347  }
348 
349  // Try to store a single MMO inline.
350  if (MMOs.size() == 1 && !getPreInstrSymbol() && !getPostInstrSymbol()) {
351  Info.set<EIIK_MMO>(MMOs[0]);
352  return;
353  }
354 
355  // Otherwise create an extra info struct with all of our info.
356  Info.set<EIIK_OutOfLine>(
358 }
359 
361  MachineMemOperand *MO) {
364  MMOs.push_back(MO);
365  setMemRefs(MF, MMOs);
366 }
367 
369  if (this == &MI)
370  // Nothing to do for a self-clone!
371  return;
372 
373  assert(&MF == MI.getMF() &&
374  "Invalid machine functions when cloning memory refrences!");
375  // See if we can just steal the extra info already allocated for the
376  // instruction. We can do this whenever the pre- and post-instruction symbols
377  // are the same (including null).
378  if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
380  Info = MI.Info;
381  return;
382  }
383 
384  // Otherwise, fall back on a copy-based clone.
385  setMemRefs(MF, MI.memoperands());
386 }
387 
388 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
389 /// identical.
392  if (LHS.size() != RHS.size())
393  return false;
394 
395  auto LHSPointees = make_pointee_range(LHS);
396  auto RHSPointees = make_pointee_range(RHS);
397  return std::equal(LHSPointees.begin(), LHSPointees.end(),
398  RHSPointees.begin());
399 }
400 
403  // Try handling easy numbers of MIs with simpler mechanisms.
404  if (MIs.empty()) {
405  dropMemRefs(MF);
406  return;
407  }
408  if (MIs.size() == 1) {
409  cloneMemRefs(MF, *MIs[0]);
410  return;
411  }
412  // Because an empty memoperands list provides *no* information and must be
413  // handled conservatively (assuming the instruction can do anything), the only
414  // way to merge with it is to drop all other memoperands.
415  if (MIs[0]->memoperands_empty()) {
416  dropMemRefs(MF);
417  return;
418  }
419 
420  // Handle the general case.
422  // Start with the first instruction.
423  assert(&MF == MIs[0]->getMF() &&
424  "Invalid machine functions when cloning memory references!");
425  MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
426  // Now walk all the other instructions and accumulate any different MMOs.
427  for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
428  assert(&MF == MI.getMF() &&
429  "Invalid machine functions when cloning memory references!");
430 
431  // Skip MIs with identical operands to the first. This is a somewhat
432  // arbitrary hack but will catch common cases without being quadratic.
433  // TODO: We could fully implement merge semantics here if needed.
434  if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
435  continue;
436 
437  // Because an empty memoperands list provides *no* information and must be
438  // handled conservatively (assuming the instruction can do anything), the
439  // only way to merge with it is to drop all other memoperands.
440  if (MI.memoperands_empty()) {
441  dropMemRefs(MF);
442  return;
443  }
444 
445  // Otherwise accumulate these into our temporary buffer of the merged state.
446  MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
447  }
448 
449  setMemRefs(MF, MergedMMOs);
450 }
451 
453  MCSymbol *OldSymbol = getPreInstrSymbol();
454  if (OldSymbol == Symbol)
455  return;
456  if (OldSymbol && !Symbol) {
457  // We're removing a symbol rather than adding one. Try to clean up any
458  // extra info carried around.
459  if (Info.is<EIIK_PreInstrSymbol>()) {
460  Info.clear();
461  return;
462  }
463 
464  if (memoperands_empty()) {
466  "Should never have only a single symbol allocated out-of-line!");
467  Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
468  return;
469  }
470 
471  // Otherwise fallback on the generic update.
472  } else if (!Info || Info.is<EIIK_PreInstrSymbol>()) {
473  // If we don't have any other extra info, we can store this inline.
474  Info.set<EIIK_PreInstrSymbol>(Symbol);
475  return;
476  }
477 
478  // Otherwise, allocate a full new set of extra info.
479  // FIXME: Maybe we should make the symbols in the extra info mutable?
480  Info.set<EIIK_OutOfLine>(
482 }
483 
485  MCSymbol *OldSymbol = getPostInstrSymbol();
486  if (OldSymbol == Symbol)
487  return;
488  if (OldSymbol && !Symbol) {
489  // We're removing a symbol rather than adding one. Try to clean up any
490  // extra info carried around.
491  if (Info.is<EIIK_PostInstrSymbol>()) {
492  Info.clear();
493  return;
494  }
495 
496  if (memoperands_empty()) {
498  "Should never have only a single symbol allocated out-of-line!");
499  Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
500  return;
501  }
502 
503  // Otherwise fallback on the generic update.
504  } else if (!Info || Info.is<EIIK_PostInstrSymbol>()) {
505  // If we don't have any other extra info, we can store this inline.
506  Info.set<EIIK_PostInstrSymbol>(Symbol);
507  return;
508  }
509 
510  // Otherwise, allocate a full new set of extra info.
511  // FIXME: Maybe we should make the symbols in the extra info mutable?
512  Info.set<EIIK_OutOfLine>(
514 }
515 
517  const MachineInstr &MI) {
518  if (this == &MI)
519  // Nothing to do for a self-clone!
520  return;
521 
522  assert(&MF == MI.getMF() &&
523  "Invalid machine functions when cloning instruction symbols!");
524 
527 }
528 
529 uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
530  // For now, the just return the union of the flags. If the flags get more
531  // complicated over time, we might need more logic here.
532  return getFlags() | Other.getFlags();
533 }
534 
536  uint16_t MIFlags = 0;
537  // Copy the wrapping flags.
538  if (const OverflowingBinaryOperator *OB =
539  dyn_cast<OverflowingBinaryOperator>(&I)) {
540  if (OB->hasNoSignedWrap())
541  MIFlags |= MachineInstr::MIFlag::NoSWrap;
542  if (OB->hasNoUnsignedWrap())
543  MIFlags |= MachineInstr::MIFlag::NoUWrap;
544  }
545 
546  // Copy the exact flag.
547  if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
548  if (PE->isExact())
549  MIFlags |= MachineInstr::MIFlag::IsExact;
550 
551  // Copy the fast-math flags.
552  if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
553  const FastMathFlags Flags = FP->getFastMathFlags();
554  if (Flags.noNaNs())
555  MIFlags |= MachineInstr::MIFlag::FmNoNans;
556  if (Flags.noInfs())
557  MIFlags |= MachineInstr::MIFlag::FmNoInfs;
558  if (Flags.noSignedZeros())
559  MIFlags |= MachineInstr::MIFlag::FmNsz;
560  if (Flags.allowReciprocal())
561  MIFlags |= MachineInstr::MIFlag::FmArcp;
562  if (Flags.allowContract())
563  MIFlags |= MachineInstr::MIFlag::FmContract;
564  if (Flags.approxFunc())
565  MIFlags |= MachineInstr::MIFlag::FmAfn;
566  if (Flags.allowReassoc())
567  MIFlags |= MachineInstr::MIFlag::FmReassoc;
568  }
569 
570  return MIFlags;
571 }
572 
574  Flags = copyFlagsFromInstruction(I);
575 }
576 
577 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
578  assert(!isBundledWithPred() && "Must be called on bundle header");
580  if (MII->getDesc().getFlags() & Mask) {
581  if (Type == AnyInBundle)
582  return true;
583  } else {
584  if (Type == AllInBundle && !MII->isBundle())
585  return false;
586  }
587  // This was the last instruction in the bundle.
588  if (!MII->isBundledWithSucc())
589  return Type == AllInBundle;
590  }
591 }
592 
594  MICheckType Check) const {
595  // If opcodes or number of operands are not the same then the two
596  // instructions are obviously not identical.
597  if (Other.getOpcode() != getOpcode() ||
598  Other.getNumOperands() != getNumOperands())
599  return false;
600 
601  if (isBundle()) {
602  // We have passed the test above that both instructions have the same
603  // opcode, so we know that both instructions are bundles here. Let's compare
604  // MIs inside the bundle.
605  assert(Other.isBundle() && "Expected that both instructions are bundles.");
608  // Loop until we analysed the last intruction inside at least one of the
609  // bundles.
610  while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
611  ++I1;
612  ++I2;
613  if (!I1->isIdenticalTo(*I2, Check))
614  return false;
615  }
616  // If we've reached the end of just one of the two bundles, but not both,
617  // the instructions are not identical.
618  if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
619  return false;
620  }
621 
622  // Check operands to make sure they match.
623  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
624  const MachineOperand &MO = getOperand(i);
625  const MachineOperand &OMO = Other.getOperand(i);
626  if (!MO.isReg()) {
627  if (!MO.isIdenticalTo(OMO))
628  return false;
629  continue;
630  }
631 
632  // Clients may or may not want to ignore defs when testing for equality.
633  // For example, machine CSE pass only cares about finding common
634  // subexpressions, so it's safe to ignore virtual register defs.
635  if (MO.isDef()) {
636  if (Check == IgnoreDefs)
637  continue;
638  else if (Check == IgnoreVRegDefs) {
641  if (!MO.isIdenticalTo(OMO))
642  return false;
643  } else {
644  if (!MO.isIdenticalTo(OMO))
645  return false;
646  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
647  return false;
648  }
649  } else {
650  if (!MO.isIdenticalTo(OMO))
651  return false;
652  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
653  return false;
654  }
655  }
656  // If DebugLoc does not match then two debug instructions are not identical.
657  if (isDebugInstr())
658  if (getDebugLoc() && Other.getDebugLoc() &&
659  getDebugLoc() != Other.getDebugLoc())
660  return false;
661  return true;
662 }
663 
665  return getParent()->getParent();
666 }
667 
669  assert(getParent() && "Not embedded in a basic block!");
670  return getParent()->remove(this);
671 }
672 
674  assert(getParent() && "Not embedded in a basic block!");
675  return getParent()->remove_instr(this);
676 }
677 
679  assert(getParent() && "Not embedded in a basic block!");
680  getParent()->erase(this);
681 }
682 
684  assert(getParent() && "Not embedded in a basic block!");
685  MachineBasicBlock *MBB = getParent();
686  MachineFunction *MF = MBB->getParent();
687  assert(MF && "Not embedded in a function!");
688 
689  MachineInstr *MI = (MachineInstr *)this;
690  MachineRegisterInfo &MRI = MF->getRegInfo();
691 
692  for (const MachineOperand &MO : MI->operands()) {
693  if (!MO.isReg() || !MO.isDef())
694  continue;
695  unsigned Reg = MO.getReg();
697  continue;
699  }
700  MI->eraseFromParent();
701 }
702 
704  assert(getParent() && "Not embedded in a basic block!");
705  getParent()->erase_instr(this);
706 }
707 
709  unsigned NumOperands = MCID->getNumOperands();
710  if (!MCID->isVariadic())
711  return NumOperands;
712 
713  for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
714  const MachineOperand &MO = getOperand(I);
715  // The operands must always be in the following order:
716  // - explicit reg defs,
717  // - other explicit operands (reg uses, immediates, etc.),
718  // - implicit reg defs
719  // - implicit reg uses
720  if (MO.isReg() && MO.isImplicit())
721  break;
722  ++NumOperands;
723  }
724  return NumOperands;
725 }
726 
728  unsigned NumDefs = MCID->getNumDefs();
729  if (!MCID->isVariadic())
730  return NumDefs;
731 
732  for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
733  const MachineOperand &MO = getOperand(I);
734  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
735  break;
736  ++NumDefs;
737  }
738  return NumDefs;
739 }
740 
742  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
745  --Pred;
746  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
747  Pred->setFlag(BundledSucc);
748 }
749 
751  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
754  ++Succ;
755  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
756  Succ->setFlag(BundledPred);
757 }
758 
760  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
763  --Pred;
764  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
765  Pred->clearFlag(BundledSucc);
766 }
767 
769  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
772  ++Succ;
773  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
774  Succ->clearFlag(BundledPred);
775 }
776 
778  if (isInlineAsm()) {
779  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
780  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
781  return true;
782  }
783  return false;
784 }
785 
787  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
788  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
789  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
790 }
791 
793  unsigned *GroupNo) const {
794  assert(isInlineAsm() && "Expected an inline asm instruction");
795  assert(OpIdx < getNumOperands() && "OpIdx out of range");
796 
797  // Ignore queries about the initial operands.
798  if (OpIdx < InlineAsm::MIOp_FirstOperand)
799  return -1;
800 
801  unsigned Group = 0;
802  unsigned NumOps;
803  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
804  i += NumOps) {
805  const MachineOperand &FlagMO = getOperand(i);
806  // If we reach the implicit register operands, stop looking.
807  if (!FlagMO.isImm())
808  return -1;
809  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
810  if (i + NumOps > OpIdx) {
811  if (GroupNo)
812  *GroupNo = Group;
813  return i;
814  }
815  ++Group;
816  }
817  return -1;
818 }
819 
821  assert(isDebugLabel() && "not a DBG_LABEL");
822  return cast<DILabel>(getOperand(0).getMetadata());
823 }
824 
826  assert(isDebugValue() && "not a DBG_VALUE");
827  return cast<DILocalVariable>(getOperand(2).getMetadata());
828 }
829 
831  assert(isDebugValue() && "not a DBG_VALUE");
832  return cast<DIExpression>(getOperand(3).getMetadata());
833 }
834 
835 const TargetRegisterClass*
837  const TargetInstrInfo *TII,
838  const TargetRegisterInfo *TRI) const {
839  assert(getParent() && "Can't have an MBB reference here!");
840  assert(getMF() && "Can't have an MF reference here!");
841  const MachineFunction &MF = *getMF();
842 
843  // Most opcodes have fixed constraints in their MCInstrDesc.
844  if (!isInlineAsm())
845  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
846 
847  if (!getOperand(OpIdx).isReg())
848  return nullptr;
849 
850  // For tied uses on inline asm, get the constraint from the def.
851  unsigned DefIdx;
852  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
853  OpIdx = DefIdx;
854 
855  // Inline asm stores register class constraints in the flag word.
856  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
857  if (FlagIdx < 0)
858  return nullptr;
859 
860  unsigned Flag = getOperand(FlagIdx).getImm();
861  unsigned RCID;
866  return TRI->getRegClass(RCID);
867 
868  // Assume that all registers in a memory operand are pointers.
870  return TRI->getPointerRegClass(MF);
871 
872  return nullptr;
873 }
874 
876  unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
877  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
878  // Check every operands inside the bundle if we have
879  // been asked to.
880  if (ExploreBundle)
881  for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
882  ++OpndIt)
883  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
884  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
885  else
886  // Otherwise, just check the current operands.
887  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
888  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
889  return CurRC;
890 }
891 
892 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
893  unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
894  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
895  assert(CurRC && "Invalid initial register class");
896  // Check if Reg is constrained by some of its use/def from MI.
897  const MachineOperand &MO = getOperand(OpIdx);
898  if (!MO.isReg() || MO.getReg() != Reg)
899  return CurRC;
900  // If yes, accumulate the constraints through the operand.
901  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
902 }
903 
905  unsigned OpIdx, const TargetRegisterClass *CurRC,
906  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
907  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
908  const MachineOperand &MO = getOperand(OpIdx);
909  assert(MO.isReg() &&
910  "Cannot get register constraints for non-register operand");
911  assert(CurRC && "Invalid initial register class");
912  if (unsigned SubIdx = MO.getSubReg()) {
913  if (OpRC)
914  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
915  else
916  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
917  } else if (OpRC)
918  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
919  return CurRC;
920 }
921 
922 /// Return the number of instructions inside the MI bundle, not counting the
923 /// header instruction.
924 unsigned MachineInstr::getBundleSize() const {
926  unsigned Size = 0;
927  while (I->isBundledWithSucc()) {
928  ++Size;
929  ++I;
930  }
931  return Size;
932 }
933 
934 /// Returns true if the MachineInstr has an implicit-use operand of exactly
935 /// the given register (not considering sub/super-registers).
937  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
938  const MachineOperand &MO = getOperand(i);
939  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
940  return true;
941  }
942  return false;
943 }
944 
945 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
946 /// the specific register or -1 if it is not found. It further tightens
947 /// the search criteria to a use that kills the register if isKill is true.
949  unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
950  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
951  const MachineOperand &MO = getOperand(i);
952  if (!MO.isReg() || !MO.isUse())
953  continue;
954  unsigned MOReg = MO.getReg();
955  if (!MOReg)
956  continue;
957  if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
958  if (!isKill || MO.isKill())
959  return i;
960  }
961  return -1;
962 }
963 
964 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
965 /// indicating if this instruction reads or writes Reg. This also considers
966 /// partial defines.
967 std::pair<bool,bool>
969  SmallVectorImpl<unsigned> *Ops) const {
970  bool PartDef = false; // Partial redefine.
971  bool FullDef = false; // Full define.
972  bool Use = false;
973 
974  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
975  const MachineOperand &MO = getOperand(i);
976  if (!MO.isReg() || MO.getReg() != Reg)
977  continue;
978  if (Ops)
979  Ops->push_back(i);
980  if (MO.isUse())
981  Use |= !MO.isUndef();
982  else if (MO.getSubReg() && !MO.isUndef())
983  // A partial def undef doesn't count as reading the register.
984  PartDef = true;
985  else
986  FullDef = true;
987  }
988  // A partial redefine uses Reg unless there is also a full define.
989  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
990 }
991 
992 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
993 /// the specified register or -1 if it is not found. If isDead is true, defs
994 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
995 /// also checks if there is a def of a super-register.
996 int
997 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
998  const TargetRegisterInfo *TRI) const {
999  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1000  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1001  const MachineOperand &MO = getOperand(i);
1002  // Accept regmask operands when Overlap is set.
1003  // Ignore them when looking for a specific def operand (Overlap == false).
1004  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1005  return i;
1006  if (!MO.isReg() || !MO.isDef())
1007  continue;
1008  unsigned MOReg = MO.getReg();
1009  bool Found = (MOReg == Reg);
1010  if (!Found && TRI && isPhys &&
1012  if (Overlap)
1013  Found = TRI->regsOverlap(MOReg, Reg);
1014  else
1015  Found = TRI->isSubRegister(MOReg, Reg);
1016  }
1017  if (Found && (!isDead || MO.isDead()))
1018  return i;
1019  }
1020  return -1;
1021 }
1022 
1023 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1024 /// operand list that is used to represent the predicate. It returns -1 if
1025 /// none is found.
1027  // Don't call MCID.findFirstPredOperandIdx() because this variant
1028  // is sometimes called on an instruction that's not yet complete, and
1029  // so the number of operands is less than the MCID indicates. In
1030  // particular, the PTX target does this.
1031  const MCInstrDesc &MCID = getDesc();
1032  if (MCID.isPredicable()) {
1033  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1034  if (MCID.OpInfo[i].isPredicate())
1035  return i;
1036  }
1037 
1038  return -1;
1039 }
1040 
1041 // MachineOperand::TiedTo is 4 bits wide.
1042 const unsigned TiedMax = 15;
1043 
1044 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1045 ///
1046 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1047 /// field. TiedTo can have these values:
1048 ///
1049 /// 0: Operand is not tied to anything.
1050 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1051 /// TiedMax: Tied to an operand >= TiedMax-1.
1052 ///
1053 /// The tied def must be one of the first TiedMax operands on a normal
1054 /// instruction. INLINEASM instructions allow more tied defs.
1055 ///
1056 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1057  MachineOperand &DefMO = getOperand(DefIdx);
1058  MachineOperand &UseMO = getOperand(UseIdx);
1059  assert(DefMO.isDef() && "DefIdx must be a def operand");
1060  assert(UseMO.isUse() && "UseIdx must be a use operand");
1061  assert(!DefMO.isTied() && "Def is already tied to another use");
1062  assert(!UseMO.isTied() && "Use is already tied to another def");
1063 
1064  if (DefIdx < TiedMax)
1065  UseMO.TiedTo = DefIdx + 1;
1066  else {
1067  // Inline asm can use the group descriptors to find tied operands, but on
1068  // normal instruction, the tied def must be within the first TiedMax
1069  // operands.
1070  assert(isInlineAsm() && "DefIdx out of range");
1071  UseMO.TiedTo = TiedMax;
1072  }
1073 
1074  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1075  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1076 }
1077 
1078 /// Given the index of a tied register operand, find the operand it is tied to.
1079 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1080 /// which must exist.
1081 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1082  const MachineOperand &MO = getOperand(OpIdx);
1083  assert(MO.isTied() && "Operand isn't tied");
1084 
1085  // Normally TiedTo is in range.
1086  if (MO.TiedTo < TiedMax)
1087  return MO.TiedTo - 1;
1088 
1089  // Uses on normal instructions can be out of range.
1090  if (!isInlineAsm()) {
1091  // Normal tied defs must be in the 0..TiedMax-1 range.
1092  if (MO.isUse())
1093  return TiedMax - 1;
1094  // MO is a def. Search for the tied use.
1095  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1096  const MachineOperand &UseMO = getOperand(i);
1097  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1098  return i;
1099  }
1100  llvm_unreachable("Can't find tied use");
1101  }
1102 
1103  // Now deal with inline asm by parsing the operand group descriptor flags.
1104  // Find the beginning of each operand group.
1105  SmallVector<unsigned, 8> GroupIdx;
1106  unsigned OpIdxGroup = ~0u;
1107  unsigned NumOps;
1108  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1109  i += NumOps) {
1110  const MachineOperand &FlagMO = getOperand(i);
1111  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1112  unsigned CurGroup = GroupIdx.size();
1113  GroupIdx.push_back(i);
1114  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1115  // OpIdx belongs to this operand group.
1116  if (OpIdx > i && OpIdx < i + NumOps)
1117  OpIdxGroup = CurGroup;
1118  unsigned TiedGroup;
1119  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1120  continue;
1121  // Operands in this group are tied to operands in TiedGroup which must be
1122  // earlier. Find the number of operands between the two groups.
1123  unsigned Delta = i - GroupIdx[TiedGroup];
1124 
1125  // OpIdx is a use tied to TiedGroup.
1126  if (OpIdxGroup == CurGroup)
1127  return OpIdx - Delta;
1128 
1129  // OpIdx is a def tied to this use group.
1130  if (OpIdxGroup == TiedGroup)
1131  return OpIdx + Delta;
1132  }
1133  llvm_unreachable("Invalid tied operand on inline asm");
1134 }
1135 
1136 /// clearKillInfo - Clears kill flags on all operands.
1137 ///
1139  for (MachineOperand &MO : operands()) {
1140  if (MO.isReg() && MO.isUse())
1141  MO.setIsKill(false);
1142  }
1143 }
1144 
1145 void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
1146  unsigned SubIdx,
1147  const TargetRegisterInfo &RegInfo) {
1149  if (SubIdx)
1150  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1151  for (MachineOperand &MO : operands()) {
1152  if (!MO.isReg() || MO.getReg() != FromReg)
1153  continue;
1154  MO.substPhysReg(ToReg, RegInfo);
1155  }
1156  } else {
1157  for (MachineOperand &MO : operands()) {
1158  if (!MO.isReg() || MO.getReg() != FromReg)
1159  continue;
1160  MO.substVirtReg(ToReg, SubIdx, RegInfo);
1161  }
1162  }
1163 }
1164 
1165 /// isSafeToMove - Return true if it is safe to move this instruction. If
1166 /// SawStore is set to true, it means that there is a store (or call) between
1167 /// the instruction's location and its intended destination.
1168 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1169  // Ignore stuff that we obviously can't move.
1170  //
1171  // Treat volatile loads as stores. This is not strictly necessary for
1172  // volatiles, but it is required for atomic loads. It is not allowed to move
1173  // a load across an atomic load with Ordering > Monotonic.
1174  if (mayStore() || isCall() || isPHI() ||
1175  (mayLoad() && hasOrderedMemoryRef())) {
1176  SawStore = true;
1177  return false;
1178  }
1179 
1180  if (isPosition() || isDebugInstr() || isTerminator() ||
1182  return false;
1183 
1184  // See if this instruction does a load. If so, we have to guarantee that the
1185  // loaded value doesn't change between the load and the its intended
1186  // destination. The check for isInvariantLoad gives the targe the chance to
1187  // classify the load as always returning a constant, e.g. a constant pool
1188  // load.
1190  // Otherwise, this is a real load. If there is a store between the load and
1191  // end of block, we can't move it.
1192  return !SawStore;
1193 
1194  return true;
1195 }
1196 
1198  bool UseTBAA) const {
1199  const MachineFunction *MF = getMF();
1200  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1201  const MachineFrameInfo &MFI = MF->getFrameInfo();
1202 
1203  // If neither instruction stores to memory, they can't alias in any
1204  // meaningful way, even if they read from the same address.
1205  if (!mayStore() && !Other.mayStore())
1206  return false;
1207 
1208  // Let the target decide if memory accesses cannot possibly overlap.
1209  if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
1210  return false;
1211 
1212  // FIXME: Need to handle multiple memory operands to support all targets.
1213  if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1214  return true;
1215 
1217  MachineMemOperand *MMOb = *Other.memoperands_begin();
1218 
1219  // The following interface to AA is fashioned after DAGCombiner::isAlias
1220  // and operates with MachineMemOperand offset with some important
1221  // assumptions:
1222  // - LLVM fundamentally assumes flat address spaces.
1223  // - MachineOperand offset can *only* result from legalization and
1224  // cannot affect queries other than the trivial case of overlap
1225  // checking.
1226  // - These offsets never wrap and never step outside
1227  // of allocated objects.
1228  // - There should never be any negative offsets here.
1229  //
1230  // FIXME: Modify API to hide this math from "user"
1231  // Even before we go to AA we can reason locally about some
1232  // memory objects. It can save compile time, and possibly catch some
1233  // corner cases not currently covered.
1234 
1235  int64_t OffsetA = MMOa->getOffset();
1236  int64_t OffsetB = MMOb->getOffset();
1237  int64_t MinOffset = std::min(OffsetA, OffsetB);
1238 
1239  uint64_t WidthA = MMOa->getSize();
1240  uint64_t WidthB = MMOb->getSize();
1241  bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1242  bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1243 
1244  const Value *ValA = MMOa->getValue();
1245  const Value *ValB = MMOb->getValue();
1246  bool SameVal = (ValA && ValB && (ValA == ValB));
1247  if (!SameVal) {
1248  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1249  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1250  if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1251  return false;
1252  if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1253  return false;
1254  if (PSVa && PSVb && (PSVa == PSVb))
1255  SameVal = true;
1256  }
1257 
1258  if (SameVal) {
1259  if (!KnownWidthA || !KnownWidthB)
1260  return true;
1261  int64_t MaxOffset = std::max(OffsetA, OffsetB);
1262  int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1263  return (MinOffset + LowWidth > MaxOffset);
1264  }
1265 
1266  if (!AA)
1267  return true;
1268 
1269  if (!ValA || !ValB)
1270  return true;
1271 
1272  assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1273  assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1274 
1275  int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
1277  int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
1279 
1280  AliasResult AAResult = AA->alias(
1281  MemoryLocation(ValA, OverlapA,
1282  UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1283  MemoryLocation(ValB, OverlapB,
1284  UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1285 
1286  return (AAResult != NoAlias);
1287 }
1288 
1289 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1290 /// or volatile memory reference, or if the information describing the memory
1291 /// reference is not available. Return false if it is known to have no ordered
1292 /// memory references.
1294  // An instruction known never to access memory won't have a volatile access.
1295  if (!mayStore() &&
1296  !mayLoad() &&
1297  !isCall() &&
1299  return false;
1300 
1301  // Otherwise, if the instruction has no memory reference information,
1302  // conservatively assume it wasn't preserved.
1303  if (memoperands_empty())
1304  return true;
1305 
1306  // Check if any of our memory operands are ordered.
1307  return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1308  return !MMO->isUnordered();
1309  });
1310 }
1311 
1312 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1313 /// trap and is loading from a location whose value is invariant across a run of
1314 /// this function.
1316  // If the instruction doesn't load at all, it isn't an invariant load.
1317  if (!mayLoad())
1318  return false;
1319 
1320  // If the instruction has lost its memoperands, conservatively assume that
1321  // it may not be an invariant load.
1322  if (memoperands_empty())
1323  return false;
1324 
1325  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1326 
1327  for (MachineMemOperand *MMO : memoperands()) {
1328  if (!MMO->isUnordered())
1329  // If the memory operand has ordering side effects, we can't move the
1330  // instruction. Such an instruction is technically an invariant load,
1331  // but the caller code would need updated to expect that.
1332  return false;
1333  if (MMO->isStore()) return false;
1334  if (MMO->isInvariant() && MMO->isDereferenceable())
1335  continue;
1336 
1337  // A load from a constant PseudoSourceValue is invariant.
1338  if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1339  if (PSV->isConstant(&MFI))
1340  continue;
1341 
1342  if (const Value *V = MMO->getValue()) {
1343  // If we have an AliasAnalysis, ask it whether the memory is constant.
1344  if (AA &&
1346  MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1347  continue;
1348  }
1349 
1350  // Otherwise assume conservatively.
1351  return false;
1352  }
1353 
1354  // Everything checks out.
1355  return true;
1356 }
1357 
1358 /// isConstantValuePHI - If the specified instruction is a PHI that always
1359 /// merges together the same virtual register, return the register, otherwise
1360 /// return 0.
1362  if (!isPHI())
1363  return 0;
1364  assert(getNumOperands() >= 3 &&
1365  "It's illegal to have a PHI without source operands");
1366 
1367  unsigned Reg = getOperand(1).getReg();
1368  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1369  if (getOperand(i).getReg() != Reg)
1370  return 0;
1371  return Reg;
1372 }
1373 
1376  return true;
1377  if (isInlineAsm()) {
1378  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1379  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1380  return true;
1381  }
1382 
1383  return false;
1384 }
1385 
1387  return mayStore() || isCall() || hasUnmodeledSideEffects();
1388 }
1389 
1390 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1391 ///
1393  for (const MachineOperand &MO : operands()) {
1394  if (!MO.isReg() || MO.isUse())
1395  continue;
1396  if (!MO.isDead())
1397  return false;
1398  }
1399  return true;
1400 }
1401 
1402 /// copyImplicitOps - Copy implicit register operands from specified
1403 /// instruction to this instruction.
1405  const MachineInstr &MI) {
1406  for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1407  i != e; ++i) {
1408  const MachineOperand &MO = MI.getOperand(i);
1409  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1410  addOperand(MF, MO);
1411  }
1412 }
1413 
1415  const MCInstrDesc &MCID = getDesc();
1416  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1417  const auto &Operand = getOperand(I);
1418  if (!Operand.isReg() || Operand.isDef())
1419  // Ignore the defined registers as MCID marks only the uses as tied.
1420  continue;
1421  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1422  int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1423  if (ExpectedTiedIdx != TiedIdx)
1424  return true;
1425  }
1426  return false;
1427 }
1428 
1429 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1430  const MachineRegisterInfo &MRI) const {
1431  const MachineOperand &Op = getOperand(OpIdx);
1432  if (!Op.isReg())
1433  return LLT{};
1434 
1435  if (isVariadic() || OpIdx >= getNumExplicitOperands())
1436  return MRI.getType(Op.getReg());
1437 
1438  auto &OpInfo = getDesc().OpInfo[OpIdx];
1439  if (!OpInfo.isGenericType())
1440  return MRI.getType(Op.getReg());
1441 
1442  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1443  return LLT{};
1444 
1445  LLT TypeToPrint = MRI.getType(Op.getReg());
1446  // Don't mark the type index printed if it wasn't actually printed: maybe
1447  // another operand with the same type index has an actual type attached:
1448  if (TypeToPrint.isValid())
1449  PrintedTypes.set(OpInfo.getGenericTypeIndex());
1450  return TypeToPrint;
1451 }
1452 
1453 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1455  dbgs() << " ";
1456  print(dbgs());
1457 }
1458 #endif
1459 
1460 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1461  bool SkipDebugLoc, bool AddNewLine,
1462  const TargetInstrInfo *TII) const {
1463  const Module *M = nullptr;
1464  const Function *F = nullptr;
1465  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1466  F = &MF->getFunction();
1467  M = F->getParent();
1468  if (!TII)
1469  TII = MF->getSubtarget().getInstrInfo();
1470  }
1471 
1472  ModuleSlotTracker MST(M);
1473  if (F)
1474  MST.incorporateFunction(*F);
1475  print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, TII);
1476 }
1477 
1479  bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1480  bool AddNewLine, const TargetInstrInfo *TII) const {
1481  // We can be a bit tidier if we know the MachineFunction.
1482  const MachineFunction *MF = nullptr;
1483  const TargetRegisterInfo *TRI = nullptr;
1484  const MachineRegisterInfo *MRI = nullptr;
1485  const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1486  tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1487 
1488  if (isCFIInstruction())
1489  assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1490 
1491  SmallBitVector PrintedTypes(8);
1492  bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1493  auto getTiedOperandIdx = [&](unsigned OpIdx) {
1494  if (!ShouldPrintRegisterTies)
1495  return 0U;
1496  const MachineOperand &MO = getOperand(OpIdx);
1497  if (MO.isReg() && MO.isTied() && !MO.isDef())
1498  return findTiedOperandIdx(OpIdx);
1499  return 0U;
1500  };
1501  unsigned StartOp = 0;
1502  unsigned e = getNumOperands();
1503 
1504  // Print explicitly defined operands on the left of an assignment syntax.
1505  while (StartOp < e) {
1506  const MachineOperand &MO = getOperand(StartOp);
1507  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1508  break;
1509 
1510  if (StartOp != 0)
1511  OS << ", ";
1512 
1513  LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1514  unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1515  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
1516  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1517  ++StartOp;
1518  }
1519 
1520  if (StartOp != 0)
1521  OS << " = ";
1522 
1524  OS << "frame-setup ";
1526  OS << "frame-destroy ";
1528  OS << "nnan ";
1530  OS << "ninf ";
1532  OS << "nsz ";
1534  OS << "arcp ";
1536  OS << "contract ";
1538  OS << "afn ";
1540  OS << "reassoc ";
1542  OS << "nuw ";
1544  OS << "nsw ";
1546  OS << "exact ";
1547 
1548  // Print the opcode name.
1549  if (TII)
1550  OS << TII->getName(getOpcode());
1551  else
1552  OS << "UNKNOWN";
1553 
1554  if (SkipOpers)
1555  return;
1556 
1557  // Print the rest of the operands.
1558  bool FirstOp = true;
1559  unsigned AsmDescOp = ~0u;
1560  unsigned AsmOpCount = 0;
1561 
1562  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1563  // Print asm string.
1564  OS << " ";
1565  const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1566  LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1567  unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1568  getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1569  ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1570  IntrinsicInfo);
1571 
1572  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1573  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1574  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1575  OS << " [sideeffect]";
1576  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1577  OS << " [mayload]";
1578  if (ExtraInfo & InlineAsm::Extra_MayStore)
1579  OS << " [maystore]";
1580  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1581  OS << " [isconvergent]";
1582  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1583  OS << " [alignstack]";
1585  OS << " [attdialect]";
1587  OS << " [inteldialect]";
1588 
1589  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1590  FirstOp = false;
1591  }
1592 
1593  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1594  const MachineOperand &MO = getOperand(i);
1595 
1596  if (FirstOp) FirstOp = false; else OS << ",";
1597  OS << " ";
1598 
1599  if (isDebugValue() && MO.isMetadata()) {
1600  // Pretty print DBG_VALUE instructions.
1601  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1602  if (DIV && !DIV->getName().empty())
1603  OS << "!\"" << DIV->getName() << '\"';
1604  else {
1605  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1606  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1607  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1608  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1609  }
1610  } else if (isDebugLabel() && MO.isMetadata()) {
1611  // Pretty print DBG_LABEL instructions.
1612  auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1613  if (DIL && !DIL->getName().empty())
1614  OS << "\"" << DIL->getName() << '\"';
1615  else {
1616  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1617  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1618  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1619  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1620  }
1621  } else if (i == AsmDescOp && MO.isImm()) {
1622  // Pretty print the inline asm operand descriptor.
1623  OS << '$' << AsmOpCount++;
1624  unsigned Flag = MO.getImm();
1625  switch (InlineAsm::getKind(Flag)) {
1626  case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1627  case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1628  case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1629  case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1630  case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1631  case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1632  default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1633  }
1634 
1635  unsigned RCID = 0;
1636  if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1637  InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1638  if (TRI) {
1639  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1640  } else
1641  OS << ":RC" << RCID;
1642  }
1643 
1644  if (InlineAsm::isMemKind(Flag)) {
1645  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1646  switch (MCID) {
1647  case InlineAsm::Constraint_es: OS << ":es"; break;
1648  case InlineAsm::Constraint_i: OS << ":i"; break;
1649  case InlineAsm::Constraint_m: OS << ":m"; break;
1650  case InlineAsm::Constraint_o: OS << ":o"; break;
1651  case InlineAsm::Constraint_v: OS << ":v"; break;
1652  case InlineAsm::Constraint_Q: OS << ":Q"; break;
1653  case InlineAsm::Constraint_R: OS << ":R"; break;
1654  case InlineAsm::Constraint_S: OS << ":S"; break;
1655  case InlineAsm::Constraint_T: OS << ":T"; break;
1656  case InlineAsm::Constraint_Um: OS << ":Um"; break;
1657  case InlineAsm::Constraint_Un: OS << ":Un"; break;
1658  case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1659  case InlineAsm::Constraint_Us: OS << ":Us"; break;
1660  case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1661  case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1662  case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1663  case InlineAsm::Constraint_X: OS << ":X"; break;
1664  case InlineAsm::Constraint_Z: OS << ":Z"; break;
1665  case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1666  case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1667  default: OS << ":?"; break;
1668  }
1669  }
1670 
1671  unsigned TiedTo = 0;
1672  if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1673  OS << " tiedto:$" << TiedTo;
1674 
1675  OS << ']';
1676 
1677  // Compute the index of the next operand descriptor.
1678  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1679  } else {
1680  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1681  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1682  if (MO.isImm() && isOperandSubregIdx(i))
1684  else
1685  MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1686  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1687  }
1688  }
1689 
1690  // Print any optional symbols attached to this instruction as-if they were
1691  // operands.
1692  if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1693  if (!FirstOp) {
1694  FirstOp = false;
1695  OS << ',';
1696  }
1697  OS << " pre-instr-symbol ";
1698  MachineOperand::printSymbol(OS, *PreInstrSymbol);
1699  }
1700  if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1701  if (!FirstOp) {
1702  FirstOp = false;
1703  OS << ',';
1704  }
1705  OS << " post-instr-symbol ";
1706  MachineOperand::printSymbol(OS, *PostInstrSymbol);
1707  }
1708 
1709  if (!SkipDebugLoc) {
1710  if (const DebugLoc &DL = getDebugLoc()) {
1711  if (!FirstOp)
1712  OS << ',';
1713  OS << " debug-location ";
1714  DL->printAsOperand(OS, MST);
1715  }
1716  }
1717 
1718  if (!memoperands_empty()) {
1720  const LLVMContext *Context = nullptr;
1721  std::unique_ptr<LLVMContext> CtxPtr;
1722  const MachineFrameInfo *MFI = nullptr;
1723  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1724  MFI = &MF->getFrameInfo();
1725  Context = &MF->getFunction().getContext();
1726  } else {
1727  CtxPtr = llvm::make_unique<LLVMContext>();
1728  Context = CtxPtr.get();
1729  }
1730 
1731  OS << " :: ";
1732  bool NeedComma = false;
1733  for (const MachineMemOperand *Op : memoperands()) {
1734  if (NeedComma)
1735  OS << ", ";
1736  Op->print(OS, MST, SSNs, *Context, MFI, TII);
1737  NeedComma = true;
1738  }
1739  }
1740 
1741  if (SkipDebugLoc)
1742  return;
1743 
1744  bool HaveSemi = false;
1745 
1746  // Print debug location information.
1747  if (const DebugLoc &DL = getDebugLoc()) {
1748  if (!HaveSemi) {
1749  OS << ';';
1750  HaveSemi = true;
1751  }
1752  OS << ' ';
1753  DL.print(OS);
1754  }
1755 
1756  // Print extra comments for DEBUG_VALUE.
1757  if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1758  if (!HaveSemi) {
1759  OS << ";";
1760  HaveSemi = true;
1761  }
1762  auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1763  OS << " line no:" << DV->getLine();
1764  if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1765  DebugLoc InlinedAtDL(InlinedAt);
1766  if (InlinedAtDL && MF) {
1767  OS << " inlined @[ ";
1768  InlinedAtDL.print(OS);
1769  OS << " ]";
1770  }
1771  }
1772  if (isIndirectDebugValue())
1773  OS << " indirect";
1774  }
1775  // TODO: DBG_LABEL
1776 
1777  if (AddNewLine)
1778  OS << '\n';
1779 }
1780 
1781 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1782  const TargetRegisterInfo *RegInfo,
1783  bool AddIfNotFound) {
1784  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1785  bool hasAliases = isPhysReg &&
1786  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1787  bool Found = false;
1788  SmallVector<unsigned,4> DeadOps;
1789  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1790  MachineOperand &MO = getOperand(i);
1791  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1792  continue;
1793 
1794  // DEBUG_VALUE nodes do not contribute to code generation and should
1795  // always be ignored. Failure to do so may result in trying to modify
1796  // KILL flags on DEBUG_VALUE nodes.
1797  if (MO.isDebug())
1798  continue;
1799 
1800  unsigned Reg = MO.getReg();
1801  if (!Reg)
1802  continue;
1803 
1804  if (Reg == IncomingReg) {
1805  if (!Found) {
1806  if (MO.isKill())
1807  // The register is already marked kill.
1808  return true;
1809  if (isPhysReg && isRegTiedToDefOperand(i))
1810  // Two-address uses of physregs must not be marked kill.
1811  return true;
1812  MO.setIsKill();
1813  Found = true;
1814  }
1815  } else if (hasAliases && MO.isKill() &&
1817  // A super-register kill already exists.
1818  if (RegInfo->isSuperRegister(IncomingReg, Reg))
1819  return true;
1820  if (RegInfo->isSubRegister(IncomingReg, Reg))
1821  DeadOps.push_back(i);
1822  }
1823  }
1824 
1825  // Trim unneeded kill operands.
1826  while (!DeadOps.empty()) {
1827  unsigned OpIdx = DeadOps.back();
1828  if (getOperand(OpIdx).isImplicit() &&
1829  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1830  RemoveOperand(OpIdx);
1831  else
1832  getOperand(OpIdx).setIsKill(false);
1833  DeadOps.pop_back();
1834  }
1835 
1836  // If not found, this means an alias of one of the operands is killed. Add a
1837  // new implicit operand if required.
1838  if (!Found && AddIfNotFound) {
1840  false /*IsDef*/,
1841  true /*IsImp*/,
1842  true /*IsKill*/));
1843  return true;
1844  }
1845  return Found;
1846 }
1847 
1849  const TargetRegisterInfo *RegInfo) {
1851  RegInfo = nullptr;
1852  for (MachineOperand &MO : operands()) {
1853  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1854  continue;
1855  unsigned OpReg = MO.getReg();
1856  if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1857  MO.setIsKill(false);
1858  }
1859 }
1860 
1862  const TargetRegisterInfo *RegInfo,
1863  bool AddIfNotFound) {
1864  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1865  bool hasAliases = isPhysReg &&
1866  MCRegAliasIterator(Reg, RegInfo, false).isValid();
1867  bool Found = false;
1868  SmallVector<unsigned,4> DeadOps;
1869  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1870  MachineOperand &MO = getOperand(i);
1871  if (!MO.isReg() || !MO.isDef())
1872  continue;
1873  unsigned MOReg = MO.getReg();
1874  if (!MOReg)
1875  continue;
1876 
1877  if (MOReg == Reg) {
1878  MO.setIsDead();
1879  Found = true;
1880  } else if (hasAliases && MO.isDead() &&
1882  // There exists a super-register that's marked dead.
1883  if (RegInfo->isSuperRegister(Reg, MOReg))
1884  return true;
1885  if (RegInfo->isSubRegister(Reg, MOReg))
1886  DeadOps.push_back(i);
1887  }
1888  }
1889 
1890  // Trim unneeded dead operands.
1891  while (!DeadOps.empty()) {
1892  unsigned OpIdx = DeadOps.back();
1893  if (getOperand(OpIdx).isImplicit() &&
1894  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1895  RemoveOperand(OpIdx);
1896  else
1897  getOperand(OpIdx).setIsDead(false);
1898  DeadOps.pop_back();
1899  }
1900 
1901  // If not found, this means an alias of one of the operands is dead. Add a
1902  // new implicit operand if required.
1903  if (Found || !AddIfNotFound)
1904  return Found;
1905 
1907  true /*IsDef*/,
1908  true /*IsImp*/,
1909  false /*IsKill*/,
1910  true /*IsDead*/));
1911  return true;
1912 }
1913 
1915  for (MachineOperand &MO : operands()) {
1916  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1917  continue;
1918  MO.setIsDead(false);
1919  }
1920 }
1921 
1922 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
1923  for (MachineOperand &MO : operands()) {
1924  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1925  continue;
1926  MO.setIsUndef(IsUndef);
1927  }
1928 }
1929 
1931  const TargetRegisterInfo *RegInfo) {
1933  MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
1934  if (MO)
1935  return;
1936  } else {
1937  for (const MachineOperand &MO : operands()) {
1938  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1939  MO.getSubReg() == 0)
1940  return;
1941  }
1942  }
1944  true /*IsDef*/,
1945  true /*IsImp*/));
1946 }
1947 
1949  const TargetRegisterInfo &TRI) {
1950  bool HasRegMask = false;
1951  for (MachineOperand &MO : operands()) {
1952  if (MO.isRegMask()) {
1953  HasRegMask = true;
1954  continue;
1955  }
1956  if (!MO.isReg() || !MO.isDef()) continue;
1957  unsigned Reg = MO.getReg();
1958  if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1959  // If there are no uses, including partial uses, the def is dead.
1960  if (llvm::none_of(UsedRegs,
1961  [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1962  MO.setIsDead();
1963  }
1964 
1965  // This is a call with a register mask operand.
1966  // Mask clobbers are always dead, so add defs for the non-dead defines.
1967  if (HasRegMask)
1968  for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1969  I != E; ++I)
1970  addRegisterDefined(*I, &TRI);
1971 }
1972 
1973 unsigned
1975  // Build up a buffer of hash code components.
1976  SmallVector<size_t, 8> HashComponents;
1977  HashComponents.reserve(MI->getNumOperands() + 1);
1978  HashComponents.push_back(MI->getOpcode());
1979  for (const MachineOperand &MO : MI->operands()) {
1980  if (MO.isReg() && MO.isDef() &&
1982  continue; // Skip virtual register defs.
1983 
1984  HashComponents.push_back(hash_value(MO));
1985  }
1986  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1987 }
1988 
1990  // Find the source location cookie.
1991  unsigned LocCookie = 0;
1992  const MDNode *LocMD = nullptr;
1993  for (unsigned i = getNumOperands(); i != 0; --i) {
1994  if (getOperand(i-1).isMetadata() &&
1995  (LocMD = getOperand(i-1).getMetadata()) &&
1996  LocMD->getNumOperands() != 0) {
1997  if (const ConstantInt *CI =
1998  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1999  LocCookie = CI->getZExtValue();
2000  break;
2001  }
2002  }
2003  }
2004 
2005  if (const MachineBasicBlock *MBB = getParent())
2006  if (const MachineFunction *MF = MBB->getParent())
2007  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2008  report_fatal_error(Msg);
2009 }
2010 
2012  const MCInstrDesc &MCID, bool IsIndirect,
2013  unsigned Reg, const MDNode *Variable,
2014  const MDNode *Expr) {
2015  assert(isa<DILocalVariable>(Variable) && "not a variable");
2016  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2017  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2018  "Expected inlined-at fields to agree");
2019  auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2020  if (IsIndirect)
2021  MIB.addImm(0U);
2022  else
2023  MIB.addReg(0U, RegState::Debug);
2024  return MIB.addMetadata(Variable).addMetadata(Expr);
2025 }
2026 
2028  const MCInstrDesc &MCID, bool IsIndirect,
2029  MachineOperand &MO, const MDNode *Variable,
2030  const MDNode *Expr) {
2031  assert(isa<DILocalVariable>(Variable) && "not a variable");
2032  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2033  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2034  "Expected inlined-at fields to agree");
2035  if (MO.isReg())
2036  return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2037 
2038  auto MIB = BuildMI(MF, DL, MCID).add(MO);
2039  if (IsIndirect)
2040  MIB.addImm(0U);
2041  else
2042  MIB.addReg(0U, RegState::Debug);
2043  return MIB.addMetadata(Variable).addMetadata(Expr);
2044  }
2045 
2048  const DebugLoc &DL, const MCInstrDesc &MCID,
2049  bool IsIndirect, unsigned Reg,
2050  const MDNode *Variable, const MDNode *Expr) {
2051  MachineFunction &MF = *BB.getParent();
2052  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2053  BB.insert(I, MI);
2054  return MachineInstrBuilder(MF, MI);
2055 }
2056 
2059  const DebugLoc &DL, const MCInstrDesc &MCID,
2060  bool IsIndirect, MachineOperand &MO,
2061  const MDNode *Variable, const MDNode *Expr) {
2062  MachineFunction &MF = *BB.getParent();
2063  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2064  BB.insert(I, MI);
2065  return MachineInstrBuilder(MF, *MI);
2066 }
2067 
2068 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2069 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2071  assert(MI.getOperand(0).isReg() && "can't spill non-register");
2073  "Expected inlined-at fields to agree");
2074 
2075  const DIExpression *Expr = MI.getDebugExpression();
2076  if (MI.isIndirectDebugValue()) {
2077  assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
2079  }
2080  return Expr;
2081 }
2082 
2085  const MachineInstr &Orig,
2086  int FrameIndex) {
2087  const DIExpression *Expr = computeExprForSpill(Orig);
2088  return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2089  .addFrameIndex(FrameIndex)
2090  .addImm(0U)
2091  .addMetadata(Orig.getDebugVariable())
2092  .addMetadata(Expr);
2093 }
2094 
2096  const DIExpression *Expr = computeExprForSpill(Orig);
2097  Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
2098  Orig.getOperand(1).ChangeToImmediate(0U);
2099  Orig.getOperand(3).setMetadata(Expr);
2100 }
2101 
2103  SmallVectorImpl<MachineInstr *> &DbgValues) {
2104  MachineInstr &MI = *this;
2105  if (!MI.getOperand(0).isReg())
2106  return;
2107 
2108  MachineBasicBlock::iterator DI = MI; ++DI;
2109  for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2110  DI != DE; ++DI) {
2111  if (!DI->isDebugValue())
2112  return;
2113  if (DI->getOperand(0).isReg() &&
2114  DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2115  DbgValues.push_back(&*DI);
2116  }
2117 }
2118 
2120  // Collect matching debug values.
2122  collectDebugValues(DbgValues);
2123 
2124  // Propagate Reg to debug value instructions.
2125  for (auto *DBI : DbgValues)
2126  DBI->getOperand(0).setReg(Reg);
2127 }
2128 
2130 
2131 static unsigned getSpillSlotSize(MMOList &Accesses,
2132  const MachineFrameInfo &MFI) {
2133  unsigned Size = 0;
2134  for (auto A : Accesses)
2135  if (MFI.isSpillSlotObjectIndex(
2136  cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2137  ->getFrameIndex()))
2138  Size += A->getSize();
2139  return Size;
2140 }
2141 
2144  int FI;
2145  if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2146  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2147  if (MFI.isSpillSlotObjectIndex(FI))
2148  return (*memoperands_begin())->getSize();
2149  }
2150  return None;
2151 }
2152 
2155  MMOList Accesses;
2156  if (TII->hasStoreToStackSlot(*this, Accesses))
2157  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2158  return None;
2159 }
2160 
2163  int FI;
2164  if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2165  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2166  if (MFI.isSpillSlotObjectIndex(FI))
2167  return (*memoperands_begin())->getSize();
2168  }
2169  return None;
2170 }
2171 
2174  MMOList Accesses;
2175  if (TII->hasLoadFromStackSlot(*this, Accesses))
2176  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2177  return None;
2178 }
static bool isReg(const MCInst &MI, unsigned OpNo)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
static bool Check(DecodeStatus &Out, DecodeStatus In)
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:526
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void bundleWithPred()
Bundle this instruction with its predecessor.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
bool isUnordered() const
Returns true if this memory operation doesn&#39;t have any ordering constraints other than normal aliasin...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs...
const MachineInstrBuilder & add(const MachineOperand &MO) const
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool hasRegisterImplicitUseOperand(unsigned Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool isDebugLabel() const
Definition: MachineInstr.h:997
void collectDebugValues(SmallVectorImpl< MachineInstr *> &DbgValues)
Scan instructions following MI and collect any matching DBG_VALUEs.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:632
bool noNaNs() const
Definition: Operator.h:205
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:548
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:473
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
iterator begin() const
Definition: ArrayRef.h:136
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static const DIExpression * computeExprForSpill(const MachineInstr &MI)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value...
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
bool isCFIInstruction() const
Definition: MachineInstr.h:989
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:361
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:523
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
This file contains the declarations for metadata subclasses.
unsigned getSubReg() const
bool isInlineAsm() const
The two locations do not alias at all.
Definition: AliasAnalysis.h:84
bool noInfs() const
Definition: Operator.h:206
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
void setIsDead(bool Val=true)
F(f)
MachineModuleInfo & getMMI() const
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1068
Manage lifetime of a slot tracker for printing IR.
void reserve(size_type N)
Definition: SmallVector.h:369
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:458
bool isPHI() const
void print(raw_ostream &OS) const
prints source location /path/to/file.exe:line:col @[inlined at]
Definition: DebugLoc.cpp:118
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:275
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:341
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static DIExpression * prepend(const DIExpression *Expr, bool DerefBefore, int64_t Offset=0, bool DerefAfter=false, bool StackValue=false)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
void clearKillInfo()
Clears kill flags on all operands.
AliasResult alias(const MemoryLocation &LocA, const MemoryLocation &LocB)
The main low level interface to the alias analysis implementation.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
A description of a memory reference used in the backend.
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:365
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:244
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1199
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:648
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
void bundleWithSucc()
Bundle this instruction with its successor.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand *> MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr)
Allocate and construct an extra info structure for a MachineInstr.
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
void setIsEarlyClobber(bool Val=true)
void unbundleFromPred()
Break bundle above this instruction.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
bool isValid() const
isValid - Returns true until all the operands have been visited.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool isBundle() const
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
void changeDebugValuesDefReg(unsigned Reg)
Find all DBG_VALUEs immediately following this instruction that point to a register def in this instr...
struct llvm::MachineOperand::@168::@170 Reg
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4433
bool allowContract() const
Definition: Operator.h:209
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
virtual const TargetInstrInfo * getInstrInfo() const
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:92
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn&#39;t ...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:554
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr&#39;s memory reference descriptor list.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
TargetInstrInfo - Interface to description of machine instruction set.
AliasResult
The possible results of an alias query.
Definition: AliasAnalysis.h:78
const Value * getValue() const
Return the base address of the memory access.
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:819
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:545
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
unsigned const MachineRegisterInfo * MRI
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr&#39;s pre- and post- instruction symbols and replace ours with it...
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:515
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:234
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:428
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed...
Definition: Operator.h:119
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:299
MCRegAliasIterator enumerates all registers aliasing Reg.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:310
This file declares a class to represent arbitrary precision floating point values and provide a varie...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:548
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1192
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:328
bool isValid() const
const PseudoSourceValue * getPseudoValue() const
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl...
Definition: Operator.h:66
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:324
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool allowReciprocal() const
Definition: Operator.h:208
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:307
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can&#39;t be determined by the instruction&#39;s descr...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:196
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:840
bool isStackAligningInlineAsm() const
static unsigned getHashValue(const MachineInstr *const &MI)
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:276
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:50
size_t size() const
Definition: SmallVector.h:52
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
static uint16_t copyFlagsFromInstruction(const Instruction &I)
bool isDebugInstr() const
Definition: MachineInstr.h:998
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:566
void eraseFromBundle()
Unlink &#39;this&#39; form its basic block and delete it.
void setIsKill(bool Val=true)
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
TargetIntrinsicInfo - Interface to description of machine instruction set.
SmallBitVector & set()
Representation for a specific memory location.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr&#39;s memory reference descriptor list and replace ours with it...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Iterator for intrusive lists based on ilist_node.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
InlineAsm::AsmDialect getInlineAsmDialect() const
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:533
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
void setFlags(unsigned flags)
Definition: MachineInstr.h:303
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
bool isDebugValue() const
Definition: MachineInstr.h:996
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
Utility class for floating point operations which can have information about relaxed accuracy require...
Definition: Operator.h:245
Module.h This file contains the declarations for the Module class.
iterator end() const
Definition: ArrayRef.h:137
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:643
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:606
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
int64_t getImm() const
void setMetadata(const MDNode *MD)
DWARF expression.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
MCSymbol reference (for debug/eh info)
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:591
Special value supplied for machine level alias analysis.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:478
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
Definition: ArrayRef.h:178
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:387
static unsigned getSpillSlotSize(MMOList &Accesses, const MachineFrameInfo &MFI)
const unsigned TiedMax
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:580
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:350
Representation of each machine instruction.
Definition: MachineInstr.h:63
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges. ...
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
This file provides utility analysis objects describing memory locations.
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr *> MIs)
Clone the merge of multiple MachineInstrs&#39; memory reference descriptors list and replace ours with it...
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
Definition: iterator.h:302
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand *> LHS, ArrayRef< MachineMemOperand *> RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isKill() const
const Module * getModule() const
MachineInstr * removeFromParent()
Unlink &#39;this&#39; from the containing basic block, and return it without deleting it. ...
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:289
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:806
bool memoperands_empty() const
Return true if we don&#39;t have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:545
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand *> MemRefs)
Assign this MachineInstr&#39;s memory reference descriptor list.
void unbundleFromSucc()
Break bundle below this instruction.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:72
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
bool isPosition() const
Definition: MachineInstr.h:994
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool allowReassoc() const
Flag queries.
Definition: Operator.h:204
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:159
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool approxFunc() const
Definition: Operator.h:210
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1074
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:294
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool mayAlias(AliasAnalysis *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction&#39;s memory access aliases the memory access of Other.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
const MDNode * getMetadata() const
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:172
bool noSignedZeros() const
Definition: Operator.h:207
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:540
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
bool isImplicit() const
Metadata reference (for debug info)
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.