LLVM  10.0.0svn
TargetInstrInfo.h
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1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the target machine instruction set to the code generator.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
14 #define LLVM_TARGET_TARGETINSTRINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/DenseMapInfo.h"
19 #include "llvm/ADT/None.h"
30 #include "llvm/MC/MCInstrInfo.h"
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 #include <utility>
37 #include <vector>
38 
39 namespace llvm {
40 
41 class DFAPacketizer;
42 class InstrItineraryData;
43 class LiveIntervals;
44 class LiveVariables;
45 class MachineMemOperand;
46 class MachineRegisterInfo;
47 class MCAsmInfo;
48 class MCInst;
49 struct MCSchedModel;
50 class Module;
51 class ScheduleDAG;
52 class ScheduleHazardRecognizer;
53 class SDNode;
54 class SelectionDAG;
55 class RegScavenger;
56 class TargetRegisterClass;
57 class TargetRegisterInfo;
58 class TargetSchedModel;
59 class TargetSubtargetInfo;
60 
61 template <class T> class SmallVectorImpl;
62 
63 using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
64 
65 //---------------------------------------------------------------------------
66 ///
67 /// TargetInstrInfo - Interface to description of machine instruction set
68 ///
69 class TargetInstrInfo : public MCInstrInfo {
70 public:
71  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
72  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
73  : CallFrameSetupOpcode(CFSetupOpcode),
74  CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
75  ReturnOpcode(ReturnOpcode) {}
76  TargetInstrInfo(const TargetInstrInfo &) = delete;
77  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
78  virtual ~TargetInstrInfo();
79 
80  static bool isGenericOpcode(unsigned Opc) {
81  return Opc <= TargetOpcode::GENERIC_OP_END;
82  }
83 
84  /// Given a machine instruction descriptor, returns the register
85  /// class constraint for OpNum, or NULL.
86  virtual
87  const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
88  const TargetRegisterInfo *TRI,
89  const MachineFunction &MF) const;
90 
91  /// Return true if the instruction is trivially rematerializable, meaning it
92  /// has no side effects and requires no operands that aren't always available.
93  /// This means the only allowed uses are constants and unallocatable physical
94  /// registers so that the instructions result is independent of the place
95  /// in the function.
97  AliasAnalysis *AA = nullptr) const {
98  return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
99  (MI.getDesc().isRematerializable() &&
101  isReallyTriviallyReMaterializableGeneric(MI, AA)));
102  }
103 
104 protected:
105  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
106  /// set, this hook lets the target specify whether the instruction is actually
107  /// trivially rematerializable, taking into consideration its operands. This
108  /// predicate must return false if the instruction has any side effects other
109  /// than producing a value, or if it requres any address registers that are
110  /// not always available.
111  /// Requirements must be check as stated in isTriviallyReMaterializable() .
113  AliasAnalysis *AA) const {
114  return false;
115  }
116 
117  /// This method commutes the operands of the given machine instruction MI.
118  /// The operands to be commuted are specified by their indices OpIdx1 and
119  /// OpIdx2.
120  ///
121  /// If a target has any instructions that are commutable but require
122  /// converting to different instructions or making non-trivial changes
123  /// to commute them, this method can be overloaded to do that.
124  /// The default implementation simply swaps the commutable operands.
125  ///
126  /// If NewMI is false, MI is modified in place and returned; otherwise, a
127  /// new machine instruction is created and returned.
128  ///
129  /// Do not call this method for a non-commutable instruction.
130  /// Even though the instruction is commutable, the method may still
131  /// fail to commute the operands, null pointer is returned in such cases.
132  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
133  unsigned OpIdx1,
134  unsigned OpIdx2) const;
135 
136  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
137  /// operand indices to (ResultIdx1, ResultIdx2).
138  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
139  /// predefined to some indices or be undefined (designated by the special
140  /// value 'CommuteAnyOperandIndex').
141  /// The predefined result indices cannot be re-defined.
142  /// The function returns true iff after the result pair redefinition
143  /// the fixed result pair is equal to or equivalent to the source pair of
144  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
145  /// the pairs (x,y) and (y,x) are equivalent.
146  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
147  unsigned CommutableOpIdx1,
148  unsigned CommutableOpIdx2);
149 
150 private:
151  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
152  /// set and the target hook isReallyTriviallyReMaterializable returns false,
153  /// this function does target-independent tests to determine if the
154  /// instruction is really trivially rematerializable.
155  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
156  AliasAnalysis *AA) const;
157 
158 public:
159  /// These methods return the opcode of the frame setup/destroy instructions
160  /// if they exist (-1 otherwise). Some targets use pseudo instructions in
161  /// order to abstract away the difference between operating with a frame
162  /// pointer and operating without, through the use of these two instructions.
163  ///
164  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
165  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
166 
167  /// Returns true if the argument is a frame pseudo instruction.
168  bool isFrameInstr(const MachineInstr &I) const {
169  return I.getOpcode() == getCallFrameSetupOpcode() ||
171  }
172 
173  /// Returns true if the argument is a frame setup pseudo instruction.
174  bool isFrameSetup(const MachineInstr &I) const {
175  return I.getOpcode() == getCallFrameSetupOpcode();
176  }
177 
178  /// Returns size of the frame associated with the given frame instruction.
179  /// For frame setup instruction this is frame that is set up space set up
180  /// after the instruction. For frame destroy instruction this is the frame
181  /// freed by the caller.
182  /// Note, in some cases a call frame (or a part of it) may be prepared prior
183  /// to the frame setup instruction. It occurs in the calls that involve
184  /// inalloca arguments. This function reports only the size of the frame part
185  /// that is set up between the frame setup and destroy pseudo instructions.
186  int64_t getFrameSize(const MachineInstr &I) const {
187  assert(isFrameInstr(I) && "Not a frame instruction");
188  assert(I.getOperand(0).getImm() >= 0);
189  return I.getOperand(0).getImm();
190  }
191 
192  /// Returns the total frame size, which is made up of the space set up inside
193  /// the pair of frame start-stop instructions and the space that is set up
194  /// prior to the pair.
195  int64_t getFrameTotalSize(const MachineInstr &I) const {
196  if (isFrameSetup(I)) {
197  assert(I.getOperand(1).getImm() >= 0 &&
198  "Frame size must not be negative");
199  return getFrameSize(I) + I.getOperand(1).getImm();
200  }
201  return getFrameSize(I);
202  }
203 
204  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
205  unsigned getReturnOpcode() const { return ReturnOpcode; }
206 
207  /// Returns the actual stack pointer adjustment made by an instruction
208  /// as part of a call sequence. By default, only call frame setup/destroy
209  /// instructions adjust the stack, but targets may want to override this
210  /// to enable more fine-grained adjustment, or adjust by a different value.
211  virtual int getSPAdjust(const MachineInstr &MI) const;
212 
213  /// Return true if the instruction is a "coalescable" extension instruction.
214  /// That is, it's like a copy where it's legal for the source to overlap the
215  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
216  /// expected the pre-extension value is available as a subreg of the result
217  /// register. This also returns the sub-register index in SubIdx.
218  virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
219  unsigned &DstReg, unsigned &SubIdx) const {
220  return false;
221  }
222 
223  /// If the specified machine instruction is a direct
224  /// load from a stack slot, return the virtual or physical register number of
225  /// the destination along with the FrameIndex of the loaded stack slot. If
226  /// not, return 0. This predicate must return 0 if the instruction has
227  /// any side effects other than loading from the stack slot.
228  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
229  int &FrameIndex) const {
230  return 0;
231  }
232 
233  /// Optional extension of isLoadFromStackSlot that returns the number of
234  /// bytes loaded from the stack. This must be implemented if a backend
235  /// supports partial stack slot spills/loads to further disambiguate
236  /// what the load does.
237  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
238  int &FrameIndex,
239  unsigned &MemBytes) const {
240  MemBytes = 0;
241  return isLoadFromStackSlot(MI, FrameIndex);
242  }
243 
244  /// Check for post-frame ptr elimination stack locations as well.
245  /// This uses a heuristic so it isn't reliable for correctness.
246  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
247  int &FrameIndex) const {
248  return 0;
249  }
250 
251  /// If the specified machine instruction has a load from a stack slot,
252  /// return true along with the FrameIndices of the loaded stack slot and the
253  /// machine mem operands containing the reference.
254  /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
255  /// any instructions that loads from the stack. This is just a hint, as some
256  /// cases may be missed.
257  virtual bool hasLoadFromStackSlot(
258  const MachineInstr &MI,
260 
261  /// If the specified machine instruction is a direct
262  /// store to a stack slot, return the virtual or physical register number of
263  /// the source reg along with the FrameIndex of the loaded stack slot. If
264  /// not, return 0. This predicate must return 0 if the instruction has
265  /// any side effects other than storing to the stack slot.
266  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
267  int &FrameIndex) const {
268  return 0;
269  }
270 
271  /// Optional extension of isStoreToStackSlot that returns the number of
272  /// bytes stored to the stack. This must be implemented if a backend
273  /// supports partial stack slot spills/loads to further disambiguate
274  /// what the store does.
275  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
276  int &FrameIndex,
277  unsigned &MemBytes) const {
278  MemBytes = 0;
279  return isStoreToStackSlot(MI, FrameIndex);
280  }
281 
282  /// Check for post-frame ptr elimination stack locations as well.
283  /// This uses a heuristic, so it isn't reliable for correctness.
284  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
285  int &FrameIndex) const {
286  return 0;
287  }
288 
289  /// If the specified machine instruction has a store to a stack slot,
290  /// return true along with the FrameIndices of the loaded stack slot and the
291  /// machine mem operands containing the reference.
292  /// If not, return false. Unlike isStoreToStackSlot,
293  /// this returns true for any instructions that stores to the
294  /// stack. This is just a hint, as some cases may be missed.
295  virtual bool hasStoreToStackSlot(
296  const MachineInstr &MI,
298 
299  /// Return true if the specified machine instruction
300  /// is a copy of one stack slot to another and has no other effect.
301  /// Provide the identity of the two frame indices.
302  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
303  int &SrcFrameIndex) const {
304  return false;
305  }
306 
307  /// Compute the size in bytes and offset within a stack slot of a spilled
308  /// register or subregister.
309  ///
310  /// \param [out] Size in bytes of the spilled value.
311  /// \param [out] Offset in bytes within the stack slot.
312  /// \returns true if both Size and Offset are successfully computed.
313  ///
314  /// Not all subregisters have computable spill slots. For example,
315  /// subregisters registers may not be byte-sized, and a pair of discontiguous
316  /// subregisters has no single offset.
317  ///
318  /// Targets with nontrivial bigendian implementations may need to override
319  /// this, particularly to support spilled vector registers.
320  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
321  unsigned &Size, unsigned &Offset,
322  const MachineFunction &MF) const;
323 
324  /// Returns the size in bytes of the specified MachineInstr, or ~0U
325  /// when this function is not implemented by a target.
326  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
327  return ~0U;
328  }
329 
330  /// Return true if the instruction is as cheap as a move instruction.
331  ///
332  /// Targets for different archs need to override this, and different
333  /// micro-architectures can also be finely tuned inside.
334  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
335  return MI.isAsCheapAsAMove();
336  }
337 
338  /// Return true if the instruction should be sunk by MachineSink.
339  ///
340  /// MachineSink determines on its own whether the instruction is safe to sink;
341  /// this gives the target a hook to override the default behavior with regards
342  /// to which instructions should be sunk.
343  virtual bool shouldSink(const MachineInstr &MI) const { return true; }
344 
345  /// Re-issue the specified 'original' instruction at the
346  /// specific location targeting a new destination register.
347  /// The register in Orig->getOperand(0).getReg() will be substituted by
348  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
349  /// SubIdx.
350  virtual void reMaterialize(MachineBasicBlock &MBB,
351  MachineBasicBlock::iterator MI, unsigned DestReg,
352  unsigned SubIdx, const MachineInstr &Orig,
353  const TargetRegisterInfo &TRI) const;
354 
355  /// Clones instruction or the whole instruction bundle \p Orig and
356  /// insert into \p MBB before \p InsertBefore. The target may update operands
357  /// that are required to be unique.
358  ///
359  /// \p Orig must not return true for MachineInstr::isNotDuplicable().
361  MachineBasicBlock::iterator InsertBefore,
362  const MachineInstr &Orig) const;
363 
364  /// This method must be implemented by targets that
365  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
366  /// may be able to convert a two-address instruction into one or more true
367  /// three-address instructions on demand. This allows the X86 target (for
368  /// example) to convert ADD and SHL instructions into LEA instructions if they
369  /// would require register copies due to two-addressness.
370  ///
371  /// This method returns a null pointer if the transformation cannot be
372  /// performed, otherwise it returns the last new instruction.
373  ///
375  MachineInstr &MI,
376  LiveVariables *LV) const {
377  return nullptr;
378  }
379 
380  // This constant can be used as an input value of operand index passed to
381  // the method findCommutedOpIndices() to tell the method that the
382  // corresponding operand index is not pre-defined and that the method
383  // can pick any commutable operand.
384  static const unsigned CommuteAnyOperandIndex = ~0U;
385 
386  /// This method commutes the operands of the given machine instruction MI.
387  ///
388  /// The operands to be commuted are specified by their indices OpIdx1 and
389  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
390  /// 'CommuteAnyOperandIndex', which means that the method is free to choose
391  /// any arbitrarily chosen commutable operand. If both arguments are set to
392  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
393  /// operands; then commutes them if such operands could be found.
394  ///
395  /// If NewMI is false, MI is modified in place and returned; otherwise, a
396  /// new machine instruction is created and returned.
397  ///
398  /// Do not call this method for a non-commutable instruction or
399  /// for non-commuable operands.
400  /// Even though the instruction is commutable, the method may still
401  /// fail to commute the operands, null pointer is returned in such cases.
402  MachineInstr *
403  commuteInstruction(MachineInstr &MI, bool NewMI = false,
404  unsigned OpIdx1 = CommuteAnyOperandIndex,
405  unsigned OpIdx2 = CommuteAnyOperandIndex) const;
406 
407  /// Returns true iff the routine could find two commutable operands in the
408  /// given machine instruction.
409  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
410  /// If any of the INPUT values is set to the special value
411  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
412  /// operand, then returns its index in the corresponding argument.
413  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
414  /// looks for 2 commutable operands.
415  /// If INPUT values refer to some operands of MI, then the method simply
416  /// returns true if the corresponding operands are commutable and returns
417  /// false otherwise.
418  ///
419  /// For example, calling this method this way:
420  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
421  /// findCommutedOpIndices(MI, Op1, Op2);
422  /// can be interpreted as a query asking to find an operand that would be
423  /// commutable with the operand#1.
424  virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
425  unsigned &SrcOpIdx2) const;
426 
427  /// A pair composed of a register and a sub-register index.
428  /// Used to give some type checking when modeling Reg:SubReg.
429  struct RegSubRegPair {
430  unsigned Reg;
431  unsigned SubReg;
432 
433  RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
434  : Reg(Reg), SubReg(SubReg) {}
435 
436  bool operator==(const RegSubRegPair& P) const {
437  return Reg == P.Reg && SubReg == P.SubReg;
438  }
439  bool operator!=(const RegSubRegPair& P) const {
440  return !(*this == P);
441  }
442  };
443 
444  /// A pair composed of a pair of a register and a sub-register index,
445  /// and another sub-register index.
446  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
448  unsigned SubIdx;
449 
450  RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
451  unsigned SubIdx = 0)
452  : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
453  };
454 
455  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
456  /// and \p DefIdx.
457  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
458  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
459  /// flag are not added to this list.
460  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
461  /// two elements:
462  /// - %1:sub1, sub0
463  /// - %2<:0>, sub1
464  ///
465  /// \returns true if it is possible to build such an input sequence
466  /// with the pair \p MI, \p DefIdx. False otherwise.
467  ///
468  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
469  ///
470  /// \note The generic implementation does not provide any support for
471  /// MI.isRegSequenceLike(). In other words, one has to override
472  /// getRegSequenceLikeInputs for target specific instructions.
473  bool
474  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
475  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
476 
477  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
478  /// and \p DefIdx.
479  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
480  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
481  /// - %1:sub1, sub0
482  ///
483  /// \returns true if it is possible to build such an input sequence
484  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
485  /// False otherwise.
486  ///
487  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
488  ///
489  /// \note The generic implementation does not provide any support for
490  /// MI.isExtractSubregLike(). In other words, one has to override
491  /// getExtractSubregLikeInputs for target specific instructions.
492  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
493  RegSubRegPairAndIdx &InputReg) const;
494 
495  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
496  /// and \p DefIdx.
497  /// \p [out] BaseReg and \p [out] InsertedReg contain
498  /// the equivalent inputs of INSERT_SUBREG.
499  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
500  /// - BaseReg: %0:sub0
501  /// - InsertedReg: %1:sub1, sub3
502  ///
503  /// \returns true if it is possible to build such an input sequence
504  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
505  /// False otherwise.
506  ///
507  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
508  ///
509  /// \note The generic implementation does not provide any support for
510  /// MI.isInsertSubregLike(). In other words, one has to override
511  /// getInsertSubregLikeInputs for target specific instructions.
512  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
513  RegSubRegPair &BaseReg,
514  RegSubRegPairAndIdx &InsertedReg) const;
515 
516  /// Return true if two machine instructions would produce identical values.
517  /// By default, this is only true when the two instructions
518  /// are deemed identical except for defs. If this function is called when the
519  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
520  /// aggressive checks.
521  virtual bool produceSameValue(const MachineInstr &MI0,
522  const MachineInstr &MI1,
523  const MachineRegisterInfo *MRI = nullptr) const;
524 
525  /// \returns true if a branch from an instruction with opcode \p BranchOpc
526  /// bytes is capable of jumping to a position \p BrOffset bytes away.
527  virtual bool isBranchOffsetInRange(unsigned BranchOpc,
528  int64_t BrOffset) const {
529  llvm_unreachable("target did not implement");
530  }
531 
532  /// \returns The block that branch instruction \p MI jumps to.
534  llvm_unreachable("target did not implement");
535  }
536 
537  /// Insert an unconditional indirect branch at the end of \p MBB to \p
538  /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
539  /// the offset of the position to insert the new branch.
540  ///
541  /// \returns The number of bytes added to the block.
543  MachineBasicBlock &NewDestBB,
544  const DebugLoc &DL,
545  int64_t BrOffset = 0,
546  RegScavenger *RS = nullptr) const {
547  llvm_unreachable("target did not implement");
548  }
549 
550  /// Analyze the branching code at the end of MBB, returning
551  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
552  /// implemented for a target). Upon success, this returns false and returns
553  /// with the following information in various cases:
554  ///
555  /// 1. If this block ends with no branches (it just falls through to its succ)
556  /// just return false, leaving TBB/FBB null.
557  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
558  /// the destination block.
559  /// 3. If this block ends with a conditional branch and it falls through to a
560  /// successor block, it sets TBB to be the branch destination block and a
561  /// list of operands that evaluate the condition. These operands can be
562  /// passed to other TargetInstrInfo methods to create new branches.
563  /// 4. If this block ends with a conditional branch followed by an
564  /// unconditional branch, it returns the 'true' destination in TBB, the
565  /// 'false' destination in FBB, and a list of operands that evaluate the
566  /// condition. These operands can be passed to other TargetInstrInfo
567  /// methods to create new branches.
568  ///
569  /// Note that removeBranch and insertBranch must be implemented to support
570  /// cases where this method returns success.
571  ///
572  /// If AllowModify is true, then this routine is allowed to modify the basic
573  /// block (e.g. delete instructions after the unconditional branch).
574  ///
575  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
576  /// before calling this function.
578  MachineBasicBlock *&FBB,
580  bool AllowModify = false) const {
581  return true;
582  }
583 
584  /// Represents a predicate at the MachineFunction level. The control flow a
585  /// MachineBranchPredicate represents is:
586  ///
587  /// Reg = LHS `Predicate` RHS == ConditionDef
588  /// if Reg then goto TrueDest else goto FalseDest
589  ///
592  PRED_EQ, // True if two values are equal
593  PRED_NE, // True if two values are not equal
594  PRED_INVALID // Sentinel value
595  };
596 
597  ComparePredicate Predicate = PRED_INVALID;
600  MachineBasicBlock *TrueDest = nullptr;
601  MachineBasicBlock *FalseDest = nullptr;
602  MachineInstr *ConditionDef = nullptr;
603 
604  /// SingleUseCondition is true if ConditionDef is dead except for the
605  /// branch(es) at the end of the basic block.
606  ///
607  bool SingleUseCondition = false;
608 
609  explicit MachineBranchPredicate() = default;
610  };
611 
612  /// Analyze the branching code at the end of MBB and parse it into the
613  /// MachineBranchPredicate structure if possible. Returns false on success
614  /// and true on failure.
615  ///
616  /// If AllowModify is true, then this routine is allowed to modify the basic
617  /// block (e.g. delete instructions after the unconditional branch).
618  ///
621  bool AllowModify = false) const {
622  return true;
623  }
624 
625  /// Remove the branching code at the end of the specific MBB.
626  /// This is only invoked in cases where AnalyzeBranch returns success. It
627  /// returns the number of instructions that were removed.
628  /// If \p BytesRemoved is non-null, report the change in code size from the
629  /// removed instructions.
630  virtual unsigned removeBranch(MachineBasicBlock &MBB,
631  int *BytesRemoved = nullptr) const {
632  llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
633  }
634 
635  /// Insert branch code into the end of the specified MachineBasicBlock. The
636  /// operands to this method are the same as those returned by AnalyzeBranch.
637  /// This is only invoked in cases where AnalyzeBranch returns success. It
638  /// returns the number of instructions inserted. If \p BytesAdded is non-null,
639  /// report the change in code size from the added instructions.
640  ///
641  /// It is also invoked by tail merging to add unconditional branches in
642  /// cases where AnalyzeBranch doesn't apply because there was no original
643  /// branch to analyze. At least this much must be implemented, else tail
644  /// merging needs to be disabled.
645  ///
646  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
647  /// before calling this function.
648  virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
649  MachineBasicBlock *FBB,
651  const DebugLoc &DL,
652  int *BytesAdded = nullptr) const {
653  llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
654  }
655 
657  MachineBasicBlock *DestBB,
658  const DebugLoc &DL,
659  int *BytesAdded = nullptr) const {
660  return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
661  BytesAdded);
662  }
663 
664  /// Analyze the loop code, return true if it cannot be understoo. Upon
665  /// success, this function returns false and returns information about the
666  /// induction variable and compare instruction used at the end.
667  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
668  MachineInstr *&CmpInst) const {
669  return true;
670  }
671 
672  /// Generate code to reduce the loop iteration by one and check if the loop
673  /// is finished. Return the value/register of the new loop count. We need
674  /// this function when peeling off one or more iterations of a loop. This
675  /// function assumes the nth iteration is peeled first.
676  virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,
677  MachineBasicBlock &PreHeader,
678  MachineInstr *IndVar, MachineInstr &Cmp,
681  unsigned Iter, unsigned MaxIter) const {
682  llvm_unreachable("Target didn't implement ReduceLoopCount");
683  }
684 
685  /// Delete the instruction OldInst and everything after it, replacing it with
686  /// an unconditional branch to NewDest. This is used by the tail merging pass.
688  MachineBasicBlock *NewDest) const;
689 
690  /// Return true if it's legal to split the given basic
691  /// block at the specified instruction (i.e. instruction would be the start
692  /// of a new basic block).
694  MachineBasicBlock::iterator MBBI) const {
695  return true;
696  }
697 
698  /// Return true if it's profitable to predicate
699  /// instructions with accumulated instruction latency of "NumCycles"
700  /// of the specified basic block, where the probability of the instructions
701  /// being executed is given by Probability, and Confidence is a measure
702  /// of our confidence that it will be properly predicted.
703  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
704  unsigned ExtraPredCycles,
705  BranchProbability Probability) const {
706  return false;
707  }
708 
709  /// Second variant of isProfitableToIfCvt. This one
710  /// checks for the case where two basic blocks from true and false path
711  /// of a if-then-else (diamond) are predicated on mutally exclusive
712  /// predicates, where the probability of the true path being taken is given
713  /// by Probability, and Confidence is a measure of our confidence that it
714  /// will be properly predicted.
715  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
716  unsigned ExtraTCycles,
717  MachineBasicBlock &FMBB, unsigned NumFCycles,
718  unsigned ExtraFCycles,
719  BranchProbability Probability) const {
720  return false;
721  }
722 
723  /// Return true if it's profitable for if-converter to duplicate instructions
724  /// of specified accumulated instruction latencies in the specified MBB to
725  /// enable if-conversion.
726  /// The probability of the instructions being executed is given by
727  /// Probability, and Confidence is a measure of our confidence that it
728  /// will be properly predicted.
730  unsigned NumCycles,
731  BranchProbability Probability) const {
732  return false;
733  }
734 
735  /// Return true if it's profitable to unpredicate
736  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
737  /// exclusive predicates.
738  /// e.g.
739  /// subeq r0, r1, #1
740  /// addne r0, r1, #1
741  /// =>
742  /// sub r0, r1, #1
743  /// addne r0, r1, #1
744  ///
745  /// This may be profitable is conditional instructions are always executed.
747  MachineBasicBlock &FMBB) const {
748  return false;
749  }
750 
751  /// Return true if it is possible to insert a select
752  /// instruction that chooses between TrueReg and FalseReg based on the
753  /// condition code in Cond.
754  ///
755  /// When successful, also return the latency in cycles from TrueReg,
756  /// FalseReg, and Cond to the destination register. In most cases, a select
757  /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
758  ///
759  /// Some x86 implementations have 2-cycle cmov instructions.
760  ///
761  /// @param MBB Block where select instruction would be inserted.
762  /// @param Cond Condition returned by AnalyzeBranch.
763  /// @param TrueReg Virtual register to select when Cond is true.
764  /// @param FalseReg Virtual register to select when Cond is false.
765  /// @param CondCycles Latency from Cond+Branch to select output.
766  /// @param TrueCycles Latency from TrueReg to select output.
767  /// @param FalseCycles Latency from FalseReg to select output.
768  virtual bool canInsertSelect(const MachineBasicBlock &MBB,
769  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
770  unsigned FalseReg, int &CondCycles,
771  int &TrueCycles, int &FalseCycles) const {
772  return false;
773  }
774 
775  /// Insert a select instruction into MBB before I that will copy TrueReg to
776  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
777  ///
778  /// This function can only be called after canInsertSelect() returned true.
779  /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
780  /// that the same flags or registers required by Cond are available at the
781  /// insertion point.
782  ///
783  /// @param MBB Block where select instruction should be inserted.
784  /// @param I Insertion point.
785  /// @param DL Source location for debugging.
786  /// @param DstReg Virtual register to be defined by select instruction.
787  /// @param Cond Condition as computed by AnalyzeBranch.
788  /// @param TrueReg Virtual register to copy when Cond is true.
789  /// @param FalseReg Virtual register to copy when Cons is false.
790  virtual void insertSelect(MachineBasicBlock &MBB,
792  unsigned DstReg, ArrayRef<MachineOperand> Cond,
793  unsigned TrueReg, unsigned FalseReg) const {
794  llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
795  }
796 
797  /// Analyze the given select instruction, returning true if
798  /// it cannot be understood. It is assumed that MI->isSelect() is true.
799  ///
800  /// When successful, return the controlling condition and the operands that
801  /// determine the true and false result values.
802  ///
803  /// Result = SELECT Cond, TrueOp, FalseOp
804  ///
805  /// Some targets can optimize select instructions, for example by predicating
806  /// the instruction defining one of the operands. Such targets should set
807  /// Optimizable.
808  ///
809  /// @param MI Select instruction to analyze.
810  /// @param Cond Condition controlling the select.
811  /// @param TrueOp Operand number of the value selected when Cond is true.
812  /// @param FalseOp Operand number of the value selected when Cond is false.
813  /// @param Optimizable Returned as true if MI is optimizable.
814  /// @returns False on success.
815  virtual bool analyzeSelect(const MachineInstr &MI,
817  unsigned &TrueOp, unsigned &FalseOp,
818  bool &Optimizable) const {
819  assert(MI.getDesc().isSelect() && "MI must be a select instruction");
820  return true;
821  }
822 
823  /// Given a select instruction that was understood by
824  /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
825  /// merging it with one of its operands. Returns NULL on failure.
826  ///
827  /// When successful, returns the new select instruction. The client is
828  /// responsible for deleting MI.
829  ///
830  /// If both sides of the select can be optimized, PreferFalse is used to pick
831  /// a side.
832  ///
833  /// @param MI Optimizable select instruction.
834  /// @param NewMIs Set that record all MIs in the basic block up to \p
835  /// MI. Has to be updated with any newly created MI or deleted ones.
836  /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
837  /// @returns Optimized instruction or NULL.
840  bool PreferFalse = false) const {
841  // This function must be implemented if Optimizable is ever set.
842  llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
843  }
844 
845  /// Emit instructions to copy a pair of physical registers.
846  ///
847  /// This function should support copies within any legal register class as
848  /// well as any cross-class copies created during instruction selection.
849  ///
850  /// The source and destination registers may overlap, which may require a
851  /// careful implementation when multiple copy instructions are required for
852  /// large registers. See for example the ARM target.
853  virtual void copyPhysReg(MachineBasicBlock &MBB,
855  unsigned DestReg, unsigned SrcReg,
856  bool KillSrc) const {
857  llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
858  }
859 
860 protected:
861  /// Target-dependent implemenation for IsCopyInstr.
862  /// If the specific machine instruction is a instruction that moves/copies
863  /// value from one register to another register return true along with
864  /// @Source machine operand and @Destination machine operand.
865  virtual bool isCopyInstrImpl(const MachineInstr &MI,
866  const MachineOperand *&Source,
867  const MachineOperand *&Destination) const {
868  return false;
869  }
870 
871 public:
872  /// If the specific machine instruction is a instruction that moves/copies
873  /// value from one register to another register return true along with
874  /// @Source machine operand and @Destination machine operand.
875  /// For COPY-instruction the method naturally returns true, for all other
876  /// instructions the method calls target-dependent implementation.
878  const MachineOperand *&Destination) const {
879  if (MI.isCopy()) {
880  Destination = &MI.getOperand(0);
881  Source = &MI.getOperand(1);
882  return true;
883  }
884  return isCopyInstrImpl(MI, Source, Destination);
885  }
886 
887  /// Store the specified register of the given register class to the specified
888  /// stack frame index. The store instruction is to be added to the given
889  /// machine basic block before the specified machine instruction. If isKill
890  /// is true, the register operand is the last use and must be marked kill.
893  unsigned SrcReg, bool isKill, int FrameIndex,
894  const TargetRegisterClass *RC,
895  const TargetRegisterInfo *TRI) const {
896  llvm_unreachable("Target didn't implement "
897  "TargetInstrInfo::storeRegToStackSlot!");
898  }
899 
900  /// Load the specified register of the given register class from the specified
901  /// stack frame index. The load instruction is to be added to the given
902  /// machine basic block before the specified machine instruction.
905  unsigned DestReg, int FrameIndex,
906  const TargetRegisterClass *RC,
907  const TargetRegisterInfo *TRI) const {
908  llvm_unreachable("Target didn't implement "
909  "TargetInstrInfo::loadRegFromStackSlot!");
910  }
911 
912  /// This function is called for all pseudo instructions
913  /// that remain after register allocation. Many pseudo instructions are
914  /// created to help register allocation. This is the place to convert them
915  /// into real instructions. The target can edit MI in place, or it can insert
916  /// new instructions and erase MI. The function should return true if
917  /// anything was changed.
918  virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
919 
920  /// Check whether the target can fold a load that feeds a subreg operand
921  /// (or a subreg operand that feeds a store).
922  /// For example, X86 may want to return true if it can fold
923  /// movl (%esp), %eax
924  /// subb, %al, ...
925  /// Into:
926  /// subb (%esp), ...
927  ///
928  /// Ideally, we'd like the target implementation of foldMemoryOperand() to
929  /// reject subregs - but since this behavior used to be enforced in the
930  /// target-independent code, moving this responsibility to the targets
931  /// has the potential of causing nasty silent breakage in out-of-tree targets.
932  virtual bool isSubregFoldable() const { return false; }
933 
934  /// Attempt to fold a load or store of the specified stack
935  /// slot into the specified machine instruction for the specified operand(s).
936  /// If this is possible, a new instruction is returned with the specified
937  /// operand folded, otherwise NULL is returned.
938  /// The new instruction is inserted before MI, and the client is responsible
939  /// for removing the old instruction.
940  /// If VRM is passed, the assigned physregs can be inspected by target to
941  /// decide on using an opcode (note that those assignments can still change).
943  int FI,
944  LiveIntervals *LIS = nullptr,
945  VirtRegMap *VRM = nullptr) const;
946 
947  /// Same as the previous version except it allows folding of any load and
948  /// store from / to any address, not just from a specific stack slot.
950  MachineInstr &LoadMI,
951  LiveIntervals *LIS = nullptr) const;
952 
953  /// Return true when there is potentially a faster code sequence
954  /// for an instruction chain ending in \p Root. All potential patterns are
955  /// returned in the \p Pattern vector. Pattern should be sorted in priority
956  /// order since the pattern evaluator stops checking as soon as it finds a
957  /// faster sequence.
958  /// \param Root - Instruction that could be combined with one of its operands
959  /// \param Patterns - Vector of possible combination patterns
960  virtual bool getMachineCombinerPatterns(
961  MachineInstr &Root,
963 
964  /// Return true when a code sequence can improve throughput. It
965  /// should be called only for instructions in loops.
966  /// \param Pattern - combiner pattern
967  virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
968 
969  /// Return true if the input \P Inst is part of a chain of dependent ops
970  /// that are suitable for reassociation, otherwise return false.
971  /// If the instruction's operands must be commuted to have a previous
972  /// instruction of the same type define the first source operand, \P Commuted
973  /// will be set to true.
974  bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
975 
976  /// Return true when \P Inst is both associative and commutative.
977  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
978  return false;
979  }
980 
981  /// Return true when \P Inst has reassociable operands in the same \P MBB.
982  virtual bool hasReassociableOperands(const MachineInstr &Inst,
983  const MachineBasicBlock *MBB) const;
984 
985  /// Return true when \P Inst has reassociable sibling.
986  bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
987 
988  /// When getMachineCombinerPatterns() finds patterns, this function generates
989  /// the instructions that could replace the original code sequence. The client
990  /// has to decide whether the actual replacement is beneficial or not.
991  /// \param Root - Instruction that could be combined with one of its operands
992  /// \param Pattern - Combination pattern for Root
993  /// \param InsInstrs - Vector of new instructions that implement P
994  /// \param DelInstrs - Old instructions, including Root, that could be
995  /// replaced by InsInstr
996  /// \param InstIdxForVirtReg - map of virtual register to instruction in
997  /// InsInstr that defines it
998  virtual void genAlternativeCodeSequence(
999  MachineInstr &Root, MachineCombinerPattern Pattern,
1002  DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1003 
1004  /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1005  /// reduce critical path length.
1006  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
1007  MachineCombinerPattern Pattern,
1010  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1011 
1012  /// This is an architecture-specific helper function of reassociateOps.
1013  /// Set special operand attributes for new instructions after reassociation.
1014  virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1015  MachineInstr &NewMI1,
1016  MachineInstr &NewMI2) const {}
1017 
1018  /// Return true when a target supports MachineCombiner.
1019  virtual bool useMachineCombiner() const { return false; }
1020 
1021  /// Return true if the given SDNode can be copied during scheduling
1022  /// even if it has glue.
1023  virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1024 
1025 protected:
1026  /// Target-dependent implementation for foldMemoryOperand.
1027  /// Target-independent code in foldMemoryOperand will
1028  /// take care of adding a MachineMemOperand to the newly created instruction.
1029  /// The instruction and any auxiliary instructions necessary will be inserted
1030  /// at InsertPt.
1031  virtual MachineInstr *
1033  ArrayRef<unsigned> Ops,
1035  LiveIntervals *LIS = nullptr,
1036  VirtRegMap *VRM = nullptr) const {
1037  return nullptr;
1038  }
1039 
1040  /// Target-dependent implementation for foldMemoryOperand.
1041  /// Target-independent code in foldMemoryOperand will
1042  /// take care of adding a MachineMemOperand to the newly created instruction.
1043  /// The instruction and any auxiliary instructions necessary will be inserted
1044  /// at InsertPt.
1047  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1048  LiveIntervals *LIS = nullptr) const {
1049  return nullptr;
1050  }
1051 
1052  /// Target-dependent implementation of getRegSequenceInputs.
1053  ///
1054  /// \returns true if it is possible to build the equivalent
1055  /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1056  ///
1057  /// \pre MI.isRegSequenceLike().
1058  ///
1059  /// \see TargetInstrInfo::getRegSequenceInputs.
1061  const MachineInstr &MI, unsigned DefIdx,
1062  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1063  return false;
1064  }
1065 
1066  /// Target-dependent implementation of getExtractSubregInputs.
1067  ///
1068  /// \returns true if it is possible to build the equivalent
1069  /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1070  ///
1071  /// \pre MI.isExtractSubregLike().
1072  ///
1073  /// \see TargetInstrInfo::getExtractSubregInputs.
1075  unsigned DefIdx,
1076  RegSubRegPairAndIdx &InputReg) const {
1077  return false;
1078  }
1079 
1080  /// Target-dependent implementation of getInsertSubregInputs.
1081  ///
1082  /// \returns true if it is possible to build the equivalent
1083  /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1084  ///
1085  /// \pre MI.isInsertSubregLike().
1086  ///
1087  /// \see TargetInstrInfo::getInsertSubregInputs.
1088  virtual bool
1089  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1090  RegSubRegPair &BaseReg,
1091  RegSubRegPairAndIdx &InsertedReg) const {
1092  return false;
1093  }
1094 
1095 public:
1096  /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1097  /// (e.g. stack) the target returns the corresponding address space.
1098  virtual unsigned
1100  return 0;
1101  }
1102 
1103  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1104  /// a store or a load and a store into two or more instruction. If this is
1105  /// possible, returns true as well as the new instructions by reference.
1106  virtual bool
1108  bool UnfoldLoad, bool UnfoldStore,
1109  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1110  return false;
1111  }
1112 
1114  SmallVectorImpl<SDNode *> &NewNodes) const {
1115  return false;
1116  }
1117 
1118  /// Returns the opcode of the would be new
1119  /// instruction after load / store are unfolded from an instruction of the
1120  /// specified opcode. It returns zero if the specified unfolding is not
1121  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1122  /// index of the operand which will hold the register holding the loaded
1123  /// value.
1124  virtual unsigned
1125  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1126  unsigned *LoadRegIndex = nullptr) const {
1127  return 0;
1128  }
1129 
1130  /// This is used by the pre-regalloc scheduler to determine if two loads are
1131  /// loading from the same base address. It should only return true if the base
1132  /// pointers are the same and the only differences between the two addresses
1133  /// are the offset. It also returns the offsets by reference.
1134  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1135  int64_t &Offset1,
1136  int64_t &Offset2) const {
1137  return false;
1138  }
1139 
1140  /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1141  /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1142  /// On some targets if two loads are loading from
1143  /// addresses in the same cache line, it's better if they are scheduled
1144  /// together. This function takes two integers that represent the load offsets
1145  /// from the common base address. It returns true if it decides it's desirable
1146  /// to schedule the two loads together. "NumLoads" is the number of loads that
1147  /// have already been scheduled after Load1.
1148  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1149  int64_t Offset1, int64_t Offset2,
1150  unsigned NumLoads) const {
1151  return false;
1152  }
1153 
1154  /// Get the base operand and byte offset of an instruction that reads/writes
1155  /// memory.
1156  virtual bool getMemOperandWithOffset(const MachineInstr &MI,
1157  const MachineOperand *&BaseOp,
1158  int64_t &Offset,
1159  const TargetRegisterInfo *TRI) const {
1160  return false;
1161  }
1162 
1163  /// Return true if the instruction contains a base register and offset. If
1164  /// true, the function also sets the operand position in the instruction
1165  /// for the base register and offset.
1166  virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1167  unsigned &BasePos,
1168  unsigned &OffsetPos) const {
1169  return false;
1170  }
1171 
1172  /// If the instruction is an increment of a constant value, return the amount.
1173  virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1174  return false;
1175  }
1176 
1177  /// Returns true if the two given memory operations should be scheduled
1178  /// adjacent. Note that you have to add:
1179  /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1180  /// or
1181  /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1182  /// to TargetPassConfig::createMachineScheduler() to have an effect.
1183  virtual bool shouldClusterMemOps(const MachineOperand &BaseOp1,
1184  const MachineOperand &BaseOp2,
1185  unsigned NumLoads) const {
1186  llvm_unreachable("target did not implement shouldClusterMemOps()");
1187  }
1188 
1189  /// Reverses the branch condition of the specified condition list,
1190  /// returning false on success and true if it cannot be reversed.
1191  virtual bool
1193  return true;
1194  }
1195 
1196  /// Insert a noop into the instruction stream at the specified point.
1197  virtual void insertNoop(MachineBasicBlock &MBB,
1198  MachineBasicBlock::iterator MI) const;
1199 
1200  /// Return the noop instruction to use for a noop.
1201  virtual void getNoop(MCInst &NopInst) const;
1202 
1203  /// Return true for post-incremented instructions.
1204  virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1205 
1206  /// Returns true if the instruction is already predicated.
1207  virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1208 
1209  /// Returns true if the instruction is a
1210  /// terminator instruction that has not been predicated.
1211  virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1212 
1213  /// Returns true if MI is an unconditional tail call.
1214  virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1215  return false;
1216  }
1217 
1218  /// Returns true if the tail call can be made conditional on BranchCond.
1220  const MachineInstr &TailCall) const {
1221  return false;
1222  }
1223 
1224  /// Replace the conditional branch in MBB with a conditional tail call.
1227  const MachineInstr &TailCall) const {
1228  llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1229  }
1230 
1231  /// Convert the instruction into a predicated instruction.
1232  /// It returns true if the operation was successful.
1233  virtual bool PredicateInstruction(MachineInstr &MI,
1234  ArrayRef<MachineOperand> Pred) const;
1235 
1236  /// Returns true if the first specified predicate
1237  /// subsumes the second, e.g. GE subsumes GT.
1239  ArrayRef<MachineOperand> Pred2) const {
1240  return false;
1241  }
1242 
1243  /// If the specified instruction defines any predicate
1244  /// or condition code register(s) used for predication, returns true as well
1245  /// as the definition predicate(s) by reference.
1246  virtual bool DefinesPredicate(MachineInstr &MI,
1247  std::vector<MachineOperand> &Pred) const {
1248  return false;
1249  }
1250 
1251  /// Return true if the specified instruction can be predicated.
1252  /// By default, this returns true for every instruction with a
1253  /// PredicateOperand.
1254  virtual bool isPredicable(const MachineInstr &MI) const {
1255  return MI.getDesc().isPredicable();
1256  }
1257 
1258  /// Return true if it's safe to move a machine
1259  /// instruction that defines the specified register class.
1260  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1261  return true;
1262  }
1263 
1264  /// Test if the given instruction should be considered a scheduling boundary.
1265  /// This primarily includes labels and terminators.
1266  virtual bool isSchedulingBoundary(const MachineInstr &MI,
1267  const MachineBasicBlock *MBB,
1268  const MachineFunction &MF) const;
1269 
1270  /// Measure the specified inline asm to determine an approximation of its
1271  /// length.
1272  virtual unsigned getInlineAsmLength(
1273  const char *Str, const MCAsmInfo &MAI,
1274  const TargetSubtargetInfo *STI = nullptr) const;
1275 
1276  /// Allocate and return a hazard recognizer to use for this target when
1277  /// scheduling the machine instructions before register allocation.
1278  virtual ScheduleHazardRecognizer *
1280  const ScheduleDAG *DAG) const;
1281 
1282  /// Allocate and return a hazard recognizer to use for this target when
1283  /// scheduling the machine instructions before register allocation.
1284  virtual ScheduleHazardRecognizer *
1286  const ScheduleDAG *DAG) const;
1287 
1288  /// Allocate and return a hazard recognizer to use for this target when
1289  /// scheduling the machine instructions after register allocation.
1290  virtual ScheduleHazardRecognizer *
1292  const ScheduleDAG *DAG) const;
1293 
1294  /// Allocate and return a hazard recognizer to use for by non-scheduling
1295  /// passes.
1296  virtual ScheduleHazardRecognizer *
1298  return nullptr;
1299  }
1300 
1301  /// Provide a global flag for disabling the PreRA hazard recognizer that
1302  /// targets may choose to honor.
1303  bool usePreRAHazardRecognizer() const;
1304 
1305  /// For a comparison instruction, return the source registers
1306  /// in SrcReg and SrcReg2 if having two register operands, and the value it
1307  /// compares against in CmpValue. Return true if the comparison instruction
1308  /// can be analyzed.
1309  virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1310  unsigned &SrcReg2, int &Mask, int &Value) const {
1311  return false;
1312  }
1313 
1314  /// See if the comparison instruction can be converted
1315  /// into something more efficient. E.g., on ARM most instructions can set the
1316  /// flags register, obviating the need for a separate CMP.
1317  virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1318  unsigned SrcReg2, int Mask, int Value,
1319  const MachineRegisterInfo *MRI) const {
1320  return false;
1321  }
1322  virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1323 
1324  /// Try to remove the load by folding it to a register operand at the use.
1325  /// We fold the load instructions if and only if the
1326  /// def and use are in the same BB. We only look at one load and see
1327  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1328  /// defined by the load we are trying to fold. DefMI returns the machine
1329  /// instruction that defines FoldAsLoadDefReg, and the function returns
1330  /// the machine instruction generated due to folding.
1332  const MachineRegisterInfo *MRI,
1333  unsigned &FoldAsLoadDefReg,
1334  MachineInstr *&DefMI) const {
1335  return nullptr;
1336  }
1337 
1338  /// 'Reg' is known to be defined by a move immediate instruction,
1339  /// try to fold the immediate into the use instruction.
1340  /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1341  /// then the caller may assume that DefMI has been erased from its parent
1342  /// block. The caller may assume that it will not be erased by this
1343  /// function otherwise.
1345  unsigned Reg, MachineRegisterInfo *MRI) const {
1346  return false;
1347  }
1348 
1349  /// Return the number of u-operations the given machine
1350  /// instruction will be decoded to on the target cpu. The itinerary's
1351  /// IssueWidth is the number of microops that can be dispatched each
1352  /// cycle. An instruction with zero microops takes no dispatch resources.
1353  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1354  const MachineInstr &MI) const;
1355 
1356  /// Return true for pseudo instructions that don't consume any
1357  /// machine resources in their current form. These are common cases that the
1358  /// scheduler should consider free, rather than conservatively handling them
1359  /// as instructions with no itinerary.
1360  bool isZeroCost(unsigned Opcode) const {
1361  return Opcode <= TargetOpcode::COPY;
1362  }
1363 
1364  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1365  SDNode *DefNode, unsigned DefIdx,
1366  SDNode *UseNode, unsigned UseIdx) const;
1367 
1368  /// Compute and return the use operand latency of a given pair of def and use.
1369  /// In most cases, the static scheduling itinerary was enough to determine the
1370  /// operand latency. But it may not be possible for instructions with variable
1371  /// number of defs / uses.
1372  ///
1373  /// This is a raw interface to the itinerary that may be directly overridden
1374  /// by a target. Use computeOperandLatency to get the best estimate of
1375  /// latency.
1376  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1377  const MachineInstr &DefMI, unsigned DefIdx,
1378  const MachineInstr &UseMI,
1379  unsigned UseIdx) const;
1380 
1381  /// Compute the instruction latency of a given instruction.
1382  /// If the instruction has higher cost when predicated, it's returned via
1383  /// PredCost.
1384  virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1385  const MachineInstr &MI,
1386  unsigned *PredCost = nullptr) const;
1387 
1388  virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1389 
1390  virtual int getInstrLatency(const InstrItineraryData *ItinData,
1391  SDNode *Node) const;
1392 
1393  /// Return the default expected latency for a def based on its opcode.
1394  unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1395  const MachineInstr &DefMI) const;
1396 
1397  int computeDefOperandLatency(const InstrItineraryData *ItinData,
1398  const MachineInstr &DefMI) const;
1399 
1400  /// Return true if this opcode has high latency to its result.
1401  virtual bool isHighLatencyDef(int opc) const { return false; }
1402 
1403  /// Compute operand latency between a def of 'Reg'
1404  /// and a use in the current loop. Return true if the target considered
1405  /// it 'high'. This is used by optimization passes such as machine LICM to
1406  /// determine whether it makes sense to hoist an instruction out even in a
1407  /// high register pressure situation.
1408  virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1409  const MachineRegisterInfo *MRI,
1410  const MachineInstr &DefMI, unsigned DefIdx,
1411  const MachineInstr &UseMI,
1412  unsigned UseIdx) const {
1413  return false;
1414  }
1415 
1416  /// Compute operand latency of a def of 'Reg'. Return true
1417  /// if the target considered it 'low'.
1418  virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1419  const MachineInstr &DefMI,
1420  unsigned DefIdx) const;
1421 
1422  /// Perform target-specific instruction verification.
1423  virtual bool verifyInstruction(const MachineInstr &MI,
1424  StringRef &ErrInfo) const {
1425  return true;
1426  }
1427 
1428  /// Return the current execution domain and bit mask of
1429  /// possible domains for instruction.
1430  ///
1431  /// Some micro-architectures have multiple execution domains, and multiple
1432  /// opcodes that perform the same operation in different domains. For
1433  /// example, the x86 architecture provides the por, orps, and orpd
1434  /// instructions that all do the same thing. There is a latency penalty if a
1435  /// register is written in one domain and read in another.
1436  ///
1437  /// This function returns a pair (domain, mask) containing the execution
1438  /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1439  /// function can be used to change the opcode to one of the domains in the
1440  /// bit mask. Instructions whose execution domain can't be changed should
1441  /// return a 0 mask.
1442  ///
1443  /// The execution domain numbers don't have any special meaning except domain
1444  /// 0 is used for instructions that are not associated with any interesting
1445  /// execution domain.
1446  ///
1447  virtual std::pair<uint16_t, uint16_t>
1449  return std::make_pair(0, 0);
1450  }
1451 
1452  /// Change the opcode of MI to execute in Domain.
1453  ///
1454  /// The bit (1 << Domain) must be set in the mask returned from
1455  /// getExecutionDomain(MI).
1456  virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1457 
1458  /// Returns the preferred minimum clearance
1459  /// before an instruction with an unwanted partial register update.
1460  ///
1461  /// Some instructions only write part of a register, and implicitly need to
1462  /// read the other parts of the register. This may cause unwanted stalls
1463  /// preventing otherwise unrelated instructions from executing in parallel in
1464  /// an out-of-order CPU.
1465  ///
1466  /// For example, the x86 instruction cvtsi2ss writes its result to bits
1467  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1468  /// the instruction needs to wait for the old value of the register to become
1469  /// available:
1470  ///
1471  /// addps %xmm1, %xmm0
1472  /// movaps %xmm0, (%rax)
1473  /// cvtsi2ss %rbx, %xmm0
1474  ///
1475  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1476  /// instruction before it can issue, even though the high bits of %xmm0
1477  /// probably aren't needed.
1478  ///
1479  /// This hook returns the preferred clearance before MI, measured in
1480  /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1481  /// instructions before MI. It should only return a positive value for
1482  /// unwanted dependencies. If the old bits of the defined register have
1483  /// useful values, or if MI is determined to otherwise read the dependency,
1484  /// the hook should return 0.
1485  ///
1486  /// The unwanted dependency may be handled by:
1487  ///
1488  /// 1. Allocating the same register for an MI def and use. That makes the
1489  /// unwanted dependency identical to a required dependency.
1490  ///
1491  /// 2. Allocating a register for the def that has no defs in the previous N
1492  /// instructions.
1493  ///
1494  /// 3. Calling breakPartialRegDependency() with the same arguments. This
1495  /// allows the target to insert a dependency breaking instruction.
1496  ///
1497  virtual unsigned
1498  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1499  const TargetRegisterInfo *TRI) const {
1500  // The default implementation returns 0 for no partial register dependency.
1501  return 0;
1502  }
1503 
1504  /// Return the minimum clearance before an instruction that reads an
1505  /// unused register.
1506  ///
1507  /// For example, AVX instructions may copy part of a register operand into
1508  /// the unused high bits of the destination register.
1509  ///
1510  /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1511  ///
1512  /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1513  /// false dependence on any previous write to %xmm0.
1514  ///
1515  /// This hook works similarly to getPartialRegUpdateClearance, except that it
1516  /// does not take an operand index. Instead sets \p OpNum to the index of the
1517  /// unused register.
1518  virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1519  const TargetRegisterInfo *TRI) const {
1520  // The default implementation returns 0 for no undef register dependency.
1521  return 0;
1522  }
1523 
1524  /// Insert a dependency-breaking instruction
1525  /// before MI to eliminate an unwanted dependency on OpNum.
1526  ///
1527  /// If it wasn't possible to avoid a def in the last N instructions before MI
1528  /// (see getPartialRegUpdateClearance), this hook will be called to break the
1529  /// unwanted dependency.
1530  ///
1531  /// On x86, an xorps instruction can be used as a dependency breaker:
1532  ///
1533  /// addps %xmm1, %xmm0
1534  /// movaps %xmm0, (%rax)
1535  /// xorps %xmm0, %xmm0
1536  /// cvtsi2ss %rbx, %xmm0
1537  ///
1538  /// An <imp-kill> operand should be added to MI if an instruction was
1539  /// inserted. This ties the instructions together in the post-ra scheduler.
1540  ///
1541  virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1542  const TargetRegisterInfo *TRI) const {}
1543 
1544  /// Create machine specific model for scheduling.
1545  virtual DFAPacketizer *
1547  return nullptr;
1548  }
1549 
1550  /// Sometimes, it is possible for the target
1551  /// to tell, even without aliasing information, that two MIs access different
1552  /// memory addresses. This function returns true if two MIs access different
1553  /// memory addresses and false otherwise.
1554  ///
1555  /// Assumes any physical registers used to compute addresses have the same
1556  /// value for both instructions. (This is the most useful assumption for
1557  /// post-RA scheduling.)
1558  ///
1559  /// See also MachineInstr::mayAlias, which is implemented on top of this
1560  /// function.
1561  virtual bool
1563  const MachineInstr &MIb,
1564  AliasAnalysis *AA = nullptr) const {
1565  assert((MIa.mayLoad() || MIa.mayStore()) &&
1566  "MIa must load from or modify a memory location");
1567  assert((MIb.mayLoad() || MIb.mayStore()) &&
1568  "MIb must load from or modify a memory location");
1569  return false;
1570  }
1571 
1572  /// Return the value to use for the MachineCSE's LookAheadLimit,
1573  /// which is a heuristic used for CSE'ing phys reg defs.
1574  virtual unsigned getMachineCSELookAheadLimit() const {
1575  // The default lookahead is small to prevent unprofitable quadratic
1576  // behavior.
1577  return 5;
1578  }
1579 
1580  /// Return an array that contains the ids of the target indices (used for the
1581  /// TargetIndex machine operand) and their names.
1582  ///
1583  /// MIR Serialization is able to serialize only the target indices that are
1584  /// defined by this method.
1587  return None;
1588  }
1589 
1590  /// Decompose the machine operand's target flags into two values - the direct
1591  /// target flag value and any of bit flags that are applied.
1592  virtual std::pair<unsigned, unsigned>
1593  decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1594  return std::make_pair(0u, 0u);
1595  }
1596 
1597  /// Return an array that contains the direct target flag values and their
1598  /// names.
1599  ///
1600  /// MIR Serialization is able to serialize only the target flags that are
1601  /// defined by this method.
1604  return None;
1605  }
1606 
1607  /// Return an array that contains the bitmask target flag values and their
1608  /// names.
1609  ///
1610  /// MIR Serialization is able to serialize only the target flags that are
1611  /// defined by this method.
1614  return None;
1615  }
1616 
1617  /// Return an array that contains the MMO target flag values and their
1618  /// names.
1619  ///
1620  /// MIR Serialization is able to serialize only the MMO target flags that are
1621  /// defined by this method.
1624  return None;
1625  }
1626 
1627  /// Determines whether \p Inst is a tail call instruction. Override this
1628  /// method on targets that do not properly set MCID::Return and MCID::Call on
1629  /// tail call instructions."
1630  virtual bool isTailCall(const MachineInstr &Inst) const {
1631  return Inst.isReturn() && Inst.isCall();
1632  }
1633 
1634  /// True if the instruction is bound to the top of its basic block and no
1635  /// other instructions shall be inserted before it. This can be implemented
1636  /// to prevent register allocator to insert spills before such instructions.
1637  virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1638  return false;
1639  }
1640 
1641  /// Returns a \p outliner::OutlinedFunction struct containing target-specific
1642  /// information for a set of outlining candidates.
1644  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
1646  "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
1647  }
1648 
1649  /// Returns how or if \p MI should be outlined.
1650  virtual outliner::InstrType
1651  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
1653  "Target didn't implement TargetInstrInfo::getOutliningType!");
1654  }
1655 
1656  /// Optional target hook that returns true if \p MBB is safe to outline from,
1657  /// and returns any target-specific information in \p Flags.
1659  unsigned &Flags) const {
1660  return true;
1661  }
1662 
1663  /// Insert a custom frame for outlined functions.
1665  const outliner::OutlinedFunction &OF) const {
1667  "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
1668  }
1669 
1670  /// Insert a call to an outlined function into the program.
1671  /// Returns an iterator to the spot where we inserted the call. This must be
1672  /// implemented by the target.
1676  const outliner::Candidate &C) const {
1678  "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1679  }
1680 
1681  /// Return true if the function can safely be outlined from.
1682  /// A function \p MF is considered safe for outlining if an outlined function
1683  /// produced from instructions in F will produce a program which produces the
1684  /// same output for any set of given inputs.
1686  bool OutlineFromLinkOnceODRs) const {
1687  llvm_unreachable("Target didn't implement "
1688  "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1689  }
1690 
1691  /// Return true if the function should be outlined from by default.
1693  return false;
1694  }
1695 
1696  /// Produce the expression describing the \p MI loading a value into
1697  /// the parameter's forwarding register.
1699  describeLoadedValue(const MachineInstr &MI) const;
1700 
1701 private:
1702  unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1703  unsigned CatchRetOpcode;
1704  unsigned ReturnOpcode;
1705 };
1706 
1707 /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1710 
1712  return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1713  RegInfo::getEmptyKey());
1714  }
1715 
1717  return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1718  RegInfo::getTombstoneKey());
1719  }
1720 
1721  /// Reuse getHashValue implementation from
1722  /// std::pair<unsigned, unsigned>.
1723  static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1724  std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1725  return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1726  }
1727 
1728  static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1729  const TargetInstrInfo::RegSubRegPair &RHS) {
1730  return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1731  RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1732  }
1733 };
1734 
1735 } // end namespace llvm
1736 
1737 #endif // LLVM_TARGET_TARGETINSTRINFO_H
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned) const
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
uint64_t CallInst * C
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:722
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val)
Reuse getHashValue implementation from std::pair<unsigned, unsigned>.
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:651
static TargetInstrInfo::RegSubRegPair getTombstoneKey()
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true...
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it&#39;s safe to move a machine instruction that defines the specified register class...
virtual bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const
Target-dependent implemenation for IsCopyInstr.
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const
Generate code to reduce the loop iteration by one and check if the loop is finished.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
RegSubRegPair(unsigned Reg=0, unsigned SubReg=0)
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
virtual bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient. ...
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
virtual bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore...
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when Inst has reassociable operands in the same MBB.
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
unsigned getCallFrameDestroyOpcode() const
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
static bool isGenericOpcode(unsigned Opc)
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
An individual sequence of instructions to be replaced with a call to an outlined function.
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Represents a predicate at the MachineFunction level.
virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE&#39;s LookAheadLimit, which is a heuristic used for CSE&#39;ing ph...
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack...
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const
Return an array that contains the bitmask target flag values and their names.
virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented...
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified &#39;original&#39; instruction at the specific location targeting a new destination re...
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const
Insert a call to an outlined function into the program.
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
Provide an instruction scheduling machine model to CodeGen passes.
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const
&#39;Reg&#39; is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr *> &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool operator!=(const RegSubRegPair &P) const
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of &#39;Reg&#39;.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
virtual MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
virtual bool isBasicBlockPrologue(const MachineInstr &MI) const
True if the instruction is bound to the top of its basic block and no other instructions shall be ins...
unsigned getCatchReturnOpcode() const
virtual bool shouldClusterMemOps(const MachineOperand &BaseOp1, const MachineOperand &BaseOp2, unsigned NumLoads) const
Returns true if the two given memory operations should be scheduled adjacent.
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:335
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
static bool isEqual(const Function &Caller, const Function &Callee)
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode *> &NewNodes) const
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:500
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
Return true if it&#39;s profitable to predicate instructions with accumulated instruction latency of "Num...
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Itinerary data supplied by a subtarget to be used by a target.
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
RegSubRegPairAndIdx(unsigned Reg=0, unsigned SubReg=0, unsigned SubIdx=0)
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
TargetInstrInfo & operator=(const TargetInstrInfo &)=delete
virtual MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
BasicBlockListType::iterator iterator
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
Return true if the function can safely be outlined from.
TargetInstrInfo - Interface to description of machine instruction set.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:641
virtual void getNoop(MCInst &NopInst) const
Return the noop instruction to use for a noop.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
TargetInstrInfo::RegSubRegPair RegSubRegPair
virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const
Return true if the function should be outlined from by default.
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor...
bool operator==(const RegSubRegPair &P) const
static const unsigned CommuteAnyOperandIndex
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:838
#define P(N)
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
unsigned const MachineRegisterInfo * MRI
virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const
virtual unsigned getPredicationCost(const MachineInstr &MI) const
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
InstrType
Represents how an instruction should be mapped by the outliner.
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
MachineInstrBuilder & UseMI
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it&#39;s legal to split the given basic block at the specified instruction (i...
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack...
The information necessary to create an outlined function for some class of candidate.
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const
Returns how or if MI should be outlined.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
Contains all data structures shared between the outliner implemented in MachineOutliner.cpp and target implementations of the outliner.
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const
Allocate and return a hazard recognizer to use for by non-scheduling passes.
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input Inst is part of a chain of dependent ops that are suitable for reassociatio...
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
A set of register units.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:322
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister...
bool isCopy() const
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Returns true if the tail call can be made conditional on BranchCond.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
virtual bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
virtual unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const
getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
virtual bool optimizeCondBranch(MachineInstr &MI) const
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const
Insert a custom frame for outlined functions.
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate Root and Prev according to Pattern to reduce critical path length...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
MachineOperand class - Representation of each machine instruction operand.
A pair composed of a register and a sub-register index.
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of &#39;Reg&#39; and a use in the current loop.
MachineInstrBuilder MachineInstrBuilder & DefMI
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Represents one node in the SelectionDAG.
virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
virtual bool isTailCall(const MachineInstr &Inst) const
Determines whether Inst is a tail call instruction.
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
int64_t getImm() const
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
unsigned getReturnOpcode() const
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI) const
Produce the expression describing the MI loading a value into the parameter&#39;s forwarding register...
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Representation of each machine instruction.
Definition: MachineInstr.h:64
static TargetInstrInfo::RegSubRegPair getEmptyKey()
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand...
virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
Analyze the loop code, return true if it cannot be understoo.
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1...
bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum...
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don&#39;t consume any machine resources in their current form...
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const
Return the current execution domain and bit mask of possible domains for instruction.
uint32_t Size
Definition: Profile.cpp:46
virtual MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
virtual bool isSubregFoldable() const
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:825
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isFrameSetup(const MachineInstr &I) const
Returns true if the argument is a frame setup pseudo instruction.
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
Second variant of isProfitableToIfCvt.
LLVM Value Representation.
Definition: Value.h:73
virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when Inst has reassociable sibling.
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when Inst is both associative and commutative.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Replace the conditional branch in MBB with a conditional tail call.
IRTranslator LLVM IR MI
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const
Returns true if MI is an unconditional tail call.
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const
Return true if the given SDNode can be copied during scheduling even if it has glue.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
bool isTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
virtual outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outli...
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, const TargetInstrInfo::RegSubRegPair &RHS)
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it&#39;s profitable to unpredicate one side of a &#39;diamond&#39;, i.e.
int computeDefOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI) const
If we can determine the operand latency from the def only, without itinerary lookup, do so.
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:935
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence...
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register. ...
A pair composed of a pair of a register and a sub-register index, and another sub-register index...