29#define DEBUG_TYPE "riscv-fold-masks"
44 MachineFunctionProperties::Property::IsSSA);
61char RISCVFoldMasks::ID = 0;
66 assert(MaskDef && MaskDef->isCopy() &&
67 MaskDef->getOperand(0).getReg() == RISCV::V0);
68 Register SrcReg =
TRI->lookThruCopyLike(MaskDef->getOperand(1).getReg(),
MRI);
71 MaskDef =
MRI->getVRegDef(SrcReg);
78 switch (MaskDef->getOpcode()) {
79 case RISCV::PseudoVMSET_M_B1:
80 case RISCV::PseudoVMSET_M_B2:
81 case RISCV::PseudoVMSET_M_B4:
82 case RISCV::PseudoVMSET_M_B8:
83 case RISCV::PseudoVMSET_M_B16:
84 case RISCV::PseudoVMSET_M_B32:
85 case RISCV::PseudoVMSET_M_B64:
95#define CASE_VMERGE_TO_VMV(lmul) \
96 case RISCV::PseudoVMERGE_VVM_##lmul: \
97 NewOpc = RISCV::PseudoVMV_V_V_##lmul; \
100 switch (
MI.getOpcode()) {
112 Register MergeReg =
MI.getOperand(1).getReg();
113 Register FalseReg =
MI.getOperand(2).getReg();
115 if (MergeReg != RISCV::NoRegister &&
TRI->lookThruCopyLike(MergeReg,
MRI) !=
116 TRI->lookThruCopyLike(FalseReg,
MRI))
119 assert(
MI.getOperand(4).isReg() &&
MI.getOperand(4).getReg() == RISCV::V0);
120 if (!isAllOnesMask(V0Defs.lookup(&
MI)))
123 MI.setDesc(
TII->get(NewOpc));
125 MI.tieOperands(0, 1);
132 MRI->recomputeRegClass(
MI.getOperand(0).getReg());
133 MRI->recomputeRegClass(
MI.getOperand(1).getReg());
139 RISCV::getMaskedPseudoInfo(
MI.getOpcode());
143 if (!isAllOnesMask(V0Defs.lookup(&
MI)))
148 const unsigned Opc =
I->UnmaskedPseudo;
150 [[maybe_unused]]
const bool HasPolicyOp =
157 "Masked and unmasked pseudos are inconsistent");
158 assert(HasPolicyOp == HasPassthru &&
"Unexpected pseudo structure");
165 unsigned MaskOpIdx =
I->MaskOpIdx +
MI.getNumExplicitDefs();
166 MI.removeOperand(MaskOpIdx);
170 MRI->recomputeRegClass(
MI.getOperand(0).getReg());
171 unsigned PassthruOpIdx =
MI.getNumExplicitDefs();
173 if (
MI.getOperand(PassthruOpIdx).getReg() != RISCV::NoRegister)
174 MRI->recomputeRegClass(
MI.getOperand(PassthruOpIdx).getReg());
176 MI.removeOperand(PassthruOpIdx);
187 if (!
ST.hasVInstructions())
190 TII =
ST.getInstrInfo();
192 TRI =
MRI->getTargetRegisterInfo();
194 bool Changed =
false;
206 if (
MI.readsRegister(RISCV::V0,
TRI))
207 V0Defs[&
MI] = CurrentV0Def;
209 if (
MI.definesRegister(RISCV::V0,
TRI))
216 Changed |= convertToUnmasked(
MI);
217 Changed |= convertVMergeToVMv(
MI);
unsigned const MachineRegisterInfo * MRI
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
#define CASE_VMERGE_TO_VMV(lmul)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass class - This class is used to implement most global optimizations.
Describe properties that are true of each instruction in the target description file.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
static MachineOperand CreateImm(int64_t Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ TAIL_UNDISTURBED_MASK_UNDISTURBED
static bool hasVecPolicyOp(uint64_t TSFlags)
static bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc)
This is an optimization pass for GlobalISel generic memory operations.
unsigned M1(unsigned Val)
FunctionPass * createRISCVFoldMasksPass()