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SIRegisterInfo.h
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1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIRegisterInfo
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 
17 #include "AMDGPURegisterInfo.h"
18 #include "SIDefines.h"
20 
21 namespace llvm {
22 
23 class GCNSubtarget;
24 class LiveIntervals;
25 class MachineRegisterInfo;
26 class SIMachineFunctionInfo;
27 
28 class SIRegisterInfo final : public AMDGPURegisterInfo {
29 private:
30  const GCNSubtarget &ST;
31  unsigned SGPRSetID;
32  unsigned VGPRSetID;
33  unsigned AGPRSetID;
34  BitVector SGPRPressureSets;
35  BitVector VGPRPressureSets;
36  BitVector AGPRPressureSets;
37  bool SpillSGPRToVGPR;
38  bool SpillSGPRToSMEM;
39  bool isWave32;
40 
41  void classifyPressureSet(unsigned PSetID, unsigned Reg,
42  BitVector &PressureSets) const;
43 public:
44  SIRegisterInfo(const GCNSubtarget &ST);
45 
46  bool spillSGPRToVGPR() const {
47  return SpillSGPRToVGPR;
48  }
49 
50  bool spillSGPRToSMEM() const {
51  return SpillSGPRToSMEM;
52  }
53 
54  /// Return the end register initially reserved for the scratch buffer in case
55  /// spilling is needed.
56  unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
57 
58  /// Return the end register initially reserved for the scratch wave offset in
59  /// case spilling is needed.
61  const MachineFunction &MF) const;
62 
63  BitVector getReservedRegs(const MachineFunction &MF) const override;
64 
65  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
66  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
68  CallingConv::ID) const override;
69 
70  // Stack access is very expensive. CSRs are also the high registers, and we
71  // want to minimize the number of used registers.
72  unsigned getCSRFirstUseCost() const override {
73  return 100;
74  }
75 
76  Register getFrameRegister(const MachineFunction &MF) const override;
77 
78  bool canRealignStack(const MachineFunction &MF) const override;
79  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
80 
81  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
83  const MachineFunction &MF) const override;
84  bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
85  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
86 
87  int64_t getMUBUFInstrOffset(const MachineInstr *MI) const;
88 
89  int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
90  int Idx) const override;
91 
92  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
93 
95  unsigned BaseReg, int FrameIdx,
96  int64_t Offset) const override;
97 
98  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
99  int64_t Offset) const override;
100 
101  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
102  int64_t Offset) const override;
103 
105  const MachineFunction &MF, unsigned Kind = 0) const override;
106 
107  /// If \p OnlyToVGPR is true, this will only succeed if this
109  int FI, RegScavenger *RS,
110  bool OnlyToVGPR = false) const;
111 
113  int FI, RegScavenger *RS,
114  bool OnlyToVGPR = false) const;
115 
117  unsigned FIOperandNum,
118  RegScavenger *RS) const override;
119 
121  int FI, RegScavenger *RS) const;
122 
123  StringRef getRegAsmName(unsigned Reg) const override;
124 
125  unsigned getHWRegIndex(unsigned Reg) const {
126  return getEncodingValue(Reg) & 0xff;
127  }
128 
129  /// Return the 'base' register class for this register.
130  /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
131  const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
132 
133  /// \returns true if this class contains only SGPR registers
134  bool isSGPRClass(const TargetRegisterClass *RC) const {
135  return !hasVGPRs(RC) && !hasAGPRs(RC);
136  }
137 
138  /// \returns true if this class ID contains only SGPR registers
139  bool isSGPRClassID(unsigned RCID) const {
140  return isSGPRClass(getRegClass(RCID));
141  }
142 
143  bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
144  const TargetRegisterClass *RC;
146  RC = MRI.getRegClass(Reg);
147  else
148  RC = getPhysRegClass(Reg);
149  return isSGPRClass(RC);
150  }
151 
152  /// \returns true if this class contains VGPR registers.
153  bool hasVGPRs(const TargetRegisterClass *RC) const;
154 
155  /// \returns true if this class contains AGPR registers.
156  bool hasAGPRs(const TargetRegisterClass *RC) const;
157 
158  /// \returns true if this class contains any vector registers.
159  bool hasVectorRegisters(const TargetRegisterClass *RC) const {
160  return hasVGPRs(RC) || hasAGPRs(RC);
161  }
162 
163  /// \returns A VGPR reg class with the same width as \p SRC
165  const TargetRegisterClass *SRC) const;
166 
167  /// \returns An AGPR reg class with the same width as \p SRC
169  const TargetRegisterClass *SRC) const;
170 
171  /// \returns A SGPR reg class with the same width as \p SRC
173  const TargetRegisterClass *VRC) const;
174 
175  /// \returns The register class that is used for a sub-register of \p RC for
176  /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
177  /// be returned.
179  unsigned SubIdx) const;
180 
181  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
182  unsigned DefSubReg,
183  const TargetRegisterClass *SrcRC,
184  unsigned SrcSubReg) const override;
185 
186  /// \returns True if operands defined with this operand type can accept
187  /// a literal constant (i.e. any 32-bit immediate).
188  bool opCanUseLiteralConstant(unsigned OpType) const {
189  // TODO: 64-bit operands have extending behavior from 32-bit literal.
190  return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
192  }
193 
194  /// \returns True if operands defined with this operand type can accept
195  /// an inline constant. i.e. An integer value in the range (-16, 64) or
196  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
197  bool opCanUseInlineConstant(unsigned OpType) const;
198 
200  const TargetRegisterClass *RC,
201  const MachineFunction &MF) const;
202 
203  unsigned getSGPRPressureSet() const { return SGPRSetID; };
204  unsigned getVGPRPressureSet() const { return VGPRSetID; };
205  unsigned getAGPRPressureSet() const { return AGPRSetID; };
206 
208  unsigned Reg) const;
209  bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
210  bool isAGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
211  bool isVectorRegister(const MachineRegisterInfo &MRI, unsigned Reg) const {
212  return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
213  }
214 
215  virtual bool
216  isDivergentRegClass(const TargetRegisterClass *RC) const override {
217  return !isSGPRClass(RC);
218  }
219 
220  bool isSGPRPressureSet(unsigned SetID) const {
221  return SGPRPressureSets.test(SetID) && !VGPRPressureSets.test(SetID) &&
222  !AGPRPressureSets.test(SetID);
223  }
224  bool isVGPRPressureSet(unsigned SetID) const {
225  return VGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID) &&
226  !AGPRPressureSets.test(SetID);
227  }
228  bool isAGPRPressureSet(unsigned SetID) const {
229  return AGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID) &&
230  !VGPRPressureSets.test(SetID);
231  }
232 
234  unsigned EltSize) const;
235 
236  bool shouldCoalesce(MachineInstr *MI,
237  const TargetRegisterClass *SrcRC,
238  unsigned SubReg,
239  const TargetRegisterClass *DstRC,
240  unsigned DstSubReg,
241  const TargetRegisterClass *NewRC,
242  LiveIntervals &LIS) const override;
243 
244  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
245  MachineFunction &MF) const override;
246 
247  unsigned getRegPressureSetLimit(const MachineFunction &MF,
248  unsigned Idx) const override;
249 
250  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
251 
252  unsigned getReturnAddressReg(const MachineFunction &MF) const;
253 
254  const TargetRegisterClass *
256  const RegisterBank &Bank,
257  const MachineRegisterInfo &MRI) const;
258 
259  const TargetRegisterClass *
261  const RegisterBank &Bank,
262  const MachineRegisterInfo &MRI) const {
263  return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank, MRI);
264  }
265 
266  const TargetRegisterClass *
268  const MachineRegisterInfo &MRI) const override;
269 
271  return isWave32 ? &AMDGPU::SReg_32_XM0RegClass
272  : &AMDGPU::SReg_64RegClass;
273  }
274 
276  return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
277  : &AMDGPU::SReg_64_XEXECRegClass;
278  }
279 
280  unsigned getVCC() const;
281 
282  const TargetRegisterClass *getRegClass(unsigned RCID) const;
283 
284  // Find reaching register definition
285  MachineInstr *findReachingDef(unsigned Reg, unsigned SubReg,
286  MachineInstr &Use,
287  MachineRegisterInfo &MRI,
288  LiveIntervals *LIS) const;
289 
290  const uint32_t *getAllVGPRRegMask() const;
291  const uint32_t *getAllAllocatableSRegMask() const;
292 
293 private:
294  void buildSpillLoadStore(MachineBasicBlock::iterator MI,
295  unsigned LoadStoreOp,
296  int Index,
297  unsigned ValueReg,
298  bool ValueIsKill,
299  unsigned ScratchRsrcReg,
300  unsigned ScratchOffsetReg,
301  int64_t InstrOffset,
302  MachineMemOperand *MMO,
303  RegScavenger *RS) const;
304 };
305 
306 } // End namespace llvm
307 
308 #endif
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
unsigned getVCC() const
unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed...
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isSGPRClassID(unsigned RCID) const
SIRegisterInfo(const GCNSubtarget &ST)
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
StringRef getRegAsmName(unsigned Reg) const override
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned Reg
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
bool test(unsigned Idx) const
Definition: BitVector.h:501
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
bool isAGPR(const MachineRegisterInfo &MRI, unsigned Reg) const
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
bool canRealignStack(const MachineFunction &MF) const override
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
A description of a memory reference used in the backend.
MachineInstr * findReachingDef(unsigned Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
unsigned SubReg
bool opCanUseLiteralConstant(unsigned OpType) const
bool isSGPRClass(const TargetRegisterClass *RC) const
TargetRegisterInfo interface that is implemented by all hw codegen targets.
bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const
bool opCanUseInlineConstant(unsigned OpType) const
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
bool isSGPRPressureSet(unsigned SetID) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
unsigned getCSRFirstUseCost() const override
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
const int * getRegUnitPressureSets(unsigned RegUnit) const override
const uint32_t * getAllAllocatableSRegMask() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const override
unsigned const MachineRegisterInfo * MRI
unsigned reservedPrivateSegmentWaveByteOffsetReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch wave offset in case spilling is needed...
unsigned getReturnAddressReg(const MachineFunction &MF) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
bool hasVGPRs(const TargetRegisterClass *RC) const
int64_t getMUBUFInstrOffset(const MachineInstr *MI) const
unsigned getSGPRPressureSet() const
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
unsigned getVGPRPressureSet() const
bool isAGPRPressureSet(unsigned SetID) const
bool hasAGPRs(const TargetRegisterClass *RC) const
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
MachineOperand class - Representation of each machine instruction operand.
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF) const
Returns a register that is not used at any point in the function.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
This class implements the register bank concept.
Definition: RegisterBank.h:28
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, unsigned Reg) const
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
Special case of eliminateFrameIndex.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const TargetRegisterClass * getBoolRC() const
unsigned getAGPRPressureSet() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
uint32_t Size
Definition: Profile.cpp:46
bool spillSGPRToVGPR() const
bool spillSGPRToSMEM() const
const TargetRegisterClass * getWaveMaskRegClass() const
bool isVGPRPressureSet(unsigned SetID) const
Register getFrameRegister(const MachineFunction &MF) const override
bool hasVectorRegisters(const TargetRegisterClass *RC) const
const TargetRegisterClass * getRegClass(unsigned RCID) const
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the &#39;base&#39; register class for this register.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
const uint32_t * getAllVGPRRegMask() const
unsigned getHWRegIndex(unsigned Reg) const
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isVectorRegister(const MachineRegisterInfo &MRI, unsigned Reg) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19