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SelectionDAGBuilder.h
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1 //===- SelectionDAGBuilder.h - Selection-DAG building -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements routines for translating from LLVM IR into SelectionDAG IR.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
14 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
15 
16 #include "StatepointLowering.h"
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/MapVector.h"
21 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/IR/CallSite.h"
29 #include "llvm/IR/DebugLoc.h"
30 #include "llvm/IR/Instruction.h"
31 #include "llvm/IR/Statepoint.h"
33 #include "llvm/Support/CodeGen.h"
36 #include <algorithm>
37 #include <cassert>
38 #include <cstdint>
39 #include <utility>
40 #include <vector>
41 
42 namespace llvm {
43 
44 class AllocaInst;
45 class AtomicCmpXchgInst;
46 class AtomicRMWInst;
47 class BasicBlock;
48 class BranchInst;
49 class CallInst;
50 class CallBrInst;
51 class CatchPadInst;
52 class CatchReturnInst;
53 class CatchSwitchInst;
54 class CleanupPadInst;
55 class CleanupReturnInst;
56 class Constant;
57 class ConstantInt;
58 class ConstrainedFPIntrinsic;
59 class DbgValueInst;
60 class DataLayout;
61 class DIExpression;
62 class DILocalVariable;
63 class DILocation;
64 class FenceInst;
65 class FunctionLoweringInfo;
66 class GCFunctionInfo;
67 class GCRelocateInst;
68 class GCResultInst;
69 class IndirectBrInst;
70 class InvokeInst;
71 class LandingPadInst;
72 class LLVMContext;
73 class LoadInst;
74 class MachineBasicBlock;
75 class PHINode;
76 class ResumeInst;
77 class ReturnInst;
78 class SDDbgValue;
79 class StoreInst;
80 class SwitchInst;
81 class TargetLibraryInfo;
82 class TargetMachine;
83 class Type;
84 class VAArgInst;
85 class UnreachableInst;
86 class Use;
87 class User;
88 class Value;
89 
90 //===----------------------------------------------------------------------===//
91 /// SelectionDAGBuilder - This is the common target-independent lowering
92 /// implementation that is parameterized by a TargetLowering object.
93 ///
95  /// The current instruction being visited.
96  const Instruction *CurInst = nullptr;
97 
99 
100  /// Maps argument value for unused arguments. This is used
101  /// to preserve debug information for incoming arguments.
102  DenseMap<const Value*, SDValue> UnusedArgNodeMap;
103 
104  /// Helper type for DanglingDebugInfoMap.
105  class DanglingDebugInfo {
106  const DbgValueInst* DI = nullptr;
107  DebugLoc dl;
108  unsigned SDNodeOrder = 0;
109 
110  public:
111  DanglingDebugInfo() = default;
112  DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO)
113  : DI(di), dl(std::move(DL)), SDNodeOrder(SDNO) {}
114 
115  const DbgValueInst* getDI() { return DI; }
116  DebugLoc getdl() { return dl; }
117  unsigned getSDNodeOrder() { return SDNodeOrder; }
118  };
119 
120  /// Helper type for DanglingDebugInfoMap.
121  typedef std::vector<DanglingDebugInfo> DanglingDebugInfoVector;
122 
123  /// Keeps track of dbg_values for which we have not yet seen the referent.
124  /// We defer handling these until we do see it.
126 
127 public:
128  /// Loads are not emitted to the program immediately. We bunch them up and
129  /// then emit token factor nodes when possible. This allows us to get simple
130  /// disambiguation between loads without worrying about alias analysis.
132 
133  /// State used while lowering a statepoint sequence (gc_statepoint,
134  /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.
136 
137 private:
138  /// CopyToReg nodes that copy values to virtual registers for export to other
139  /// blocks need to be emitted before any terminator instruction, but they have
140  /// no other ordering requirements. We bunch them up and the emit a single
141  /// tokenfactor for them just before terminator instructions.
142  SmallVector<SDValue, 8> PendingExports;
143 
144  /// A unique monotonically increasing number used to order the SDNodes we
145  /// create.
146  unsigned SDNodeOrder;
147 
148  enum CaseClusterKind {
149  /// A cluster of adjacent case labels with the same destination, or just one
150  /// case.
151  CC_Range,
152  /// A cluster of cases suitable for jump table lowering.
153  CC_JumpTable,
154  /// A cluster of cases suitable for bit test lowering.
155  CC_BitTests
156  };
157 
158  /// A cluster of case labels.
159  struct CaseCluster {
160  CaseClusterKind Kind;
161  const ConstantInt *Low, *High;
162  union {
163  MachineBasicBlock *MBB;
164  unsigned JTCasesIndex;
165  unsigned BTCasesIndex;
166  };
167  BranchProbability Prob;
168 
169  static CaseCluster range(const ConstantInt *Low, const ConstantInt *High,
171  CaseCluster C;
172  C.Kind = CC_Range;
173  C.Low = Low;
174  C.High = High;
175  C.MBB = MBB;
176  C.Prob = Prob;
177  return C;
178  }
179 
180  static CaseCluster jumpTable(const ConstantInt *Low,
181  const ConstantInt *High, unsigned JTCasesIndex,
182  BranchProbability Prob) {
183  CaseCluster C;
184  C.Kind = CC_JumpTable;
185  C.Low = Low;
186  C.High = High;
187  C.JTCasesIndex = JTCasesIndex;
188  C.Prob = Prob;
189  return C;
190  }
191 
192  static CaseCluster bitTests(const ConstantInt *Low, const ConstantInt *High,
193  unsigned BTCasesIndex, BranchProbability Prob) {
194  CaseCluster C;
195  C.Kind = CC_BitTests;
196  C.Low = Low;
197  C.High = High;
198  C.BTCasesIndex = BTCasesIndex;
199  C.Prob = Prob;
200  return C;
201  }
202  };
203 
204  using CaseClusterVector = std::vector<CaseCluster>;
205  using CaseClusterIt = CaseClusterVector::iterator;
206 
207  struct CaseBits {
208  uint64_t Mask = 0;
209  MachineBasicBlock* BB = nullptr;
210  unsigned Bits = 0;
211  BranchProbability ExtraProb;
212 
213  CaseBits() = default;
214  CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
215  BranchProbability Prob):
216  Mask(mask), BB(bb), Bits(bits), ExtraProb(Prob) {}
217  };
218 
219  using CaseBitsVector = std::vector<CaseBits>;
220 
221  /// Sort Clusters and merge adjacent cases.
222  void sortAndRangeify(CaseClusterVector &Clusters);
223 
224  /// This structure is used to communicate between SelectionDAGBuilder and
225  /// SDISel for the code generation of additional basic blocks needed by
226  /// multi-case switch statements.
227  struct CaseBlock {
228  // The condition code to use for the case block's setcc node.
229  // Besides the integer condition codes, this can also be SETTRUE, in which
230  // case no comparison gets emitted.
231  ISD::CondCode CC;
232 
233  // The LHS/MHS/RHS of the comparison to emit.
234  // Emit by default LHS op RHS. MHS is used for range comparisons:
235  // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
236  const Value *CmpLHS, *CmpMHS, *CmpRHS;
237 
238  // The block to branch to if the setcc is true/false.
239  MachineBasicBlock *TrueBB, *FalseBB;
240 
241  // The block into which to emit the code for the setcc and branches.
242  MachineBasicBlock *ThisBB;
243 
244  /// The debug location of the instruction this CaseBlock was
245  /// produced from.
246  SDLoc DL;
247 
248  // Branch weights.
249  BranchProbability TrueProb, FalseProb;
250 
251  CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
252  const Value *cmpmiddle, MachineBasicBlock *truebb,
253  MachineBasicBlock *falsebb, MachineBasicBlock *me,
254  SDLoc dl,
257  : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
258  TrueBB(truebb), FalseBB(falsebb), ThisBB(me), DL(dl),
259  TrueProb(trueprob), FalseProb(falseprob) {}
260  };
261 
262  struct JumpTable {
263  /// The virtual register containing the index of the jump table entry
264  /// to jump to.
265  unsigned Reg;
266  /// The JumpTableIndex for this jump table in the function.
267  unsigned JTI;
268  /// The MBB into which to emit the code for the indirect jump.
269  MachineBasicBlock *MBB;
270  /// The MBB of the default bb, which is a successor of the range
271  /// check MBB. This is when updating PHI nodes in successors.
273 
274  JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
275  MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
276  };
277  struct JumpTableHeader {
278  APInt First;
279  APInt Last;
280  const Value *SValue;
281  MachineBasicBlock *HeaderBB;
282  bool Emitted;
283  bool OmitRangeCheck;
284 
285  JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
286  bool E = false)
287  : First(std::move(F)), Last(std::move(L)), SValue(SV), HeaderBB(H),
288  Emitted(E), OmitRangeCheck(false) {}
289  };
290  using JumpTableBlock = std::pair<JumpTableHeader, JumpTable>;
291 
292  struct BitTestCase {
293  uint64_t Mask;
294  MachineBasicBlock *ThisBB;
295  MachineBasicBlock *TargetBB;
296  BranchProbability ExtraProb;
297 
298  BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
299  BranchProbability Prob):
300  Mask(M), ThisBB(T), TargetBB(Tr), ExtraProb(Prob) {}
301  };
302 
304 
305  struct BitTestBlock {
306  APInt First;
307  APInt Range;
308  const Value *SValue;
309  unsigned Reg;
310  MVT RegVT;
311  bool Emitted;
312  bool ContiguousRange;
313  MachineBasicBlock *Parent;
315  BitTestInfo Cases;
316  BranchProbability Prob;
317  BranchProbability DefaultProb;
318 
319  BitTestBlock(APInt F, APInt R, const Value *SV, unsigned Rg, MVT RgVT,
320  bool E, bool CR, MachineBasicBlock *P, MachineBasicBlock *D,
322  : First(std::move(F)), Range(std::move(R)), SValue(SV), Reg(Rg),
323  RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
324  Cases(std::move(C)), Prob(Pr) {}
325  };
326 
327  /// Return the range of value in [First..Last].
328  uint64_t getJumpTableRange(const CaseClusterVector &Clusters, unsigned First,
329  unsigned Last) const;
330 
331  /// Return the number of cases in [First..Last].
332  uint64_t getJumpTableNumCases(const SmallVectorImpl<unsigned> &TotalCases,
333  unsigned First, unsigned Last) const;
334 
335  /// Build a jump table cluster from Clusters[First..Last]. Returns false if it
336  /// decides it's not a good idea.
337  bool buildJumpTable(const CaseClusterVector &Clusters, unsigned First,
338  unsigned Last, const SwitchInst *SI,
339  MachineBasicBlock *DefaultMBB, CaseCluster &JTCluster);
340 
341  /// Find clusters of cases suitable for jump table lowering.
342  void findJumpTables(CaseClusterVector &Clusters, const SwitchInst *SI,
343  MachineBasicBlock *DefaultMBB);
344 
345  /// Build a bit test cluster from Clusters[First..Last]. Returns false if it
346  /// decides it's not a good idea.
347  bool buildBitTests(CaseClusterVector &Clusters, unsigned First, unsigned Last,
348  const SwitchInst *SI, CaseCluster &BTCluster);
349 
350  /// Find clusters of cases suitable for bit test lowering.
351  void findBitTestClusters(CaseClusterVector &Clusters, const SwitchInst *SI);
352 
353  struct SwitchWorkListItem {
354  MachineBasicBlock *MBB;
355  CaseClusterIt FirstCluster;
356  CaseClusterIt LastCluster;
357  const ConstantInt *GE;
358  const ConstantInt *LT;
359  BranchProbability DefaultProb;
360  };
362 
363  /// Determine the rank by weight of CC in [First,Last]. If CC has more weight
364  /// than each cluster in the range, its rank is 0.
365  static unsigned caseClusterRank(const CaseCluster &CC, CaseClusterIt First,
366  CaseClusterIt Last);
367 
368  /// Emit comparison and split W into two subtrees.
369  void splitWorkItem(SwitchWorkList &WorkList, const SwitchWorkListItem &W,
370  Value *Cond, MachineBasicBlock *SwitchMBB);
371 
372  /// Lower W.
373  void lowerWorkItem(SwitchWorkListItem W, Value *Cond,
374  MachineBasicBlock *SwitchMBB,
375  MachineBasicBlock *DefaultMBB);
376 
377  /// Peel the top probability case if it exceeds the threshold
378  MachineBasicBlock *peelDominantCaseCluster(const SwitchInst &SI,
379  CaseClusterVector &Clusters,
380  BranchProbability &PeeledCaseProb);
381 
382  /// A class which encapsulates all of the information needed to generate a
383  /// stack protector check and signals to isel via its state being initialized
384  /// that a stack protector needs to be generated.
385  ///
386  /// *NOTE* The following is a high level documentation of SelectionDAG Stack
387  /// Protector Generation. The reason that it is placed here is for a lack of
388  /// other good places to stick it.
389  ///
390  /// High Level Overview of SelectionDAG Stack Protector Generation:
391  ///
392  /// Previously, generation of stack protectors was done exclusively in the
393  /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
394  /// splitting basic blocks at the IR level to create the success/failure basic
395  /// blocks in the tail of the basic block in question. As a result of this,
396  /// calls that would have qualified for the sibling call optimization were no
397  /// longer eligible for optimization since said calls were no longer right in
398  /// the "tail position" (i.e. the immediate predecessor of a ReturnInst
399  /// instruction).
400  ///
401  /// Then it was noticed that since the sibling call optimization causes the
402  /// callee to reuse the caller's stack, if we could delay the generation of
403  /// the stack protector check until later in CodeGen after the sibling call
404  /// decision was made, we get both the tail call optimization and the stack
405  /// protector check!
406  ///
407  /// A few goals in solving this problem were:
408  ///
409  /// 1. Preserve the architecture independence of stack protector generation.
410  ///
411  /// 2. Preserve the normal IR level stack protector check for platforms like
412  /// OpenBSD for which we support platform-specific stack protector
413  /// generation.
414  ///
415  /// The main problem that guided the present solution is that one can not
416  /// solve this problem in an architecture independent manner at the IR level
417  /// only. This is because:
418  ///
419  /// 1. The decision on whether or not to perform a sibling call on certain
420  /// platforms (for instance i386) requires lower level information
421  /// related to available registers that can not be known at the IR level.
422  ///
423  /// 2. Even if the previous point were not true, the decision on whether to
424  /// perform a tail call is done in LowerCallTo in SelectionDAG which
425  /// occurs after the Stack Protector Pass. As a result, one would need to
426  /// put the relevant callinst into the stack protector check success
427  /// basic block (where the return inst is placed) and then move it back
428  /// later at SelectionDAG/MI time before the stack protector check if the
429  /// tail call optimization failed. The MI level option was nixed
430  /// immediately since it would require platform-specific pattern
431  /// matching. The SelectionDAG level option was nixed because
432  /// SelectionDAG only processes one IR level basic block at a time
433  /// implying one could not create a DAG Combine to move the callinst.
434  ///
435  /// To get around this problem a few things were realized:
436  ///
437  /// 1. While one can not handle multiple IR level basic blocks at the
438  /// SelectionDAG Level, one can generate multiple machine basic blocks
439  /// for one IR level basic block. This is how we handle bit tests and
440  /// switches.
441  ///
442  /// 2. At the MI level, tail calls are represented via a special return
443  /// MIInst called "tcreturn". Thus if we know the basic block in which we
444  /// wish to insert the stack protector check, we get the correct behavior
445  /// by always inserting the stack protector check right before the return
446  /// statement. This is a "magical transformation" since no matter where
447  /// the stack protector check intrinsic is, we always insert the stack
448  /// protector check code at the end of the BB.
449  ///
450  /// Given the aforementioned constraints, the following solution was devised:
451  ///
452  /// 1. On platforms that do not support SelectionDAG stack protector check
453  /// generation, allow for the normal IR level stack protector check
454  /// generation to continue.
455  ///
456  /// 2. On platforms that do support SelectionDAG stack protector check
457  /// generation:
458  ///
459  /// a. Use the IR level stack protector pass to decide if a stack
460  /// protector is required/which BB we insert the stack protector check
461  /// in by reusing the logic already therein. If we wish to generate a
462  /// stack protector check in a basic block, we place a special IR
463  /// intrinsic called llvm.stackprotectorcheck right before the BB's
464  /// returninst or if there is a callinst that could potentially be
465  /// sibling call optimized, before the call inst.
466  ///
467  /// b. Then when a BB with said intrinsic is processed, we codegen the BB
468  /// normally via SelectBasicBlock. In said process, when we visit the
469  /// stack protector check, we do not actually emit anything into the
470  /// BB. Instead, we just initialize the stack protector descriptor
471  /// class (which involves stashing information/creating the success
472  /// mbbb and the failure mbb if we have not created one for this
473  /// function yet) and export the guard variable that we are going to
474  /// compare.
475  ///
476  /// c. After we finish selecting the basic block, in FinishBasicBlock if
477  /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
478  /// initialized, we produce the validation code with one of these
479  /// techniques:
480  /// 1) with a call to a guard check function
481  /// 2) with inlined instrumentation
482  ///
483  /// 1) We insert a call to the check function before the terminator.
484  ///
485  /// 2) We first find a splice point in the parent basic block
486  /// before the terminator and then splice the terminator of said basic
487  /// block into the success basic block. Then we code-gen a new tail for
488  /// the parent basic block consisting of the two loads, the comparison,
489  /// and finally two branches to the success/failure basic blocks. We
490  /// conclude by code-gening the failure basic block if we have not
491  /// code-gened it already (all stack protector checks we generate in
492  /// the same function, use the same failure basic block).
493  class StackProtectorDescriptor {
494  public:
495  StackProtectorDescriptor() = default;
496 
497  /// Returns true if all fields of the stack protector descriptor are
498  /// initialized implying that we should/are ready to emit a stack protector.
499  bool shouldEmitStackProtector() const {
500  return ParentMBB && SuccessMBB && FailureMBB;
501  }
502 
503  bool shouldEmitFunctionBasedCheckStackProtector() const {
504  return ParentMBB && !SuccessMBB && !FailureMBB;
505  }
506 
507  /// Initialize the stack protector descriptor structure for a new basic
508  /// block.
509  void initialize(const BasicBlock *BB, MachineBasicBlock *MBB,
510  bool FunctionBasedInstrumentation) {
511  // Make sure we are not initialized yet.
512  assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
513  "already initialized!");
514  ParentMBB = MBB;
515  if (!FunctionBasedInstrumentation) {
516  SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true);
517  FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB);
518  }
519  }
520 
521  /// Reset state that changes when we handle different basic blocks.
522  ///
523  /// This currently includes:
524  ///
525  /// 1. The specific basic block we are generating a
526  /// stack protector for (ParentMBB).
527  ///
528  /// 2. The successor machine basic block that will contain the tail of
529  /// parent mbb after we create the stack protector check (SuccessMBB). This
530  /// BB is visited only on stack protector check success.
531  void resetPerBBState() {
532  ParentMBB = nullptr;
533  SuccessMBB = nullptr;
534  }
535 
536  /// Reset state that only changes when we switch functions.
537  ///
538  /// This currently includes:
539  ///
540  /// 1. FailureMBB since we reuse the failure code path for all stack
541  /// protector checks created in an individual function.
542  ///
543  /// 2.The guard variable since the guard variable we are checking against is
544  /// always the same.
545  void resetPerFunctionState() {
546  FailureMBB = nullptr;
547  }
548 
549  MachineBasicBlock *getParentMBB() { return ParentMBB; }
550  MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
551  MachineBasicBlock *getFailureMBB() { return FailureMBB; }
552 
553  private:
554  /// The basic block for which we are generating the stack protector.
555  ///
556  /// As a result of stack protector generation, we will splice the
557  /// terminators of this basic block into the successor mbb SuccessMBB and
558  /// replace it with a compare/branch to the successor mbbs
559  /// SuccessMBB/FailureMBB depending on whether or not the stack protector
560  /// was violated.
561  MachineBasicBlock *ParentMBB = nullptr;
562 
563  /// A basic block visited on stack protector check success that contains the
564  /// terminators of ParentMBB.
565  MachineBasicBlock *SuccessMBB = nullptr;
566 
567  /// This basic block visited on stack protector check failure that will
568  /// contain a call to __stack_chk_fail().
569  MachineBasicBlock *FailureMBB = nullptr;
570 
571  /// Add a successor machine basic block to ParentMBB. If the successor mbb
572  /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
573  /// block will be created. Assign a large weight if IsLikely is true.
574  MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
575  MachineBasicBlock *ParentMBB,
576  bool IsLikely,
577  MachineBasicBlock *SuccMBB = nullptr);
578  };
579 
580 private:
581  const TargetMachine &TM;
582 
583 public:
584  /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
585  /// nodes without a corresponding SDNode.
586  static const unsigned LowestSDNodeOrder = 1;
587 
589  const DataLayout *DL = nullptr;
590  AliasAnalysis *AA = nullptr;
592 
593  /// Vector of CaseBlock structures used to communicate SwitchInst code
594  /// generation information.
595  std::vector<CaseBlock> SwitchCases;
596 
597  /// Vector of JumpTable structures used to communicate SwitchInst code
598  /// generation information.
599  std::vector<JumpTableBlock> JTCases;
600 
601  /// Vector of BitTestBlock structures used to communicate SwitchInst code
602  /// generation information.
603  std::vector<BitTestBlock> BitTestCases;
604 
605  /// A StackProtectorDescriptor structure used to communicate stack protector
606  /// information in between SelectBasicBlock and FinishBasicBlock.
607  StackProtectorDescriptor SPDescriptor;
608 
609  // Emit PHI-node-operand constants only once even if used by multiple
610  // PHI nodes.
612 
613  /// Information about the function as a whole.
615 
616  /// Garbage collection metadata for the function.
618 
619  /// Map a landing pad to the call site indexes.
621 
622  /// This is set to true if a call in the current block has been translated as
623  /// a tail call. In this case, no subsequent DAG nodes should be created.
624  bool HasTailCall = false;
625 
627 
630  : SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), DAG(dag),
631  FuncInfo(funcinfo) {}
632 
633  void init(GCFunctionInfo *gfi, AliasAnalysis *AA,
634  const TargetLibraryInfo *li);
635 
636  /// Clear out the current SelectionDAG and the associated state and prepare
637  /// this SelectionDAGBuilder object to be used for a new block. This doesn't
638  /// clear out information about additional blocks that are needed to complete
639  /// switch lowering or PHI node updating; that information is cleared out as
640  /// it is consumed.
641  void clear();
642 
643  /// Clear the dangling debug information map. This function is separated from
644  /// the clear so that debug information that is dangling in a basic block can
645  /// be properly resolved in a different basic block. This allows the
646  /// SelectionDAG to resolve dangling debug information attached to PHI nodes.
647  void clearDanglingDebugInfo();
648 
649  /// Return the current virtual root of the Selection DAG, flushing any
650  /// PendingLoad items. This must be done before emitting a store or any other
651  /// node that may need to be ordered after any prior load instructions.
652  SDValue getRoot();
653 
654  /// Similar to getRoot, but instead of flushing all the PendingLoad items,
655  /// flush all the PendingExports items. It is necessary to do this before
656  /// emitting a terminator instruction.
658 
659  SDLoc getCurSDLoc() const {
660  return SDLoc(CurInst, SDNodeOrder);
661  }
662 
664  return CurInst ? CurInst->getDebugLoc() : DebugLoc();
665  }
666 
667  void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
668 
669  void visit(const Instruction &I);
670 
671  void visit(unsigned Opcode, const User &I);
672 
673  /// If there was virtual register allocated for the value V emit CopyFromReg
674  /// of the specified type Ty. Return empty SDValue() otherwise.
675  SDValue getCopyFromRegs(const Value *V, Type *Ty);
676 
677  /// If we have dangling debug info that describes \p Variable, or an
678  /// overlapping part of variable considering the \p Expr, then this method
679  /// will drop that debug info as it isn't valid any longer.
680  void dropDanglingDebugInfo(const DILocalVariable *Variable,
681  const DIExpression *Expr);
682 
683  /// If we saw an earlier dbg_value referring to V, generate the debug data
684  /// structures now that we've seen its definition.
685  void resolveDanglingDebugInfo(const Value *V, SDValue Val);
686 
687  /// For the given dangling debuginfo record, perform last-ditch efforts to
688  /// resolve the debuginfo to something that is represented in this DAG. If
689  /// this cannot be done, produce an Undef debug value record.
690  void salvageUnresolvedDbgValue(DanglingDebugInfo &DDI);
691 
692  /// For a given Value, attempt to create and record a SDDbgValue in the
693  /// SelectionDAG.
694  bool handleDebugValue(const Value *V, DILocalVariable *Var,
695  DIExpression *Expr, DebugLoc CurDL,
696  DebugLoc InstDL, unsigned Order);
697 
698  /// Evict any dangling debug information, attempting to salvage it first.
699  void resolveOrClearDbgInfo();
700 
701  SDValue getValue(const Value *V);
702  bool findValue(const Value *V) const;
703 
704  /// Return the SDNode for the specified IR value if it exists.
706  if (NodeMap.find(V) == NodeMap.end())
707  return nullptr;
708  return NodeMap[V].getNode();
709  }
710 
712  SDValue getValueImpl(const Value *V);
713 
714  void setValue(const Value *V, SDValue NewN) {
715  SDValue &N = NodeMap[V];
716  assert(!N.getNode() && "Already set a value for this node!");
717  N = NewN;
718  }
719 
720  void setUnusedArgValue(const Value *V, SDValue NewN) {
721  SDValue &N = UnusedArgNodeMap[V];
722  assert(!N.getNode() && "Already set a value for this node!");
723  N = NewN;
724  }
725 
726  void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
728  MachineBasicBlock *SwitchBB,
730  BranchProbability FProb, bool InvertCond);
732  MachineBasicBlock *FBB,
733  MachineBasicBlock *CurBB,
734  MachineBasicBlock *SwitchBB,
736  bool InvertCond);
737  bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
738  bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
739  void CopyToExportRegsIfNeeded(const Value *V);
740  void ExportFromCurrentBlock(const Value *V);
741  void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
742  const BasicBlock *EHPadBB = nullptr);
743 
744  // Lower range metadata from 0 to N to assert zext to an integer of nearest
745  // floor power of two.
747  SDValue Op);
748 
750  const CallBase *Call, unsigned ArgIdx,
751  unsigned NumArgs, SDValue Callee,
752  Type *ReturnTy, bool IsPatchPoint);
753 
754  std::pair<SDValue, SDValue>
756  const BasicBlock *EHPadBB = nullptr);
757 
758  /// When an MBB was split during scheduling, update the
759  /// references that need to refer to the last resulting block.
761 
762  /// Describes a gc.statepoint or a gc.statepoint like thing for the purposes
763  /// of lowering into a STATEPOINT node.
765  /// Bases[i] is the base pointer for Ptrs[i]. Together they denote the set
766  /// of gc pointers this STATEPOINT has to relocate.
769 
770  /// The set of gc.relocate calls associated with this gc.statepoint.
772 
773  /// The full list of gc arguments to the gc.statepoint being lowered.
775 
776  /// The gc.statepoint instruction.
777  const Instruction *StatepointInstr = nullptr;
778 
779  /// The list of gc transition arguments present in the gc.statepoint being
780  /// lowered.
782 
783  /// The ID that the resulting STATEPOINT instruction has to report.
784  unsigned ID = -1;
785 
786  /// Information regarding the underlying call instruction.
788 
789  /// The deoptimization state associated with this gc.statepoint call, if
790  /// any.
792 
793  /// Flags associated with the meta arguments being lowered.
794  uint64_t StatepointFlags = -1;
795 
796  /// The number of patchable bytes the call needs to get lowered into.
797  unsigned NumPatchBytes = -1;
798 
799  /// The exception handling unwind destination, in case this represents an
800  /// invoke of gc.statepoint.
801  const BasicBlock *EHPadBB = nullptr;
802 
803  explicit StatepointLoweringInfo(SelectionDAG &DAG) : CLI(DAG) {}
804  };
805 
806  /// Lower \p SLI into a STATEPOINT instruction.
808 
809  // This function is responsible for the whole statepoint lowering process.
810  // It uniformly handles invoke and call statepoints.
812  const BasicBlock *EHPadBB = nullptr);
813 
814  void LowerCallSiteWithDeoptBundle(const CallBase *Call, SDValue Callee,
815  const BasicBlock *EHPadBB);
816 
817  void LowerDeoptimizeCall(const CallInst *CI);
819 
820  void LowerCallSiteWithDeoptBundleImpl(const CallBase *Call, SDValue Callee,
821  const BasicBlock *EHPadBB,
822  bool VarArgDisallowed,
823  bool ForceVoidReturnTy);
824 
825  /// Returns the type of FrameIndex and TargetFrameIndex nodes.
828  }
829 
830 private:
831  // Terminator instructions.
832  void visitRet(const ReturnInst &I);
833  void visitBr(const BranchInst &I);
834  void visitSwitch(const SwitchInst &I);
835  void visitIndirectBr(const IndirectBrInst &I);
836  void visitUnreachable(const UnreachableInst &I);
837  void visitCleanupRet(const CleanupReturnInst &I);
838  void visitCatchSwitch(const CatchSwitchInst &I);
839  void visitCatchRet(const CatchReturnInst &I);
840  void visitCatchPad(const CatchPadInst &I);
841  void visitCleanupPad(const CleanupPadInst &CPI);
842 
843  BranchProbability getEdgeProbability(const MachineBasicBlock *Src,
844  const MachineBasicBlock *Dst) const;
845  void addSuccessorWithProb(
848 
849 public:
850  void visitSwitchCase(CaseBlock &CB,
851  MachineBasicBlock *SwitchBB);
852  void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
853  MachineBasicBlock *ParentBB);
854  void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
855  void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
856  void visitBitTestCase(BitTestBlock &BB,
857  MachineBasicBlock* NextMBB,
858  BranchProbability BranchProbToNext,
859  unsigned Reg,
860  BitTestCase &B,
861  MachineBasicBlock *SwitchBB);
862  void visitJumpTable(JumpTable &JT);
863  void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
864  MachineBasicBlock *SwitchBB);
865 
866 private:
867  // These all get lowered before this pass.
868  void visitInvoke(const InvokeInst &I);
869  void visitCallBr(const CallBrInst &I);
870  void visitResume(const ResumeInst &I);
871 
872  void visitUnary(const User &I, unsigned Opcode);
873  void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); }
874 
875  void visitBinary(const User &I, unsigned Opcode);
876  void visitShift(const User &I, unsigned Opcode);
877  void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
878  void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
879  void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
880  void visitFSub(const User &I);
881  void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
882  void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
883  void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
884  void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
885  void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
886  void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
887  void visitSDiv(const User &I);
888  void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
889  void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
890  void visitOr (const User &I) { visitBinary(I, ISD::OR); }
891  void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
892  void visitShl (const User &I) { visitShift(I, ISD::SHL); }
893  void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
894  void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
895  void visitICmp(const User &I);
896  void visitFCmp(const User &I);
897  // Visit the conversion instructions
898  void visitTrunc(const User &I);
899  void visitZExt(const User &I);
900  void visitSExt(const User &I);
901  void visitFPTrunc(const User &I);
902  void visitFPExt(const User &I);
903  void visitFPToUI(const User &I);
904  void visitFPToSI(const User &I);
905  void visitUIToFP(const User &I);
906  void visitSIToFP(const User &I);
907  void visitPtrToInt(const User &I);
908  void visitIntToPtr(const User &I);
909  void visitBitCast(const User &I);
910  void visitAddrSpaceCast(const User &I);
911 
912  void visitExtractElement(const User &I);
913  void visitInsertElement(const User &I);
914  void visitShuffleVector(const User &I);
915 
916  void visitExtractValue(const User &I);
917  void visitInsertValue(const User &I);
918  void visitLandingPad(const LandingPadInst &LP);
919 
920  void visitGetElementPtr(const User &I);
921  void visitSelect(const User &I);
922 
923  void visitAlloca(const AllocaInst &I);
924  void visitLoad(const LoadInst &I);
925  void visitStore(const StoreInst &I);
926  void visitMaskedLoad(const CallInst &I, bool IsExpanding = false);
927  void visitMaskedStore(const CallInst &I, bool IsCompressing = false);
928  void visitMaskedGather(const CallInst &I);
929  void visitMaskedScatter(const CallInst &I);
930  void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
931  void visitAtomicRMW(const AtomicRMWInst &I);
932  void visitFence(const FenceInst &I);
933  void visitPHI(const PHINode &I);
934  void visitCall(const CallInst &I);
935  bool visitMemCmpCall(const CallInst &I);
936  bool visitMemPCpyCall(const CallInst &I);
937  bool visitMemChrCall(const CallInst &I);
938  bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
939  bool visitStrCmpCall(const CallInst &I);
940  bool visitStrLenCall(const CallInst &I);
941  bool visitStrNLenCall(const CallInst &I);
942  bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
943  bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode);
944  void visitAtomicLoad(const LoadInst &I);
945  void visitAtomicStore(const StoreInst &I);
946  void visitLoadFromSwiftError(const LoadInst &I);
947  void visitStoreToSwiftError(const StoreInst &I);
948 
949  void visitInlineAsm(ImmutableCallSite CS);
950  void visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
951  void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
952  void visitConstrainedFPIntrinsic(const ConstrainedFPIntrinsic &FPI);
953 
954  void visitVAStart(const CallInst &I);
955  void visitVAArg(const VAArgInst &I);
956  void visitVAEnd(const CallInst &I);
957  void visitVACopy(const CallInst &I);
958  void visitStackmap(const CallInst &I);
959  void visitPatchpoint(ImmutableCallSite CS,
960  const BasicBlock *EHPadBB = nullptr);
961 
962  // These two are implemented in StatepointLowering.cpp
963  void visitGCRelocate(const GCRelocateInst &Relocate);
964  void visitGCResult(const GCResultInst &I);
965 
966  void visitVectorReduce(const CallInst &I, unsigned Intrinsic);
967 
968  void visitUserOp1(const Instruction &I) {
969  llvm_unreachable("UserOp1 should not exist at instruction selection time!");
970  }
971  void visitUserOp2(const Instruction &I) {
972  llvm_unreachable("UserOp2 should not exist at instruction selection time!");
973  }
974 
975  void processIntegerCallValue(const Instruction &I,
976  SDValue Value, bool IsSigned);
977 
978  void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
979 
980  void emitInlineAsmError(ImmutableCallSite CS, const Twine &Message);
981 
982  /// If V is an function argument then create corresponding DBG_VALUE machine
983  /// instruction for it now. At the end of instruction selection, they will be
984  /// inserted to the entry BB.
985  bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable,
986  DIExpression *Expr, DILocation *DL,
987  bool IsDbgDeclare, const SDValue &N);
988 
989  /// Return the next block after MBB, or nullptr if there is none.
990  MachineBasicBlock *NextBlock(MachineBasicBlock *MBB);
991 
992  /// Update the DAG and DAG builder with the relevant information after
993  /// a new root node has been created which could be a tail call.
994  void updateDAGForMaybeTailCall(SDValue MaybeTC);
995 
996  /// Return the appropriate SDDbgValue based on N.
997  SDDbgValue *getDbgValue(SDValue N, DILocalVariable *Variable,
998  DIExpression *Expr, const DebugLoc &dl,
999  unsigned DbgSDNodeOrder);
1000 
1001  /// Lowers CallInst to an external symbol.
1002  void lowerCallToExternalSymbol(const CallInst &I, const char *FunctionName);
1003 };
1004 
1005 /// This struct represents the registers (physical or virtual)
1006 /// that a particular set of values is assigned, and the type information about
1007 /// the value. The most common situation is to represent one value at a time,
1008 /// but struct or array values are handled element-wise as multiple values. The
1009 /// splitting of aggregates is performed recursively, so that we never have
1010 /// aggregate-typed registers. The values at this point do not necessarily have
1011 /// legal types, so each value may require one or more registers of some legal
1012 /// type.
1013 ///
1015  /// The value types of the values, which may not be legal, and
1016  /// may need be promoted or synthesized from one or more registers.
1018 
1019  /// The value types of the registers. This is the same size as ValueVTs and it
1020  /// records, for each value, what the type of the assigned register or
1021  /// registers are. (Individual values are never synthesized from more than one
1022  /// type of register.)
1023  ///
1024  /// With virtual registers, the contents of RegVTs is redundant with TLI's
1025  /// getRegisterType member function, however when with physical registers
1026  /// it is necessary to have a separate record of the types.
1028 
1029  /// This list holds the registers assigned to the values.
1030  /// Each legal or promoted value requires one register, and each
1031  /// expanded value requires multiple registers.
1033 
1034  /// This list holds the number of registers for each value.
1036 
1037  /// Records if this value needs to be treated in an ABI dependant manner,
1038  /// different to normal type legalization.
1040 
1041  RegsForValue() = default;
1042  RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt, EVT valuevt,
1045  const DataLayout &DL, unsigned Reg, Type *Ty,
1047 
1048  bool isABIMangled() const {
1049  return CallConv.hasValue();
1050  }
1051 
1052  /// Add the specified values to this one.
1053  void append(const RegsForValue &RHS) {
1054  ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
1055  RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
1056  Regs.append(RHS.Regs.begin(), RHS.Regs.end());
1057  RegCount.push_back(RHS.Regs.size());
1058  }
1059 
1060  /// Emit a series of CopyFromReg nodes that copies from this value and returns
1061  /// the result as a ValueVTs value. This uses Chain/Flag as the input and
1062  /// updates them for the output Chain/Flag. If the Flag pointer is NULL, no
1063  /// flag is used.
1065  const SDLoc &dl, SDValue &Chain, SDValue *Flag,
1066  const Value *V = nullptr) const;
1067 
1068  /// Emit a series of CopyToReg nodes that copies the specified value into the
1069  /// registers specified by this object. This uses Chain/Flag as the input and
1070  /// updates them for the output Chain/Flag. If the Flag pointer is nullptr, no
1071  /// flag is used. If V is not nullptr, then it is used in printing better
1072  /// diagnostic messages on error.
1073  void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl,
1074  SDValue &Chain, SDValue *Flag, const Value *V = nullptr,
1075  ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
1076 
1077  /// Add this value to the specified inlineasm node operand list. This adds the
1078  /// code marker, matching input operand index (if applicable), and includes
1079  /// the number of values added into it.
1080  void AddInlineAsmOperands(unsigned Code, bool HasMatching,
1081  unsigned MatchingIdx, const SDLoc &dl,
1082  SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
1083 
1084  /// Check if the total RegCount is greater than one.
1085  bool occupiesMultipleRegs() const {
1086  return std::accumulate(RegCount.begin(), RegCount.end(), 0) > 1;
1087  }
1088 
1089  /// Return a list of registers and their sizes.
1090  SmallVector<std::pair<unsigned, unsigned>, 4> getRegsAndSizes() const;
1091 };
1092 
1093 } // end namespace llvm
1094 
1095 #endif // LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
uint64_t CallInst * C
Return a value (possibly void), from a function.
std::vector< BitTestBlock > BitTestCases
Vector of BitTestBlock structures used to communicate SwitchInst code generation information.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
Represents calls to the gc.result intrinsic.
Definition: Statepoint.h:393
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:48
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void ExportFromCurrentBlock(const Value *V)
ExportFromCurrentBlock - If this condition isn&#39;t known to be exported from the current basic block...
const TargetLibraryInfo * LibInfo
StatepointFlags
The statepoint intrinsic accepts a set of flags as its third argument.
Definition: Statepoint.h:40
Various leaf nodes.
Definition: ISDOpcodes.h:59
DenseMap< MachineBasicBlock *, SmallVector< unsigned, 4 > > LPadToCallSiteMap
Map a landing pad to the call site indexes.
void LowerDeoptimizeCall(const CallInst *CI)
An instruction for ordering other memory operations.
Definition: Instructions.h:454
TargetLowering::CallLoweringInfo CLI
Information regarding the underlying call instruction.
void CopyValueToVirtualRegister(const Value *V, unsigned Reg)
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:528
SmallVector< const GCRelocateInst *, 16 > GCRelocates
The set of gc.relocate calls associated with this gc.statepoint.
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
A specialization of it&#39;s base class for read only access to a gc.statepoint.
Definition: Statepoint.h:292
void push_back(const T &Elt)
Definition: SmallVector.h:211
void LowerCallSiteWithDeoptBundle(const CallBase *Call, SDValue Callee, const BasicBlock *EHPadBB)
SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo, CodeGenOpt::Level ol)
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
void setValue(const Value *V, SDValue NewN)
void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH, MachineBasicBlock *SwitchBB)
visitJumpTableHeader - This function emits necessary code to produce index in the JumpTable from swit...
Optional< CallingConv::ID > CallConv
Records if this value needs to be treated in an ABI dependant manner, different to normal type legali...
SDNode * getNodeForIRValue(const Value *V)
Return the SDNode for the specified IR value if it exists.
demanded bits
This class implements a map that also provides access to all stored values in a deterministic order...
Definition: MapVector.h:37
A debug info location.
Definition: DebugLoc.h:33
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1077
F(f)
An instruction for reading from memory.
Definition: Instructions.h:167
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
SDNode * getNode() const
get the SDNode which holds the desired result
This is the common base class for constrained floating point intrinsics.
SDValue getValueImpl(const Value *V)
getValueImpl - Helper function for getValue and getNonRegisterValue.
uint64_t High
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, Instruction::BinaryOps Opc, BranchProbability TProb, BranchProbability FProb, bool InvertCond)
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, BranchProbability TProb, BranchProbability FProb, bool InvertCond)
EmitBranchForMergedCondition - Helper method for FindMergedConditions.
SDValue getValue(const Value *V)
getValue - Return an SDValue for the given Value.
StackProtectorDescriptor SPDescriptor
A StackProtectorDescriptor structure used to communicate stack protector information in between Selec...
void visitSPDescriptorParent(StackProtectorDescriptor &SPD, MachineBasicBlock *ParentBB)
Codegen a new tail for a stack protector check ParentMBB which has had its tail spliced into a stack ...
SDValue getRoot()
Return the current virtual root of the Selection DAG, flushing any PendingLoad items.
void visitSwitchCase(CaseBlock &CB, MachineBasicBlock *SwitchBB)
visitSwitchCase - Emits the necessary code to represent a single node in the binary search tree resul...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
Shift and rotation operations.
Definition: ISDOpcodes.h:434
void resolveOrClearDbgInfo()
Evict any dangling debug information, attempting to salvage it first.
void visitJumpTable(JumpTable &JT)
visitJumpTable - Emit JumpTable node in the current MBB
ArrayRef< const Use > GCTransitionArgs
The list of gc transition arguments present in the gc.statepoint being lowered.
SmallVector< EVT, 4 > ValueVTs
The value types of the values, which may not be legal, and may need be promoted or synthesized from o...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:403
SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SI)
Lower SLI into a STATEPOINT instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SDValue getNonRegisterValue(const Value *V)
getNonRegisterValue - Return an SDValue for the given Value, but don&#39;t look in FuncInfo.ValueMap for a virtual register.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool ShouldEmitAsBranches(const std::vector< CaseBlock > &Cases)
If the set of cases should be emitted as a series of branches, return true.
SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, SDValue Op)
An instruction for storing to memory.
Definition: Instructions.h:320
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
void init(GCFunctionInfo *gfi, AliasAnalysis *AA, const TargetLibraryInfo *li)
bool findValue(const Value *V) const
Debug location.
void append(const RegsForValue &RHS)
Add the specified values to this one.
void salvageUnresolvedDbgValue(DanglingDebugInfo &DDI)
For the given dangling debuginfo record, perform last-ditch efforts to resolve the debuginfo to somet...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
bool handleDebugValue(const Value *V, DILocalVariable *Var, DIExpression *Expr, DebugLoc CurDL, DebugLoc InstDL, unsigned Order)
For a given Value, attempt to create and record a SDDbgValue in the SelectionDAG. ...
#define P(N)
std::pair< SDValue, SDValue > lowerInvokable(TargetLowering::CallLoweringInfo &CLI, const BasicBlock *EHPadBB=nullptr)
The landingpad instruction holds all of the information necessary to generate correct exception handl...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
bool HasTailCall
This is set to true if a call in the current block has been translated as a tail call.
ArrayRef< const Use > DeoptState
The deoptimization state associated with this gc.statepoint call, if any.
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
Conditional or Unconditional Branch instruction.
This function has undefined behavior.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Resume the propagation of an exception.
Indirect Branch Instruction.
#define H(x, y, z)
Definition: MD5.cpp:57
void LowerCallSiteWithDeoptBundleImpl(const CallBase *Call, SDValue Callee, const BasicBlock *EHPadBB, bool VarArgDisallowed, bool ForceVoidReturnTy)
void dropDanglingDebugInfo(const DILocalVariable *Variable, const DIExpression *Expr)
If we have dangling debug info that describes Variable, or an overlapping part of variable considerin...
This class tracks both per-statepoint and per-selectiondag information.
Extended Value Type.
Definition: ValueTypes.h:33
This class represents the va_arg llvm instruction, which returns an argument of the specified type gi...
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CallBr instruction, tracking function calls that may not return control but instead transfer it to a ...
void CopyToExportRegsIfNeeded(const Value *V)
CopyToExportRegsIfNeeded - If the given value has virtual registers created for it, emit nodes to copy the value into the virtual registers.
static BranchProbability getUnknown()
void visitSPDescriptorFailure(StackProtectorDescriptor &SPD)
Codegen the failure basic block for a stack protector check.
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:406
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
SmallVector< unsigned, 4 > RegCount
This list holds the number of registers for each value.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
This struct represents the registers (physical or virtual) that a particular set of values is assigne...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
Provides information about what library functions are available for the current target.
void clear()
Clear out the current SelectionDAG and the associated state and prepare this SelectionDAGBuilder obje...
void visit(const Instruction &I)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Represents one node in the SelectionDAG.
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last)
When an MBB was split during scheduling, update the references that need to refer to the last resulti...
DWARF expression.
GCFunctionInfo * GFI
Garbage collection metadata for the function.
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, ArrayRef< StringRef > StandardNames)
Initialize the set of available library functions based on the specified target triple.
void visitBitTestCase(BitTestBlock &BB, MachineBasicBlock *NextMBB, BranchProbability BranchProbToNext, unsigned Reg, BitTestCase &B, MachineBasicBlock *SwitchBB)
visitBitTestCase - this function produces one "bit test"
std::vector< JumpTableBlock > JTCases
Vector of JumpTable structures used to communicate SwitchInst code generation information.
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:495
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:387
could "use" a pointer
SmallVector< SDValue, 8 > PendingLoads
Loads are not emitted to the program immediately.
bool hasValue() const
Definition: Optional.h:259
void LowerStatepoint(ImmutableStatepoint ISP, const BasicBlock *EHPadBB=nullptr)
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
Definition: Instruction.h:321
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:411
This represents the llvm.dbg.value instruction.
Establish a view to a call site for examination.
Definition: CallSite.h:892
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
SmallVector< const Value *, 16 > Bases
Bases[i] is the base pointer for Ptrs[i].
StatepointLoweringState StatepointLowering
State used while lowering a statepoint sequence (gc_statepoint, gc_relocate, and gc_result).
SDValue getCopyFromRegs(const Value *V, Type *Ty)
If there was virtual register allocated for the value V emit CopyFromReg of the specified type Ty...
void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall, const BasicBlock *EHPadBB=nullptr)
Multiway switch.
FunctionLoweringInfo & FuncInfo
Information about the function as a whole.
SmallVector< MVT, 4 > RegVTs
The value types of the registers.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void setUnusedArgValue(const Value *V, SDValue NewN)
Represents calls to the gc.relocate intrinsic.
Definition: Statepoint.h:360
LLVM Value Representation.
Definition: Value.h:72
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
void populateCallLoweringInfo(TargetLowering::CallLoweringInfo &CLI, const CallBase *Call, unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, bool IsPatchPoint)
Populate a CallLowerinInfo (into CLI) based on the properties of the call being lowered.
ArrayRef< const Use > GCArgs
The full list of gc arguments to the gc.statepoint being lowered.
MVT getFrameIndexTy()
Returns the type of FrameIndex and TargetFrameIndex nodes.
Invoke instruction.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
std::vector< CaseBlock > SwitchCases
Vector of CaseBlock structures used to communicate SwitchInst code generation information.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
SDValue getControlRoot()
Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports i...
Garbage collection metadata for a single function.
Definition: GCMetadata.h:77
void clearDanglingDebugInfo()
Clear the dangling debug information map.
DenseMap< const Constant *, unsigned > ConstantsOut
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB)
Holds the information from a dbg_value node through SDISel.
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:610
SmallVector< unsigned, 4 > Regs
This list holds the registers assigned to the values.
void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB)
visitBitTestHeader - This function emits necessary code to produce value suitable for "bit tests" ...
static const unsigned LowestSDNodeOrder
Lowest valid SDNodeOrder.
void resolveDanglingDebugInfo(const Value *V, SDValue Val)
If we saw an earlier dbg_value referring to V, generate the debug data structures now that we&#39;ve seen...
Describes a gc.statepoint or a gc.statepoint like thing for the purposes of lowering into a STATEPOIN...
This file describes how to lower LLVM code to machine code.
an instruction to allocate memory on the stack
Definition: Instructions.h:59
bool occupiesMultipleRegs() const
Check if the total RegCount is greater than one.