14#ifndef LLVM_TARGETPARSER_AARCH64TARGETPARSER_H
15#define LLVM_TARGETPARSER_AARCH64TARGETPARSER_H
99 "Number of features in CPUFeatures are limited to 62 entries");
219 {
"f32mm",
AArch64::AEK_F32MM,
"+f32mm",
"-f32mm",
FEAT_SVE_F32MM,
"+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350},
220 {
"f64mm",
AArch64::AEK_F64MM,
"+f64mm",
"-f64mm",
FEAT_SVE_F64MM,
"+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360},
226 {
"fp16fml",
AArch64::AEK_FP16FML,
"+fp16fml",
"-fp16fml",
FEAT_FP16FML,
"+fp16fml,+fullfp16,+fp-armv8,+neon", 40},
258 {
"sha3",
AArch64::AEK_SHA3,
"+sha3",
"-sha3",
FEAT_SHA3,
"+sha3,+sha2,+fp-armv8,+neon", 140},
269 {
"sve-bf16",
AArch64::AEK_NONE, {}, {},
FEAT_SVE_BF16,
"+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320},
270 {
"sve-ebf16",
AArch64::AEK_NONE, {}, {},
FEAT_SVE_EBF16,
"+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330},
271 {
"sve-i8mm",
AArch64::AEK_NONE, {}, {},
FEAT_SVE_I8MM,
"+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340},
272 {
"sve",
AArch64::AEK_SVE,
"+sve",
"-sve",
FEAT_SVE,
"+sve,+fullfp16,+fp-armv8,+neon", 310},
273 {
"sve2-aes",
AArch64::AEK_SVE2AES,
"+sve2-aes",
"-sve2-aes",
FEAT_SVE_AES,
"+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380},
274 {
"sve2-bitperm",
AArch64::AEK_SVE2BITPERM,
"+sve2-bitperm",
"-sve2-bitperm",
FEAT_SVE_BITPERM,
"+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400},
275 {
"sve2-pmull128",
AArch64::AEK_NONE, {}, {},
FEAT_SVE_PMULL128,
"+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390},
276 {
"sve2-sha3",
AArch64::AEK_SVE2SHA3,
"+sve2-sha3",
"-sve2-sha3",
FEAT_SVE_SHA3,
"+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410},
277 {
"sve2-sm4",
AArch64::AEK_SVE2SM4,
"+sve2-sm4",
"-sve2-sm4",
FEAT_SVE_SM4,
"+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420},
278 {
"sve2",
AArch64::AEK_SVE2,
"+sve2",
"-sve2",
FEAT_SVE2,
"+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370},
279 {
"sve2p1",
AArch64::AEK_SVE2p1,
"+sve2p1",
"-sve2p1",
FEAT_INIT,
"+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon", 0},
315 return this->Name ==
Other.Name;
318 return this->Name !=
Other.Name;
332 if (this->Profile !=
Other.Profile)
335 return this->Version >
Other.Version;
337 if (this->Version.
getMajor() == 9 &&
Other.Version.getMajor() == 8) {
339 "AArch64::ArchInfo should have a minor version.");
340 return this->Version.
getMinor().value_or(0) + 5 >=
341 Other.Version.getMinor().value_or(0);
389static constexpr std::array<const ArchInfo *, 17>
ArchInfos = {
700 std::vector<StringRef> &Features);
This file defines the StringMap class.
static constexpr ImpliedExtsEntry ImpliedExts[]
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Defines the llvm::VersionTuple class, which represents a version in the form major[....
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
StringRef - Represent a constant reference to a string, i.e.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Triple - Helper class for working with autoconf configuration names.
Represents a version number in the form major[.minor[.subminor[.build]]].
unsigned getMajor() const
Retrieve the major version number.
std::optional< unsigned > getMinor() const
Retrieve the minor version number, if provided.
void PrintSupportedExtensions(StringMap< StringRef > DescMap)
constexpr ArchInfo ARMV8_9A
bool isX18ReservedByDefault(const Triple &TT)
StringRef getArchExtFeature(StringRef ArchExt)
std::optional< ExtensionInfo > parseArchExtension(StringRef Extension)
constexpr ArchInfo ARMV8_3A
constexpr CpuInfo CpuInfos[]
constexpr ArchInfo ARMV8_7A
constexpr ArchInfo ARMV8R
std::optional< CpuInfo > parseCpu(StringRef Name)
constexpr ArchInfo ARMV8_4A
uint64_t getCpuSupportsMask(ArrayRef< StringRef > FeatureStrs)
constexpr ArchInfo ARMV9_3A
constexpr ArchInfo ARMV8_6A
constexpr ArchInfo ARMV8_5A
constexpr ArchInfo ARMV8A
constexpr ArchInfo ARMV9_1A
constexpr ArchInfo ARMV9A
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values)
std::optional< ArchInfo > parseArch(StringRef Arch)
constexpr ArchInfo ARMV9_2A
constexpr CpuAlias CpuAliases[]
constexpr ArchInfo ARMV9_4A
constexpr ArchInfo ARMV9_5A
std::optional< ArchInfo > getArchForCpu(StringRef CPU)
static constexpr std::array< const ArchInfo *, 17 > ArchInfos
StringRef resolveCPUAlias(StringRef CPU)
bool getExtensionFeatures(const AArch64::ExtensionBitset &Extensions, std::vector< StringRef > &Features)
constexpr ArchInfo ARMV8_8A
constexpr ArchInfo ARMV8_1A
constexpr ArchInfo ARMV8_2A
Bitset< AEK_NUM_EXTENSIONS > ExtensionBitset
constexpr ExtensionInfo Extensions[]
This is an optimization pass for GlobalISel generic memory operations.
StringRef getSubArch() const
bool implies(const ArchInfo &Other) const
AArch64::ExtensionBitset DefaultExts
static std::optional< ArchInfo > findBySubArch(StringRef SubArch)
bool operator==(const ArchInfo &Other) const
bool operator!=(const ArchInfo &Other) const
AArch64::ExtensionBitset getImpliedExtensions() const
AArch64::ExtensionBitset DefaultExtensions
static constexpr unsigned MaxFMVPriority
StringRef DependentFeatures