LLVM 23.0.0git
MipsRegisterInfo.h
Go to the documentation of this file.
1//===- MipsRegisterInfo.h - Mips Register Information Impl ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H
14#define LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H
15
16#include "Mips.h"
18#include <cstdint>
19
20#define GET_REGINFO_HEADER
21#include "MipsGenRegisterInfo.inc"
22
23namespace llvm {
24
25class MCRegisterClass;
26using TargetRegisterClass = MCRegisterClass;
27
29private:
30 const bool ArePtrs64bit;
31
32public:
33 explicit MipsRegisterInfo(const MipsSubtarget &STI);
34
35 /// Get PIC indirect call register
36 static unsigned getPICCallReg();
37
38 /// Code Generation virtual methods...
39 const TargetRegisterClass *getPointerRegClass(unsigned Kind) const override;
40
42 MachineFunction &MF) const override;
43 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
45 CallingConv::ID) const override;
46 static const uint32_t *getMips16RetHelperMask();
47
48 BitVector getReservedRegs(const MachineFunction &MF) const override;
49
50 /// Stack Frame Processing Methods
52 int SPAdj, unsigned FIOperandNum,
53 RegScavenger *RS = nullptr) const override;
54
55 // Stack realignment queries.
56 bool canRealignStack(const MachineFunction &MF) const override;
57
58 /// Debug information queries.
59 Register getFrameRegister(const MachineFunction &MF) const override;
60
61 /// Return GPR register class.
62 virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
63
64private:
65 virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
66 int FrameIndex, uint64_t StackSize,
67 int64_t SPOffset) const = 0;
68};
69
70} // end namespace llvm
71
72#endif // LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H
uint64_t IntrinsicInst * II
MachineInstrBundleIterator< MachineInstr > iterator
static unsigned getPICCallReg()
Get PIC indirect call register.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Register getFrameRegister(const MachineFunction &MF) const override
Debug information queries.
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Stack Frame Processing Methods.
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
static const uint32_t * getMips16RetHelperMask()
bool canRealignStack(const MachineFunction &MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
MipsRegisterInfo(const MipsSubtarget &STI)
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Mips Callee Saved Registers.
const TargetRegisterClass * getPointerRegClass(unsigned Kind) const override
Code Generation virtual methods...
virtual const TargetRegisterClass * intRegClass(unsigned Size) const =0
Return GPR register class.
Wrapper class representing virtual and physical registers.
Definition Register.h:20
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
MCRegisterClass TargetRegisterClass
Definition FastISel.h:58