LLVM  13.0.0git
MipsRegisterInfo.cpp
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1 //===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the MIPS implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsRegisterInfo.h"
15 #include "Mips.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/Support/Debug.h"
33 #include <cstdint>
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mips-reg-info"
38 
39 #define GET_REGINFO_TARGET_DESC
40 #include "MipsGenRegisterInfo.inc"
41 
43 
44 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
45 
46 const TargetRegisterClass *
48  unsigned Kind) const {
49  MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
50  MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
51 
52  switch (PtrClassKind) {
54  return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
56  return &Mips::GPRMM16RegClass;
58  return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
60  return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
61  }
62 
63  llvm_unreachable("Unknown pointer kind");
64 }
65 
66 unsigned
68  MachineFunction &MF) const {
69  switch (RC->getID()) {
70  default:
71  return 0;
72  case Mips::GPR32RegClassID:
73  case Mips::GPR64RegClassID:
74  case Mips::DSPRRegClassID: {
76  return 28 - TFI->hasFP(MF);
77  }
78  case Mips::FGR32RegClassID:
79  return 32;
80  case Mips::AFGR64RegClassID:
81  return 16;
82  case Mips::FGR64RegClassID:
83  return 32;
84  }
85 }
86 
87 //===----------------------------------------------------------------------===//
88 // Callee Saved Registers methods
89 //===----------------------------------------------------------------------===//
90 
91 /// Mips Callee Saved Registers
92 const MCPhysReg *
94  const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
95  const Function &F = MF->getFunction();
96  if (F.hasFnAttribute("interrupt")) {
97  if (Subtarget.hasMips64())
98  return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
99  : CSR_Interrupt_64_SaveList;
100  else
101  return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
102  : CSR_Interrupt_32_SaveList;
103  }
104 
105  if (Subtarget.isSingleFloat())
106  return CSR_SingleFloatOnly_SaveList;
107 
108  if (Subtarget.isABI_N64())
109  return CSR_N64_SaveList;
110 
111  if (Subtarget.isABI_N32())
112  return CSR_N32_SaveList;
113 
114  if (Subtarget.isFP64bit())
115  return CSR_O32_FP64_SaveList;
116 
117  if (Subtarget.isFPXX())
118  return CSR_O32_FPXX_SaveList;
119 
120  return CSR_O32_SaveList;
121 }
122 
123 const uint32_t *
125  CallingConv::ID) const {
126  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
127  if (Subtarget.isSingleFloat())
128  return CSR_SingleFloatOnly_RegMask;
129 
130  if (Subtarget.isABI_N64())
131  return CSR_N64_RegMask;
132 
133  if (Subtarget.isABI_N32())
134  return CSR_N32_RegMask;
135 
136  if (Subtarget.isFP64bit())
137  return CSR_O32_FP64_RegMask;
138 
139  if (Subtarget.isFPXX())
140  return CSR_O32_FPXX_RegMask;
141 
142  return CSR_O32_RegMask;
143 }
144 
146  return CSR_Mips16RetHelper_RegMask;
147 }
148 
151  static const MCPhysReg ReservedGPR32[] = {
152  Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
153  };
154 
155  static const MCPhysReg ReservedGPR64[] = {
156  Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
157  };
158 
159  BitVector Reserved(getNumRegs());
160  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
161 
162  for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
163  Reserved.set(ReservedGPR32[I]);
164 
165  // Reserve registers for the NaCl sandbox.
166  if (Subtarget.isTargetNaCl()) {
167  Reserved.set(Mips::T6); // Reserved for control flow mask.
168  Reserved.set(Mips::T7); // Reserved for memory access mask.
169  Reserved.set(Mips::T8); // Reserved for thread pointer.
170  }
171 
172  for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
173  Reserved.set(ReservedGPR64[I]);
174 
175  // For mno-abicalls, GP is a program invariant!
176  if (!Subtarget.isABICalls()) {
177  Reserved.set(Mips::GP);
178  Reserved.set(Mips::GP_64);
179  }
180 
181  if (Subtarget.isFP64bit()) {
182  // Reserve all registers in AFGR64.
183  for (MCPhysReg Reg : Mips::AFGR64RegClass)
184  Reserved.set(Reg);
185  } else {
186  // Reserve all registers in FGR64.
187  for (MCPhysReg Reg : Mips::FGR64RegClass)
188  Reserved.set(Reg);
189  }
190  // Reserve FP if this function should have a dedicated frame pointer register.
191  if (Subtarget.getFrameLowering()->hasFP(MF)) {
192  if (Subtarget.inMips16Mode())
193  Reserved.set(Mips::S0);
194  else {
195  Reserved.set(Mips::FP);
196  Reserved.set(Mips::FP_64);
197 
198  // Reserve the base register if we need to both realign the stack and
199  // allocate variable-sized objects at runtime. This should test the
200  // same conditions as MipsFrameLowering::hasBP().
201  if (hasStackRealignment(MF) && MF.getFrameInfo().hasVarSizedObjects()) {
202  Reserved.set(Mips::S7);
203  Reserved.set(Mips::S7_64);
204  }
205  }
206  }
207 
208  // Reserve hardware registers.
209  Reserved.set(Mips::HWR29);
210 
211  // Reserve DSP control register.
212  Reserved.set(Mips::DSPPos);
213  Reserved.set(Mips::DSPSCount);
214  Reserved.set(Mips::DSPCarry);
215  Reserved.set(Mips::DSPEFI);
216  Reserved.set(Mips::DSPOutFlag);
217 
218  // Reserve MSA control registers.
219  for (MCPhysReg Reg : Mips::MSACtrlRegClass)
220  Reserved.set(Reg);
221 
222  // Reserve RA if in mips16 mode.
223  if (Subtarget.inMips16Mode()) {
224  const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
225  Reserved.set(Mips::RA);
226  Reserved.set(Mips::RA_64);
227  Reserved.set(Mips::T0);
228  Reserved.set(Mips::T1);
229  if (MF.getFunction().hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
230  Reserved.set(Mips::S2);
231  }
232 
233  // Reserve GP if small section is used.
234  if (Subtarget.useSmallSection()) {
235  Reserved.set(Mips::GP);
236  Reserved.set(Mips::GP_64);
237  }
238 
239  return Reserved;
240 }
241 
242 bool
244  return true;
245 }
246 
247 // FrameIndex represent objects inside a abstract stack.
248 // We must replace FrameIndex with an stack/frame pointer
249 // direct reference.
252  unsigned FIOperandNum, RegScavenger *RS) const {
253  MachineInstr &MI = *II;
254  MachineFunction &MF = *MI.getParent()->getParent();
255 
256  LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
257  errs() << "<--------->\n"
258  << MI);
259 
260  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
261  uint64_t stackSize = MF.getFrameInfo().getStackSize();
262  int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex);
263 
264  LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
265  << "spOffset : " << spOffset << "\n"
266  << "stackSize : " << stackSize << "\n"
267  << "alignment : "
269  << "\n");
270 
271  eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
272 }
273 
276  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
277  const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
278  bool IsN64 =
279  static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
280 
281  if (Subtarget.inMips16Mode())
282  return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
283  else
284  return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
285  (IsN64 ? Mips::SP_64 : Mips::SP);
286 }
287 
289  // Avoid realigning functions that explicitly do not want to be realigned.
290  // Normally, we should report an error when a function should be dynamically
291  // realigned but also has the attribute no-realign-stack. Unfortunately,
292  // with this attribute, MachineFrameInfo clamps each new object's alignment
293  // to that of the stack's alignment as specified by the ABI. As a result,
294  // the information of whether we have objects with larger alignment
295  // requirement than the stack's alignment is already lost at this point.
297  return false;
298 
299  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
300  unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
301  unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
302 
303  // Support dynamic stack realignment for all targets except Mips16.
304  if (Subtarget.inMips16Mode())
305  return false;
306 
307  // We can't perform dynamic stack realignment if we can't reserve the
308  // frame pointer register.
309  if (!MF.getRegInfo().canReserveReg(FP))
310  return false;
311 
312  // We can realign the stack if we know the maximum call frame size and we
313  // don't have variable sized objects.
314  if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
315  return true;
316 
317  // We have to reserve the base pointer register in the presence of variable
318  // sized objects.
319  return MF.getRegInfo().canReserveReg(BP);
320 }
llvm::EngineKind::Kind
Kind
Definition: ExecutionEngine.h:524
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:351
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
MachineInstr.h
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:69
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
TargetFrameLowering.h
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:42
llvm::MipsABIInfo
Definition: MipsABIInfo.h:22
llvm::Function
Definition: Function.h:61
llvm::DebugStr
std::string DebugStr(const Align &A)
Definition: Alignment.h:360
ErrorHandling.h
llvm::MipsSubtarget::hasMips64r6
bool hasMips64r6() const
Definition: MipsSubtarget.h:276
llvm::MachineRegisterInfo::canReserveReg
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
Definition: MachineRegisterInfo.h:882
llvm::MipsSubtarget::hasMips64
bool hasMips64() const
Definition: MipsSubtarget.h:272
T1
#define T1
Definition: Mips16ISelLowering.cpp:340
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:345
llvm::MipsFunctionInfo::hasSaveS2
bool hasSaveS2() const
Definition: MipsMachineFunction.h:77
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:894
STLExtras.h
llvm::MipsSubtarget::isFPXX
bool isFPXX() const
Definition: MipsSubtarget.h:283
MipsTargetMachine.h
llvm::MipsRegisterInfo::MipsPtrClass::GlobalPointer
@ GlobalPointer
The global pointer only.
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::MipsFunctionInfo
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Definition: MipsMachineFunction.h:25
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
MipsGenRegisterInfo
llvm::MipsRegisterInfo::MipsPtrClass::Default
@ Default
The default register class for integer values.
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:460
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::MipsRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Mips Callee Saved Registers.
Definition: MipsRegisterInfo.cpp:93
llvm::MipsSubtarget::isGP32bit
bool isGP32bit() const
Definition: MipsSubtarget.h:290
llvm::MipsRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Debug information queries.
Definition: MipsRegisterInfo.cpp:275
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::MipsSubtarget::inMips16Mode
bool inMips16Mode() const
Definition: MipsSubtarget.h:300
llvm::TargetFrameLowering::hasReservedCallFrame
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: TargetFrameLowering.h:278
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
Mips.h
llvm::MipsRegisterInfo::getMips16RetHelperMask
static const uint32_t * getMips16RetHelperMask()
Definition: MipsRegisterInfo.cpp:145
MipsRegisterInfo.h
llvm::MipsRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: MipsRegisterInfo.cpp:67
llvm::TargetFrameLowering::hasFP
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
BitVector.h
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:563
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:504
llvm::BitVector
Definition: BitVector.h:74
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1348
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::MipsSubtarget::hasMips32r6
bool hasMips32r6() const
Definition: MipsSubtarget.h:268
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MipsSubtarget::isABI_N32
bool isABI_N32() const
Definition: MipsSubtarget.cpp:277
llvm::MipsRegisterInfo::MipsPtrClass::GPR16MM
@ GPR16MM
The subset of registers permitted in certain microMIPS instructions such as lw16.
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:471
MipsMachineFunction.h
llvm::MipsSubtarget::isSingleFloat
bool isSingleFloat() const
Definition: MipsSubtarget.h:297
MCRegisterInfo.h
llvm::X86II::T8
@ T8
Definition: X86BaseInfo.h:803
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:522
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::MipsSubtarget::isABI_N64
bool isABI_N64() const
Definition: MipsSubtarget.cpp:276
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MipsRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind) const override
Code Generation virtual methods...
Definition: MipsRegisterInfo.cpp:47
llvm::MipsRegisterInfo::MipsPtrClass::StackPointer
@ StackPointer
The stack pointer only.
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
uint32_t
TargetSubtargetInfo.h
llvm::MipsRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Stack Frame Processing Methods.
Definition: MipsRegisterInfo.cpp:251
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:93
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:551
MachineFrameInfo.h
MipsABIInfo.h
llvm::MipsSubtarget::getFrameLowering
const TargetFrameLowering * getFrameLowering() const override
Definition: MipsSubtarget.h:383
Function.h
llvm::MipsSubtarget::isABICalls
bool isABICalls() const
Definition: MipsSubtarget.h:282
llvm::MipsRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: MipsRegisterInfo.cpp:150
llvm::MipsSubtarget::useSmallSection
bool useSmallSection() const
Definition: MipsSubtarget.h:329
llvm::MipsSubtarget::isTargetNaCl
bool isTargetNaCl() const
Definition: MipsSubtarget.h:352
llvm::PseudoProbeAttributes::Reserved
@ Reserved
MipsSubtarget.h
llvm::MipsRegisterInfo::canRealignStack
bool canRealignStack(const MachineFunction &MF) const override
Definition: MipsRegisterInfo.cpp:288
llvm::MipsSubtarget::isFP64bit
bool isFP64bit() const
Definition: MipsSubtarget.h:284
llvm::MipsRegisterInfo::getPICCallReg
static unsigned getPICCallReg()
Get PIC indirect call register.
Definition: MipsRegisterInfo.cpp:44
raw_ostream.h
MachineFunction.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MipsRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: MipsRegisterInfo.cpp:124
llvm::MipsRegisterInfo::MipsPtrClass
MipsPtrClass
Definition: MipsRegisterInfo.h:29
llvm::MipsRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Definition: MipsRegisterInfo.cpp:243
TargetRegisterInfo.h
Debug.h
llvm::MipsRegisterInfo::MipsRegisterInfo
MipsRegisterInfo()
Definition: MipsRegisterInfo.cpp:42