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37 #define DEBUG_TYPE "mips-reg-info"
39 #define GET_REGINFO_TARGET_DESC
40 #include "MipsGenRegisterInfo.inc"
48 unsigned Kind)
const {
52 switch (PtrClassKind) {
54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
56 return &Mips::GPRMM16RegClass;
58 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
60 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
69 switch (RC->
getID()) {
72 case Mips::GPR32RegClassID:
73 case Mips::GPR64RegClassID:
74 case Mips::DSPRRegClassID: {
76 return 28 - TFI->
hasFP(MF);
78 case Mips::FGR32RegClassID:
80 case Mips::AFGR64RegClassID:
82 case Mips::FGR64RegClassID:
96 if (
F.hasFnAttribute(
"interrupt")) {
98 return Subtarget.
hasMips64r6() ? CSR_Interrupt_64R6_SaveList
99 : CSR_Interrupt_64_SaveList;
101 return Subtarget.
hasMips32r6() ? CSR_Interrupt_32R6_SaveList
102 : CSR_Interrupt_32_SaveList;
106 return CSR_SingleFloatOnly_SaveList;
109 return CSR_N64_SaveList;
112 return CSR_N32_SaveList;
115 return CSR_O32_FP64_SaveList;
118 return CSR_O32_FPXX_SaveList;
120 return CSR_O32_SaveList;
128 return CSR_SingleFloatOnly_RegMask;
131 return CSR_N64_RegMask;
134 return CSR_N32_RegMask;
137 return CSR_O32_FP64_RegMask;
140 return CSR_O32_FPXX_RegMask;
142 return CSR_O32_RegMask;
146 return CSR_Mips16RetHelper_RegMask;
151 static const MCPhysReg ReservedGPR32[] = {
152 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
155 static const MCPhysReg ReservedGPR64[] = {
156 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
167 Reserved.
set(Mips::T6);
168 Reserved.
set(Mips::T7);
177 Reserved.
set(Mips::GP);
178 Reserved.
set(Mips::GP_64);
193 Reserved.
set(Mips::S0);
195 Reserved.
set(Mips::FP);
196 Reserved.
set(Mips::FP_64);
202 Reserved.
set(Mips::S7);
203 Reserved.
set(Mips::S7_64);
209 Reserved.
set(Mips::HWR29);
212 Reserved.
set(Mips::DSPPos);
213 Reserved.
set(Mips::DSPSCount);
214 Reserved.
set(Mips::DSPCarry);
215 Reserved.
set(Mips::DSPEFI);
216 Reserved.
set(Mips::DSPOutFlag);
225 Reserved.
set(Mips::RA);
226 Reserved.
set(Mips::RA_64);
227 Reserved.
set(Mips::T0);
230 Reserved.
set(Mips::S2);
235 Reserved.
set(Mips::GP);
236 Reserved.
set(Mips::GP_64);
257 errs() <<
"<--------->\n"
260 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
265 <<
"spOffset : " << spOffset <<
"\n"
266 <<
"stackSize : " << stackSize <<
"\n"
271 eliminateFI(
MI, FIOperandNum,
FrameIndex, stackSize, spOffset);
282 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
284 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
285 (IsN64 ? Mips::SP_64 : Mips::SP);
300 unsigned FP = Subtarget.
isGP32bit() ? Mips::FP : Mips::FP_64;
301 unsigned BP = Subtarget.
isGP32bit() ? Mips::S7 : Mips::S7_64;
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Generic address nodes are lowered to some combination of target independent and machine specific ABI
unsigned getID() const
Return the register class ID number.
This is an optimization pass for GlobalISel generic memory operations.
Information about stack frame layout on the target.
std::string DebugStr(const Align &A)
Reg
All possible values of the reg field in the ModR/M byte.
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ GlobalPointer
The global pointer only.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
@ Default
The default register class for integer values.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Mips Callee Saved Registers.
Register getFrameRegister(const MachineFunction &MF) const override
Debug information queries.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool inMips16Mode() const
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
static const uint32_t * getMips16RetHelperMask()
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Representation of each machine instruction.
@ GPR16MM
The subset of registers permitted in certain microMIPS instructions such as lw16.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
bool isSingleFloat() const
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
SI optimize exec mask operations pre RA
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind) const override
Code Generation virtual methods...
@ StackPointer
The stack pointer only.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Stack Frame Processing Methods.
Wrapper class representing virtual and physical registers.
Function & getFunction()
Return the LLVM function that this machine code represents.
virtual const TargetFrameLowering * getFrameLowering() const
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetFrameLowering * getFrameLowering() const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool useSmallSection() const
bool isTargetNaCl() const
bool canRealignStack(const MachineFunction &MF) const override
static unsigned getPICCallReg()
Get PIC indirect call register.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override