LLVM 17.0.0git
TargetRegisterInfo.h
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1//==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes an abstract interface used to get information about a
10// target machines register file. This information is used for a variety of
11// purposed, especially register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16#define LLVM_CODEGEN_TARGETREGISTERINFO_H
17
18#include "llvm/ADT/ArrayRef.h"
20#include "llvm/ADT/StringRef.h"
23#include "llvm/IR/CallingConv.h"
24#include "llvm/MC/LaneBitmask.h"
30#include <cassert>
31#include <cstdint>
32
33namespace llvm {
34
35class BitVector;
36class DIExpression;
37class LiveRegMatrix;
38class MachineFunction;
39class MachineInstr;
40class RegScavenger;
41class VirtRegMap;
42class LiveIntervals;
43class LiveInterval;
44
46public:
47 using iterator = const MCPhysReg *;
48 using const_iterator = const MCPhysReg *;
49 using sc_iterator = const TargetRegisterClass* const *;
50
51 // Instance variables filled by tablegen, do not use!
56 /// Classes with a higher priority value are assigned first by register
57 /// allocators using a greedy heuristic. The value is in the range [0,31].
58 const uint8_t AllocationPriority;
59
60 // Change allocation priority heuristic used by greedy.
61 const bool GlobalPriority;
62
63 /// Configurable target specific flags.
64 const uint8_t TSFlags;
65 /// Whether the class supports two (or more) disjunct subregister indices.
67 /// Whether a combination of subregisters can cover every register in the
68 /// class. See also the CoveredBySubRegs description in Target.td.
69 const bool CoveredBySubRegs;
72
73 /// Return the register class ID number.
74 unsigned getID() const { return MC->getID(); }
75
76 /// begin/end - Return all of the registers in this class.
77 ///
78 iterator begin() const { return MC->begin(); }
79 iterator end() const { return MC->end(); }
80
81 /// Return the number of registers in this class.
82 unsigned getNumRegs() const { return MC->getNumRegs(); }
83
85 getRegisters() const {
86 return make_range(MC->begin(), MC->end());
87 }
88
89 /// Return the specified register in the class.
90 MCRegister getRegister(unsigned i) const {
91 return MC->getRegister(i);
92 }
93
94 /// Return true if the specified register is included in this register class.
95 /// This does not include virtual registers.
96 bool contains(Register Reg) const {
97 /// FIXME: Historically this function has returned false when given vregs
98 /// but it should probably only receive physical registers
99 if (!Reg.isPhysical())
100 return false;
101 return MC->contains(Reg.asMCReg());
102 }
103
104 /// Return true if both registers are in this class.
105 bool contains(Register Reg1, Register Reg2) const {
106 /// FIXME: Historically this function has returned false when given a vregs
107 /// but it should probably only receive physical registers
108 if (!Reg1.isPhysical() || !Reg2.isPhysical())
109 return false;
110 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg());
111 }
112
113 /// Return the cost of copying a value between two registers in this class.
114 /// A negative number means the register class is very expensive
115 /// to copy e.g. status flag register classes.
116 int getCopyCost() const { return MC->getCopyCost(); }
117
118 /// Return true if this register class may be used to create virtual
119 /// registers.
120 bool isAllocatable() const { return MC->isAllocatable(); }
121
122 /// Return true if the specified TargetRegisterClass
123 /// is a proper sub-class of this TargetRegisterClass.
124 bool hasSubClass(const TargetRegisterClass *RC) const {
125 return RC != this && hasSubClassEq(RC);
126 }
127
128 /// Returns true if RC is a sub-class of or equal to this class.
129 bool hasSubClassEq(const TargetRegisterClass *RC) const {
130 unsigned ID = RC->getID();
131 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
132 }
133
134 /// Return true if the specified TargetRegisterClass is a
135 /// proper super-class of this TargetRegisterClass.
136 bool hasSuperClass(const TargetRegisterClass *RC) const {
137 return RC->hasSubClass(this);
138 }
139
140 /// Returns true if RC is a super-class of or equal to this class.
141 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
142 return RC->hasSubClassEq(this);
143 }
144
145 /// Returns a bit vector of subclasses, including this one.
146 /// The vector is indexed by class IDs.
147 ///
148 /// To use it, consider the returned array as a chunk of memory that
149 /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
150 /// contains a bitset of the ID of the subclasses in big-endian style.
151
152 /// I.e., the representation of the memory from left to right at the
153 /// bit level looks like:
154 /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
155 /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
156 /// Where the number represents the class ID and XXX bits that
157 /// should be ignored.
158 ///
159 /// See the implementation of hasSubClassEq for an example of how it
160 /// can be used.
161 const uint32_t *getSubClassMask() const {
162 return SubClassMask;
163 }
164
165 /// Returns a 0-terminated list of sub-register indices that project some
166 /// super-register class into this register class. The list has an entry for
167 /// each Idx such that:
168 ///
169 /// There exists SuperRC where:
170 /// For all Reg in SuperRC:
171 /// this->contains(Reg:Idx)
173 return SuperRegIndices;
174 }
175
176 /// Returns a NULL-terminated list of super-classes. The
177 /// classes are ordered by ID which is also a topological ordering from large
178 /// to small classes. The list does NOT include the current class.
180 return SuperClasses;
181 }
182
183 /// Return true if this TargetRegisterClass is a subset
184 /// class of at least one other TargetRegisterClass.
185 bool isASubClass() const {
186 return SuperClasses[0] != nullptr;
187 }
188
189 /// Returns the preferred order for allocating registers from this register
190 /// class in MF. The raw order comes directly from the .td file and may
191 /// include reserved registers that are not allocatable.
192 /// Register allocators should also make sure to allocate
193 /// callee-saved registers only after all the volatiles are used. The
194 /// RegisterClassInfo class provides filtered allocation orders with
195 /// callee-saved registers moved to the end.
196 ///
197 /// The MachineFunction argument can be used to tune the allocatable
198 /// registers based on the characteristics of the function, subtarget, or
199 /// other criteria.
200 ///
201 /// By default, this method returns all registers in the class.
203 return OrderFunc ? OrderFunc(MF) : ArrayRef(begin(), getNumRegs());
204 }
205
206 /// Returns the combination of all lane masks of register in this class.
207 /// The lane masks of the registers are the combination of all lane masks
208 /// of their subregisters. Returns 1 if there are no subregisters.
210 return LaneMask;
211 }
212};
213
214/// Extra information, not in MCRegisterDesc, about registers.
215/// These are used by codegen, not by MC.
217 const uint8_t *CostPerUse; // Extra cost of instructions using register.
218 unsigned NumCosts; // Number of cost values associated with each register.
219 const bool
220 *InAllocatableClass; // Register belongs to an allocatable regclass.
221};
222
223/// Each TargetRegisterClass has a per register weight, and weight
224/// limit which must be less than the limits of its pressure sets.
226 unsigned RegWeight;
227 unsigned WeightLimit;
228};
229
230/// TargetRegisterInfo base class - We assume that the target defines a static
231/// array of TargetRegisterDesc objects that represent all of the machine
232/// registers that the target has. As such, we simply have to track a pointer
233/// to this array so that we can turn register number into a register
234/// descriptor.
235///
237public:
238 using regclass_iterator = const TargetRegisterClass * const *;
243 };
244private:
245 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
246 const char *const *SubRegIndexNames; // Names of subreg indexes.
247 // Pointer to array of lane masks, one per sub-reg index.
248 const LaneBitmask *SubRegIndexLaneMasks;
249
250 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
251 LaneBitmask CoveringLanes;
252 const RegClassInfo *const RCInfos;
253 unsigned HwMode;
254
255protected:
259 const char *const *SRINames,
260 const LaneBitmask *SRILaneMasks,
261 LaneBitmask CoveringLanes,
262 const RegClassInfo *const RCIs,
263 unsigned Mode = 0);
265
266public:
267 // Register numbers can represent physical registers, virtual registers, and
268 // sometimes stack slots. The unsigned values are divided into these ranges:
269 //
270 // 0 Not a register, can be used as a sentinel.
271 // [1;2^30) Physical registers assigned by TableGen.
272 // [2^30;2^31) Stack slots. (Rarely used.)
273 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
274 //
275 // Further sentinels can be allocated from the small negative integers.
276 // DenseMapInfo<unsigned> uses -1u and -2u.
277
278 /// Return the size in bits of a register from class RC.
279 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
280 return getRegClassInfo(RC).RegSize;
281 }
282
283 /// Return the size in bytes of the stack slot allocated to hold a spilled
284 /// copy of a register from class RC.
285 unsigned getSpillSize(const TargetRegisterClass &RC) const {
286 return getRegClassInfo(RC).SpillSize / 8;
287 }
288
289 /// Return the minimum required alignment in bytes for a spill slot for
290 /// a register of this class.
292 return Align(getRegClassInfo(RC).SpillAlignment / 8);
293 }
294
295 /// Return true if the given TargetRegisterClass has the ValueType T.
297 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
298 if (MVT(*I) == T)
299 return true;
300 return false;
301 }
302
303 /// Return true if the given TargetRegisterClass is compatible with LLT T.
305 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) {
306 MVT VT(*I);
307 if (VT == MVT::Untyped)
308 return true;
309
310 if (LLT(VT) == T)
311 return true;
312 }
313 return false;
314 }
315
316 /// Loop over all of the value types that can be represented by values
317 /// in the given register class.
319 return getRegClassInfo(RC).VTList;
320 }
321
324 while (*I != MVT::Other)
325 ++I;
326 return I;
327 }
328
329 /// Returns the Register Class of a physical register of the given type,
330 /// picking the most sub register class of the right type that contains this
331 /// physreg.
333 MVT VT = MVT::Other) const;
334
335 /// Returns the Register Class of a physical register of the given type,
336 /// picking the most sub register class of the right type that contains this
337 /// physreg. If there is no register class compatible with the given type,
338 /// returns nullptr.
340 LLT Ty = LLT()) const;
341
342 /// Return the maximal subclass of the given register class that is
343 /// allocatable or NULL.
344 const TargetRegisterClass *
346
347 /// Returns a bitset indexed by register number indicating if a register is
348 /// allocatable or not. If a register class is specified, returns the subset
349 /// for the class.
351 const TargetRegisterClass *RC = nullptr) const;
352
353 /// Get a list of cost values for all registers that correspond to the index
354 /// returned by RegisterCostTableIndex.
356 unsigned Idx = getRegisterCostTableIndex(MF);
357 unsigned NumRegs = getNumRegs();
358 assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds");
359
360 return ArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
361 }
362
363 /// Return true if the register is in the allocation of any register class.
365 return InfoDesc->InAllocatableClass[RegNo];
366 }
367
368 /// Return the human-readable symbolic target-specific
369 /// name for the specified SubRegIndex.
370 const char *getSubRegIndexName(unsigned SubIdx) const {
371 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
372 "This is not a subregister index");
373 return SubRegIndexNames[SubIdx-1];
374 }
375
376 /// Return a bitmask representing the parts of a register that are covered by
377 /// SubIdx \see LaneBitmask.
378 ///
379 /// SubIdx == 0 is allowed, it has the lane mask ~0u.
380 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
381 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
382 return SubRegIndexLaneMasks[SubIdx];
383 }
384
385 /// Try to find one or more subregister indexes to cover \p LaneMask.
386 ///
387 /// If this is possible, returns true and appends the best matching set of
388 /// indexes to \p Indexes. If this is not possible, returns false.
390 const TargetRegisterClass *RC,
391 LaneBitmask LaneMask,
392 SmallVectorImpl<unsigned> &Indexes) const;
393
394 /// The lane masks returned by getSubRegIndexLaneMask() above can only be
395 /// used to determine if sub-registers overlap - they can't be used to
396 /// determine if a set of sub-registers completely cover another
397 /// sub-register.
398 ///
399 /// The X86 general purpose registers have two lanes corresponding to the
400 /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
401 /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
402 /// sub_32bit sub-register.
403 ///
404 /// On the other hand, the ARM NEON lanes fully cover their registers: The
405 /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
406 /// This is related to the CoveredBySubRegs property on register definitions.
407 ///
408 /// This function returns a bit mask of lanes that completely cover their
409 /// sub-registers. More precisely, given:
410 ///
411 /// Covering = getCoveringLanes();
412 /// MaskA = getSubRegIndexLaneMask(SubA);
413 /// MaskB = getSubRegIndexLaneMask(SubB);
414 ///
415 /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
416 /// SubB.
417 LaneBitmask getCoveringLanes() const { return CoveringLanes; }
418
419 /// Returns true if the two registers are equal or alias each other.
420 /// The registers may be virtual registers.
421 bool regsOverlap(Register RegA, Register RegB) const {
422 if (RegA == RegB)
423 return true;
424 if (RegA.isPhysical() && RegB.isPhysical())
425 return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg());
426 return false;
427 }
428
429 /// Returns true if Reg contains RegUnit.
430 bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
431 for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
432 if (Register(*Units) == RegUnit)
433 return true;
434 return false;
435 }
436
437 /// Returns the original SrcReg unless it is the target of a copy-like
438 /// operation, in which case we chain backwards through all such operations
439 /// to the ultimate source register. If a physical register is encountered,
440 /// we stop the search.
441 virtual Register lookThruCopyLike(Register SrcReg,
442 const MachineRegisterInfo *MRI) const;
443
444 /// Find the original SrcReg unless it is the target of a copy-like operation,
445 /// in which case we chain backwards through all such operations to the
446 /// ultimate source register. If a physical register is encountered, we stop
447 /// the search.
448 /// Return the original SrcReg if all the definitions in the chain only have
449 /// one user and not a physical register.
450 virtual Register
452 const MachineRegisterInfo *MRI) const;
453
454 /// Return a null-terminated list of all of the callee-saved registers on
455 /// this target. The register should be in the order of desired callee-save
456 /// stack frame offset. The first register is closest to the incoming stack
457 /// pointer if stack grows down, and vice versa.
458 /// Notice: This function does not take into account disabled CSRs.
459 /// In most cases you will want to use instead the function
460 /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
461 virtual const MCPhysReg*
463
464 /// Return a mask of call-preserved registers for the given calling convention
465 /// on the current function. The mask should include all call-preserved
466 /// aliases. This is used by the register allocator to determine which
467 /// registers can be live across a call.
468 ///
469 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
470 /// A set bit indicates that all bits of the corresponding register are
471 /// preserved across the function call. The bit mask is expected to be
472 /// sub-register complete, i.e. if A is preserved, so are all its
473 /// sub-registers.
474 ///
475 /// Bits are numbered from the LSB, so the bit for physical register Reg can
476 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
477 ///
478 /// A NULL pointer means that no register mask will be used, and call
479 /// instructions should use implicit-def operands to indicate call clobbered
480 /// registers.
481 ///
483 CallingConv::ID) const {
484 // The default mask clobbers everything. All targets should override.
485 return nullptr;
486 }
487
488 /// Return a register mask for the registers preserved by the unwinder,
489 /// or nullptr if no custom mask is needed.
490 virtual const uint32_t *
492 return nullptr;
493 }
494
495 /// Return a register mask that clobbers everything.
496 virtual const uint32_t *getNoPreservedMask() const {
497 llvm_unreachable("target does not provide no preserved mask");
498 }
499
500 /// Return a list of all of the registers which are clobbered "inside" a call
501 /// to the given function. For example, these might be needed for PLT
502 /// sequences of long-branch veneers.
503 virtual ArrayRef<MCPhysReg>
505 return {};
506 }
507
508 /// Return true if all bits that are set in mask \p mask0 are also set in
509 /// \p mask1.
510 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
511
512 /// Return all the call-preserved register masks defined for this target.
515
516 /// Returns a bitset indexed by physical register number indicating if a
517 /// register is a special register that has particular uses and should be
518 /// considered unavailable at all times, e.g. stack pointer, return address.
519 /// A reserved register:
520 /// - is not allocatable
521 /// - is considered always live
522 /// - is ignored by liveness tracking
523 /// It is often necessary to reserve the super registers of a reserved
524 /// register as well, to avoid them getting allocated indirectly. You may use
525 /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
526 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
527
528 /// Returns either a string explaining why the given register is reserved for
529 /// this function, or an empty optional if no explanation has been written.
530 /// The absence of an explanation does not mean that the register is not
531 /// reserved (meaning, you should check that PhysReg is in fact reserved
532 /// before calling this).
533 virtual std::optional<std::string>
535 return {};
536 }
537
538 /// Returns false if we can't guarantee that Physreg, specified as an IR asm
539 /// clobber constraint, will be preserved across the statement.
540 virtual bool isAsmClobberable(const MachineFunction &MF,
541 MCRegister PhysReg) const {
542 return true;
543 }
544
545 /// Returns true if PhysReg cannot be written to in inline asm statements.
547 unsigned PhysReg) const {
548 return false;
549 }
550
551 /// Returns true if PhysReg is unallocatable and constant throughout the
552 /// function. Used by MachineRegisterInfo::isConstantPhysReg().
553 virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }
554
555 /// Returns true if the register class is considered divergent.
556 virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
557 return false;
558 }
559
560 /// Physical registers that may be modified within a function but are
561 /// guaranteed to be restored before any uses. This is useful for targets that
562 /// have call sequences where a GOT register may be updated by the caller
563 /// prior to a call and is guaranteed to be restored (also by the caller)
564 /// after the call.
566 const MachineFunction &MF) const {
567 return false;
568 }
569
570 /// This is a wrapper around getCallPreservedMask().
571 /// Return true if the register is preserved after the call.
572 virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
573 const MachineFunction &MF) const;
574
575 /// Returns true if PhysReg can be used as an argument to a function.
576 virtual bool isArgumentRegister(const MachineFunction &MF,
577 MCRegister PhysReg) const {
578 return false;
579 }
580
581 /// Returns true if PhysReg is a fixed register.
582 virtual bool isFixedRegister(const MachineFunction &MF,
583 MCRegister PhysReg) const {
584 return false;
585 }
586
587 /// Returns true if PhysReg is a general purpose register.
589 MCRegister PhysReg) const {
590 return false;
591 }
592
593 /// Prior to adding the live-out mask to a stackmap or patchpoint
594 /// instruction, provide the target the opportunity to adjust it (mainly to
595 /// remove pseudo-registers that should be ignored).
596 virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
597
598 /// Return a super-register of the specified register
599 /// Reg so its sub-register of index SubIdx is Reg.
601 const TargetRegisterClass *RC) const {
602 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
603 }
604
605 /// Return a subclass of the specified register
606 /// class A so that each register in it has a sub-register of the
607 /// specified sub-register index which is in the specified register class B.
608 ///
609 /// TableGen will synthesize missing A sub-classes.
610 virtual const TargetRegisterClass *
612 const TargetRegisterClass *B, unsigned Idx) const;
613
614 // For a copy-like instruction that defines a register of class DefRC with
615 // subreg index DefSubReg, reading from another source with class SrcRC and
616 // subregister SrcSubReg return true if this is a preferable copy
617 // instruction or an earlier use should be used.
618 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
619 unsigned DefSubReg,
620 const TargetRegisterClass *SrcRC,
621 unsigned SrcSubReg) const;
622
623 /// Returns the largest legal sub-class of RC that
624 /// supports the sub-register index Idx.
625 /// If no such sub-class exists, return NULL.
626 /// If all registers in RC already have an Idx sub-register, return RC.
627 ///
628 /// TableGen generates a version of this function that is good enough in most
629 /// cases. Targets can override if they have constraints that TableGen
630 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
631 /// supported by the full GR32 register class in 64-bit mode, but only by the
632 /// GR32_ABCD regiister class in 32-bit mode.
633 ///
634 /// TableGen will synthesize missing RC sub-classes.
635 virtual const TargetRegisterClass *
636 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
637 assert(Idx == 0 && "Target has no sub-registers");
638 return RC;
639 }
640
641 /// Return a register class that can be used for a subregister copy from/into
642 /// \p SuperRC at \p SubRegIdx.
643 virtual const TargetRegisterClass *
645 unsigned SubRegIdx) const {
646 return nullptr;
647 }
648
649 /// Return the subregister index you get from composing
650 /// two subregister indices.
651 ///
652 /// The special null sub-register index composes as the identity.
653 ///
654 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
655 /// returns c. Note that composeSubRegIndices does not tell you about illegal
656 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
657 /// b, composeSubRegIndices doesn't tell you.
658 ///
659 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
660 /// ssub_0:S0 - ssub_3:S3 subregs.
661 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
662 unsigned composeSubRegIndices(unsigned a, unsigned b) const {
663 if (!a) return b;
664 if (!b) return a;
665 return composeSubRegIndicesImpl(a, b);
666 }
667
668 /// Transforms a LaneMask computed for one subregister to the lanemask that
669 /// would have been computed when composing the subsubregisters with IdxA
670 /// first. @sa composeSubRegIndices()
672 LaneBitmask Mask) const {
673 if (!IdxA)
674 return Mask;
675 return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
676 }
677
678 /// Transform a lanemask given for a virtual register to the corresponding
679 /// lanemask before using subregister with index \p IdxA.
680 /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
681 /// valie lane mask (no invalid bits set) the following holds:
682 /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
683 /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
684 /// => X1 == Mask
686 LaneBitmask LaneMask) const {
687 if (!IdxA)
688 return LaneMask;
689 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
690 }
691
692 /// Debugging helper: dump register in human readable form to dbgs() stream.
693 static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
694 const TargetRegisterInfo *TRI = nullptr);
695
696 /// Return target defined base register class for a physical register.
697 /// This is the register class with the lowest BaseClassOrder containing the
698 /// register.
699 /// Will be nullptr if the register is not in any base register class.
701 return nullptr;
702 }
703
704protected:
705 /// Overridden by TableGen in targets that have sub-registers.
706 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
707 llvm_unreachable("Target has no sub-registers");
708 }
709
710 /// Overridden by TableGen in targets that have sub-registers.
711 virtual LaneBitmask
713 llvm_unreachable("Target has no sub-registers");
714 }
715
717 LaneBitmask) const {
718 llvm_unreachable("Target has no sub-registers");
719 }
720
721 /// Return the register cost table index. This implementation is sufficient
722 /// for most architectures and can be overriden by targets in case there are
723 /// multiple cost values associated with each register.
724 virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const {
725 return 0;
726 }
727
728public:
729 /// Find a common super-register class if it exists.
730 ///
731 /// Find a register class, SuperRC and two sub-register indices, PreA and
732 /// PreB, such that:
733 ///
734 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
735 ///
736 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
737 ///
738 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
739 ///
740 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
741 /// requirements, and there is no register class with a smaller spill size
742 /// that satisfies the requirements.
743 ///
744 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
745 ///
746 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
747 /// that case, the returned register class will be a sub-class of the
748 /// corresponding argument register class.
749 ///
750 /// The function returns NULL if no register class can be found.
752 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
753 const TargetRegisterClass *RCB, unsigned SubB,
754 unsigned &PreA, unsigned &PreB) const;
755
756 //===--------------------------------------------------------------------===//
757 // Register Class Information
758 //
759protected:
761 return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
762 }
763
764public:
765 /// Register class iterators
766 regclass_iterator regclass_begin() const { return RegClassBegin; }
767 regclass_iterator regclass_end() const { return RegClassEnd; }
770 }
771
772 unsigned getNumRegClasses() const {
773 return (unsigned)(regclass_end()-regclass_begin());
774 }
775
776 /// Returns the register class associated with the enumeration value.
777 /// See class MCOperandInfo.
778 const TargetRegisterClass *getRegClass(unsigned i) const {
779 assert(i < getNumRegClasses() && "Register Class ID out of range");
780 return RegClassBegin[i];
781 }
782
783 /// Returns the name of the register class.
784 const char *getRegClassName(const TargetRegisterClass *Class) const {
785 return MCRegisterInfo::getRegClassName(Class->MC);
786 }
787
788 /// Find the largest common subclass of A and B.
789 /// Return NULL if there is no common subclass.
790 const TargetRegisterClass *
792 const TargetRegisterClass *B) const;
793
794 /// Returns a TargetRegisterClass used for pointer values.
795 /// If a target supports multiple different pointer register classes,
796 /// kind specifies which one is indicated.
797 virtual const TargetRegisterClass *
798 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
799 llvm_unreachable("Target didn't implement getPointerRegClass!");
800 }
801
802 /// Returns a legal register class to copy a register in the specified class
803 /// to or from. If it is possible to copy the register directly without using
804 /// a cross register class copy, return the specified RC. Returns NULL if it
805 /// is not possible to copy between two registers of the specified class.
806 virtual const TargetRegisterClass *
808 return RC;
809 }
810
811 /// Returns the largest super class of RC that is legal to use in the current
812 /// sub-target and has the same spill size.
813 /// The returned register class can be used to create virtual registers which
814 /// means that all its registers can be copied and spilled.
815 virtual const TargetRegisterClass *
817 const MachineFunction &) const {
818 /// The default implementation is very conservative and doesn't allow the
819 /// register allocator to inflate register classes.
820 return RC;
821 }
822
823 /// Return the register pressure "high water mark" for the specific register
824 /// class. The scheduler is in high register pressure mode (for the specific
825 /// register class) if it goes over the limit.
826 ///
827 /// Note: this is the old register pressure model that relies on a manually
828 /// specified representative register class per value type.
829 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
830 MachineFunction &MF) const {
831 return 0;
832 }
833
834 /// Return a heuristic for the machine scheduler to compare the profitability
835 /// of increasing one register pressure set versus another. The scheduler
836 /// will prefer increasing the register pressure of the set which returns
837 /// the largest value for this function.
838 virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
839 unsigned PSetID) const {
840 return PSetID;
841 }
842
843 /// Get the weight in units of pressure for this register class.
845 const TargetRegisterClass *RC) const = 0;
846
847 /// Returns size in bits of a phys/virtual/generic register.
848 unsigned getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
849
850 /// Get the weight in units of pressure for this register unit.
851 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
852
853 /// Get the number of dimensions of register pressure.
854 virtual unsigned getNumRegPressureSets() const = 0;
855
856 /// Get the name of this register unit pressure set.
857 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
858
859 /// Get the register unit pressure limit for this dimension.
860 /// This limit must be adjusted dynamically for reserved registers.
861 virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
862 unsigned Idx) const = 0;
863
864 /// Get the dimensions of register pressure impacted by this register class.
865 /// Returns a -1 terminated array of pressure set IDs.
866 virtual const int *getRegClassPressureSets(
867 const TargetRegisterClass *RC) const = 0;
868
869 /// Get the dimensions of register pressure impacted by this register unit.
870 /// Returns a -1 terminated array of pressure set IDs.
871 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
872
873 /// Get a list of 'hint' registers that the register allocator should try
874 /// first when allocating a physical register for the virtual register
875 /// VirtReg. These registers are effectively moved to the front of the
876 /// allocation order. If true is returned, regalloc will try to only use
877 /// hints to the greatest extent possible even if it means spilling.
878 ///
879 /// The Order argument is the allocation order for VirtReg's register class
880 /// as returned from RegisterClassInfo::getOrder(). The hint registers must
881 /// come from Order, and they must not be reserved.
882 ///
883 /// The default implementation of this function will only add target
884 /// independent register allocation hints. Targets that override this
885 /// function should typically call this default implementation as well and
886 /// expect to see generic copy hints added.
887 virtual bool
890 const MachineFunction &MF,
891 const VirtRegMap *VRM = nullptr,
892 const LiveRegMatrix *Matrix = nullptr) const;
893
894 /// A callback to allow target a chance to update register allocation hints
895 /// when a register is "changed" (e.g. coalesced) to another register.
896 /// e.g. On ARM, some virtual registers should target register pairs,
897 /// if one of pair is coalesced to another register, the allocation hint of
898 /// the other half of the pair should be changed to point to the new register.
900 MachineFunction &MF) const {
901 // Do nothing.
902 }
903
904 /// Allow the target to reverse allocation order of local live ranges. This
905 /// will generally allocate shorter local live ranges first. For targets with
906 /// many registers, this could reduce regalloc compile time by a large
907 /// factor. It is disabled by default for three reasons:
908 /// (1) Top-down allocation is simpler and easier to debug for targets that
909 /// don't benefit from reversing the order.
910 /// (2) Bottom-up allocation could result in poor evicition decisions on some
911 /// targets affecting the performance of compiled code.
912 /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
913 virtual bool reverseLocalAssignment() const { return false; }
914
915 /// Allow the target to override the cost of using a callee-saved register for
916 /// the first time. Default value of 0 means we will use a callee-saved
917 /// register if it is available.
918 virtual unsigned getCSRFirstUseCost() const { return 0; }
919
920 /// Returns true if the target requires (and can make use of) the register
921 /// scavenger.
922 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
923 return false;
924 }
925
926 /// Returns true if the target wants to use frame pointer based accesses to
927 /// spill to the scavenger emergency spill slot.
928 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
929 return true;
930 }
931
932 /// Returns true if the target requires post PEI scavenging of registers for
933 /// materializing frame index constants.
934 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
935 return false;
936 }
937
938 /// Returns true if the target requires using the RegScavenger directly for
939 /// frame elimination despite using requiresFrameIndexScavenging.
941 const MachineFunction &MF) const {
942 return false;
943 }
944
945 /// Returns true if the target wants the LocalStackAllocation pass to be run
946 /// and virtual base registers used for more efficient stack access.
947 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
948 return false;
949 }
950
951 /// Return true if target has reserved a spill slot in the stack frame of
952 /// the given function for the specified register. e.g. On x86, if the frame
953 /// register is required, the first fixed stack object is reserved as its
954 /// spill slot. This tells PEI not to create a new stack frame
955 /// object for the given register. It should be called only after
956 /// determineCalleeSaves().
958 int &FrameIdx) const {
959 return false;
960 }
961
962 /// Returns true if the live-ins should be tracked after register allocation.
963 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
964 return true;
965 }
966
967 /// True if the stack can be realigned for the target.
968 virtual bool canRealignStack(const MachineFunction &MF) const;
969
970 /// True if storage within the function requires the stack pointer to be
971 /// aligned more than the normal calling convention calls for.
972 virtual bool shouldRealignStack(const MachineFunction &MF) const;
973
974 /// True if stack realignment is required and still possible.
975 bool hasStackRealignment(const MachineFunction &MF) const {
976 return shouldRealignStack(MF) && canRealignStack(MF);
977 }
978
979 /// Get the offset from the referenced frame index in the instruction,
980 /// if there is one.
982 int Idx) const {
983 return 0;
984 }
985
986 /// Returns true if the instruction's frame index reference would be better
987 /// served by a base register other than FP or SP.
988 /// Used by LocalStackFrameAllocation to determine which frame index
989 /// references it should create new base registers for.
990 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
991 return false;
992 }
993
994 /// Insert defining instruction(s) for a pointer to FrameIdx before
995 /// insertion point I. Return materialized frame pointer.
997 int FrameIdx,
998 int64_t Offset) const {
999 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
1000 "target");
1001 }
1002
1003 /// Resolve a frame index operand of an instruction
1004 /// to reference the indicated base register plus offset instead.
1006 int64_t Offset) const {
1007 llvm_unreachable("resolveFrameIndex does not exist on this target");
1008 }
1009
1010 /// Determine whether a given base register plus offset immediate is
1011 /// encodable to resolve a frame index.
1012 virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
1013 int64_t Offset) const {
1014 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
1015 }
1016
1017 /// Gets the DWARF expression opcodes for \p Offset.
1018 virtual void getOffsetOpcodes(const StackOffset &Offset,
1019 SmallVectorImpl<uint64_t> &Ops) const;
1020
1021 /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
1022 DIExpression *
1023 prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
1024 const StackOffset &Offset) const;
1025
1026 /// Spill the register so it can be used by the register scavenger.
1027 /// Return true if the register was spilled, false otherwise.
1028 /// If this function does not spill the register, the scavenger
1029 /// will instead spill it to the emergency spill slot.
1033 const TargetRegisterClass *RC,
1034 Register Reg) const {
1035 return false;
1036 }
1037
1038 /// Process frame indices in reverse block order. This changes the behavior of
1039 /// the RegScavenger passed to eliminateFrameIndex. If this is true targets
1040 /// should scavengeRegisterBackwards in eliminateFrameIndex. New targets
1041 /// should prefer reverse scavenging behavior.
1042 virtual bool supportsBackwardScavenger() const { return false; }
1043
1044 /// This method must be overriden to eliminate abstract frame indices from
1045 /// instructions which may use them. The instruction referenced by the
1046 /// iterator contains an MO_FrameIndex operand which must be eliminated by
1047 /// this method. This method may modify or replace the specified instruction,
1048 /// as long as it keeps the iterator pointing at the finished product.
1049 /// SPAdj is the SP adjustment due to call frame setup instruction.
1050 /// FIOperandNum is the FI operand number.
1051 /// Returns true if the current instruction was removed and the iterator
1052 /// is not longer valid
1054 int SPAdj, unsigned FIOperandNum,
1055 RegScavenger *RS = nullptr) const = 0;
1056
1057 /// Return the assembly name for \p Reg.
1059 // FIXME: We are assuming that the assembly name is equal to the TableGen
1060 // name converted to lower case
1061 //
1062 // The TableGen name is the name of the definition for this register in the
1063 // target's tablegen files. For example, the TableGen name of
1064 // def EAX : Register <...>; is "EAX"
1065 return StringRef(getName(Reg));
1066 }
1067
1068 //===--------------------------------------------------------------------===//
1069 /// Subtarget Hooks
1070
1071 /// SrcRC and DstRC will be morphed into NewRC if this returns true.
1073 const TargetRegisterClass *SrcRC,
1074 unsigned SubReg,
1075 const TargetRegisterClass *DstRC,
1076 unsigned DstSubReg,
1077 const TargetRegisterClass *NewRC,
1078 LiveIntervals &LIS) const
1079 { return true; }
1080
1081 /// Region split has a high compile time cost especially for large live range.
1082 /// This method is used to decide whether or not \p VirtReg should
1083 /// go through this expensive splitting heuristic.
1084 virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF,
1085 const LiveInterval &VirtReg) const;
1086
1087 /// Last chance recoloring has a high compile time cost especially for
1088 /// targets with a lot of registers.
1089 /// This method is used to decide whether or not \p VirtReg should
1090 /// go through this expensive heuristic.
1091 /// When this target hook is hit, by returning false, there is a high
1092 /// chance that the register allocation will fail altogether (usually with
1093 /// "ran out of registers").
1094 /// That said, this error usually points to another problem in the
1095 /// optimization pipeline.
1096 virtual bool
1098 const LiveInterval &VirtReg) const {
1099 return true;
1100 }
1101
1102 /// Deferred spilling delays the spill insertion of a virtual register
1103 /// after every other allocation. By deferring the spilling, it is
1104 /// sometimes possible to eliminate that spilling altogether because
1105 /// something else could have been eliminated, thus leaving some space
1106 /// for the virtual register.
1107 /// However, this comes with a compile time impact because it adds one
1108 /// more stage to the greedy register allocator.
1109 /// This method is used to decide whether \p VirtReg should use the deferred
1110 /// spilling stage instead of being spilled right away.
1111 virtual bool
1113 const LiveInterval &VirtReg) const {
1114 return false;
1115 }
1116
1117 /// When prioritizing live ranges in register allocation, if this hook returns
1118 /// true then the AllocationPriority of the register class will be treated as
1119 /// more important than whether the range is local to a basic block or global.
1120 virtual bool
1122 return false;
1123 }
1124
1125 //===--------------------------------------------------------------------===//
1126 /// Debug information queries.
1127
1128 /// getFrameRegister - This method should return the register used as a base
1129 /// for values allocated in the current stack frame.
1130 virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
1131
1132 /// Mark a register and all its aliases as reserved in the given set.
1133 void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const;
1134
1135 /// Returns true if for every register in the set all super registers are part
1136 /// of the set as well.
1137 bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
1138 ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1139
1140 virtual const TargetRegisterClass *
1142 const MachineRegisterInfo &MRI) const {
1143 return nullptr;
1144 }
1145
1146 /// Returns the physical register number of sub-register "Index"
1147 /// for physical register RegNo. Return zero if the sub-register does not
1148 /// exist.
1149 inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
1150 return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx);
1151 }
1152
1153 /// Some targets have non-allocatable registers that aren't technically part
1154 /// of the explicit callee saved register list, but should be handled as such
1155 /// in certain cases.
1157 return false;
1158 }
1159};
1160
1161//===----------------------------------------------------------------------===//
1162// SuperRegClassIterator
1163//===----------------------------------------------------------------------===//
1164//
1165// Iterate over the possible super-registers for a given register class. The
1166// iterator will visit a list of pairs (Idx, Mask) corresponding to the
1167// possible classes of super-registers.
1168//
1169// Each bit mask will have at least one set bit, and each set bit in Mask
1170// corresponds to a SuperRC such that:
1171//
1172// For all Reg in SuperRC: Reg:Idx is in RC.
1173//
1174// The iterator can include (O, RC->getSubClassMask()) as the first entry which
1175// also satisfies the above requirement, assuming Reg:0 == Reg.
1176//
1178 const unsigned RCMaskWords;
1179 unsigned SubReg = 0;
1180 const uint16_t *Idx;
1181 const uint32_t *Mask;
1182
1183public:
1184 /// Create a SuperRegClassIterator that visits all the super-register classes
1185 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1187 const TargetRegisterInfo *TRI,
1188 bool IncludeSelf = false)
1189 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1190 Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1191 if (!IncludeSelf)
1192 ++*this;
1193 }
1194
1195 /// Returns true if this iterator is still pointing at a valid entry.
1196 bool isValid() const { return Idx; }
1197
1198 /// Returns the current sub-register index.
1199 unsigned getSubReg() const { return SubReg; }
1200
1201 /// Returns the bit mask of register classes that getSubReg() projects into
1202 /// RC.
1203 /// See TargetRegisterClass::getSubClassMask() for how to use it.
1204 const uint32_t *getMask() const { return Mask; }
1205
1206 /// Advance iterator to the next entry.
1207 void operator++() {
1208 assert(isValid() && "Cannot move iterator past end.");
1209 Mask += RCMaskWords;
1210 SubReg = *Idx++;
1211 if (!SubReg)
1212 Idx = nullptr;
1213 }
1214};
1215
1216//===----------------------------------------------------------------------===//
1217// BitMaskClassIterator
1218//===----------------------------------------------------------------------===//
1219/// This class encapuslates the logic to iterate over bitmask returned by
1220/// the various RegClass related APIs.
1221/// E.g., this class can be used to iterate over the subclasses provided by
1222/// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1224 /// Total number of register classes.
1225 const unsigned NumRegClasses;
1226 /// Base index of CurrentChunk.
1227 /// In other words, the number of bit we read to get at the
1228 /// beginning of that chunck.
1229 unsigned Base = 0;
1230 /// Adjust base index of CurrentChunk.
1231 /// Base index + how many bit we read within CurrentChunk.
1232 unsigned Idx = 0;
1233 /// Current register class ID.
1234 unsigned ID = 0;
1235 /// Mask we are iterating over.
1236 const uint32_t *Mask;
1237 /// Current chunk of the Mask we are traversing.
1238 uint32_t CurrentChunk;
1239
1240 /// Move ID to the next set bit.
1241 void moveToNextID() {
1242 // If the current chunk of memory is empty, move to the next one,
1243 // while making sure we do not go pass the number of register
1244 // classes.
1245 while (!CurrentChunk) {
1246 // Move to the next chunk.
1247 Base += 32;
1248 if (Base >= NumRegClasses) {
1249 ID = NumRegClasses;
1250 return;
1251 }
1252 CurrentChunk = *++Mask;
1253 Idx = Base;
1254 }
1255 // Otherwise look for the first bit set from the right
1256 // (representation of the class ID is big endian).
1257 // See getSubClassMask for more details on the representation.
1258 unsigned Offset = llvm::countr_zero(CurrentChunk);
1259 // Add the Offset to the adjusted base number of this chunk: Idx.
1260 // This is the ID of the register class.
1261 ID = Idx + Offset;
1262
1263 // Consume the zeros, if any, and the bit we just read
1264 // so that we are at the right spot for the next call.
1265 // Do not do Offset + 1 because Offset may be 31 and 32
1266 // will be UB for the shift, though in that case we could
1267 // have make the chunk being equal to 0, but that would
1268 // have introduced a if statement.
1269 moveNBits(Offset);
1270 moveNBits(1);
1271 }
1272
1273 /// Move \p NumBits Bits forward in CurrentChunk.
1274 void moveNBits(unsigned NumBits) {
1275 assert(NumBits < 32 && "Undefined behavior spotted!");
1276 // Consume the bit we read for the next call.
1277 CurrentChunk >>= NumBits;
1278 // Adjust the base for the chunk.
1279 Idx += NumBits;
1280 }
1281
1282public:
1283 /// Create a BitMaskClassIterator that visits all the register classes
1284 /// represented by \p Mask.
1285 ///
1286 /// \pre \p Mask != nullptr
1288 : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1289 // Move to the first ID.
1290 moveToNextID();
1291 }
1292
1293 /// Returns true if this iterator is still pointing at a valid entry.
1294 bool isValid() const { return getID() != NumRegClasses; }
1295
1296 /// Returns the current register class ID.
1297 unsigned getID() const { return ID; }
1298
1299 /// Advance iterator to the next entry.
1300 void operator++() {
1301 assert(isValid() && "Cannot move iterator past end.");
1302 moveToNextID();
1303 }
1304};
1305
1306// This is useful when building IndexedMaps keyed on virtual registers
1309 unsigned operator()(Register Reg) const {
1311 }
1312};
1313
1314/// Prints virtual and physical registers with or without a TRI instance.
1315///
1316/// The format is:
1317/// %noreg - NoRegister
1318/// %5 - a virtual register.
1319/// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1320/// %eax - a physical register
1321/// %physreg17 - a physical register when no TRI instance given.
1322///
1323/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1324Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
1325 unsigned SubIdx = 0,
1326 const MachineRegisterInfo *MRI = nullptr);
1327
1328/// Create Printable object to print register units on a \ref raw_ostream.
1329///
1330/// Register units are named after their root registers:
1331///
1332/// al - Single root.
1333/// fp0~st7 - Dual roots.
1334///
1335/// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1336Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1337
1338/// Create Printable object to print virtual registers and physical
1339/// registers on a \ref raw_ostream.
1340Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1341
1342/// Create Printable object to print register classes or register banks
1343/// on a \ref raw_ostream.
1344Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
1345 const TargetRegisterInfo *TRI);
1346
1347} // end namespace llvm
1348
1349#endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineBasicBlock & MBB
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
A common definition of LaneBitmask for use in TableGen and CodeGen.
Live Register Matrix
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
void operator++()
Advance iterator to the next entry.
unsigned getID() const
Returns the current register class ID.
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
DWARF expression.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getID() const
getID() - Return the register class ID number.
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
iterator begin() const
begin/end - Return all of the registers in this class.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
iterator end() const
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
const char * getRegClassName(const MCRegisterClass *Class) const
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
Definition: Register.h:120
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:36
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
void operator++()
Advance iterator to the next entry.
unsigned getSubReg() const
Returns the current sub-register index.
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
const TargetRegisterClass *const * sc_iterator
unsigned getNumRegs() const
Return the number of registers in this class.
const uint8_t TSFlags
Configurable target specific flags.
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
unsigned getID() const
Return the register class ID number.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
const sc_iterator SuperClasses
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &)
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
const uint16_t * SuperRegIndices
const MCRegisterClass * MC
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
bool contains(Register Reg1, Register Reg2) const
Return true if both registers are in this class.
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
iterator begin() const
begin/end - Return all of the registers in this class.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
const TargetRegisterClass *const * regclass_iterator
virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index.
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const
Return true if the given TargetRegisterClass is compatible with LLT T.
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
virtual bool shouldUseDeferredSpillingForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Deferred spilling delays the spill insertion of a virtual register after every other allocation.
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
iterator_range< regclass_iterator > regclasses() const
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
virtual const TargetRegisterClass * getPhysRegBaseClass(MCRegister Reg) const
Return target defined base register class for a physical register.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const
Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint,...
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
virtual bool supportsBackwardScavenger() const
Process frame indices in reverse block order.
virtual bool shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Last chance recoloring has a high compile time cost especially for targets with a lot of registers.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time.
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) const
Returns true if PhysReg cannot be written to in inline asm statements.
virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
virtual std::optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const
Returns either a string explaining why the given register is reserved for this function,...
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
virtual bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a general purpose register.
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
regclass_iterator regclass_begin() const
Register class iterators.
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
unsigned getNumRegClasses() const
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
virtual ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const
Return a list of all of the registers which are clobbered "inside" a call to the given function.
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const
Some targets have non-allocatable registers that aren't technically part of the explicit callee saved...
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
const RegClassInfo & getRegClassInfo(const TargetRegisterClass &RC) const
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
virtual bool isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg can be used as an argument to a function.
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
virtual const TargetRegisterClass * getSubRegisterClass(const TargetRegisterClass *SuperRC, unsigned SubRegIdx) const
Return a register class that can be used for a subregister copy from/into SuperRC at SubRegIdx.
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
virtual bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
regclass_iterator regclass_end() const
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for a pointer to FrameIdx before insertion point I.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
virtual ArrayRef< const char * > getRegMaskNames() const =0
virtual bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a fixed register.
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
virtual StringRef getRegAsmName(MCRegister Reg) const
Return the assembly name for Reg.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const
Return the register cost table index.
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction's frame index reference would be better served by a base register oth...
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
virtual bool regClassPriorityTrumpsGlobalness(const MachineFunction &MF) const
When prioritizing live ranges in register allocation, if this hook returns true then the AllocationPr...
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
virtual void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: bit.h:179
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
Extra information, not in MCRegisterDesc, about registers.
unsigned operator()(Register Reg) const