LLVM 19.0.0git
TargetRegisterInfo.h
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1//==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes an abstract interface used to get information about a
10// target machines register file. This information is used for a variety of
11// purposed, especially register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16#define LLVM_CODEGEN_TARGETREGISTERINFO_H
17
18#include "llvm/ADT/ArrayRef.h"
20#include "llvm/ADT/StringRef.h"
24#include "llvm/IR/CallingConv.h"
25#include "llvm/MC/LaneBitmask.h"
30#include <cassert>
31#include <cstdint>
32
33namespace llvm {
34
35class BitVector;
36class DIExpression;
37class LiveRegMatrix;
38class MachineFunction;
39class MachineInstr;
40class RegScavenger;
41class VirtRegMap;
42class LiveIntervals;
43class LiveInterval;
44
46public:
47 using iterator = const MCPhysReg *;
48 using const_iterator = const MCPhysReg *;
49 using sc_iterator = const TargetRegisterClass* const *;
50
51 // Instance variables filled by tablegen, do not use!
56 /// Classes with a higher priority value are assigned first by register
57 /// allocators using a greedy heuristic. The value is in the range [0,31].
58 const uint8_t AllocationPriority;
59
60 // Change allocation priority heuristic used by greedy.
61 const bool GlobalPriority;
62
63 /// Configurable target specific flags.
64 const uint8_t TSFlags;
65 /// Whether the class supports two (or more) disjunct subregister indices.
67 /// Whether a combination of subregisters can cover every register in the
68 /// class. See also the CoveredBySubRegs description in Target.td.
69 const bool CoveredBySubRegs;
72
73 /// Return the register class ID number.
74 unsigned getID() const { return MC->getID(); }
75
76 /// begin/end - Return all of the registers in this class.
77 ///
78 iterator begin() const { return MC->begin(); }
79 iterator end() const { return MC->end(); }
80
81 /// Return the number of registers in this class.
82 unsigned getNumRegs() const { return MC->getNumRegs(); }
83
85 return ArrayRef(begin(), getNumRegs());
86 }
87
88 /// Return the specified register in the class.
89 MCRegister getRegister(unsigned i) const {
90 return MC->getRegister(i);
91 }
92
93 /// Return true if the specified register is included in this register class.
94 /// This does not include virtual registers.
95 bool contains(Register Reg) const {
96 /// FIXME: Historically this function has returned false when given vregs
97 /// but it should probably only receive physical registers
98 if (!Reg.isPhysical())
99 return false;
100 return MC->contains(Reg.asMCReg());
101 }
102
103 /// Return true if both registers are in this class.
104 bool contains(Register Reg1, Register Reg2) const {
105 /// FIXME: Historically this function has returned false when given a vregs
106 /// but it should probably only receive physical registers
107 if (!Reg1.isPhysical() || !Reg2.isPhysical())
108 return false;
109 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg());
110 }
111
112 /// Return the cost of copying a value between two registers in this class.
113 /// A negative number means the register class is very expensive
114 /// to copy e.g. status flag register classes.
115 int getCopyCost() const { return MC->getCopyCost(); }
116
117 /// Return true if this register class may be used to create virtual
118 /// registers.
119 bool isAllocatable() const { return MC->isAllocatable(); }
120
121 /// Return true if this register class has a defined BaseClassOrder.
122 bool isBaseClass() const { return MC->isBaseClass(); }
123
124 /// Return true if the specified TargetRegisterClass
125 /// is a proper sub-class of this TargetRegisterClass.
126 bool hasSubClass(const TargetRegisterClass *RC) const {
127 return RC != this && hasSubClassEq(RC);
128 }
129
130 /// Returns true if RC is a sub-class of or equal to this class.
131 bool hasSubClassEq(const TargetRegisterClass *RC) const {
132 unsigned ID = RC->getID();
133 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
134 }
135
136 /// Return true if the specified TargetRegisterClass is a
137 /// proper super-class of this TargetRegisterClass.
138 bool hasSuperClass(const TargetRegisterClass *RC) const {
139 return RC->hasSubClass(this);
140 }
141
142 /// Returns true if RC is a super-class of or equal to this class.
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
144 return RC->hasSubClassEq(this);
145 }
146
147 /// Returns a bit vector of subclasses, including this one.
148 /// The vector is indexed by class IDs.
149 ///
150 /// To use it, consider the returned array as a chunk of memory that
151 /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
152 /// contains a bitset of the ID of the subclasses in big-endian style.
153
154 /// I.e., the representation of the memory from left to right at the
155 /// bit level looks like:
156 /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
157 /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
158 /// Where the number represents the class ID and XXX bits that
159 /// should be ignored.
160 ///
161 /// See the implementation of hasSubClassEq for an example of how it
162 /// can be used.
163 const uint32_t *getSubClassMask() const {
164 return SubClassMask;
165 }
166
167 /// Returns a 0-terminated list of sub-register indices that project some
168 /// super-register class into this register class. The list has an entry for
169 /// each Idx such that:
170 ///
171 /// There exists SuperRC where:
172 /// For all Reg in SuperRC:
173 /// this->contains(Reg:Idx)
175 return SuperRegIndices;
176 }
177
178 /// Returns a NULL-terminated list of super-classes. The
179 /// classes are ordered by ID which is also a topological ordering from large
180 /// to small classes. The list does NOT include the current class.
182 return SuperClasses;
183 }
184
185 /// Return true if this TargetRegisterClass is a subset
186 /// class of at least one other TargetRegisterClass.
187 bool isASubClass() const {
188 return SuperClasses[0] != nullptr;
189 }
190
191 /// Returns the preferred order for allocating registers from this register
192 /// class in MF. The raw order comes directly from the .td file and may
193 /// include reserved registers that are not allocatable.
194 /// Register allocators should also make sure to allocate
195 /// callee-saved registers only after all the volatiles are used. The
196 /// RegisterClassInfo class provides filtered allocation orders with
197 /// callee-saved registers moved to the end.
198 ///
199 /// The MachineFunction argument can be used to tune the allocatable
200 /// registers based on the characteristics of the function, subtarget, or
201 /// other criteria.
202 ///
203 /// By default, this method returns all registers in the class.
205 return OrderFunc ? OrderFunc(MF) : getRegisters();
206 }
207
208 /// Returns the combination of all lane masks of register in this class.
209 /// The lane masks of the registers are the combination of all lane masks
210 /// of their subregisters. Returns 1 if there are no subregisters.
212 return LaneMask;
213 }
214};
215
216/// Extra information, not in MCRegisterDesc, about registers.
217/// These are used by codegen, not by MC.
219 const uint8_t *CostPerUse; // Extra cost of instructions using register.
220 unsigned NumCosts; // Number of cost values associated with each register.
221 const bool
222 *InAllocatableClass; // Register belongs to an allocatable regclass.
223};
224
225/// Each TargetRegisterClass has a per register weight, and weight
226/// limit which must be less than the limits of its pressure sets.
228 unsigned RegWeight;
229 unsigned WeightLimit;
230};
231
232/// TargetRegisterInfo base class - We assume that the target defines a static
233/// array of TargetRegisterDesc objects that represent all of the machine
234/// registers that the target has. As such, we simply have to track a pointer
235/// to this array so that we can turn register number into a register
236/// descriptor.
237///
239public:
240 using regclass_iterator = const TargetRegisterClass * const *;
244 unsigned VTListOffset;
245 };
246private:
247 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
248 const char *const *SubRegIndexNames; // Names of subreg indexes.
249 // Pointer to array of lane masks, one per sub-reg index.
250 const LaneBitmask *SubRegIndexLaneMasks;
251
252 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
253 LaneBitmask CoveringLanes;
254 const RegClassInfo *const RCInfos;
255 const MVT::SimpleValueType *const RCVTLists;
256 unsigned HwMode;
257
258protected:
262 const char *const *SRINames,
263 const LaneBitmask *SRILaneMasks,
264 LaneBitmask CoveringLanes,
265 const RegClassInfo *const RCIs,
266 const MVT::SimpleValueType *const RCVTLists,
267 unsigned Mode = 0);
269
270public:
271 /// Return the number of registers for the function. (may overestimate)
272 virtual unsigned getNumSupportedRegs(const MachineFunction &) const {
273 return getNumRegs();
274 }
275
276 // Register numbers can represent physical registers, virtual registers, and
277 // sometimes stack slots. The unsigned values are divided into these ranges:
278 //
279 // 0 Not a register, can be used as a sentinel.
280 // [1;2^30) Physical registers assigned by TableGen.
281 // [2^30;2^31) Stack slots. (Rarely used.)
282 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
283 //
284 // Further sentinels can be allocated from the small negative integers.
285 // DenseMapInfo<unsigned> uses -1u and -2u.
286
287 /// Return the size in bits of a register from class RC.
290 }
291
292 /// Return the size in bytes of the stack slot allocated to hold a spilled
293 /// copy of a register from class RC.
294 unsigned getSpillSize(const TargetRegisterClass &RC) const {
295 return getRegClassInfo(RC).SpillSize / 8;
296 }
297
298 /// Return the minimum required alignment in bytes for a spill slot for
299 /// a register of this class.
301 return Align(getRegClassInfo(RC).SpillAlignment / 8);
302 }
303
304 /// Return true if the given TargetRegisterClass has the ValueType T.
306 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
307 if (MVT(*I) == T)
308 return true;
309 return false;
310 }
311
312 /// Return true if the given TargetRegisterClass is compatible with LLT T.
314 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) {
315 MVT VT(*I);
316 if (VT == MVT::Untyped)
317 return true;
318
319 if (LLT(VT) == T)
320 return true;
321 }
322 return false;
323 }
324
325 /// Loop over all of the value types that can be represented by values
326 /// in the given register class.
328 return &RCVTLists[getRegClassInfo(RC).VTListOffset];
329 }
330
333 while (*I != MVT::Other)
334 ++I;
335 return I;
336 }
337
338 /// Returns the Register Class of a physical register of the given type,
339 /// picking the most sub register class of the right type that contains this
340 /// physreg.
342 MVT VT = MVT::Other) const;
343
344 /// Returns the Register Class of a physical register of the given type,
345 /// picking the most sub register class of the right type that contains this
346 /// physreg. If there is no register class compatible with the given type,
347 /// returns nullptr.
349 LLT Ty = LLT()) const;
350
351 /// Return the maximal subclass of the given register class that is
352 /// allocatable or NULL.
353 const TargetRegisterClass *
355
356 /// Returns a bitset indexed by register number indicating if a register is
357 /// allocatable or not. If a register class is specified, returns the subset
358 /// for the class.
360 const TargetRegisterClass *RC = nullptr) const;
361
362 /// Get a list of cost values for all registers that correspond to the index
363 /// returned by RegisterCostTableIndex.
365 unsigned Idx = getRegisterCostTableIndex(MF);
366 unsigned NumRegs = getNumRegs();
367 assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds");
368
369 return ArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
370 }
371
372 /// Return true if the register is in the allocation of any register class.
374 return InfoDesc->InAllocatableClass[RegNo];
375 }
376
377 /// Return the human-readable symbolic target-specific
378 /// name for the specified SubRegIndex.
379 const char *getSubRegIndexName(unsigned SubIdx) const {
380 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
381 "This is not a subregister index");
382 return SubRegIndexNames[SubIdx-1];
383 }
384
385 /// Return a bitmask representing the parts of a register that are covered by
386 /// SubIdx \see LaneBitmask.
387 ///
388 /// SubIdx == 0 is allowed, it has the lane mask ~0u.
389 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
390 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
391 return SubRegIndexLaneMasks[SubIdx];
392 }
393
394 /// Try to find one or more subregister indexes to cover \p LaneMask.
395 ///
396 /// If this is possible, returns true and appends the best matching set of
397 /// indexes to \p Indexes. If this is not possible, returns false.
399 const TargetRegisterClass *RC,
400 LaneBitmask LaneMask,
401 SmallVectorImpl<unsigned> &Indexes) const;
402
403 /// The lane masks returned by getSubRegIndexLaneMask() above can only be
404 /// used to determine if sub-registers overlap - they can't be used to
405 /// determine if a set of sub-registers completely cover another
406 /// sub-register.
407 ///
408 /// The X86 general purpose registers have two lanes corresponding to the
409 /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
410 /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
411 /// sub_32bit sub-register.
412 ///
413 /// On the other hand, the ARM NEON lanes fully cover their registers: The
414 /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
415 /// This is related to the CoveredBySubRegs property on register definitions.
416 ///
417 /// This function returns a bit mask of lanes that completely cover their
418 /// sub-registers. More precisely, given:
419 ///
420 /// Covering = getCoveringLanes();
421 /// MaskA = getSubRegIndexLaneMask(SubA);
422 /// MaskB = getSubRegIndexLaneMask(SubB);
423 ///
424 /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
425 /// SubB.
426 LaneBitmask getCoveringLanes() const { return CoveringLanes; }
427
428 /// Returns true if the two registers are equal or alias each other.
429 /// The registers may be virtual registers.
430 bool regsOverlap(Register RegA, Register RegB) const {
431 if (RegA == RegB)
432 return true;
433 if (RegA.isPhysical() && RegB.isPhysical())
434 return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg());
435 return false;
436 }
437
438 /// Returns true if Reg contains RegUnit.
439 bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
440 for (MCRegUnit Unit : regunits(Reg))
441 if (Register(Unit) == RegUnit)
442 return true;
443 return false;
444 }
445
446 /// Returns the original SrcReg unless it is the target of a copy-like
447 /// operation, in which case we chain backwards through all such operations
448 /// to the ultimate source register. If a physical register is encountered,
449 /// we stop the search.
450 virtual Register lookThruCopyLike(Register SrcReg,
451 const MachineRegisterInfo *MRI) const;
452
453 /// Find the original SrcReg unless it is the target of a copy-like operation,
454 /// in which case we chain backwards through all such operations to the
455 /// ultimate source register. If a physical register is encountered, we stop
456 /// the search.
457 /// Return the original SrcReg if all the definitions in the chain only have
458 /// one user and not a physical register.
459 virtual Register
461 const MachineRegisterInfo *MRI) const;
462
463 /// Return a null-terminated list of all of the callee-saved registers on
464 /// this target. The register should be in the order of desired callee-save
465 /// stack frame offset. The first register is closest to the incoming stack
466 /// pointer if stack grows down, and vice versa.
467 /// Notice: This function does not take into account disabled CSRs.
468 /// In most cases you will want to use instead the function
469 /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
470 virtual const MCPhysReg*
472
473 /// Return a mask of call-preserved registers for the given calling convention
474 /// on the current function. The mask should include all call-preserved
475 /// aliases. This is used by the register allocator to determine which
476 /// registers can be live across a call.
477 ///
478 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
479 /// A set bit indicates that all bits of the corresponding register are
480 /// preserved across the function call. The bit mask is expected to be
481 /// sub-register complete, i.e. if A is preserved, so are all its
482 /// sub-registers.
483 ///
484 /// Bits are numbered from the LSB, so the bit for physical register Reg can
485 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
486 ///
487 /// A NULL pointer means that no register mask will be used, and call
488 /// instructions should use implicit-def operands to indicate call clobbered
489 /// registers.
490 ///
492 CallingConv::ID) const {
493 // The default mask clobbers everything. All targets should override.
494 return nullptr;
495 }
496
497 /// Return a register mask for the registers preserved by the unwinder,
498 /// or nullptr if no custom mask is needed.
499 virtual const uint32_t *
501 return nullptr;
502 }
503
504 /// Return a register mask that clobbers everything.
505 virtual const uint32_t *getNoPreservedMask() const {
506 llvm_unreachable("target does not provide no preserved mask");
507 }
508
509 /// Return a list of all of the registers which are clobbered "inside" a call
510 /// to the given function. For example, these might be needed for PLT
511 /// sequences of long-branch veneers.
512 virtual ArrayRef<MCPhysReg>
514 return {};
515 }
516
517 /// Return true if all bits that are set in mask \p mask0 are also set in
518 /// \p mask1.
519 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
520
521 /// Return all the call-preserved register masks defined for this target.
524
525 /// Returns a bitset indexed by physical register number indicating if a
526 /// register is a special register that has particular uses and should be
527 /// considered unavailable at all times, e.g. stack pointer, return address.
528 /// A reserved register:
529 /// - is not allocatable
530 /// - is considered always live
531 /// - is ignored by liveness tracking
532 /// It is often necessary to reserve the super registers of a reserved
533 /// register as well, to avoid them getting allocated indirectly. You may use
534 /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
535 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
536
537 /// Returns either a string explaining why the given register is reserved for
538 /// this function, or an empty optional if no explanation has been written.
539 /// The absence of an explanation does not mean that the register is not
540 /// reserved (meaning, you should check that PhysReg is in fact reserved
541 /// before calling this).
542 virtual std::optional<std::string>
544 return {};
545 }
546
547 /// Returns false if we can't guarantee that Physreg, specified as an IR asm
548 /// clobber constraint, will be preserved across the statement.
549 virtual bool isAsmClobberable(const MachineFunction &MF,
550 MCRegister PhysReg) const {
551 return true;
552 }
553
554 /// Returns true if PhysReg cannot be written to in inline asm statements.
556 unsigned PhysReg) const {
557 return false;
558 }
559
560 /// Returns true if PhysReg is unallocatable and constant throughout the
561 /// function. Used by MachineRegisterInfo::isConstantPhysReg().
562 virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }
563
564 /// Returns true if the register class is considered divergent.
565 virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
566 return false;
567 }
568
569 /// Returns true if the register is considered uniform.
571 const RegisterBankInfo &RBI, Register Reg) const {
572 return false;
573 }
574
575 /// Physical registers that may be modified within a function but are
576 /// guaranteed to be restored before any uses. This is useful for targets that
577 /// have call sequences where a GOT register may be updated by the caller
578 /// prior to a call and is guaranteed to be restored (also by the caller)
579 /// after the call.
581 const MachineFunction &MF) const {
582 return false;
583 }
584
585 /// This is a wrapper around getCallPreservedMask().
586 /// Return true if the register is preserved after the call.
587 virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
588 const MachineFunction &MF) const;
589
590 /// Returns true if PhysReg can be used as an argument to a function.
591 virtual bool isArgumentRegister(const MachineFunction &MF,
592 MCRegister PhysReg) const {
593 return false;
594 }
595
596 /// Returns true if PhysReg is a fixed register.
597 virtual bool isFixedRegister(const MachineFunction &MF,
598 MCRegister PhysReg) const {
599 return false;
600 }
601
602 /// Returns true if PhysReg is a general purpose register.
604 MCRegister PhysReg) const {
605 return false;
606 }
607
608 /// Prior to adding the live-out mask to a stackmap or patchpoint
609 /// instruction, provide the target the opportunity to adjust it (mainly to
610 /// remove pseudo-registers that should be ignored).
611 virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
612
613 /// Return a super-register of the specified register
614 /// Reg so its sub-register of index SubIdx is Reg.
616 const TargetRegisterClass *RC) const {
617 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
618 }
619
620 /// Return a subclass of the specified register
621 /// class A so that each register in it has a sub-register of the
622 /// specified sub-register index which is in the specified register class B.
623 ///
624 /// TableGen will synthesize missing A sub-classes.
625 virtual const TargetRegisterClass *
627 const TargetRegisterClass *B, unsigned Idx) const;
628
629 // For a copy-like instruction that defines a register of class DefRC with
630 // subreg index DefSubReg, reading from another source with class SrcRC and
631 // subregister SrcSubReg return true if this is a preferable copy
632 // instruction or an earlier use should be used.
633 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
634 unsigned DefSubReg,
635 const TargetRegisterClass *SrcRC,
636 unsigned SrcSubReg) const;
637
638 /// Returns the largest legal sub-class of RC that
639 /// supports the sub-register index Idx.
640 /// If no such sub-class exists, return NULL.
641 /// If all registers in RC already have an Idx sub-register, return RC.
642 ///
643 /// TableGen generates a version of this function that is good enough in most
644 /// cases. Targets can override if they have constraints that TableGen
645 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
646 /// supported by the full GR32 register class in 64-bit mode, but only by the
647 /// GR32_ABCD regiister class in 32-bit mode.
648 ///
649 /// TableGen will synthesize missing RC sub-classes.
650 virtual const TargetRegisterClass *
651 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
652 assert(Idx == 0 && "Target has no sub-registers");
653 return RC;
654 }
655
656 /// Return a register class that can be used for a subregister copy from/into
657 /// \p SuperRC at \p SubRegIdx.
658 virtual const TargetRegisterClass *
660 unsigned SubRegIdx) const {
661 return nullptr;
662 }
663
664 /// Return the subregister index you get from composing
665 /// two subregister indices.
666 ///
667 /// The special null sub-register index composes as the identity.
668 ///
669 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
670 /// returns c. Note that composeSubRegIndices does not tell you about illegal
671 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
672 /// b, composeSubRegIndices doesn't tell you.
673 ///
674 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
675 /// ssub_0:S0 - ssub_3:S3 subregs.
676 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
677 unsigned composeSubRegIndices(unsigned a, unsigned b) const {
678 if (!a) return b;
679 if (!b) return a;
680 return composeSubRegIndicesImpl(a, b);
681 }
682
683 /// Transforms a LaneMask computed for one subregister to the lanemask that
684 /// would have been computed when composing the subsubregisters with IdxA
685 /// first. @sa composeSubRegIndices()
687 LaneBitmask Mask) const {
688 if (!IdxA)
689 return Mask;
690 return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
691 }
692
693 /// Transform a lanemask given for a virtual register to the corresponding
694 /// lanemask before using subregister with index \p IdxA.
695 /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
696 /// valie lane mask (no invalid bits set) the following holds:
697 /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
698 /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
699 /// => X1 == Mask
701 LaneBitmask LaneMask) const {
702 if (!IdxA)
703 return LaneMask;
704 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
705 }
706
707 /// Debugging helper: dump register in human readable form to dbgs() stream.
708 static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
709 const TargetRegisterInfo *TRI = nullptr);
710
711 /// Return target defined base register class for a physical register.
712 /// This is the register class with the lowest BaseClassOrder containing the
713 /// register.
714 /// Will be nullptr if the register is not in any base register class.
716 return nullptr;
717 }
718
719protected:
720 /// Overridden by TableGen in targets that have sub-registers.
721 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
722 llvm_unreachable("Target has no sub-registers");
723 }
724
725 /// Overridden by TableGen in targets that have sub-registers.
726 virtual LaneBitmask
728 llvm_unreachable("Target has no sub-registers");
729 }
730
732 LaneBitmask) const {
733 llvm_unreachable("Target has no sub-registers");
734 }
735
736 /// Return the register cost table index. This implementation is sufficient
737 /// for most architectures and can be overriden by targets in case there are
738 /// multiple cost values associated with each register.
739 virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const {
740 return 0;
741 }
742
743public:
744 /// Find a common super-register class if it exists.
745 ///
746 /// Find a register class, SuperRC and two sub-register indices, PreA and
747 /// PreB, such that:
748 ///
749 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
750 ///
751 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
752 ///
753 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
754 ///
755 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
756 /// requirements, and there is no register class with a smaller spill size
757 /// that satisfies the requirements.
758 ///
759 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
760 ///
761 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
762 /// that case, the returned register class will be a sub-class of the
763 /// corresponding argument register class.
764 ///
765 /// The function returns NULL if no register class can be found.
767 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
768 const TargetRegisterClass *RCB, unsigned SubB,
769 unsigned &PreA, unsigned &PreB) const;
770
771 //===--------------------------------------------------------------------===//
772 // Register Class Information
773 //
774protected:
776 return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
777 }
778
779public:
780 /// Register class iterators
781 regclass_iterator regclass_begin() const { return RegClassBegin; }
782 regclass_iterator regclass_end() const { return RegClassEnd; }
785 }
786
787 unsigned getNumRegClasses() const {
788 return (unsigned)(regclass_end()-regclass_begin());
789 }
790
791 /// Returns the register class associated with the enumeration value.
792 /// See class MCOperandInfo.
793 const TargetRegisterClass *getRegClass(unsigned i) const {
794 assert(i < getNumRegClasses() && "Register Class ID out of range");
795 return RegClassBegin[i];
796 }
797
798 /// Returns the name of the register class.
799 const char *getRegClassName(const TargetRegisterClass *Class) const {
800 return MCRegisterInfo::getRegClassName(Class->MC);
801 }
802
803 /// Find the largest common subclass of A and B.
804 /// Return NULL if there is no common subclass.
805 const TargetRegisterClass *
807 const TargetRegisterClass *B) const;
808
809 /// Returns a TargetRegisterClass used for pointer values.
810 /// If a target supports multiple different pointer register classes,
811 /// kind specifies which one is indicated.
812 virtual const TargetRegisterClass *
813 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
814 llvm_unreachable("Target didn't implement getPointerRegClass!");
815 }
816
817 /// Returns a legal register class to copy a register in the specified class
818 /// to or from. If it is possible to copy the register directly without using
819 /// a cross register class copy, return the specified RC. Returns NULL if it
820 /// is not possible to copy between two registers of the specified class.
821 virtual const TargetRegisterClass *
823 return RC;
824 }
825
826 /// Returns the largest super class of RC that is legal to use in the current
827 /// sub-target and has the same spill size.
828 /// The returned register class can be used to create virtual registers which
829 /// means that all its registers can be copied and spilled.
830 virtual const TargetRegisterClass *
832 const MachineFunction &) const {
833 /// The default implementation is very conservative and doesn't allow the
834 /// register allocator to inflate register classes.
835 return RC;
836 }
837
838 /// Return the register pressure "high water mark" for the specific register
839 /// class. The scheduler is in high register pressure mode (for the specific
840 /// register class) if it goes over the limit.
841 ///
842 /// Note: this is the old register pressure model that relies on a manually
843 /// specified representative register class per value type.
844 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
845 MachineFunction &MF) const {
846 return 0;
847 }
848
849 /// Return a heuristic for the machine scheduler to compare the profitability
850 /// of increasing one register pressure set versus another. The scheduler
851 /// will prefer increasing the register pressure of the set which returns
852 /// the largest value for this function.
853 virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
854 unsigned PSetID) const {
855 return PSetID;
856 }
857
858 /// Get the weight in units of pressure for this register class.
860 const TargetRegisterClass *RC) const = 0;
861
862 /// Returns size in bits of a phys/virtual/generic register.
864
865 /// Get the weight in units of pressure for this register unit.
866 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
867
868 /// Get the number of dimensions of register pressure.
869 virtual unsigned getNumRegPressureSets() const = 0;
870
871 /// Get the name of this register unit pressure set.
872 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
873
874 /// Get the register unit pressure limit for this dimension.
875 /// This limit must be adjusted dynamically for reserved registers.
876 virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
877 unsigned Idx) const = 0;
878
879 /// Get the dimensions of register pressure impacted by this register class.
880 /// Returns a -1 terminated array of pressure set IDs.
881 virtual const int *getRegClassPressureSets(
882 const TargetRegisterClass *RC) const = 0;
883
884 /// Get the dimensions of register pressure impacted by this register unit.
885 /// Returns a -1 terminated array of pressure set IDs.
886 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
887
888 /// Get a list of 'hint' registers that the register allocator should try
889 /// first when allocating a physical register for the virtual register
890 /// VirtReg. These registers are effectively moved to the front of the
891 /// allocation order. If true is returned, regalloc will try to only use
892 /// hints to the greatest extent possible even if it means spilling.
893 ///
894 /// The Order argument is the allocation order for VirtReg's register class
895 /// as returned from RegisterClassInfo::getOrder(). The hint registers must
896 /// come from Order, and they must not be reserved.
897 ///
898 /// The default implementation of this function will only add target
899 /// independent register allocation hints. Targets that override this
900 /// function should typically call this default implementation as well and
901 /// expect to see generic copy hints added.
902 virtual bool
905 const MachineFunction &MF,
906 const VirtRegMap *VRM = nullptr,
907 const LiveRegMatrix *Matrix = nullptr) const;
908
909 /// A callback to allow target a chance to update register allocation hints
910 /// when a register is "changed" (e.g. coalesced) to another register.
911 /// e.g. On ARM, some virtual registers should target register pairs,
912 /// if one of pair is coalesced to another register, the allocation hint of
913 /// the other half of the pair should be changed to point to the new register.
915 MachineFunction &MF) const {
916 // Do nothing.
917 }
918
919 /// Allow the target to reverse allocation order of local live ranges. This
920 /// will generally allocate shorter local live ranges first. For targets with
921 /// many registers, this could reduce regalloc compile time by a large
922 /// factor. It is disabled by default for three reasons:
923 /// (1) Top-down allocation is simpler and easier to debug for targets that
924 /// don't benefit from reversing the order.
925 /// (2) Bottom-up allocation could result in poor evicition decisions on some
926 /// targets affecting the performance of compiled code.
927 /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
928 virtual bool reverseLocalAssignment() const { return false; }
929
930 /// Allow the target to override the cost of using a callee-saved register for
931 /// the first time. Default value of 0 means we will use a callee-saved
932 /// register if it is available.
933 virtual unsigned getCSRFirstUseCost() const { return 0; }
934
935 /// Returns true if the target requires (and can make use of) the register
936 /// scavenger.
937 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
938 return false;
939 }
940
941 /// Returns true if the target wants to use frame pointer based accesses to
942 /// spill to the scavenger emergency spill slot.
943 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
944 return true;
945 }
946
947 /// Returns true if the target requires post PEI scavenging of registers for
948 /// materializing frame index constants.
949 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
950 return false;
951 }
952
953 /// Returns true if the target requires using the RegScavenger directly for
954 /// frame elimination despite using requiresFrameIndexScavenging.
956 const MachineFunction &MF) const {
957 return false;
958 }
959
960 /// Returns true if the target wants the LocalStackAllocation pass to be run
961 /// and virtual base registers used for more efficient stack access.
962 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
963 return false;
964 }
965
966 /// Return true if target has reserved a spill slot in the stack frame of
967 /// the given function for the specified register. e.g. On x86, if the frame
968 /// register is required, the first fixed stack object is reserved as its
969 /// spill slot. This tells PEI not to create a new stack frame
970 /// object for the given register. It should be called only after
971 /// determineCalleeSaves().
973 int &FrameIdx) const {
974 return false;
975 }
976
977 /// Returns true if the live-ins should be tracked after register allocation.
978 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
979 return true;
980 }
981
982 /// True if the stack can be realigned for the target.
983 virtual bool canRealignStack(const MachineFunction &MF) const;
984
985 /// True if storage within the function requires the stack pointer to be
986 /// aligned more than the normal calling convention calls for.
987 virtual bool shouldRealignStack(const MachineFunction &MF) const;
988
989 /// True if stack realignment is required and still possible.
990 bool hasStackRealignment(const MachineFunction &MF) const {
991 return shouldRealignStack(MF) && canRealignStack(MF);
992 }
993
994 /// Get the offset from the referenced frame index in the instruction,
995 /// if there is one.
997 int Idx) const {
998 return 0;
999 }
1000
1001 /// Returns true if the instruction's frame index reference would be better
1002 /// served by a base register other than FP or SP.
1003 /// Used by LocalStackFrameAllocation to determine which frame index
1004 /// references it should create new base registers for.
1005 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1006 return false;
1007 }
1008
1009 /// Insert defining instruction(s) for a pointer to FrameIdx before
1010 /// insertion point I. Return materialized frame pointer.
1012 int FrameIdx,
1013 int64_t Offset) const {
1014 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
1015 "target");
1016 }
1017
1018 /// Resolve a frame index operand of an instruction
1019 /// to reference the indicated base register plus offset instead.
1021 int64_t Offset) const {
1022 llvm_unreachable("resolveFrameIndex does not exist on this target");
1023 }
1024
1025 /// Determine whether a given base register plus offset immediate is
1026 /// encodable to resolve a frame index.
1027 virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
1028 int64_t Offset) const {
1029 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
1030 }
1031
1032 /// Gets the DWARF expression opcodes for \p Offset.
1033 virtual void getOffsetOpcodes(const StackOffset &Offset,
1034 SmallVectorImpl<uint64_t> &Ops) const;
1035
1036 /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
1037 DIExpression *
1038 prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
1039 const StackOffset &Offset) const;
1040
1041 /// Spill the register so it can be used by the register scavenger.
1042 /// Return true if the register was spilled, false otherwise.
1043 /// If this function does not spill the register, the scavenger
1044 /// will instead spill it to the emergency spill slot.
1048 const TargetRegisterClass *RC,
1049 Register Reg) const {
1050 return false;
1051 }
1052
1053 /// Process frame indices in reverse block order. This changes the behavior of
1054 /// the RegScavenger passed to eliminateFrameIndex. If this is true targets
1055 /// should scavengeRegisterBackwards in eliminateFrameIndex. New targets
1056 /// should prefer reverse scavenging behavior.
1057 /// TODO: Remove this when all targets return true.
1058 virtual bool eliminateFrameIndicesBackwards() const { return true; }
1059
1060 /// This method must be overriden to eliminate abstract frame indices from
1061 /// instructions which may use them. The instruction referenced by the
1062 /// iterator contains an MO_FrameIndex operand which must be eliminated by
1063 /// this method. This method may modify or replace the specified instruction,
1064 /// as long as it keeps the iterator pointing at the finished product.
1065 /// SPAdj is the SP adjustment due to call frame setup instruction.
1066 /// FIOperandNum is the FI operand number.
1067 /// Returns true if the current instruction was removed and the iterator
1068 /// is not longer valid
1070 int SPAdj, unsigned FIOperandNum,
1071 RegScavenger *RS = nullptr) const = 0;
1072
1073 /// Return the assembly name for \p Reg.
1075 // FIXME: We are assuming that the assembly name is equal to the TableGen
1076 // name converted to lower case
1077 //
1078 // The TableGen name is the name of the definition for this register in the
1079 // target's tablegen files. For example, the TableGen name of
1080 // def EAX : Register <...>; is "EAX"
1081 return StringRef(getName(Reg));
1082 }
1083
1084 //===--------------------------------------------------------------------===//
1085 /// Subtarget Hooks
1086
1087 /// SrcRC and DstRC will be morphed into NewRC if this returns true.
1089 const TargetRegisterClass *SrcRC,
1090 unsigned SubReg,
1091 const TargetRegisterClass *DstRC,
1092 unsigned DstSubReg,
1093 const TargetRegisterClass *NewRC,
1094 LiveIntervals &LIS) const
1095 { return true; }
1096
1097 /// Region split has a high compile time cost especially for large live range.
1098 /// This method is used to decide whether or not \p VirtReg should
1099 /// go through this expensive splitting heuristic.
1100 virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF,
1101 const LiveInterval &VirtReg) const;
1102
1103 /// Last chance recoloring has a high compile time cost especially for
1104 /// targets with a lot of registers.
1105 /// This method is used to decide whether or not \p VirtReg should
1106 /// go through this expensive heuristic.
1107 /// When this target hook is hit, by returning false, there is a high
1108 /// chance that the register allocation will fail altogether (usually with
1109 /// "ran out of registers").
1110 /// That said, this error usually points to another problem in the
1111 /// optimization pipeline.
1112 virtual bool
1114 const LiveInterval &VirtReg) const {
1115 return true;
1116 }
1117
1118 /// Deferred spilling delays the spill insertion of a virtual register
1119 /// after every other allocation. By deferring the spilling, it is
1120 /// sometimes possible to eliminate that spilling altogether because
1121 /// something else could have been eliminated, thus leaving some space
1122 /// for the virtual register.
1123 /// However, this comes with a compile time impact because it adds one
1124 /// more stage to the greedy register allocator.
1125 /// This method is used to decide whether \p VirtReg should use the deferred
1126 /// spilling stage instead of being spilled right away.
1127 virtual bool
1129 const LiveInterval &VirtReg) const {
1130 return false;
1131 }
1132
1133 /// When prioritizing live ranges in register allocation, if this hook returns
1134 /// true then the AllocationPriority of the register class will be treated as
1135 /// more important than whether the range is local to a basic block or global.
1136 virtual bool
1138 return false;
1139 }
1140
1141 //===--------------------------------------------------------------------===//
1142 /// Debug information queries.
1143
1144 /// getFrameRegister - This method should return the register used as a base
1145 /// for values allocated in the current stack frame.
1146 virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
1147
1148 /// Mark a register and all its aliases as reserved in the given set.
1149 void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const;
1150
1151 /// Returns true if for every register in the set all super registers are part
1152 /// of the set as well.
1153 bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
1154 ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1155
1156 virtual const TargetRegisterClass *
1158 const MachineRegisterInfo &MRI) const {
1159 return nullptr;
1160 }
1161
1162 /// Returns the physical register number of sub-register "Index"
1163 /// for physical register RegNo. Return zero if the sub-register does not
1164 /// exist.
1165 inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
1166 return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx);
1167 }
1168
1169 /// Some targets have non-allocatable registers that aren't technically part
1170 /// of the explicit callee saved register list, but should be handled as such
1171 /// in certain cases.
1173 return false;
1174 }
1175
1176 /// Returns the Largest Super Class that is being initialized. There
1177 /// should be a Pseudo Instruction implemented for the super class
1178 /// that is being returned to ensure that Init Undef can apply the
1179 /// initialization correctly.
1180 virtual const TargetRegisterClass *
1182 llvm_unreachable("Unexpected target register class.");
1183 }
1184
1185 /// Returns if the architecture being targeted has the required Pseudo
1186 /// Instructions for initializing the register. By default this returns false,
1187 /// but where it is overriden for an architecture, the behaviour will be
1188 /// different. This can either be a check to ensure the Register Class is
1189 /// present, or to return true as an indication the architecture supports the
1190 /// pass. If using the method that does not check for the Register Class, it
1191 /// is imperative to ensure all required Pseudo Instructions are implemented,
1192 /// otherwise compilation may fail with an `Unexpected register class` error.
1193 virtual bool
1195 return false;
1196 }
1197};
1198
1199//===----------------------------------------------------------------------===//
1200// SuperRegClassIterator
1201//===----------------------------------------------------------------------===//
1202//
1203// Iterate over the possible super-registers for a given register class. The
1204// iterator will visit a list of pairs (Idx, Mask) corresponding to the
1205// possible classes of super-registers.
1206//
1207// Each bit mask will have at least one set bit, and each set bit in Mask
1208// corresponds to a SuperRC such that:
1209//
1210// For all Reg in SuperRC: Reg:Idx is in RC.
1211//
1212// The iterator can include (O, RC->getSubClassMask()) as the first entry which
1213// also satisfies the above requirement, assuming Reg:0 == Reg.
1214//
1216 const unsigned RCMaskWords;
1217 unsigned SubReg = 0;
1218 const uint16_t *Idx;
1219 const uint32_t *Mask;
1220
1221public:
1222 /// Create a SuperRegClassIterator that visits all the super-register classes
1223 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1225 const TargetRegisterInfo *TRI,
1226 bool IncludeSelf = false)
1227 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1228 Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1229 if (!IncludeSelf)
1230 ++*this;
1231 }
1232
1233 /// Returns true if this iterator is still pointing at a valid entry.
1234 bool isValid() const { return Idx; }
1235
1236 /// Returns the current sub-register index.
1237 unsigned getSubReg() const { return SubReg; }
1238
1239 /// Returns the bit mask of register classes that getSubReg() projects into
1240 /// RC.
1241 /// See TargetRegisterClass::getSubClassMask() for how to use it.
1242 const uint32_t *getMask() const { return Mask; }
1243
1244 /// Advance iterator to the next entry.
1245 void operator++() {
1246 assert(isValid() && "Cannot move iterator past end.");
1247 Mask += RCMaskWords;
1248 SubReg = *Idx++;
1249 if (!SubReg)
1250 Idx = nullptr;
1251 }
1252};
1253
1254//===----------------------------------------------------------------------===//
1255// BitMaskClassIterator
1256//===----------------------------------------------------------------------===//
1257/// This class encapuslates the logic to iterate over bitmask returned by
1258/// the various RegClass related APIs.
1259/// E.g., this class can be used to iterate over the subclasses provided by
1260/// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1262 /// Total number of register classes.
1263 const unsigned NumRegClasses;
1264 /// Base index of CurrentChunk.
1265 /// In other words, the number of bit we read to get at the
1266 /// beginning of that chunck.
1267 unsigned Base = 0;
1268 /// Adjust base index of CurrentChunk.
1269 /// Base index + how many bit we read within CurrentChunk.
1270 unsigned Idx = 0;
1271 /// Current register class ID.
1272 unsigned ID = 0;
1273 /// Mask we are iterating over.
1274 const uint32_t *Mask;
1275 /// Current chunk of the Mask we are traversing.
1276 uint32_t CurrentChunk;
1277
1278 /// Move ID to the next set bit.
1279 void moveToNextID() {
1280 // If the current chunk of memory is empty, move to the next one,
1281 // while making sure we do not go pass the number of register
1282 // classes.
1283 while (!CurrentChunk) {
1284 // Move to the next chunk.
1285 Base += 32;
1286 if (Base >= NumRegClasses) {
1287 ID = NumRegClasses;
1288 return;
1289 }
1290 CurrentChunk = *++Mask;
1291 Idx = Base;
1292 }
1293 // Otherwise look for the first bit set from the right
1294 // (representation of the class ID is big endian).
1295 // See getSubClassMask for more details on the representation.
1296 unsigned Offset = llvm::countr_zero(CurrentChunk);
1297 // Add the Offset to the adjusted base number of this chunk: Idx.
1298 // This is the ID of the register class.
1299 ID = Idx + Offset;
1300
1301 // Consume the zeros, if any, and the bit we just read
1302 // so that we are at the right spot for the next call.
1303 // Do not do Offset + 1 because Offset may be 31 and 32
1304 // will be UB for the shift, though in that case we could
1305 // have make the chunk being equal to 0, but that would
1306 // have introduced a if statement.
1307 moveNBits(Offset);
1308 moveNBits(1);
1309 }
1310
1311 /// Move \p NumBits Bits forward in CurrentChunk.
1312 void moveNBits(unsigned NumBits) {
1313 assert(NumBits < 32 && "Undefined behavior spotted!");
1314 // Consume the bit we read for the next call.
1315 CurrentChunk >>= NumBits;
1316 // Adjust the base for the chunk.
1317 Idx += NumBits;
1318 }
1319
1320public:
1321 /// Create a BitMaskClassIterator that visits all the register classes
1322 /// represented by \p Mask.
1323 ///
1324 /// \pre \p Mask != nullptr
1326 : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1327 // Move to the first ID.
1328 moveToNextID();
1329 }
1330
1331 /// Returns true if this iterator is still pointing at a valid entry.
1332 bool isValid() const { return getID() != NumRegClasses; }
1333
1334 /// Returns the current register class ID.
1335 unsigned getID() const { return ID; }
1336
1337 /// Advance iterator to the next entry.
1338 void operator++() {
1339 assert(isValid() && "Cannot move iterator past end.");
1340 moveToNextID();
1341 }
1342};
1343
1344// This is useful when building IndexedMaps keyed on virtual registers
1347 unsigned operator()(Register Reg) const {
1349 }
1350};
1351
1352/// Prints virtual and physical registers with or without a TRI instance.
1353///
1354/// The format is:
1355/// %noreg - NoRegister
1356/// %5 - a virtual register.
1357/// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1358/// %eax - a physical register
1359/// %physreg17 - a physical register when no TRI instance given.
1360///
1361/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1362Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
1363 unsigned SubIdx = 0,
1364 const MachineRegisterInfo *MRI = nullptr);
1365
1366/// Create Printable object to print register units on a \ref raw_ostream.
1367///
1368/// Register units are named after their root registers:
1369///
1370/// al - Single root.
1371/// fp0~st7 - Dual roots.
1372///
1373/// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1374Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1375
1376/// Create Printable object to print virtual registers and physical
1377/// registers on a \ref raw_ostream.
1378Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1379
1380/// Create Printable object to print register classes or register banks
1381/// on a \ref raw_ostream.
1382Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
1383 const TargetRegisterInfo *TRI);
1384
1385} // end namespace llvm
1386
1387#endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
unsigned RegSize
MachineBasicBlock & MBB
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
A common definition of LaneBitmask for use in TableGen and CodeGen.
Live Register Matrix
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
void operator++()
Advance iterator to the next entry.
unsigned getID() const
Returns the current register class ID.
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
DWARF expression.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:687
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getID() const
getID() - Return the register class ID number.
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
iterator begin() const
begin/end - Return all of the registers in this class.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
bool isBaseClass() const
Return true if this register class has a defined BaseClassOrder.
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
iterator end() const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
const char * getRegClassName(const MCRegisterClass *Class) const
iterator_range< MCRegUnitIterator > regunits(MCRegister Reg) const
Returns an iterator range over all regunits for Reg.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
Definition: Register.h:110
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
void operator++()
Advance iterator to the next entry.
unsigned getSubReg() const
Returns the current sub-register index.
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
const TargetRegisterClass *const * sc_iterator
unsigned getNumRegs() const
Return the number of registers in this class.
const uint8_t TSFlags
Configurable target specific flags.
ArrayRef< MCPhysReg > getRegisters() const
bool isBaseClass() const
Return true if this register class has a defined BaseClassOrder.
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
unsigned getID() const
Return the register class ID number.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
const sc_iterator SuperClasses
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &)
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
const uint16_t * SuperRegIndices
const MCRegisterClass * MC
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
bool contains(Register Reg1, Register Reg2) const
Return true if both registers are in this class.
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
iterator begin() const
begin/end - Return all of the registers in this class.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
const TargetRegisterClass *const * regclass_iterator
virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index.
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const
Return true if the given TargetRegisterClass is compatible with LLT T.
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
virtual bool shouldUseDeferredSpillingForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Deferred spilling delays the spill insertion of a virtual register after every other allocation.
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
iterator_range< regclass_iterator > regclasses() const
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
virtual const TargetRegisterClass * getPhysRegBaseClass(MCRegister Reg) const
Return target defined base register class for a physical register.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const
Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint,...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
virtual bool shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Last chance recoloring has a high compile time cost especially for targets with a lot of registers.
virtual bool eliminateFrameIndicesBackwards() const
Process frame indices in reverse block order.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time.
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) const
Returns true if PhysReg cannot be written to in inline asm statements.
virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...
virtual bool isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const
Returns true if the register is considered uniform.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
virtual std::optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const
Returns either a string explaining why the given register is reserved for this function,...
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
virtual bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a general purpose register.
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
regclass_iterator regclass_begin() const
Register class iterators.
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
virtual bool doesRegClassHavePseudoInitUndef(const TargetRegisterClass *RC) const
Returns if the architecture being targeted has the required Pseudo Instructions for initializing the ...
unsigned getNumRegClasses() const
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
virtual ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const
Return a list of all of the registers which are clobbered "inside" a call to the given function.
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const
Some targets have non-allocatable registers that aren't technically part of the explicit callee saved...
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
const RegClassInfo & getRegClassInfo(const TargetRegisterClass &RC) const
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
virtual bool isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg can be used as an argument to a function.
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
virtual const TargetRegisterClass * getSubRegisterClass(const TargetRegisterClass *SuperRC, unsigned SubRegIdx) const
Return a register class that can be used for a subregister copy from/into SuperRC at SubRegIdx.
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
virtual bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
regclass_iterator regclass_end() const
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for a pointer to FrameIdx before insertion point I.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
virtual unsigned getNumSupportedRegs(const MachineFunction &) const
Return the number of registers for the function. (may overestimate)
virtual ArrayRef< const char * > getRegMaskNames() const =0
virtual bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a fixed register.
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
virtual StringRef getRegAsmName(MCRegister Reg) const
Return the assembly name for Reg.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
virtual const TargetRegisterClass * getLargestSuperClass(const TargetRegisterClass *RC) const
Returns the Largest Super Class that is being initialized.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const
Return the register cost table index.
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction's frame index reference would be better served by a base register oth...
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
virtual bool regClassPriorityTrumpsGlobalness(const MachineFunction &MF) const
When prioritizing live ranges in register allocation, if this hook returns true then the AllocationPr...
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
virtual void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
Definition: TypeSize.h:330
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: bit.h:215
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
Extra information, not in MCRegisterDesc, about registers.
unsigned operator()(Register Reg) const