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TargetRegisterInfo.h
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1 //==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes an abstract interface used to get information about a
10 // target machines register file. This information is used for a variety of
11 // purposed, especially register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16 #define LLVM_CODEGEN_TARGETREGISTERINFO_H
17 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/Optional.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
24 #include "llvm/IR/CallingConv.h"
25 #include "llvm/MC/LaneBitmask.h"
26 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/Support/Printable.h"
31 #include <cassert>
32 #include <cstdint>
33 
34 namespace llvm {
35 
36 class BitVector;
37 class DIExpression;
38 class LiveRegMatrix;
39 class MachineFunction;
40 class MachineInstr;
41 class RegScavenger;
42 class VirtRegMap;
43 class LiveIntervals;
44 class LiveInterval;
45 
47 public:
48  using iterator = const MCPhysReg *;
49  using const_iterator = const MCPhysReg *;
50  using sc_iterator = const TargetRegisterClass* const *;
51 
52  // Instance variables filled by tablegen, do not use!
57  /// Classes with a higher priority value are assigned first by register
58  /// allocators using a greedy heuristic. The value is in the range [0,31].
59  const uint8_t AllocationPriority;
60 
61  // Change allocation priority heuristic used by greedy.
62  const bool GlobalPriority;
63 
64  /// Configurable target specific flags.
65  const uint8_t TSFlags;
66  /// Whether the class supports two (or more) disjunct subregister indices.
67  const bool HasDisjunctSubRegs;
68  /// Whether a combination of subregisters can cover every register in the
69  /// class. See also the CoveredBySubRegs description in Target.td.
70  const bool CoveredBySubRegs;
73 
74  /// Return the register class ID number.
75  unsigned getID() const { return MC->getID(); }
76 
77  /// begin/end - Return all of the registers in this class.
78  ///
79  iterator begin() const { return MC->begin(); }
80  iterator end() const { return MC->end(); }
81 
82  /// Return the number of registers in this class.
83  unsigned getNumRegs() const { return MC->getNumRegs(); }
84 
86  getRegisters() const {
87  return make_range(MC->begin(), MC->end());
88  }
89 
90  /// Return the specified register in the class.
91  MCRegister getRegister(unsigned i) const {
92  return MC->getRegister(i);
93  }
94 
95  /// Return true if the specified register is included in this register class.
96  /// This does not include virtual registers.
97  bool contains(Register Reg) const {
98  /// FIXME: Historically this function has returned false when given vregs
99  /// but it should probably only receive physical registers
100  if (!Reg.isPhysical())
101  return false;
102  return MC->contains(Reg.asMCReg());
103  }
104 
105  /// Return true if both registers are in this class.
106  bool contains(Register Reg1, Register Reg2) const {
107  /// FIXME: Historically this function has returned false when given a vregs
108  /// but it should probably only receive physical registers
109  if (!Reg1.isPhysical() || !Reg2.isPhysical())
110  return false;
111  return MC->contains(Reg1.asMCReg(), Reg2.asMCReg());
112  }
113 
114  /// Return the cost of copying a value between two registers in this class.
115  /// A negative number means the register class is very expensive
116  /// to copy e.g. status flag register classes.
117  int getCopyCost() const { return MC->getCopyCost(); }
118 
119  /// Return true if this register class may be used to create virtual
120  /// registers.
121  bool isAllocatable() const { return MC->isAllocatable(); }
122 
123  /// Return true if the specified TargetRegisterClass
124  /// is a proper sub-class of this TargetRegisterClass.
125  bool hasSubClass(const TargetRegisterClass *RC) const {
126  return RC != this && hasSubClassEq(RC);
127  }
128 
129  /// Returns true if RC is a sub-class of or equal to this class.
130  bool hasSubClassEq(const TargetRegisterClass *RC) const {
131  unsigned ID = RC->getID();
132  return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
133  }
134 
135  /// Return true if the specified TargetRegisterClass is a
136  /// proper super-class of this TargetRegisterClass.
137  bool hasSuperClass(const TargetRegisterClass *RC) const {
138  return RC->hasSubClass(this);
139  }
140 
141  /// Returns true if RC is a super-class of or equal to this class.
142  bool hasSuperClassEq(const TargetRegisterClass *RC) const {
143  return RC->hasSubClassEq(this);
144  }
145 
146  /// Returns a bit vector of subclasses, including this one.
147  /// The vector is indexed by class IDs.
148  ///
149  /// To use it, consider the returned array as a chunk of memory that
150  /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
151  /// contains a bitset of the ID of the subclasses in big-endian style.
152 
153  /// I.e., the representation of the memory from left to right at the
154  /// bit level looks like:
155  /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
156  /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
157  /// Where the number represents the class ID and XXX bits that
158  /// should be ignored.
159  ///
160  /// See the implementation of hasSubClassEq for an example of how it
161  /// can be used.
162  const uint32_t *getSubClassMask() const {
163  return SubClassMask;
164  }
165 
166  /// Returns a 0-terminated list of sub-register indices that project some
167  /// super-register class into this register class. The list has an entry for
168  /// each Idx such that:
169  ///
170  /// There exists SuperRC where:
171  /// For all Reg in SuperRC:
172  /// this->contains(Reg:Idx)
173  const uint16_t *getSuperRegIndices() const {
174  return SuperRegIndices;
175  }
176 
177  /// Returns a NULL-terminated list of super-classes. The
178  /// classes are ordered by ID which is also a topological ordering from large
179  /// to small classes. The list does NOT include the current class.
181  return SuperClasses;
182  }
183 
184  /// Return true if this TargetRegisterClass is a subset
185  /// class of at least one other TargetRegisterClass.
186  bool isASubClass() const {
187  return SuperClasses[0] != nullptr;
188  }
189 
190  /// Returns the preferred order for allocating registers from this register
191  /// class in MF. The raw order comes directly from the .td file and may
192  /// include reserved registers that are not allocatable.
193  /// Register allocators should also make sure to allocate
194  /// callee-saved registers only after all the volatiles are used. The
195  /// RegisterClassInfo class provides filtered allocation orders with
196  /// callee-saved registers moved to the end.
197  ///
198  /// The MachineFunction argument can be used to tune the allocatable
199  /// registers based on the characteristics of the function, subtarget, or
200  /// other criteria.
201  ///
202  /// By default, this method returns all registers in the class.
204  return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
205  }
206 
207  /// Returns the combination of all lane masks of register in this class.
208  /// The lane masks of the registers are the combination of all lane masks
209  /// of their subregisters. Returns 1 if there are no subregisters.
211  return LaneMask;
212  }
213 };
214 
215 /// Extra information, not in MCRegisterDesc, about registers.
216 /// These are used by codegen, not by MC.
218  const uint8_t *CostPerUse; // Extra cost of instructions using register.
219  unsigned NumCosts; // Number of cost values associated with each register.
220  const bool
221  *InAllocatableClass; // Register belongs to an allocatable regclass.
222 };
223 
224 /// Each TargetRegisterClass has a per register weight, and weight
225 /// limit which must be less than the limits of its pressure sets.
227  unsigned RegWeight;
228  unsigned WeightLimit;
229 };
230 
231 /// TargetRegisterInfo base class - We assume that the target defines a static
232 /// array of TargetRegisterDesc objects that represent all of the machine
233 /// registers that the target has. As such, we simply have to track a pointer
234 /// to this array so that we can turn register number into a register
235 /// descriptor.
236 ///
238 public:
239  using regclass_iterator = const TargetRegisterClass * const *;
241  struct RegClassInfo {
244  };
245 private:
246  const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
247  const char *const *SubRegIndexNames; // Names of subreg indexes.
248  // Pointer to array of lane masks, one per sub-reg index.
249  const LaneBitmask *SubRegIndexLaneMasks;
250 
251  regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
252  LaneBitmask CoveringLanes;
253  const RegClassInfo *const RCInfos;
254  unsigned HwMode;
255 
256 protected:
258  regclass_iterator RCB,
259  regclass_iterator RCE,
260  const char *const *SRINames,
261  const LaneBitmask *SRILaneMasks,
262  LaneBitmask CoveringLanes,
263  const RegClassInfo *const RCIs,
264  unsigned Mode = 0);
265  virtual ~TargetRegisterInfo();
266 
267 public:
268  // Register numbers can represent physical registers, virtual registers, and
269  // sometimes stack slots. The unsigned values are divided into these ranges:
270  //
271  // 0 Not a register, can be used as a sentinel.
272  // [1;2^30) Physical registers assigned by TableGen.
273  // [2^30;2^31) Stack slots. (Rarely used.)
274  // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
275  //
276  // Further sentinels can be allocated from the small negative integers.
277  // DenseMapInfo<unsigned> uses -1u and -2u.
278 
279  /// Return the size in bits of a register from class RC.
280  unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
281  return getRegClassInfo(RC).RegSize;
282  }
283 
284  /// Return the size in bytes of the stack slot allocated to hold a spilled
285  /// copy of a register from class RC.
286  unsigned getSpillSize(const TargetRegisterClass &RC) const {
287  return getRegClassInfo(RC).SpillSize / 8;
288  }
289 
290  /// Return the minimum required alignment in bytes for a spill slot for
291  /// a register of this class.
293  return Align(getRegClassInfo(RC).SpillAlignment / 8);
294  }
295 
296  /// Return true if the given TargetRegisterClass has the ValueType T.
297  bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
298  for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
299  if (MVT(*I) == T)
300  return true;
301  return false;
302  }
303 
304  /// Return true if the given TargetRegisterClass is compatible with LLT T.
305  bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const {
306  for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) {
307  MVT VT(*I);
308  if (VT == MVT::Untyped)
309  return true;
310 
311  if (LLT(VT) == T)
312  return true;
313  }
314  return false;
315  }
316 
317  /// Loop over all of the value types that can be represented by values
318  /// in the given register class.
320  return getRegClassInfo(RC).VTList;
321  }
322 
325  while (*I != MVT::Other)
326  ++I;
327  return I;
328  }
329 
330  /// Returns the Register Class of a physical register of the given type,
331  /// picking the most sub register class of the right type that contains this
332  /// physreg.
334  MVT VT = MVT::Other) const;
335 
336  /// Returns the Register Class of a physical register of the given type,
337  /// picking the most sub register class of the right type that contains this
338  /// physreg. If there is no register class compatible with the given type,
339  /// returns nullptr.
341  LLT Ty = LLT()) const;
342 
343  /// Return the maximal subclass of the given register class that is
344  /// allocatable or NULL.
345  const TargetRegisterClass *
346  getAllocatableClass(const TargetRegisterClass *RC) const;
347 
348  /// Returns a bitset indexed by register number indicating if a register is
349  /// allocatable or not. If a register class is specified, returns the subset
350  /// for the class.
352  const TargetRegisterClass *RC = nullptr) const;
353 
354  /// Get a list of cost values for all registers that correspond to the index
355  /// returned by RegisterCostTableIndex.
357  unsigned Idx = getRegisterCostTableIndex(MF);
358  unsigned NumRegs = getNumRegs();
359  assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds");
360 
361  return makeArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
362  }
363 
364  /// Return true if the register is in the allocation of any register class.
365  bool isInAllocatableClass(MCRegister RegNo) const {
366  return InfoDesc->InAllocatableClass[RegNo];
367  }
368 
369  /// Return the human-readable symbolic target-specific
370  /// name for the specified SubRegIndex.
371  const char *getSubRegIndexName(unsigned SubIdx) const {
372  assert(SubIdx && SubIdx < getNumSubRegIndices() &&
373  "This is not a subregister index");
374  return SubRegIndexNames[SubIdx-1];
375  }
376 
377  /// Return a bitmask representing the parts of a register that are covered by
378  /// SubIdx \see LaneBitmask.
379  ///
380  /// SubIdx == 0 is allowed, it has the lane mask ~0u.
381  LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
382  assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
383  return SubRegIndexLaneMasks[SubIdx];
384  }
385 
386  /// Try to find one or more subregister indexes to cover \p LaneMask.
387  ///
388  /// If this is possible, returns true and appends the best matching set of
389  /// indexes to \p Indexes. If this is not possible, returns false.
391  const TargetRegisterClass *RC,
392  LaneBitmask LaneMask,
393  SmallVectorImpl<unsigned> &Indexes) const;
394 
395  /// The lane masks returned by getSubRegIndexLaneMask() above can only be
396  /// used to determine if sub-registers overlap - they can't be used to
397  /// determine if a set of sub-registers completely cover another
398  /// sub-register.
399  ///
400  /// The X86 general purpose registers have two lanes corresponding to the
401  /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
402  /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
403  /// sub_32bit sub-register.
404  ///
405  /// On the other hand, the ARM NEON lanes fully cover their registers: The
406  /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
407  /// This is related to the CoveredBySubRegs property on register definitions.
408  ///
409  /// This function returns a bit mask of lanes that completely cover their
410  /// sub-registers. More precisely, given:
411  ///
412  /// Covering = getCoveringLanes();
413  /// MaskA = getSubRegIndexLaneMask(SubA);
414  /// MaskB = getSubRegIndexLaneMask(SubB);
415  ///
416  /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
417  /// SubB.
418  LaneBitmask getCoveringLanes() const { return CoveringLanes; }
419 
420  /// Returns true if the two registers are equal or alias each other.
421  /// The registers may be virtual registers.
422  bool regsOverlap(Register RegA, Register RegB) const {
423  if (RegA == RegB)
424  return true;
425  if (RegA.isPhysical() && RegB.isPhysical())
426  return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg());
427  return false;
428  }
429 
430  /// Returns true if Reg contains RegUnit.
431  bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
432  for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
433  if (Register(*Units) == RegUnit)
434  return true;
435  return false;
436  }
437 
438  /// Returns the original SrcReg unless it is the target of a copy-like
439  /// operation, in which case we chain backwards through all such operations
440  /// to the ultimate source register. If a physical register is encountered,
441  /// we stop the search.
442  virtual Register lookThruCopyLike(Register SrcReg,
443  const MachineRegisterInfo *MRI) const;
444 
445  /// Find the original SrcReg unless it is the target of a copy-like operation,
446  /// in which case we chain backwards through all such operations to the
447  /// ultimate source register. If a physical register is encountered, we stop
448  /// the search.
449  /// Return the original SrcReg if all the definitions in the chain only have
450  /// one user and not a physical register.
451  virtual Register
453  const MachineRegisterInfo *MRI) const;
454 
455  /// Return a null-terminated list of all of the callee-saved registers on
456  /// this target. The register should be in the order of desired callee-save
457  /// stack frame offset. The first register is closest to the incoming stack
458  /// pointer if stack grows down, and vice versa.
459  /// Notice: This function does not take into account disabled CSRs.
460  /// In most cases you will want to use instead the function
461  /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
462  virtual const MCPhysReg*
463  getCalleeSavedRegs(const MachineFunction *MF) const = 0;
464 
465  /// Return a mask of call-preserved registers for the given calling convention
466  /// on the current function. The mask should include all call-preserved
467  /// aliases. This is used by the register allocator to determine which
468  /// registers can be live across a call.
469  ///
470  /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
471  /// A set bit indicates that all bits of the corresponding register are
472  /// preserved across the function call. The bit mask is expected to be
473  /// sub-register complete, i.e. if A is preserved, so are all its
474  /// sub-registers.
475  ///
476  /// Bits are numbered from the LSB, so the bit for physical register Reg can
477  /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
478  ///
479  /// A NULL pointer means that no register mask will be used, and call
480  /// instructions should use implicit-def operands to indicate call clobbered
481  /// registers.
482  ///
484  CallingConv::ID) const {
485  // The default mask clobbers everything. All targets should override.
486  return nullptr;
487  }
488 
489  /// Return a register mask for the registers preserved by the unwinder,
490  /// or nullptr if no custom mask is needed.
491  virtual const uint32_t *
493  return nullptr;
494  }
495 
496  /// Return a register mask that clobbers everything.
497  virtual const uint32_t *getNoPreservedMask() const {
498  llvm_unreachable("target does not provide no preserved mask");
499  }
500 
501  /// Return a list of all of the registers which are clobbered "inside" a call
502  /// to the given function. For example, these might be needed for PLT
503  /// sequences of long-branch veneers.
504  virtual ArrayRef<MCPhysReg>
506  return {};
507  }
508 
509  /// Return true if all bits that are set in mask \p mask0 are also set in
510  /// \p mask1.
511  bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
512 
513  /// Return all the call-preserved register masks defined for this target.
514  virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
515  virtual ArrayRef<const char *> getRegMaskNames() const = 0;
516 
517  /// Returns a bitset indexed by physical register number indicating if a
518  /// register is a special register that has particular uses and should be
519  /// considered unavailable at all times, e.g. stack pointer, return address.
520  /// A reserved register:
521  /// - is not allocatable
522  /// - is considered always live
523  /// - is ignored by liveness tracking
524  /// It is often necessary to reserve the super registers of a reserved
525  /// register as well, to avoid them getting allocated indirectly. You may use
526  /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
527  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
528 
529  /// Returns either a string explaining why the given register is reserved for
530  /// this function, or an empty optional if no explanation has been written.
531  /// The absence of an explanation does not mean that the register is not
532  /// reserved (meaning, you should check that PhysReg is in fact reserved
533  /// before calling this).
535  explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const {
536  return {};
537  }
538 
539  /// Returns false if we can't guarantee that Physreg, specified as an IR asm
540  /// clobber constraint, will be preserved across the statement.
541  virtual bool isAsmClobberable(const MachineFunction &MF,
542  MCRegister PhysReg) const {
543  return true;
544  }
545 
546  /// Returns true if PhysReg cannot be written to in inline asm statements.
547  virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF,
548  unsigned PhysReg) const {
549  return false;
550  }
551 
552  /// Returns true if PhysReg is unallocatable and constant throughout the
553  /// function. Used by MachineRegisterInfo::isConstantPhysReg().
554  virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }
555 
556  /// Returns true if the register class is considered divergent.
557  virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
558  return false;
559  }
560 
561  /// Physical registers that may be modified within a function but are
562  /// guaranteed to be restored before any uses. This is useful for targets that
563  /// have call sequences where a GOT register may be updated by the caller
564  /// prior to a call and is guaranteed to be restored (also by the caller)
565  /// after the call.
566  virtual bool isCallerPreservedPhysReg(MCRegister PhysReg,
567  const MachineFunction &MF) const {
568  return false;
569  }
570 
571  /// This is a wrapper around getCallPreservedMask().
572  /// Return true if the register is preserved after the call.
573  virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
574  const MachineFunction &MF) const;
575 
576  /// Returns true if PhysReg can be used as an argument to a function.
577  virtual bool isArgumentRegister(const MachineFunction &MF,
578  MCRegister PhysReg) const {
579  return false;
580  }
581 
582  /// Returns true if PhysReg is a fixed register.
583  virtual bool isFixedRegister(const MachineFunction &MF,
584  MCRegister PhysReg) const {
585  return false;
586  }
587 
588  /// Returns true if PhysReg is a general purpose register.
590  MCRegister PhysReg) const {
591  return false;
592  }
593 
594  /// Prior to adding the live-out mask to a stackmap or patchpoint
595  /// instruction, provide the target the opportunity to adjust it (mainly to
596  /// remove pseudo-registers that should be ignored).
597  virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
598 
599  /// Return a super-register of the specified register
600  /// Reg so its sub-register of index SubIdx is Reg.
602  const TargetRegisterClass *RC) const {
603  return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
604  }
605 
606  /// Return a subclass of the specified register
607  /// class A so that each register in it has a sub-register of the
608  /// specified sub-register index which is in the specified register class B.
609  ///
610  /// TableGen will synthesize missing A sub-classes.
611  virtual const TargetRegisterClass *
613  const TargetRegisterClass *B, unsigned Idx) const;
614 
615  // For a copy-like instruction that defines a register of class DefRC with
616  // subreg index DefSubReg, reading from another source with class SrcRC and
617  // subregister SrcSubReg return true if this is a preferable copy
618  // instruction or an earlier use should be used.
619  virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
620  unsigned DefSubReg,
621  const TargetRegisterClass *SrcRC,
622  unsigned SrcSubReg) const;
623 
624  /// Returns the largest legal sub-class of RC that
625  /// supports the sub-register index Idx.
626  /// If no such sub-class exists, return NULL.
627  /// If all registers in RC already have an Idx sub-register, return RC.
628  ///
629  /// TableGen generates a version of this function that is good enough in most
630  /// cases. Targets can override if they have constraints that TableGen
631  /// doesn't understand. For example, the x86 sub_8bit sub-register index is
632  /// supported by the full GR32 register class in 64-bit mode, but only by the
633  /// GR32_ABCD regiister class in 32-bit mode.
634  ///
635  /// TableGen will synthesize missing RC sub-classes.
636  virtual const TargetRegisterClass *
637  getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
638  assert(Idx == 0 && "Target has no sub-registers");
639  return RC;
640  }
641 
642  /// Return a register class that can be used for a subregister copy from/into
643  /// \p SuperRC at \p SubRegIdx.
644  virtual const TargetRegisterClass *
646  unsigned SubRegIdx) const {
647  return nullptr;
648  }
649 
650  /// Return the subregister index you get from composing
651  /// two subregister indices.
652  ///
653  /// The special null sub-register index composes as the identity.
654  ///
655  /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
656  /// returns c. Note that composeSubRegIndices does not tell you about illegal
657  /// compositions. If R does not have a subreg a, or R:a does not have a subreg
658  /// b, composeSubRegIndices doesn't tell you.
659  ///
660  /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
661  /// ssub_0:S0 - ssub_3:S3 subregs.
662  /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
663  unsigned composeSubRegIndices(unsigned a, unsigned b) const {
664  if (!a) return b;
665  if (!b) return a;
666  return composeSubRegIndicesImpl(a, b);
667  }
668 
669  /// Transforms a LaneMask computed for one subregister to the lanemask that
670  /// would have been computed when composing the subsubregisters with IdxA
671  /// first. @sa composeSubRegIndices()
673  LaneBitmask Mask) const {
674  if (!IdxA)
675  return Mask;
676  return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
677  }
678 
679  /// Transform a lanemask given for a virtual register to the corresponding
680  /// lanemask before using subregister with index \p IdxA.
681  /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
682  /// valie lane mask (no invalid bits set) the following holds:
683  /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
684  /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
685  /// => X1 == Mask
687  LaneBitmask LaneMask) const {
688  if (!IdxA)
689  return LaneMask;
690  return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
691  }
692 
693  /// Debugging helper: dump register in human readable form to dbgs() stream.
694  static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
695  const TargetRegisterInfo *TRI = nullptr);
696 
697 protected:
698  /// Overridden by TableGen in targets that have sub-registers.
699  virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
700  llvm_unreachable("Target has no sub-registers");
701  }
702 
703  /// Overridden by TableGen in targets that have sub-registers.
704  virtual LaneBitmask
706  llvm_unreachable("Target has no sub-registers");
707  }
708 
710  LaneBitmask) const {
711  llvm_unreachable("Target has no sub-registers");
712  }
713 
714  /// Return the register cost table index. This implementation is sufficient
715  /// for most architectures and can be overriden by targets in case there are
716  /// multiple cost values associated with each register.
717  virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const {
718  return 0;
719  }
720 
721 public:
722  /// Find a common super-register class if it exists.
723  ///
724  /// Find a register class, SuperRC and two sub-register indices, PreA and
725  /// PreB, such that:
726  ///
727  /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
728  ///
729  /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
730  ///
731  /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
732  ///
733  /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
734  /// requirements, and there is no register class with a smaller spill size
735  /// that satisfies the requirements.
736  ///
737  /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
738  ///
739  /// Either of the PreA and PreB sub-register indices may be returned as 0. In
740  /// that case, the returned register class will be a sub-class of the
741  /// corresponding argument register class.
742  ///
743  /// The function returns NULL if no register class can be found.
744  const TargetRegisterClass*
745  getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
746  const TargetRegisterClass *RCB, unsigned SubB,
747  unsigned &PreA, unsigned &PreB) const;
748 
749  //===--------------------------------------------------------------------===//
750  // Register Class Information
751  //
752 protected:
754  return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
755  }
756 
757 public:
758  /// Register class iterators
759  regclass_iterator regclass_begin() const { return RegClassBegin; }
760  regclass_iterator regclass_end() const { return RegClassEnd; }
763  }
764 
765  unsigned getNumRegClasses() const {
766  return (unsigned)(regclass_end()-regclass_begin());
767  }
768 
769  /// Returns the register class associated with the enumeration value.
770  /// See class MCOperandInfo.
771  const TargetRegisterClass *getRegClass(unsigned i) const {
772  assert(i < getNumRegClasses() && "Register Class ID out of range");
773  return RegClassBegin[i];
774  }
775 
776  /// Returns the name of the register class.
777  const char *getRegClassName(const TargetRegisterClass *Class) const {
778  return MCRegisterInfo::getRegClassName(Class->MC);
779  }
780 
781  /// Find the largest common subclass of A and B.
782  /// Return NULL if there is no common subclass.
783  const TargetRegisterClass *
785  const TargetRegisterClass *B) const;
786 
787  /// Returns a TargetRegisterClass used for pointer values.
788  /// If a target supports multiple different pointer register classes,
789  /// kind specifies which one is indicated.
790  virtual const TargetRegisterClass *
791  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
792  llvm_unreachable("Target didn't implement getPointerRegClass!");
793  }
794 
795  /// Returns a legal register class to copy a register in the specified class
796  /// to or from. If it is possible to copy the register directly without using
797  /// a cross register class copy, return the specified RC. Returns NULL if it
798  /// is not possible to copy between two registers of the specified class.
799  virtual const TargetRegisterClass *
801  return RC;
802  }
803 
804  /// Returns the largest super class of RC that is legal to use in the current
805  /// sub-target and has the same spill size.
806  /// The returned register class can be used to create virtual registers which
807  /// means that all its registers can be copied and spilled.
808  virtual const TargetRegisterClass *
810  const MachineFunction &) const {
811  /// The default implementation is very conservative and doesn't allow the
812  /// register allocator to inflate register classes.
813  return RC;
814  }
815 
816  /// Return the register pressure "high water mark" for the specific register
817  /// class. The scheduler is in high register pressure mode (for the specific
818  /// register class) if it goes over the limit.
819  ///
820  /// Note: this is the old register pressure model that relies on a manually
821  /// specified representative register class per value type.
822  virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
823  MachineFunction &MF) const {
824  return 0;
825  }
826 
827  /// Return a heuristic for the machine scheduler to compare the profitability
828  /// of increasing one register pressure set versus another. The scheduler
829  /// will prefer increasing the register pressure of the set which returns
830  /// the largest value for this function.
831  virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
832  unsigned PSetID) const {
833  return PSetID;
834  }
835 
836  /// Get the weight in units of pressure for this register class.
837  virtual const RegClassWeight &getRegClassWeight(
838  const TargetRegisterClass *RC) const = 0;
839 
840  /// Returns size in bits of a phys/virtual/generic register.
841  unsigned getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
842 
843  /// Get the weight in units of pressure for this register unit.
844  virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
845 
846  /// Get the number of dimensions of register pressure.
847  virtual unsigned getNumRegPressureSets() const = 0;
848 
849  /// Get the name of this register unit pressure set.
850  virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
851 
852  /// Get the register unit pressure limit for this dimension.
853  /// This limit must be adjusted dynamically for reserved registers.
854  virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
855  unsigned Idx) const = 0;
856 
857  /// Get the dimensions of register pressure impacted by this register class.
858  /// Returns a -1 terminated array of pressure set IDs.
859  virtual const int *getRegClassPressureSets(
860  const TargetRegisterClass *RC) const = 0;
861 
862  /// Get the dimensions of register pressure impacted by this register unit.
863  /// Returns a -1 terminated array of pressure set IDs.
864  virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
865 
866  /// Get a list of 'hint' registers that the register allocator should try
867  /// first when allocating a physical register for the virtual register
868  /// VirtReg. These registers are effectively moved to the front of the
869  /// allocation order. If true is returned, regalloc will try to only use
870  /// hints to the greatest extent possible even if it means spilling.
871  ///
872  /// The Order argument is the allocation order for VirtReg's register class
873  /// as returned from RegisterClassInfo::getOrder(). The hint registers must
874  /// come from Order, and they must not be reserved.
875  ///
876  /// The default implementation of this function will only add target
877  /// independent register allocation hints. Targets that override this
878  /// function should typically call this default implementation as well and
879  /// expect to see generic copy hints added.
880  virtual bool
883  const MachineFunction &MF,
884  const VirtRegMap *VRM = nullptr,
885  const LiveRegMatrix *Matrix = nullptr) const;
886 
887  /// A callback to allow target a chance to update register allocation hints
888  /// when a register is "changed" (e.g. coalesced) to another register.
889  /// e.g. On ARM, some virtual registers should target register pairs,
890  /// if one of pair is coalesced to another register, the allocation hint of
891  /// the other half of the pair should be changed to point to the new register.
892  virtual void updateRegAllocHint(Register Reg, Register NewReg,
893  MachineFunction &MF) const {
894  // Do nothing.
895  }
896 
897  /// Allow the target to reverse allocation order of local live ranges. This
898  /// will generally allocate shorter local live ranges first. For targets with
899  /// many registers, this could reduce regalloc compile time by a large
900  /// factor. It is disabled by default for three reasons:
901  /// (1) Top-down allocation is simpler and easier to debug for targets that
902  /// don't benefit from reversing the order.
903  /// (2) Bottom-up allocation could result in poor evicition decisions on some
904  /// targets affecting the performance of compiled code.
905  /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
906  virtual bool reverseLocalAssignment() const { return false; }
907 
908  /// Allow the target to override the cost of using a callee-saved register for
909  /// the first time. Default value of 0 means we will use a callee-saved
910  /// register if it is available.
911  virtual unsigned getCSRFirstUseCost() const { return 0; }
912 
913  /// Returns true if the target requires (and can make use of) the register
914  /// scavenger.
915  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
916  return false;
917  }
918 
919  /// Returns true if the target wants to use frame pointer based accesses to
920  /// spill to the scavenger emergency spill slot.
921  virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
922  return true;
923  }
924 
925  /// Returns true if the target requires post PEI scavenging of registers for
926  /// materializing frame index constants.
927  virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
928  return false;
929  }
930 
931  /// Returns true if the target requires using the RegScavenger directly for
932  /// frame elimination despite using requiresFrameIndexScavenging.
934  const MachineFunction &MF) const {
935  return false;
936  }
937 
938  /// Returns true if the target wants the LocalStackAllocation pass to be run
939  /// and virtual base registers used for more efficient stack access.
940  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
941  return false;
942  }
943 
944  /// Return true if target has reserved a spill slot in the stack frame of
945  /// the given function for the specified register. e.g. On x86, if the frame
946  /// register is required, the first fixed stack object is reserved as its
947  /// spill slot. This tells PEI not to create a new stack frame
948  /// object for the given register. It should be called only after
949  /// determineCalleeSaves().
951  int &FrameIdx) const {
952  return false;
953  }
954 
955  /// Returns true if the live-ins should be tracked after register allocation.
956  virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
957  return true;
958  }
959 
960  /// True if the stack can be realigned for the target.
961  virtual bool canRealignStack(const MachineFunction &MF) const;
962 
963  /// True if storage within the function requires the stack pointer to be
964  /// aligned more than the normal calling convention calls for.
965  virtual bool shouldRealignStack(const MachineFunction &MF) const;
966 
967  /// True if stack realignment is required and still possible.
968  bool hasStackRealignment(const MachineFunction &MF) const {
969  return shouldRealignStack(MF) && canRealignStack(MF);
970  }
971 
972  /// Get the offset from the referenced frame index in the instruction,
973  /// if there is one.
974  virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
975  int Idx) const {
976  return 0;
977  }
978 
979  /// Returns true if the instruction's frame index reference would be better
980  /// served by a base register other than FP or SP.
981  /// Used by LocalStackFrameAllocation to determine which frame index
982  /// references it should create new base registers for.
983  virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
984  return false;
985  }
986 
987  /// Insert defining instruction(s) for a pointer to FrameIdx before
988  /// insertion point I. Return materialized frame pointer.
990  int FrameIdx,
991  int64_t Offset) const {
992  llvm_unreachable("materializeFrameBaseRegister does not exist on this "
993  "target");
994  }
995 
996  /// Resolve a frame index operand of an instruction
997  /// to reference the indicated base register plus offset instead.
998  virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
999  int64_t Offset) const {
1000  llvm_unreachable("resolveFrameIndex does not exist on this target");
1001  }
1002 
1003  /// Determine whether a given base register plus offset immediate is
1004  /// encodable to resolve a frame index.
1005  virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
1006  int64_t Offset) const {
1007  llvm_unreachable("isFrameOffsetLegal does not exist on this target");
1008  }
1009 
1010  /// Gets the DWARF expression opcodes for \p Offset.
1011  virtual void getOffsetOpcodes(const StackOffset &Offset,
1012  SmallVectorImpl<uint64_t> &Ops) const;
1013 
1014  /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
1015  DIExpression *
1016  prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
1017  const StackOffset &Offset) const;
1018 
1019  /// Spill the register so it can be used by the register scavenger.
1020  /// Return true if the register was spilled, false otherwise.
1021  /// If this function does not spill the register, the scavenger
1022  /// will instead spill it to the emergency spill slot.
1026  const TargetRegisterClass *RC,
1027  Register Reg) const {
1028  return false;
1029  }
1030 
1031  /// This method must be overriden to eliminate abstract frame indices from
1032  /// instructions which may use them. The instruction referenced by the
1033  /// iterator contains an MO_FrameIndex operand which must be eliminated by
1034  /// this method. This method may modify or replace the specified instruction,
1035  /// as long as it keeps the iterator pointing at the finished product.
1036  /// SPAdj is the SP adjustment due to call frame setup instruction.
1037  /// FIOperandNum is the FI operand number.
1039  int SPAdj, unsigned FIOperandNum,
1040  RegScavenger *RS = nullptr) const = 0;
1041 
1042  /// Return the assembly name for \p Reg.
1044  // FIXME: We are assuming that the assembly name is equal to the TableGen
1045  // name converted to lower case
1046  //
1047  // The TableGen name is the name of the definition for this register in the
1048  // target's tablegen files. For example, the TableGen name of
1049  // def EAX : Register <...>; is "EAX"
1050  return StringRef(getName(Reg));
1051  }
1052 
1053  //===--------------------------------------------------------------------===//
1054  /// Subtarget Hooks
1055 
1056  /// SrcRC and DstRC will be morphed into NewRC if this returns true.
1058  const TargetRegisterClass *SrcRC,
1059  unsigned SubReg,
1060  const TargetRegisterClass *DstRC,
1061  unsigned DstSubReg,
1062  const TargetRegisterClass *NewRC,
1063  LiveIntervals &LIS) const
1064  { return true; }
1065 
1066  /// Region split has a high compile time cost especially for large live range.
1067  /// This method is used to decide whether or not \p VirtReg should
1068  /// go through this expensive splitting heuristic.
1069  virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF,
1070  const LiveInterval &VirtReg) const;
1071 
1072  /// Last chance recoloring has a high compile time cost especially for
1073  /// targets with a lot of registers.
1074  /// This method is used to decide whether or not \p VirtReg should
1075  /// go through this expensive heuristic.
1076  /// When this target hook is hit, by returning false, there is a high
1077  /// chance that the register allocation will fail altogether (usually with
1078  /// "ran out of registers").
1079  /// That said, this error usually points to another problem in the
1080  /// optimization pipeline.
1081  virtual bool
1083  const LiveInterval &VirtReg) const {
1084  return true;
1085  }
1086 
1087  /// Deferred spilling delays the spill insertion of a virtual register
1088  /// after every other allocation. By deferring the spilling, it is
1089  /// sometimes possible to eliminate that spilling altogether because
1090  /// something else could have been eliminated, thus leaving some space
1091  /// for the virtual register.
1092  /// However, this comes with a compile time impact because it adds one
1093  /// more stage to the greedy register allocator.
1094  /// This method is used to decide whether \p VirtReg should use the deferred
1095  /// spilling stage instead of being spilled right away.
1096  virtual bool
1098  const LiveInterval &VirtReg) const {
1099  return false;
1100  }
1101 
1102  /// When prioritizing live ranges in register allocation, if this hook returns
1103  /// true then the AllocationPriority of the register class will be treated as
1104  /// more important than whether the range is local to a basic block or global.
1105  virtual bool
1107  return false;
1108  }
1109 
1110  //===--------------------------------------------------------------------===//
1111  /// Debug information queries.
1112 
1113  /// getFrameRegister - This method should return the register used as a base
1114  /// for values allocated in the current stack frame.
1115  virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
1116 
1117  /// Mark a register and all its aliases as reserved in the given set.
1119 
1120  /// Returns true if for every register in the set all super registers are part
1121  /// of the set as well.
1123  ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1124 
1125  virtual const TargetRegisterClass *
1127  const MachineRegisterInfo &MRI) const {
1128  return nullptr;
1129  }
1130 
1131  /// Returns the physical register number of sub-register "Index"
1132  /// for physical register RegNo. Return zero if the sub-register does not
1133  /// exist.
1134  inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
1135  return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx);
1136  }
1137 
1138  /// Some targets have non-allocatable registers that aren't technically part
1139  /// of the explicit callee saved register list, but should be handled as such
1140  /// in certain cases.
1142  return false;
1143  }
1144 };
1145 
1146 //===----------------------------------------------------------------------===//
1147 // SuperRegClassIterator
1148 //===----------------------------------------------------------------------===//
1149 //
1150 // Iterate over the possible super-registers for a given register class. The
1151 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
1152 // possible classes of super-registers.
1153 //
1154 // Each bit mask will have at least one set bit, and each set bit in Mask
1155 // corresponds to a SuperRC such that:
1156 //
1157 // For all Reg in SuperRC: Reg:Idx is in RC.
1158 //
1159 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
1160 // also satisfies the above requirement, assuming Reg:0 == Reg.
1161 //
1163  const unsigned RCMaskWords;
1164  unsigned SubReg = 0;
1165  const uint16_t *Idx;
1166  const uint32_t *Mask;
1167 
1168 public:
1169  /// Create a SuperRegClassIterator that visits all the super-register classes
1170  /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1172  const TargetRegisterInfo *TRI,
1173  bool IncludeSelf = false)
1174  : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1175  Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1176  if (!IncludeSelf)
1177  ++*this;
1178  }
1179 
1180  /// Returns true if this iterator is still pointing at a valid entry.
1181  bool isValid() const { return Idx; }
1182 
1183  /// Returns the current sub-register index.
1184  unsigned getSubReg() const { return SubReg; }
1185 
1186  /// Returns the bit mask of register classes that getSubReg() projects into
1187  /// RC.
1188  /// See TargetRegisterClass::getSubClassMask() for how to use it.
1189  const uint32_t *getMask() const { return Mask; }
1190 
1191  /// Advance iterator to the next entry.
1192  void operator++() {
1193  assert(isValid() && "Cannot move iterator past end.");
1194  Mask += RCMaskWords;
1195  SubReg = *Idx++;
1196  if (!SubReg)
1197  Idx = nullptr;
1198  }
1199 };
1200 
1201 //===----------------------------------------------------------------------===//
1202 // BitMaskClassIterator
1203 //===----------------------------------------------------------------------===//
1204 /// This class encapuslates the logic to iterate over bitmask returned by
1205 /// the various RegClass related APIs.
1206 /// E.g., this class can be used to iterate over the subclasses provided by
1207 /// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1209  /// Total number of register classes.
1210  const unsigned NumRegClasses;
1211  /// Base index of CurrentChunk.
1212  /// In other words, the number of bit we read to get at the
1213  /// beginning of that chunck.
1214  unsigned Base = 0;
1215  /// Adjust base index of CurrentChunk.
1216  /// Base index + how many bit we read within CurrentChunk.
1217  unsigned Idx = 0;
1218  /// Current register class ID.
1219  unsigned ID = 0;
1220  /// Mask we are iterating over.
1221  const uint32_t *Mask;
1222  /// Current chunk of the Mask we are traversing.
1223  uint32_t CurrentChunk;
1224 
1225  /// Move ID to the next set bit.
1226  void moveToNextID() {
1227  // If the current chunk of memory is empty, move to the next one,
1228  // while making sure we do not go pass the number of register
1229  // classes.
1230  while (!CurrentChunk) {
1231  // Move to the next chunk.
1232  Base += 32;
1233  if (Base >= NumRegClasses) {
1234  ID = NumRegClasses;
1235  return;
1236  }
1237  CurrentChunk = *++Mask;
1238  Idx = Base;
1239  }
1240  // Otherwise look for the first bit set from the right
1241  // (representation of the class ID is big endian).
1242  // See getSubClassMask for more details on the representation.
1243  unsigned Offset = countTrailingZeros(CurrentChunk);
1244  // Add the Offset to the adjusted base number of this chunk: Idx.
1245  // This is the ID of the register class.
1246  ID = Idx + Offset;
1247 
1248  // Consume the zeros, if any, and the bit we just read
1249  // so that we are at the right spot for the next call.
1250  // Do not do Offset + 1 because Offset may be 31 and 32
1251  // will be UB for the shift, though in that case we could
1252  // have make the chunk being equal to 0, but that would
1253  // have introduced a if statement.
1254  moveNBits(Offset);
1255  moveNBits(1);
1256  }
1257 
1258  /// Move \p NumBits Bits forward in CurrentChunk.
1259  void moveNBits(unsigned NumBits) {
1260  assert(NumBits < 32 && "Undefined behavior spotted!");
1261  // Consume the bit we read for the next call.
1262  CurrentChunk >>= NumBits;
1263  // Adjust the base for the chunk.
1264  Idx += NumBits;
1265  }
1266 
1267 public:
1268  /// Create a BitMaskClassIterator that visits all the register classes
1269  /// represented by \p Mask.
1270  ///
1271  /// \pre \p Mask != nullptr
1273  : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1274  // Move to the first ID.
1275  moveToNextID();
1276  }
1277 
1278  /// Returns true if this iterator is still pointing at a valid entry.
1279  bool isValid() const { return getID() != NumRegClasses; }
1280 
1281  /// Returns the current register class ID.
1282  unsigned getID() const { return ID; }
1283 
1284  /// Advance iterator to the next entry.
1285  void operator++() {
1286  assert(isValid() && "Cannot move iterator past end.");
1287  moveToNextID();
1288  }
1289 };
1290 
1291 // This is useful when building IndexedMaps keyed on virtual registers
1294  unsigned operator()(Register Reg) const {
1295  return Register::virtReg2Index(Reg);
1296  }
1297 };
1298 
1299 /// Prints virtual and physical registers with or without a TRI instance.
1300 ///
1301 /// The format is:
1302 /// %noreg - NoRegister
1303 /// %5 - a virtual register.
1304 /// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1305 /// %eax - a physical register
1306 /// %physreg17 - a physical register when no TRI instance given.
1307 ///
1308 /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1309 Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
1310  unsigned SubIdx = 0,
1311  const MachineRegisterInfo *MRI = nullptr);
1312 
1313 /// Create Printable object to print register units on a \ref raw_ostream.
1314 ///
1315 /// Register units are named after their root registers:
1316 ///
1317 /// al - Single root.
1318 /// fp0~st7 - Dual roots.
1319 ///
1320 /// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1321 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1322 
1323 /// Create Printable object to print virtual registers and physical
1324 /// registers on a \ref raw_ostream.
1325 Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1326 
1327 /// Create Printable object to print register classes or register banks
1328 /// on a \ref raw_ostream.
1329 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
1330  const TargetRegisterInfo *TRI);
1331 
1332 } // end namespace llvm
1333 
1334 #endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
llvm::TargetRegisterInfo::trackLivenessAfterRegAlloc
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
Definition: TargetRegisterInfo.h:956
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::TargetRegisterInfo::getRegAsmName
virtual StringRef getRegAsmName(MCRegister Reg) const
Return the assembly name for Reg.
Definition: TargetRegisterInfo.h:1043
i
i
Definition: README.txt:29
llvm::TargetRegisterInfoDesc::InAllocatableClass
const bool * InAllocatableClass
Definition: TargetRegisterInfo.h:221
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:637
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:809
llvm::TargetRegisterInfo::getConstrainedRegClassForOperand
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
Definition: TargetRegisterInfo.h:1126
llvm::TargetRegisterInfo::shouldRegionSplitForVirtReg
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
Definition: TargetRegisterInfo.cpp:69
llvm::TargetRegisterInfo::~TargetRegisterInfo
virtual ~TargetRegisterInfo()
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MathExtras.h
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:75
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetRegisterInfo::isFixedRegister
virtual bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a fixed register.
Definition: TargetRegisterInfo.h:583
llvm::TargetRegisterInfo::shouldUseLastChanceRecoloringForVirtReg
virtual bool shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Last chance recoloring has a high compile time cost especially for targets with a lot of registers.
Definition: TargetRegisterInfo.h:1082
llvm::SuperRegClassIterator::getSubReg
unsigned getSubReg() const
Returns the current sub-register index.
Definition: TargetRegisterInfo.h:1184
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::TargetRegisterInfo::getCrossCopyRegClass
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
Definition: TargetRegisterInfo.h:800
llvm::TargetRegisterClass::isASubClass
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
Definition: TargetRegisterInfo.h:186
llvm::TargetRegisterInfo::getIntraCallClobberedRegs
virtual ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const
Return a list of all of the registers which are clobbered "inside" a call to the given function.
Definition: TargetRegisterInfo.h:505
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:105
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
Optional.h
llvm::TargetRegisterInfo::resolveFrameIndex
virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...
Definition: TargetRegisterInfo.h:998
llvm::TargetRegisterClass::getLaneMask
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
Definition: TargetRegisterInfo.h:210
llvm::TargetRegisterInfo::isGeneralPurposeRegister
virtual bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a general purpose register.
Definition: TargetRegisterInfo.h:589
llvm::printVRegOrUnit
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Definition: TargetRegisterInfo.cpp:165
llvm::MCRegisterClass::end
iterator end() const
Definition: MCRegisterInfo.h:53
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:121
llvm::VirtReg2IndexFunctor
Definition: TargetRegisterInfo.h:1292
llvm::MCRegisterClass::getNumRegs
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
Definition: MCRegisterInfo.h:57
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
Printable.h
llvm::TargetRegisterInfo::isArgumentRegister
virtual bool isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg can be used as an argument to a function.
Definition: TargetRegisterInfo.h:577
StringRef.h
llvm::TargetRegisterInfo::dumpReg
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
Definition: TargetRegisterInfo.cpp:670
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
llvm::TargetRegisterInfo::getRegMaskNames
virtual ArrayRef< const char * > getRegMaskNames() const =0
llvm::TargetRegisterClass::GlobalPriority
const bool GlobalPriority
Definition: TargetRegisterInfo.h:62
llvm::TargetRegisterInfo::getRegisterCosts
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
Definition: TargetRegisterInfo.h:356
llvm::TargetRegisterInfo::getMinimalPhysRegClassLLT
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:230
llvm::TargetRegisterInfo::isInAllocatableClass
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition: TargetRegisterInfo.h:365
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1181
llvm::TargetRegisterInfo::isConstantPhysReg
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: TargetRegisterInfo.h:554
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:256
llvm::TargetRegisterInfo::getOffsetOpcodes
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
Definition: TargetRegisterInfo.cpp:643
llvm::TargetRegisterInfo::isAsmClobberable
virtual bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const
Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint,...
Definition: TargetRegisterInfo.h:541
llvm::TargetRegisterInfo::shouldRealignStack
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
Definition: TargetRegisterInfo.cpp:483
llvm::TargetRegisterInfo::updateRegAllocHint
virtual void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
Definition: TargetRegisterInfo.h:892
MachineBasicBlock.h
llvm::TargetRegisterInfoDesc::NumCosts
unsigned NumCosts
Definition: TargetRegisterInfo.h:219
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::TargetRegisterClass::getCopyCost
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Definition: TargetRegisterInfo.h:117
llvm::TargetRegisterInfo::markSuperRegs
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
Definition: TargetRegisterInfo.cpp:80
llvm::TargetRegisterInfo::getRegisterCostTableIndex
virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const
Return the register cost table index.
Definition: TargetRegisterInfo.h:717
llvm::TargetRegisterInfo::regclass_begin
regclass_iterator regclass_begin() const
Register class iterators.
Definition: TargetRegisterInfo.h:759
llvm::TargetRegisterInfo::requiresFrameIndexScavenging
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
Definition: TargetRegisterInfo.h:927
llvm::Optional< std::string >
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::TargetRegisterInfo::getCSRFirstUseCost
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time.
Definition: TargetRegisterInfo.h:911
llvm::TargetRegisterInfo::isCalleeSavedPhysReg
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
Definition: TargetRegisterInfo.cpp:465
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2558
llvm::TargetRegisterInfo::getRegPressureSetLimit
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
llvm::TargetRegisterInfo::RegClassInfo
Definition: TargetRegisterInfo.h:241
llvm::TargetRegisterInfo::getRegClassInfo
const RegClassInfo & getRegClassInfo(const TargetRegisterClass &RC) const
Definition: TargetRegisterInfo.h:753
RegisterSet
SmallSet< unsigned, 4 > RegisterSet
Definition: Thumb2ITBlockPass.cpp:39
llvm::TargetRegisterInfo::useFPForScavengingIndex
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
Definition: TargetRegisterInfo.h:921
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::TargetRegisterClass::SubClassMask
const uint32_t * SubClassMask
Definition: TargetRegisterInfo.h:54
llvm::MCRegisterInfo::getNumSubRegIndices
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
Definition: MCRegisterInfo.h:498
llvm::TargetRegisterClass::getSubClassMask
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
Definition: TargetRegisterInfo.h:162
llvm::TargetRegisterInfo::legalclasstypes_end
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
Definition: TargetRegisterInfo.h:323
llvm::BitMaskClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1279
llvm::MCRegisterClass::getCopyCost
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
Definition: MCRegisterInfo.h:91
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
llvm::MCRegisterInfo::regsOverlap
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
Definition: MCRegisterInfo.cpp:126
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:33
llvm::TargetRegisterInfo::getCalleeSavedRegs
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetRegisterInfo::RegClassInfo::RegSize
unsigned RegSize
Definition: TargetRegisterInfo.h:242
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::SuperRegClassIterator::SuperRegClassIterator
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
Definition: TargetRegisterInfo.h:1171
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:97
llvm::TargetRegisterInfo::getRegUnitWeight
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:479
llvm::TargetRegisterInfoDesc::CostPerUse
const uint8_t * CostPerUse
Definition: TargetRegisterInfo.h:218
llvm::TargetRegisterInfo::getRegUnitPressureSets
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:381
llvm::TargetRegisterClass::SuperRegIndices
const uint16_t * SuperRegIndices
Definition: TargetRegisterInfo.h:55
llvm::TargetRegisterClass::CoveredBySubRegs
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
Definition: TargetRegisterInfo.h:70
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:203
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const
Return true if the given TargetRegisterClass is compatible with LLT T.
Definition: TargetRegisterInfo.h:305
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetRegisterInfo::hasRegUnit
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
Definition: TargetRegisterInfo.h:431
llvm::TargetRegisterInfo::isNonallocatableRegisterCalleeSave
virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const
Some targets have non-allocatable registers that aren't technically part of the explicit callee saved...
Definition: TargetRegisterInfo.h:1141
llvm::TargetRegisterInfo::getRegClassPressureSets
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
b
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Definition: README.txt:418
llvm::TargetRegisterClass::AllocationPriority
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
Definition: TargetRegisterInfo.h:59
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::TargetRegisterInfo::composeSubRegIndicesImpl
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
Definition: TargetRegisterInfo.h:699
llvm::MCRegisterClass::getRegister
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
Definition: MCRegisterInfo.h:61
llvm::TargetRegisterInfo::requiresVirtualBaseRegisters
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
Definition: TargetRegisterInfo.h:940
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:142
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:303
llvm::BitVector
Definition: BitVector.h:75
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::TargetRegisterClass::hasSuperClass
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:137
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
llvm::TargetRegisterClass::OrderFunc
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &)
Definition: TargetRegisterInfo.h:72
llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Definition: TargetRegisterInfo.h:709
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1162
llvm::TargetRegisterInfo::isCallerPreservedPhysReg
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
Definition: TargetRegisterInfo.h:566
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:142
llvm::MCRegisterClass::begin
iterator begin() const
begin/end - Return all of the registers in this class.
Definition: MCRegisterInfo.h:52
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:791
llvm::TargetRegisterInfo::regclasses
iterator_range< regclass_iterator > regclasses() const
Definition: TargetRegisterInfo.h:761
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:492
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:292
llvm::RegClassWeight
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
Definition: TargetRegisterInfo.h:226
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:286
llvm::TargetRegisterClass::LaneMask
const LaneBitmask LaneMask
Definition: TargetRegisterInfo.h:56
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:422
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:771
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::TargetRegisterInfo::saveScavengerRegister
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
Definition: TargetRegisterInfo.h:1023
llvm::VirtReg2IndexFunctor::operator()
unsigned operator()(Register Reg) const
Definition: TargetRegisterInfo.h:1294
llvm::TargetRegisterClass::TSFlags
const uint8_t TSFlags
Configurable target specific flags.
Definition: TargetRegisterInfo.h:65
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:777
llvm::TargetRegisterInfo::getCommonSuperRegClass
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
Definition: TargetRegisterInfo.cpp:319
llvm::SuperRegClassIterator::operator++
void operator++()
Advance iterator to the next entry.
Definition: TargetRegisterInfo.h:1192
llvm::TargetRegisterClass::SuperClasses
const sc_iterator SuperClasses
Definition: TargetRegisterInfo.h:71
llvm::TargetRegisterInfo::getFrameRegister
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:601
llvm::TargetRegisterClass::HasDisjunctSubRegs
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
Definition: TargetRegisterInfo.h:67
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetRegisterInfo::getNumRegPressureSets
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:422
llvm::TargetRegisterInfo::eliminateFrameIndex
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
llvm::TargetRegisterInfo::reverseLocalAssignment
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
Definition: TargetRegisterInfo.h:906
MCRegisterInfo.h
llvm::TargetRegisterInfo::regclass_end
regclass_iterator regclass_end() const
Definition: TargetRegisterInfo.h:760
llvm::TargetRegisterInfo::regClassPriorityTrumpsGlobalness
virtual bool regClassPriorityTrumpsGlobalness(const MachineFunction &MF) const
When prioritizing live ranges in register allocation, if this hook returns true then the AllocationPr...
Definition: TargetRegisterInfo.h:1106
ArrayRef.h
llvm::TargetRegisterInfo::getRegPressureSetName
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetRegisterInfo::composeSubRegIndexLaneMaskImpl
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
Definition: TargetRegisterInfo.h:705
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:289
iterator_range.h
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::Register::asMCReg
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
Definition: Register.h:120
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::TargetRegisterInfo::needsFrameBaseReg
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction's frame index reference would be better served by a base register oth...
Definition: TargetRegisterInfo.h:983
llvm::RegClassWeight::RegWeight
unsigned RegWeight
Definition: TargetRegisterInfo.h:227
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:175
llvm::TargetRegisterInfo::TargetRegisterInfo
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0)
Definition: TargetRegisterInfo.cpp:53
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::BitMaskClassIterator::BitMaskClassIterator
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask.
Definition: TargetRegisterInfo.h:1272
llvm::TargetRegisterInfo::shouldCoalesce
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
Definition: TargetRegisterInfo.h:1057
RegInfo
Definition: AMDGPUAsmParser.cpp:2561
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:153
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:663
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::TargetRegisterInfo::getCoveringSubRegIndexes
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
Definition: TargetRegisterInfo.cpp:524
llvm::MCRegisterClass::getID
unsigned getID() const
getID() - Return the register class ID number.
Definition: MCRegisterInfo.h:48
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:297
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::RegClassWeight::WeightLimit
unsigned WeightLimit
Definition: TargetRegisterInfo.h:228
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCRegisterInfo::getRegClassName
const char * getRegClassName(const MCRegisterClass *Class) const
Definition: MCRegisterInfo.h:548
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetRegisterInfo::isInlineAsmReadOnlyReg
virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) const
Returns true if PhysReg cannot be written to in inline asm statements.
Definition: TargetRegisterInfo.h:547
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetRegisterInfo::lookThruSingleUseCopyChain
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
Definition: TargetRegisterInfo.cpp:618
llvm::BitMaskClassIterator::operator++
void operator++()
Advance iterator to the next entry.
Definition: TargetRegisterInfo.h:1285
llvm::TargetRegisterInfo::shouldRewriteCopySrc
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Definition: TargetRegisterInfo.cpp:413
llvm::TargetRegisterClass::getNumRegs
unsigned getNumRegs() const
Return the number of registers in this class.
Definition: TargetRegisterInfo.h:83
llvm::TargetRegisterInfo::shouldUseDeferredSpillingForVirtReg
virtual bool shouldUseDeferredSpillingForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Deferred spilling delays the spill insertion of a virtual register after every other allocation.
Definition: TargetRegisterInfo.h:1097
llvm::TargetRegisterClass::begin
iterator begin() const
begin/end - Return all of the registers in this class.
Definition: TargetRegisterInfo.h:79
llvm::TargetRegisterInfo::lookThruCopyLike
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Definition: TargetRegisterInfo.cpp:596
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:280
uint16_t
llvm::TargetRegisterClass::getRegister
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
Definition: TargetRegisterInfo.h:91
llvm::TargetRegisterClass::getSuperClasses
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
Definition: TargetRegisterInfo.h:180
llvm::TargetRegisterInfo::getCustomEHPadPreservedMask
virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...
Definition: TargetRegisterInfo.h:492
llvm::TargetRegisterInfo::isDivergentRegClass
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
Definition: TargetRegisterInfo.h:557
llvm::TargetRegisterInfo::composeSubRegIndexLaneMask
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
Definition: TargetRegisterInfo.h:672
llvm::TargetRegisterClass::getSuperRegIndices
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
Definition: TargetRegisterInfo.h:173
llvm::TargetRegisterInfo::getFrameIndexInstrOffset
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
Definition: TargetRegisterInfo.h:974
llvm::TargetRegisterInfo::getRegPressureSetScore
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
Definition: TargetRegisterInfo.h:831
llvm::TargetRegisterClass::sc_iterator
const TargetRegisterClass *const * sc_iterator
Definition: TargetRegisterInfo.h:50
llvm::TargetRegisterInfo::explainReservedReg
virtual llvm::Optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const
Returns either a string explaining why the given register is reserved for this function,...
Definition: TargetRegisterInfo.h:535
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::TargetRegisterInfo::RegClassInfo::VTList
vt_iterator VTList
Definition: TargetRegisterInfo.h:243
llvm::TargetRegisterClass::contains
bool contains(Register Reg1, Register Reg2) const
Return true if both registers are in this class.
Definition: TargetRegisterInfo.h:106
llvm::TargetRegisterClass::MC
const MCRegisterClass * MC
Definition: TargetRegisterInfo.h:53
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:765
llvm::TargetRegisterInfo::getNoPreservedMask
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
Definition: TargetRegisterInfo.h:497
llvm::TargetRegisterInfo::regclass_iterator
const TargetRegisterClass *const * regclass_iterator
Definition: TargetRegisterInfo.h:239
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::TargetRegisterInfo::hasStackRealignment
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
Definition: TargetRegisterInfo.h:968
llvm::TargetRegisterInfo::materializeFrameBaseRegister
virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for a pointer to FrameIdx before insertion point I.
Definition: TargetRegisterInfo.h:989
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:680
llvm::TargetRegisterClass::hasSubClass
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:125
llvm::TargetRegisterInfo::getSubRegisterClass
virtual const TargetRegisterClass * getSubRegisterClass(const TargetRegisterClass *SuperRC, unsigned SubRegIdx) const
Return a register class that can be used for a subregister copy from/into SuperRC at SubRegIdx.
Definition: TargetRegisterInfo.h:645
llvm::TargetRegisterInfo::requiresRegisterScavenging
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger.
Definition: TargetRegisterInfo.h:915
SmallVector.h
llvm::TargetRegisterInfo::getCoveringLanes
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
Definition: TargetRegisterInfo.h:418
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::SuperRegClassIterator::getMask
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
Definition: TargetRegisterInfo.h:1189
llvm::TargetRegisterInfo::getRegClassWeight
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
LaneBitmask.h
llvm::TargetRegisterInfoDesc
Extra information, not in MCRegisterDesc, about registers.
Definition: TargetRegisterInfo.h:217
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:195
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::TargetRegisterInfo::RegClassInfo::SpillSize
unsigned SpillSize
Definition: TargetRegisterInfo.h:242
llvm::MVT::Untyped
@ Untyped
Definition: MachineValueType.h:276
llvm::SmallVectorImpl< unsigned >
llvm::MCRegisterClass::isAllocatable
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
Definition: MCRegisterInfo.h:95
llvm::BitMaskClassIterator
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
Definition: TargetRegisterInfo.h:1208
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1134
llvm::TargetRegisterInfo::checkAllSuperRegsMarked
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
Definition: TargetRegisterInfo.cpp:86
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:130
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::TargetRegisterInfo::isFrameOffsetLegal
virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index.
Definition: TargetRegisterInfo.h:1005
llvm::TargetRegisterInfo::adjustStackMapLiveOutMask
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
Definition: TargetRegisterInfo.h:597
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:371
llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMask
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
Definition: TargetRegisterInfo.h:686
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::TargetRegisterInfo::RegClassInfo::SpillAlignment
unsigned SpillAlignment
Definition: TargetRegisterInfo.h:242
llvm::TargetRegisterInfo::hasReservedSpillSlot
virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
Definition: TargetRegisterInfo.h:950
llvm::TargetRegisterClass::end
iterator end() const
Definition: TargetRegisterInfo.h:80
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:483
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:86
llvm::BitMaskClassIterator::getID
unsigned getID() const
Returns the current register class ID.
Definition: TargetRegisterInfo.h:1282
llvm::TargetRegisterInfo::prependOffsetExpression
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
Definition: TargetRegisterInfo.cpp:650
llvm::TargetRegisterInfo::getRegMasks
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
llvm::TargetRegisterInfo::getRegPressureLimit
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
Definition: TargetRegisterInfo.h:822
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::TargetRegisterInfo::legalclasstypes_begin
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
Definition: TargetRegisterInfo.h:319
llvm::TargetRegisterInfo::requiresFrameIndexReplacementScavenging
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
Definition: TargetRegisterInfo.h:933
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40
llvm::LLT
Definition: LowLevelTypeImpl.h:39