LLVM  13.0.0git
TargetRegisterInfo.h
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1 //==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes an abstract interface used to get information about a
10 // target machines register file. This information is used for a variety of
11 // purposed, especially register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16 #define LLVM_CODEGEN_TARGETREGISTERINFO_H
17 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/MC/LaneBitmask.h"
25 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/Support/Printable.h"
30 #include <cassert>
31 #include <cstdint>
32 #include <functional>
33 
34 namespace llvm {
35 
36 class BitVector;
37 class DIExpression;
38 class LiveRegMatrix;
39 class MachineFunction;
40 class MachineInstr;
41 class RegScavenger;
42 class VirtRegMap;
43 class LiveIntervals;
44 class LiveInterval;
45 
47 public:
48  using iterator = const MCPhysReg *;
49  using const_iterator = const MCPhysReg *;
50  using sc_iterator = const TargetRegisterClass* const *;
51 
52  // Instance variables filled by tablegen, do not use!
57  /// Classes with a higher priority value are assigned first by register
58  /// allocators using a greedy heuristic. The value is in the range [0,63].
59  const uint8_t AllocationPriority;
60  /// Whether the class supports two (or more) disjunct subregister indices.
61  const bool HasDisjunctSubRegs;
62  /// Whether a combination of subregisters can cover every register in the
63  /// class. See also the CoveredBySubRegs description in Target.td.
64  const bool CoveredBySubRegs;
67 
68  /// Return the register class ID number.
69  unsigned getID() const { return MC->getID(); }
70 
71  /// begin/end - Return all of the registers in this class.
72  ///
73  iterator begin() const { return MC->begin(); }
74  iterator end() const { return MC->end(); }
75 
76  /// Return the number of registers in this class.
77  unsigned getNumRegs() const { return MC->getNumRegs(); }
78 
80  getRegisters() const {
81  return make_range(MC->begin(), MC->end());
82  }
83 
84  /// Return the specified register in the class.
85  MCRegister getRegister(unsigned i) const {
86  return MC->getRegister(i);
87  }
88 
89  /// Return true if the specified register is included in this register class.
90  /// This does not include virtual registers.
91  bool contains(Register Reg) const {
92  /// FIXME: Historically this function has returned false when given vregs
93  /// but it should probably only receive physical registers
94  if (!Reg.isPhysical())
95  return false;
96  return MC->contains(Reg.asMCReg());
97  }
98 
99  /// Return true if both registers are in this class.
100  bool contains(Register Reg1, Register Reg2) const {
101  /// FIXME: Historically this function has returned false when given a vregs
102  /// but it should probably only receive physical registers
103  if (!Reg1.isPhysical() || !Reg2.isPhysical())
104  return false;
105  return MC->contains(Reg1.asMCReg(), Reg2.asMCReg());
106  }
107 
108  /// Return the cost of copying a value between two registers in this class.
109  /// A negative number means the register class is very expensive
110  /// to copy e.g. status flag register classes.
111  int getCopyCost() const { return MC->getCopyCost(); }
112 
113  /// Return true if this register class may be used to create virtual
114  /// registers.
115  bool isAllocatable() const { return MC->isAllocatable(); }
116 
117  /// Return true if the specified TargetRegisterClass
118  /// is a proper sub-class of this TargetRegisterClass.
119  bool hasSubClass(const TargetRegisterClass *RC) const {
120  return RC != this && hasSubClassEq(RC);
121  }
122 
123  /// Returns true if RC is a sub-class of or equal to this class.
124  bool hasSubClassEq(const TargetRegisterClass *RC) const {
125  unsigned ID = RC->getID();
126  return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
127  }
128 
129  /// Return true if the specified TargetRegisterClass is a
130  /// proper super-class of this TargetRegisterClass.
131  bool hasSuperClass(const TargetRegisterClass *RC) const {
132  return RC->hasSubClass(this);
133  }
134 
135  /// Returns true if RC is a super-class of or equal to this class.
136  bool hasSuperClassEq(const TargetRegisterClass *RC) const {
137  return RC->hasSubClassEq(this);
138  }
139 
140  /// Returns a bit vector of subclasses, including this one.
141  /// The vector is indexed by class IDs.
142  ///
143  /// To use it, consider the returned array as a chunk of memory that
144  /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
145  /// contains a bitset of the ID of the subclasses in big-endian style.
146 
147  /// I.e., the representation of the memory from left to right at the
148  /// bit level looks like:
149  /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
150  /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
151  /// Where the number represents the class ID and XXX bits that
152  /// should be ignored.
153  ///
154  /// See the implementation of hasSubClassEq for an example of how it
155  /// can be used.
156  const uint32_t *getSubClassMask() const {
157  return SubClassMask;
158  }
159 
160  /// Returns a 0-terminated list of sub-register indices that project some
161  /// super-register class into this register class. The list has an entry for
162  /// each Idx such that:
163  ///
164  /// There exists SuperRC where:
165  /// For all Reg in SuperRC:
166  /// this->contains(Reg:Idx)
167  const uint16_t *getSuperRegIndices() const {
168  return SuperRegIndices;
169  }
170 
171  /// Returns a NULL-terminated list of super-classes. The
172  /// classes are ordered by ID which is also a topological ordering from large
173  /// to small classes. The list does NOT include the current class.
175  return SuperClasses;
176  }
177 
178  /// Return true if this TargetRegisterClass is a subset
179  /// class of at least one other TargetRegisterClass.
180  bool isASubClass() const {
181  return SuperClasses[0] != nullptr;
182  }
183 
184  /// Returns the preferred order for allocating registers from this register
185  /// class in MF. The raw order comes directly from the .td file and may
186  /// include reserved registers that are not allocatable.
187  /// Register allocators should also make sure to allocate
188  /// callee-saved registers only after all the volatiles are used. The
189  /// RegisterClassInfo class provides filtered allocation orders with
190  /// callee-saved registers moved to the end.
191  ///
192  /// The MachineFunction argument can be used to tune the allocatable
193  /// registers based on the characteristics of the function, subtarget, or
194  /// other criteria.
195  ///
196  /// By default, this method returns all registers in the class.
198  return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
199  }
200 
201  /// Returns the combination of all lane masks of register in this class.
202  /// The lane masks of the registers are the combination of all lane masks
203  /// of their subregisters. Returns 1 if there are no subregisters.
205  return LaneMask;
206  }
207 };
208 
209 /// Extra information, not in MCRegisterDesc, about registers.
210 /// These are used by codegen, not by MC.
212  const uint8_t *CostPerUse; // Extra cost of instructions using register.
213  unsigned NumCosts; // Number of cost values associated with each register.
214  const bool
215  *InAllocatableClass; // Register belongs to an allocatable regclass.
216 };
217 
218 /// Each TargetRegisterClass has a per register weight, and weight
219 /// limit which must be less than the limits of its pressure sets.
221  unsigned RegWeight;
222  unsigned WeightLimit;
223 };
224 
225 /// TargetRegisterInfo base class - We assume that the target defines a static
226 /// array of TargetRegisterDesc objects that represent all of the machine
227 /// registers that the target has. As such, we simply have to track a pointer
228 /// to this array so that we can turn register number into a register
229 /// descriptor.
230 ///
232 public:
233  using regclass_iterator = const TargetRegisterClass * const *;
235  struct RegClassInfo {
238  };
239 private:
240  const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
241  const char *const *SubRegIndexNames; // Names of subreg indexes.
242  // Pointer to array of lane masks, one per sub-reg index.
243  const LaneBitmask *SubRegIndexLaneMasks;
244 
245  regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
246  LaneBitmask CoveringLanes;
247  const RegClassInfo *const RCInfos;
248  unsigned HwMode;
249 
250 protected:
252  regclass_iterator RCB,
253  regclass_iterator RCE,
254  const char *const *SRINames,
255  const LaneBitmask *SRILaneMasks,
256  LaneBitmask CoveringLanes,
257  const RegClassInfo *const RCIs,
258  unsigned Mode = 0);
259  virtual ~TargetRegisterInfo();
260 
261 public:
262  // Register numbers can represent physical registers, virtual registers, and
263  // sometimes stack slots. The unsigned values are divided into these ranges:
264  //
265  // 0 Not a register, can be used as a sentinel.
266  // [1;2^30) Physical registers assigned by TableGen.
267  // [2^30;2^31) Stack slots. (Rarely used.)
268  // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
269  //
270  // Further sentinels can be allocated from the small negative integers.
271  // DenseMapInfo<unsigned> uses -1u and -2u.
272 
273  /// Return the size in bits of a register from class RC.
274  unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
275  return getRegClassInfo(RC).RegSize;
276  }
277 
278  /// Return the size in bytes of the stack slot allocated to hold a spilled
279  /// copy of a register from class RC.
280  unsigned getSpillSize(const TargetRegisterClass &RC) const {
281  return getRegClassInfo(RC).SpillSize / 8;
282  }
283 
284  /// Return the minimum required alignment in bytes for a spill slot for
285  /// a register of this class.
286  unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
287  return getRegClassInfo(RC).SpillAlignment / 8;
288  }
289 
290  /// Return the minimum required alignment in bytes for a spill slot for
291  /// a register of this class.
293  return Align(getRegClassInfo(RC).SpillAlignment / 8);
294  }
295 
296  /// Return true if the given TargetRegisterClass has the ValueType T.
297  bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
298  for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
299  if (MVT(*I) == T)
300  return true;
301  return false;
302  }
303 
304  /// Return true if the given TargetRegisterClass is compatible with LLT T.
305  bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const {
306  for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) {
307  MVT VT(*I);
308  if (VT == MVT::Untyped)
309  return true;
310 
311  if (LLT(VT) == T)
312  return true;
313  }
314  return false;
315  }
316 
317  /// Loop over all of the value types that can be represented by values
318  /// in the given register class.
320  return getRegClassInfo(RC).VTList;
321  }
322 
325  while (*I != MVT::Other)
326  ++I;
327  return I;
328  }
329 
330  /// Returns the Register Class of a physical register of the given type,
331  /// picking the most sub register class of the right type that contains this
332  /// physreg.
334  MVT VT = MVT::Other) const;
335 
336  /// Returns the Register Class of a physical register of the given type,
337  /// picking the most sub register class of the right type that contains this
338  /// physreg. If there is no register class compatible with the given type,
339  /// returns nullptr.
341  LLT Ty = LLT()) const;
342 
343  /// Return the maximal subclass of the given register class that is
344  /// allocatable or NULL.
345  const TargetRegisterClass *
346  getAllocatableClass(const TargetRegisterClass *RC) const;
347 
348  /// Returns a bitset indexed by register number indicating if a register is
349  /// allocatable or not. If a register class is specified, returns the subset
350  /// for the class.
352  const TargetRegisterClass *RC = nullptr) const;
353 
354  /// Get a list of cost values for all registers that correspond to the index
355  /// returned by RegisterCostTableIndex.
357  unsigned Idx = getRegisterCostTableIndex(MF);
358  unsigned NumRegs = getNumRegs();
359  assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds");
360 
361  return makeArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
362  }
363 
364  /// Return true if the register is in the allocation of any register class.
365  bool isInAllocatableClass(MCRegister RegNo) const {
366  return InfoDesc->InAllocatableClass[RegNo];
367  }
368 
369  /// Return the human-readable symbolic target-specific
370  /// name for the specified SubRegIndex.
371  const char *getSubRegIndexName(unsigned SubIdx) const {
372  assert(SubIdx && SubIdx < getNumSubRegIndices() &&
373  "This is not a subregister index");
374  return SubRegIndexNames[SubIdx-1];
375  }
376 
377  /// Return a bitmask representing the parts of a register that are covered by
378  /// SubIdx \see LaneBitmask.
379  ///
380  /// SubIdx == 0 is allowed, it has the lane mask ~0u.
381  LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
382  assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
383  return SubRegIndexLaneMasks[SubIdx];
384  }
385 
386  /// Try to find one or more subregister indexes to cover \p LaneMask.
387  ///
388  /// If this is possible, returns true and appends the best matching set of
389  /// indexes to \p Indexes. If this is not possible, returns false.
391  const TargetRegisterClass *RC,
392  LaneBitmask LaneMask,
393  SmallVectorImpl<unsigned> &Indexes) const;
394 
395  /// The lane masks returned by getSubRegIndexLaneMask() above can only be
396  /// used to determine if sub-registers overlap - they can't be used to
397  /// determine if a set of sub-registers completely cover another
398  /// sub-register.
399  ///
400  /// The X86 general purpose registers have two lanes corresponding to the
401  /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
402  /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
403  /// sub_32bit sub-register.
404  ///
405  /// On the other hand, the ARM NEON lanes fully cover their registers: The
406  /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
407  /// This is related to the CoveredBySubRegs property on register definitions.
408  ///
409  /// This function returns a bit mask of lanes that completely cover their
410  /// sub-registers. More precisely, given:
411  ///
412  /// Covering = getCoveringLanes();
413  /// MaskA = getSubRegIndexLaneMask(SubA);
414  /// MaskB = getSubRegIndexLaneMask(SubB);
415  ///
416  /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
417  /// SubB.
418  LaneBitmask getCoveringLanes() const { return CoveringLanes; }
419 
420  /// Returns true if the two registers are equal or alias each other.
421  /// The registers may be virtual registers.
422  bool regsOverlap(Register regA, Register regB) const {
423  if (regA == regB) return true;
424  if (!regA.isPhysical() || !regB.isPhysical())
425  return false;
426 
427  // Regunits are numerically ordered. Find a common unit.
428  MCRegUnitIterator RUA(regA.asMCReg(), this);
429  MCRegUnitIterator RUB(regB.asMCReg(), this);
430  do {
431  if (*RUA == *RUB) return true;
432  if (*RUA < *RUB) ++RUA;
433  else ++RUB;
434  } while (RUA.isValid() && RUB.isValid());
435  return false;
436  }
437 
438  /// Returns true if Reg contains RegUnit.
439  bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
440  for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
441  if (Register(*Units) == RegUnit)
442  return true;
443  return false;
444  }
445 
446  /// Returns the original SrcReg unless it is the target of a copy-like
447  /// operation, in which case we chain backwards through all such operations
448  /// to the ultimate source register. If a physical register is encountered,
449  /// we stop the search.
450  virtual Register lookThruCopyLike(Register SrcReg,
451  const MachineRegisterInfo *MRI) const;
452 
453  /// Find the original SrcReg unless it is the target of a copy-like operation,
454  /// in which case we chain backwards through all such operations to the
455  /// ultimate source register. If a physical register is encountered, we stop
456  /// the search.
457  /// Return the original SrcReg if all the definitions in the chain only have
458  /// one user and not a physical register.
459  virtual Register
461  const MachineRegisterInfo *MRI) const;
462 
463  /// Return a null-terminated list of all of the callee-saved registers on
464  /// this target. The register should be in the order of desired callee-save
465  /// stack frame offset. The first register is closest to the incoming stack
466  /// pointer if stack grows down, and vice versa.
467  /// Notice: This function does not take into account disabled CSRs.
468  /// In most cases you will want to use instead the function
469  /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
470  virtual const MCPhysReg*
471  getCalleeSavedRegs(const MachineFunction *MF) const = 0;
472 
473  /// Return a mask of call-preserved registers for the given calling convention
474  /// on the current function. The mask should include all call-preserved
475  /// aliases. This is used by the register allocator to determine which
476  /// registers can be live across a call.
477  ///
478  /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
479  /// A set bit indicates that all bits of the corresponding register are
480  /// preserved across the function call. The bit mask is expected to be
481  /// sub-register complete, i.e. if A is preserved, so are all its
482  /// sub-registers.
483  ///
484  /// Bits are numbered from the LSB, so the bit for physical register Reg can
485  /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
486  ///
487  /// A NULL pointer means that no register mask will be used, and call
488  /// instructions should use implicit-def operands to indicate call clobbered
489  /// registers.
490  ///
492  CallingConv::ID) const {
493  // The default mask clobbers everything. All targets should override.
494  return nullptr;
495  }
496 
497  /// Return a register mask for the registers preserved by the unwinder,
498  /// or nullptr if no custom mask is needed.
499  virtual const uint32_t *
501  return nullptr;
502  }
503 
504  /// Return a register mask that clobbers everything.
505  virtual const uint32_t *getNoPreservedMask() const {
506  llvm_unreachable("target does not provide no preserved mask");
507  }
508 
509  /// Return a list of all of the registers which are clobbered "inside" a call
510  /// to the given function. For example, these might be needed for PLT
511  /// sequences of long-branch veneers.
512  virtual ArrayRef<MCPhysReg>
514  return {};
515  }
516 
517  /// Return true if all bits that are set in mask \p mask0 are also set in
518  /// \p mask1.
519  bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
520 
521  /// Return all the call-preserved register masks defined for this target.
522  virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
523  virtual ArrayRef<const char *> getRegMaskNames() const = 0;
524 
525  /// Returns a bitset indexed by physical register number indicating if a
526  /// register is a special register that has particular uses and should be
527  /// considered unavailable at all times, e.g. stack pointer, return address.
528  /// A reserved register:
529  /// - is not allocatable
530  /// - is considered always live
531  /// - is ignored by liveness tracking
532  /// It is often necessary to reserve the super registers of a reserved
533  /// register as well, to avoid them getting allocated indirectly. You may use
534  /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
535  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
536 
537  /// Returns false if we can't guarantee that Physreg, specified as an IR asm
538  /// clobber constraint, will be preserved across the statement.
539  virtual bool isAsmClobberable(const MachineFunction &MF,
540  MCRegister PhysReg) const {
541  return true;
542  }
543 
544  /// Returns true if PhysReg cannot be written to in inline asm statements.
545  virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF,
546  unsigned PhysReg) const {
547  return false;
548  }
549 
550  /// Returns true if PhysReg is unallocatable and constant throughout the
551  /// function. Used by MachineRegisterInfo::isConstantPhysReg().
552  virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }
553 
554  /// Returns true if the register class is considered divergent.
555  virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
556  return false;
557  }
558 
559  /// Physical registers that may be modified within a function but are
560  /// guaranteed to be restored before any uses. This is useful for targets that
561  /// have call sequences where a GOT register may be updated by the caller
562  /// prior to a call and is guaranteed to be restored (also by the caller)
563  /// after the call.
564  virtual bool isCallerPreservedPhysReg(MCRegister PhysReg,
565  const MachineFunction &MF) const {
566  return false;
567  }
568 
569  /// This is a wrapper around getCallPreservedMask().
570  /// Return true if the register is preserved after the call.
571  virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
572  const MachineFunction &MF) const;
573 
574  /// Prior to adding the live-out mask to a stackmap or patchpoint
575  /// instruction, provide the target the opportunity to adjust it (mainly to
576  /// remove pseudo-registers that should be ignored).
577  virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
578 
579  /// Return a super-register of the specified register
580  /// Reg so its sub-register of index SubIdx is Reg.
582  const TargetRegisterClass *RC) const {
583  return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
584  }
585 
586  /// Return a subclass of the specified register
587  /// class A so that each register in it has a sub-register of the
588  /// specified sub-register index which is in the specified register class B.
589  ///
590  /// TableGen will synthesize missing A sub-classes.
591  virtual const TargetRegisterClass *
593  const TargetRegisterClass *B, unsigned Idx) const;
594 
595  // For a copy-like instruction that defines a register of class DefRC with
596  // subreg index DefSubReg, reading from another source with class SrcRC and
597  // subregister SrcSubReg return true if this is a preferable copy
598  // instruction or an earlier use should be used.
599  virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
600  unsigned DefSubReg,
601  const TargetRegisterClass *SrcRC,
602  unsigned SrcSubReg) const;
603 
604  /// Returns the largest legal sub-class of RC that
605  /// supports the sub-register index Idx.
606  /// If no such sub-class exists, return NULL.
607  /// If all registers in RC already have an Idx sub-register, return RC.
608  ///
609  /// TableGen generates a version of this function that is good enough in most
610  /// cases. Targets can override if they have constraints that TableGen
611  /// doesn't understand. For example, the x86 sub_8bit sub-register index is
612  /// supported by the full GR32 register class in 64-bit mode, but only by the
613  /// GR32_ABCD regiister class in 32-bit mode.
614  ///
615  /// TableGen will synthesize missing RC sub-classes.
616  virtual const TargetRegisterClass *
617  getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
618  assert(Idx == 0 && "Target has no sub-registers");
619  return RC;
620  }
621 
622  /// Return the subregister index you get from composing
623  /// two subregister indices.
624  ///
625  /// The special null sub-register index composes as the identity.
626  ///
627  /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
628  /// returns c. Note that composeSubRegIndices does not tell you about illegal
629  /// compositions. If R does not have a subreg a, or R:a does not have a subreg
630  /// b, composeSubRegIndices doesn't tell you.
631  ///
632  /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
633  /// ssub_0:S0 - ssub_3:S3 subregs.
634  /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
635  unsigned composeSubRegIndices(unsigned a, unsigned b) const {
636  if (!a) return b;
637  if (!b) return a;
638  return composeSubRegIndicesImpl(a, b);
639  }
640 
641  /// Transforms a LaneMask computed for one subregister to the lanemask that
642  /// would have been computed when composing the subsubregisters with IdxA
643  /// first. @sa composeSubRegIndices()
645  LaneBitmask Mask) const {
646  if (!IdxA)
647  return Mask;
648  return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
649  }
650 
651  /// Transform a lanemask given for a virtual register to the corresponding
652  /// lanemask before using subregister with index \p IdxA.
653  /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
654  /// valie lane mask (no invalid bits set) the following holds:
655  /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
656  /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
657  /// => X1 == Mask
659  LaneBitmask LaneMask) const {
660  if (!IdxA)
661  return LaneMask;
662  return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
663  }
664 
665  /// Debugging helper: dump register in human readable form to dbgs() stream.
666  static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
667  const TargetRegisterInfo *TRI = nullptr);
668 
669 protected:
670  /// Overridden by TableGen in targets that have sub-registers.
671  virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
672  llvm_unreachable("Target has no sub-registers");
673  }
674 
675  /// Overridden by TableGen in targets that have sub-registers.
676  virtual LaneBitmask
678  llvm_unreachable("Target has no sub-registers");
679  }
680 
682  LaneBitmask) const {
683  llvm_unreachable("Target has no sub-registers");
684  }
685 
686  /// Return the register cost table index. This implementation is sufficient
687  /// for most architectures and can be overriden by targets in case there are
688  /// multiple cost values associated with each register.
689  virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const {
690  return 0;
691  }
692 
693 public:
694  /// Find a common super-register class if it exists.
695  ///
696  /// Find a register class, SuperRC and two sub-register indices, PreA and
697  /// PreB, such that:
698  ///
699  /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
700  ///
701  /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
702  ///
703  /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
704  ///
705  /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
706  /// requirements, and there is no register class with a smaller spill size
707  /// that satisfies the requirements.
708  ///
709  /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
710  ///
711  /// Either of the PreA and PreB sub-register indices may be returned as 0. In
712  /// that case, the returned register class will be a sub-class of the
713  /// corresponding argument register class.
714  ///
715  /// The function returns NULL if no register class can be found.
716  const TargetRegisterClass*
717  getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
718  const TargetRegisterClass *RCB, unsigned SubB,
719  unsigned &PreA, unsigned &PreB) const;
720 
721  //===--------------------------------------------------------------------===//
722  // Register Class Information
723  //
724 protected:
726  return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
727  }
728 
729 public:
730  /// Register class iterators
731  regclass_iterator regclass_begin() const { return RegClassBegin; }
732  regclass_iterator regclass_end() const { return RegClassEnd; }
735  }
736 
737  unsigned getNumRegClasses() const {
738  return (unsigned)(regclass_end()-regclass_begin());
739  }
740 
741  /// Returns the register class associated with the enumeration value.
742  /// See class MCOperandInfo.
743  const TargetRegisterClass *getRegClass(unsigned i) const {
744  assert(i < getNumRegClasses() && "Register Class ID out of range");
745  return RegClassBegin[i];
746  }
747 
748  /// Returns the name of the register class.
749  const char *getRegClassName(const TargetRegisterClass *Class) const {
750  return MCRegisterInfo::getRegClassName(Class->MC);
751  }
752 
753  /// Find the largest common subclass of A and B.
754  /// Return NULL if there is no common subclass.
755  const TargetRegisterClass *
757  const TargetRegisterClass *B) const;
758 
759  /// Returns a TargetRegisterClass used for pointer values.
760  /// If a target supports multiple different pointer register classes,
761  /// kind specifies which one is indicated.
762  virtual const TargetRegisterClass *
763  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
764  llvm_unreachable("Target didn't implement getPointerRegClass!");
765  }
766 
767  /// Returns a legal register class to copy a register in the specified class
768  /// to or from. If it is possible to copy the register directly without using
769  /// a cross register class copy, return the specified RC. Returns NULL if it
770  /// is not possible to copy between two registers of the specified class.
771  virtual const TargetRegisterClass *
773  return RC;
774  }
775 
776  /// Returns the largest super class of RC that is legal to use in the current
777  /// sub-target and has the same spill size.
778  /// The returned register class can be used to create virtual registers which
779  /// means that all its registers can be copied and spilled.
780  virtual const TargetRegisterClass *
782  const MachineFunction &) const {
783  /// The default implementation is very conservative and doesn't allow the
784  /// register allocator to inflate register classes.
785  return RC;
786  }
787 
788  /// Return the register pressure "high water mark" for the specific register
789  /// class. The scheduler is in high register pressure mode (for the specific
790  /// register class) if it goes over the limit.
791  ///
792  /// Note: this is the old register pressure model that relies on a manually
793  /// specified representative register class per value type.
794  virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
795  MachineFunction &MF) const {
796  return 0;
797  }
798 
799  /// Return a heuristic for the machine scheduler to compare the profitability
800  /// of increasing one register pressure set versus another. The scheduler
801  /// will prefer increasing the register pressure of the set which returns
802  /// the largest value for this function.
803  virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
804  unsigned PSetID) const {
805  return PSetID;
806  }
807 
808  /// Get the weight in units of pressure for this register class.
809  virtual const RegClassWeight &getRegClassWeight(
810  const TargetRegisterClass *RC) const = 0;
811 
812  /// Returns size in bits of a phys/virtual/generic register.
813  unsigned getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
814 
815  /// Get the weight in units of pressure for this register unit.
816  virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
817 
818  /// Get the number of dimensions of register pressure.
819  virtual unsigned getNumRegPressureSets() const = 0;
820 
821  /// Get the name of this register unit pressure set.
822  virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
823 
824  /// Get the register unit pressure limit for this dimension.
825  /// This limit must be adjusted dynamically for reserved registers.
826  virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
827  unsigned Idx) const = 0;
828 
829  /// Get the dimensions of register pressure impacted by this register class.
830  /// Returns a -1 terminated array of pressure set IDs.
831  virtual const int *getRegClassPressureSets(
832  const TargetRegisterClass *RC) const = 0;
833 
834  /// Get the dimensions of register pressure impacted by this register unit.
835  /// Returns a -1 terminated array of pressure set IDs.
836  virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
837 
838  /// Get a list of 'hint' registers that the register allocator should try
839  /// first when allocating a physical register for the virtual register
840  /// VirtReg. These registers are effectively moved to the front of the
841  /// allocation order. If true is returned, regalloc will try to only use
842  /// hints to the greatest extent possible even if it means spilling.
843  ///
844  /// The Order argument is the allocation order for VirtReg's register class
845  /// as returned from RegisterClassInfo::getOrder(). The hint registers must
846  /// come from Order, and they must not be reserved.
847  ///
848  /// The default implementation of this function will only add target
849  /// independent register allocation hints. Targets that override this
850  /// function should typically call this default implementation as well and
851  /// expect to see generic copy hints added.
852  virtual bool
855  const MachineFunction &MF,
856  const VirtRegMap *VRM = nullptr,
857  const LiveRegMatrix *Matrix = nullptr) const;
858 
859  /// A callback to allow target a chance to update register allocation hints
860  /// when a register is "changed" (e.g. coalesced) to another register.
861  /// e.g. On ARM, some virtual registers should target register pairs,
862  /// if one of pair is coalesced to another register, the allocation hint of
863  /// the other half of the pair should be changed to point to the new register.
864  virtual void updateRegAllocHint(Register Reg, Register NewReg,
865  MachineFunction &MF) const {
866  // Do nothing.
867  }
868 
869  /// Allow the target to reverse allocation order of local live ranges. This
870  /// will generally allocate shorter local live ranges first. For targets with
871  /// many registers, this could reduce regalloc compile time by a large
872  /// factor. It is disabled by default for three reasons:
873  /// (1) Top-down allocation is simpler and easier to debug for targets that
874  /// don't benefit from reversing the order.
875  /// (2) Bottom-up allocation could result in poor evicition decisions on some
876  /// targets affecting the performance of compiled code.
877  /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
878  virtual bool reverseLocalAssignment() const { return false; }
879 
880  /// Allow the target to override the cost of using a callee-saved register for
881  /// the first time. Default value of 0 means we will use a callee-saved
882  /// register if it is available.
883  virtual unsigned getCSRFirstUseCost() const { return 0; }
884 
885  /// Returns true if the target requires (and can make use of) the register
886  /// scavenger.
887  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
888  return false;
889  }
890 
891  /// Returns true if the target wants to use frame pointer based accesses to
892  /// spill to the scavenger emergency spill slot.
893  virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
894  return true;
895  }
896 
897  /// Returns true if the target requires post PEI scavenging of registers for
898  /// materializing frame index constants.
899  virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
900  return false;
901  }
902 
903  /// Returns true if the target requires using the RegScavenger directly for
904  /// frame elimination despite using requiresFrameIndexScavenging.
906  const MachineFunction &MF) const {
907  return false;
908  }
909 
910  /// Returns true if the target wants the LocalStackAllocation pass to be run
911  /// and virtual base registers used for more efficient stack access.
912  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
913  return false;
914  }
915 
916  /// Return true if target has reserved a spill slot in the stack frame of
917  /// the given function for the specified register. e.g. On x86, if the frame
918  /// register is required, the first fixed stack object is reserved as its
919  /// spill slot. This tells PEI not to create a new stack frame
920  /// object for the given register. It should be called only after
921  /// determineCalleeSaves().
923  int &FrameIdx) const {
924  return false;
925  }
926 
927  /// Returns true if the live-ins should be tracked after register allocation.
928  virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
929  return true;
930  }
931 
932  /// True if the stack can be realigned for the target.
933  virtual bool canRealignStack(const MachineFunction &MF) const;
934 
935  /// True if storage within the function requires the stack pointer to be
936  /// aligned more than the normal calling convention calls for.
937  virtual bool shouldRealignStack(const MachineFunction &MF) const;
938 
939  /// True if stack realignment is required and still possible.
940  bool hasStackRealignment(const MachineFunction &MF) const {
941  return shouldRealignStack(MF) && canRealignStack(MF);
942  }
943 
944  /// Get the offset from the referenced frame index in the instruction,
945  /// if there is one.
946  virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
947  int Idx) const {
948  return 0;
949  }
950 
951  /// Returns true if the instruction's frame index reference would be better
952  /// served by a base register other than FP or SP.
953  /// Used by LocalStackFrameAllocation to determine which frame index
954  /// references it should create new base registers for.
955  virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
956  return false;
957  }
958 
959  /// Insert defining instruction(s) for a pointer to FrameIdx before
960  /// insertion point I. Return materialized frame pointer.
962  int FrameIdx,
963  int64_t Offset) const {
964  llvm_unreachable("materializeFrameBaseRegister does not exist on this "
965  "target");
966  }
967 
968  /// Resolve a frame index operand of an instruction
969  /// to reference the indicated base register plus offset instead.
970  virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
971  int64_t Offset) const {
972  llvm_unreachable("resolveFrameIndex does not exist on this target");
973  }
974 
975  /// Determine whether a given base register plus offset immediate is
976  /// encodable to resolve a frame index.
977  virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
978  int64_t Offset) const {
979  llvm_unreachable("isFrameOffsetLegal does not exist on this target");
980  }
981 
982  /// Gets the DWARF expression opcodes for \p Offset.
983  virtual void getOffsetOpcodes(const StackOffset &Offset,
984  SmallVectorImpl<uint64_t> &Ops) const;
985 
986  /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
987  DIExpression *
988  prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
989  const StackOffset &Offset) const;
990 
991  /// Spill the register so it can be used by the register scavenger.
992  /// Return true if the register was spilled, false otherwise.
993  /// If this function does not spill the register, the scavenger
994  /// will instead spill it to the emergency spill slot.
998  const TargetRegisterClass *RC,
999  Register Reg) const {
1000  return false;
1001  }
1002 
1003  /// This method must be overriden to eliminate abstract frame indices from
1004  /// instructions which may use them. The instruction referenced by the
1005  /// iterator contains an MO_FrameIndex operand which must be eliminated by
1006  /// this method. This method may modify or replace the specified instruction,
1007  /// as long as it keeps the iterator pointing at the finished product.
1008  /// SPAdj is the SP adjustment due to call frame setup instruction.
1009  /// FIOperandNum is the FI operand number.
1011  int SPAdj, unsigned FIOperandNum,
1012  RegScavenger *RS = nullptr) const = 0;
1013 
1014  /// Return the assembly name for \p Reg.
1016  // FIXME: We are assuming that the assembly name is equal to the TableGen
1017  // name converted to lower case
1018  //
1019  // The TableGen name is the name of the definition for this register in the
1020  // target's tablegen files. For example, the TableGen name of
1021  // def EAX : Register <...>; is "EAX"
1022  return StringRef(getName(Reg));
1023  }
1024 
1025  //===--------------------------------------------------------------------===//
1026  /// Subtarget Hooks
1027 
1028  /// SrcRC and DstRC will be morphed into NewRC if this returns true.
1030  const TargetRegisterClass *SrcRC,
1031  unsigned SubReg,
1032  const TargetRegisterClass *DstRC,
1033  unsigned DstSubReg,
1034  const TargetRegisterClass *NewRC,
1035  LiveIntervals &LIS) const
1036  { return true; }
1037 
1038  /// Region split has a high compile time cost especially for large live range.
1039  /// This method is used to decide whether or not \p VirtReg should
1040  /// go through this expensive splitting heuristic.
1041  virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF,
1042  const LiveInterval &VirtReg) const;
1043 
1044  /// Last chance recoloring has a high compile time cost especially for
1045  /// targets with a lot of registers.
1046  /// This method is used to decide whether or not \p VirtReg should
1047  /// go through this expensive heuristic.
1048  /// When this target hook is hit, by returning false, there is a high
1049  /// chance that the register allocation will fail altogether (usually with
1050  /// "ran out of registers").
1051  /// That said, this error usually points to another problem in the
1052  /// optimization pipeline.
1053  virtual bool
1055  const LiveInterval &VirtReg) const {
1056  return true;
1057  }
1058 
1059  /// Deferred spilling delays the spill insertion of a virtual register
1060  /// after every other allocation. By deferring the spilling, it is
1061  /// sometimes possible to eliminate that spilling altogether because
1062  /// something else could have been eliminated, thus leaving some space
1063  /// for the virtual register.
1064  /// However, this comes with a compile time impact because it adds one
1065  /// more stage to the greedy register allocator.
1066  /// This method is used to decide whether \p VirtReg should use the deferred
1067  /// spilling stage instead of being spilled right away.
1068  virtual bool
1070  const LiveInterval &VirtReg) const {
1071  return false;
1072  }
1073 
1074  //===--------------------------------------------------------------------===//
1075  /// Debug information queries.
1076 
1077  /// getFrameRegister - This method should return the register used as a base
1078  /// for values allocated in the current stack frame.
1079  virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
1080 
1081  /// Mark a register and all its aliases as reserved in the given set.
1083 
1084  /// Returns true if for every register in the set all super registers are part
1085  /// of the set as well.
1087  ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1088 
1089  virtual const TargetRegisterClass *
1091  const MachineRegisterInfo &MRI) const {
1092  return nullptr;
1093  }
1094 
1095  /// Returns the physical register number of sub-register "Index"
1096  /// for physical register RegNo. Return zero if the sub-register does not
1097  /// exist.
1098  inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
1099  return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx);
1100  }
1101 };
1102 
1103 //===----------------------------------------------------------------------===//
1104 // SuperRegClassIterator
1105 //===----------------------------------------------------------------------===//
1106 //
1107 // Iterate over the possible super-registers for a given register class. The
1108 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
1109 // possible classes of super-registers.
1110 //
1111 // Each bit mask will have at least one set bit, and each set bit in Mask
1112 // corresponds to a SuperRC such that:
1113 //
1114 // For all Reg in SuperRC: Reg:Idx is in RC.
1115 //
1116 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
1117 // also satisfies the above requirement, assuming Reg:0 == Reg.
1118 //
1120  const unsigned RCMaskWords;
1121  unsigned SubReg = 0;
1122  const uint16_t *Idx;
1123  const uint32_t *Mask;
1124 
1125 public:
1126  /// Create a SuperRegClassIterator that visits all the super-register classes
1127  /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1129  const TargetRegisterInfo *TRI,
1130  bool IncludeSelf = false)
1131  : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1132  Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1133  if (!IncludeSelf)
1134  ++*this;
1135  }
1136 
1137  /// Returns true if this iterator is still pointing at a valid entry.
1138  bool isValid() const { return Idx; }
1139 
1140  /// Returns the current sub-register index.
1141  unsigned getSubReg() const { return SubReg; }
1142 
1143  /// Returns the bit mask of register classes that getSubReg() projects into
1144  /// RC.
1145  /// See TargetRegisterClass::getSubClassMask() for how to use it.
1146  const uint32_t *getMask() const { return Mask; }
1147 
1148  /// Advance iterator to the next entry.
1149  void operator++() {
1150  assert(isValid() && "Cannot move iterator past end.");
1151  Mask += RCMaskWords;
1152  SubReg = *Idx++;
1153  if (!SubReg)
1154  Idx = nullptr;
1155  }
1156 };
1157 
1158 //===----------------------------------------------------------------------===//
1159 // BitMaskClassIterator
1160 //===----------------------------------------------------------------------===//
1161 /// This class encapuslates the logic to iterate over bitmask returned by
1162 /// the various RegClass related APIs.
1163 /// E.g., this class can be used to iterate over the subclasses provided by
1164 /// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1166  /// Total number of register classes.
1167  const unsigned NumRegClasses;
1168  /// Base index of CurrentChunk.
1169  /// In other words, the number of bit we read to get at the
1170  /// beginning of that chunck.
1171  unsigned Base = 0;
1172  /// Adjust base index of CurrentChunk.
1173  /// Base index + how many bit we read within CurrentChunk.
1174  unsigned Idx = 0;
1175  /// Current register class ID.
1176  unsigned ID = 0;
1177  /// Mask we are iterating over.
1178  const uint32_t *Mask;
1179  /// Current chunk of the Mask we are traversing.
1180  uint32_t CurrentChunk;
1181 
1182  /// Move ID to the next set bit.
1183  void moveToNextID() {
1184  // If the current chunk of memory is empty, move to the next one,
1185  // while making sure we do not go pass the number of register
1186  // classes.
1187  while (!CurrentChunk) {
1188  // Move to the next chunk.
1189  Base += 32;
1190  if (Base >= NumRegClasses) {
1191  ID = NumRegClasses;
1192  return;
1193  }
1194  CurrentChunk = *++Mask;
1195  Idx = Base;
1196  }
1197  // Otherwise look for the first bit set from the right
1198  // (representation of the class ID is big endian).
1199  // See getSubClassMask for more details on the representation.
1200  unsigned Offset = countTrailingZeros(CurrentChunk);
1201  // Add the Offset to the adjusted base number of this chunk: Idx.
1202  // This is the ID of the register class.
1203  ID = Idx + Offset;
1204 
1205  // Consume the zeros, if any, and the bit we just read
1206  // so that we are at the right spot for the next call.
1207  // Do not do Offset + 1 because Offset may be 31 and 32
1208  // will be UB for the shift, though in that case we could
1209  // have make the chunk being equal to 0, but that would
1210  // have introduced a if statement.
1211  moveNBits(Offset);
1212  moveNBits(1);
1213  }
1214 
1215  /// Move \p NumBits Bits forward in CurrentChunk.
1216  void moveNBits(unsigned NumBits) {
1217  assert(NumBits < 32 && "Undefined behavior spotted!");
1218  // Consume the bit we read for the next call.
1219  CurrentChunk >>= NumBits;
1220  // Adjust the base for the chunk.
1221  Idx += NumBits;
1222  }
1223 
1224 public:
1225  /// Create a BitMaskClassIterator that visits all the register classes
1226  /// represented by \p Mask.
1227  ///
1228  /// \pre \p Mask != nullptr
1230  : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1231  // Move to the first ID.
1232  moveToNextID();
1233  }
1234 
1235  /// Returns true if this iterator is still pointing at a valid entry.
1236  bool isValid() const { return getID() != NumRegClasses; }
1237 
1238  /// Returns the current register class ID.
1239  unsigned getID() const { return ID; }
1240 
1241  /// Advance iterator to the next entry.
1242  void operator++() {
1243  assert(isValid() && "Cannot move iterator past end.");
1244  moveToNextID();
1245  }
1246 };
1247 
1248 // This is useful when building IndexedMaps keyed on virtual registers
1251  unsigned operator()(Register Reg) const {
1252  return Register::virtReg2Index(Reg);
1253  }
1254 };
1255 
1256 /// Prints virtual and physical registers with or without a TRI instance.
1257 ///
1258 /// The format is:
1259 /// %noreg - NoRegister
1260 /// %5 - a virtual register.
1261 /// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1262 /// %eax - a physical register
1263 /// %physreg17 - a physical register when no TRI instance given.
1264 ///
1265 /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1266 Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
1267  unsigned SubIdx = 0,
1268  const MachineRegisterInfo *MRI = nullptr);
1269 
1270 /// Create Printable object to print register units on a \ref raw_ostream.
1271 ///
1272 /// Register units are named after their root registers:
1273 ///
1274 /// al - Single root.
1275 /// fp0~st7 - Dual roots.
1276 ///
1277 /// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1278 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1279 
1280 /// Create Printable object to print virtual registers and physical
1281 /// registers on a \ref raw_ostream.
1282 Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1283 
1284 /// Create Printable object to print register classes or register banks
1285 /// on a \ref raw_ostream.
1286 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
1287  const TargetRegisterInfo *TRI);
1288 
1289 } // end namespace llvm
1290 
1291 #endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
llvm::TargetRegisterInfo::trackLivenessAfterRegAlloc
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
Definition: TargetRegisterInfo.h:928
llvm::LaneBitmask
Definition: LaneBitmask.h:39
llvm::TargetRegisterInfo::getRegAsmName
virtual StringRef getRegAsmName(MCRegister Reg) const
Return the assembly name for Reg.
Definition: TargetRegisterInfo.h:1015
i
i
Definition: README.txt:29
llvm::TargetRegisterInfoDesc::InAllocatableClass
const bool * InAllocatableClass
Definition: TargetRegisterInfo.h:215
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:617
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:781
llvm::TargetRegisterInfo::getConstrainedRegClassForOperand
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
Definition: TargetRegisterInfo.h:1090
llvm::TargetRegisterInfo::shouldRegionSplitForVirtReg
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
Definition: TargetRegisterInfo.cpp:68
llvm::TargetRegisterInfo::~TargetRegisterInfo
virtual ~TargetRegisterInfo()
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
MathExtras.h
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:69
llvm
Definition: AllocatorList.h:23
llvm::TargetRegisterInfo::shouldUseLastChanceRecoloringForVirtReg
virtual bool shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Last chance recoloring has a high compile time cost especially for targets with a lot of registers.
Definition: TargetRegisterInfo.h:1054
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::SuperRegClassIterator::getSubReg
unsigned getSubReg() const
Returns the current sub-register index.
Definition: TargetRegisterInfo.h:1141
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::TargetRegisterInfo::getCrossCopyRegClass
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
Definition: TargetRegisterInfo.h:772
llvm::TargetRegisterClass::isASubClass
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
Definition: TargetRegisterInfo.h:180
llvm::TargetRegisterInfo::getIntraCallClobberedRegs
virtual ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const
Return a list of all of the registers which are clobbered "inside" a call to the given function.
Definition: TargetRegisterInfo.h:513
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:100
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::TargetRegisterInfo::resolveFrameIndex
virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...
Definition: TargetRegisterInfo.h:970
llvm::TargetRegisterClass::getLaneMask
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
Definition: TargetRegisterInfo.h:204
llvm::printVRegOrUnit
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Definition: TargetRegisterInfo.cpp:164
llvm::MCRegisterClass::end
iterator end() const
Definition: MCRegisterInfo.h:53
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:115
llvm::VirtReg2IndexFunctor
Definition: TargetRegisterInfo.h:1249
llvm::MCRegisterClass::getNumRegs
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
Definition: MCRegisterInfo.h:57
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
Printable.h
StringRef.h
llvm::TargetRegisterInfo::dumpReg
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
Definition: TargetRegisterInfo.cpp:668
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
llvm::TargetRegisterInfo::getRegMaskNames
virtual ArrayRef< const char * > getRegMaskNames() const =0
llvm::TargetRegisterInfo::getRegisterCosts
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
Definition: TargetRegisterInfo.h:356
llvm::TargetRegisterInfo::getMinimalPhysRegClassLLT
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:229
llvm::TargetRegisterInfo::isInAllocatableClass
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition: TargetRegisterInfo.h:365
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1138
llvm::TargetRegisterInfo::isConstantPhysReg
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: TargetRegisterInfo.h:552
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:255
llvm::TargetRegisterInfo::getOffsetOpcodes
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
Definition: TargetRegisterInfo.cpp:641
llvm::TargetRegisterInfo::isAsmClobberable
virtual bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const
Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint,...
Definition: TargetRegisterInfo.h:539
llvm::TargetRegisterInfo::shouldRealignStack
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
Definition: TargetRegisterInfo.cpp:481
llvm::TargetRegisterInfo::updateRegAllocHint
virtual void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
Definition: TargetRegisterInfo.h:864
MachineBasicBlock.h
llvm::TargetRegisterInfoDesc::NumCosts
unsigned NumCosts
Definition: TargetRegisterInfo.h:213
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::TargetRegisterClass::getCopyCost
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Definition: TargetRegisterInfo.h:111
llvm::TargetRegisterInfo::markSuperRegs
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
Definition: TargetRegisterInfo.cpp:79
llvm::TargetRegisterInfo::getRegisterCostTableIndex
virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const
Return the register cost table index.
Definition: TargetRegisterInfo.h:689
llvm::TargetRegisterInfo::regclass_begin
regclass_iterator regclass_begin() const
Register class iterators.
Definition: TargetRegisterInfo.h:731
llvm::TargetRegisterInfo::requiresFrameIndexScavenging
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
Definition: TargetRegisterInfo.h:899
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::TargetRegisterInfo::getCSRFirstUseCost
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time.
Definition: TargetRegisterInfo.h:883
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::TargetRegisterInfo::isCalleeSavedPhysReg
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
Definition: TargetRegisterInfo.cpp:463
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2559
llvm::TargetRegisterInfo::getRegPressureSetLimit
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
llvm::TargetRegisterInfo::RegClassInfo
Definition: TargetRegisterInfo.h:235
llvm::TargetRegisterInfo::getRegClassInfo
const RegClassInfo & getRegClassInfo(const TargetRegisterClass &RC) const
Definition: TargetRegisterInfo.h:725
RegisterSet
SmallSet< unsigned, 4 > RegisterSet
Definition: Thumb2ITBlockPass.cpp:39
llvm::TargetRegisterInfo::useFPForScavengingIndex
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
Definition: TargetRegisterInfo.h:893
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::TargetRegisterClass::SubClassMask
const uint32_t * SubClassMask
Definition: TargetRegisterInfo.h:54
llvm::MCRegisterInfo::getNumSubRegIndices
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
Definition: MCRegisterInfo.h:498
llvm::TargetRegisterClass::getSubClassMask
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
Definition: TargetRegisterInfo.h:156
llvm::TargetRegisterInfo::legalclasstypes_end
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
Definition: TargetRegisterInfo.h:323
llvm::BitMaskClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1236
llvm::MCRegisterClass::getCopyCost
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
Definition: MCRegisterInfo.h:91
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:32
llvm::TargetRegisterInfo::getCalleeSavedRegs
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
llvm::TargetRegisterInfo::RegClassInfo::RegSize
unsigned RegSize
Definition: TargetRegisterInfo.h:236
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::SuperRegClassIterator::SuperRegClassIterator
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
Definition: TargetRegisterInfo.h:1128
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:91
llvm::TargetRegisterInfo::getRegUnitWeight
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:477
llvm::TargetRegisterInfoDesc::CostPerUse
const uint8_t * CostPerUse
Definition: TargetRegisterInfo.h:212
llvm::TargetRegisterInfo::getRegUnitPressureSets
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:381
llvm::TargetRegisterClass::SuperRegIndices
const uint16_t * SuperRegIndices
Definition: TargetRegisterInfo.h:55
llvm::TargetRegisterClass::CoveredBySubRegs
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
Definition: TargetRegisterInfo.h:64
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:197
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const
Return true if the given TargetRegisterClass is compatible with LLT T.
Definition: TargetRegisterInfo.h:305
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetRegisterInfo::hasRegUnit
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
Definition: TargetRegisterInfo.h:439
llvm::TargetRegisterInfo::getRegClassPressureSets
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
b
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Definition: README.txt:418
llvm::TargetRegisterClass::AllocationPriority
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
Definition: TargetRegisterInfo.h:59
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::TargetRegisterInfo::composeSubRegIndicesImpl
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
Definition: TargetRegisterInfo.h:671
llvm::MCRegisterClass::getRegister
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
Definition: MCRegisterInfo.h:61
llvm::TargetRegisterInfo::requiresVirtualBaseRegisters
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
Definition: TargetRegisterInfo.h:912
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:136
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:422
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:301
llvm::BitVector
Definition: BitVector.h:74
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::TargetRegisterClass::hasSuperClass
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:131
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::TargetRegisterClass::OrderFunc
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &)
Definition: TargetRegisterInfo.h:66
llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Definition: TargetRegisterInfo.h:681
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1119
llvm::TargetRegisterInfo::isCallerPreservedPhysReg
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
Definition: TargetRegisterInfo.h:564
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:141
llvm::MCRegisterClass::begin
iterator begin() const
begin/end - Return all of the registers in this class.
Definition: MCRegisterInfo.h:52
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:763
llvm::TargetRegisterInfo::regclasses
iterator_range< regclass_iterator > regclasses() const
Definition: TargetRegisterInfo.h:733
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:490
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:292
llvm::RegClassWeight
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
Definition: TargetRegisterInfo.h:220
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:280
llvm::TargetRegisterClass::LaneMask
const LaneBitmask LaneMask
Definition: TargetRegisterInfo.h:56
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:743
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::TargetRegisterInfo::saveScavengerRegister
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
Definition: TargetRegisterInfo.h:995
llvm::VirtReg2IndexFunctor::operator()
unsigned operator()(Register Reg) const
Definition: TargetRegisterInfo.h:1251
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:749
llvm::TargetRegisterInfo::getCommonSuperRegClass
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
Definition: TargetRegisterInfo.cpp:317
llvm::SuperRegClassIterator::operator++
void operator++()
Advance iterator to the next entry.
Definition: TargetRegisterInfo.h:1149
llvm::TargetRegisterClass::SuperClasses
const sc_iterator SuperClasses
Definition: TargetRegisterInfo.h:65
llvm::TargetRegisterInfo::getFrameRegister
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:581
llvm::TargetRegisterClass::HasDisjunctSubRegs
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
Definition: TargetRegisterInfo.h:61
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetRegisterInfo::getNumRegPressureSets
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:420
llvm::TargetRegisterInfo::eliminateFrameIndex
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
llvm::TargetRegisterInfo::reverseLocalAssignment
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
Definition: TargetRegisterInfo.h:878
MCRegisterInfo.h
llvm::TargetRegisterInfo::regclass_end
regclass_iterator regclass_end() const
Definition: TargetRegisterInfo.h:732
ArrayRef.h
llvm::TargetRegisterInfo::getRegPressureSetName
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetRegisterInfo::composeSubRegIndexLaneMaskImpl
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
Definition: TargetRegisterInfo.h:677
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:39
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:287
iterator_range.h
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::Register::asMCReg
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
Definition: Register.h:120
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::TargetRegisterInfo::needsFrameBaseReg
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction's frame index reference would be better served by a base register oth...
Definition: TargetRegisterInfo.h:955
llvm::RegClassWeight::RegWeight
unsigned RegWeight
Definition: TargetRegisterInfo.h:221
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:174
llvm::TargetRegisterInfo::TargetRegisterInfo
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0)
Definition: TargetRegisterInfo.cpp:52
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::BitMaskClassIterator::BitMaskClassIterator
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask.
Definition: TargetRegisterInfo.h:1229
llvm::TargetRegisterInfo::shouldCoalesce
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
Definition: TargetRegisterInfo.h:1029
RegInfo
Definition: AMDGPUAsmParser.cpp:2355
Matrix
Live Register Matrix
Definition: LiveRegMatrix.cpp:44
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:635
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::TargetRegisterInfo::getCoveringSubRegIndexes
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
Definition: TargetRegisterInfo.cpp:522
llvm::MCRegisterClass::getID
unsigned getID() const
getID() - Return the register class ID number.
Definition: MCRegisterInfo.h:48
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:297
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::RegClassWeight::WeightLimit
unsigned WeightLimit
Definition: TargetRegisterInfo.h:222
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCRegisterInfo::getRegClassName
const char * getRegClassName(const MCRegisterClass *Class) const
Definition: MCRegisterInfo.h:548
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetRegisterInfo::isInlineAsmReadOnlyReg
virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) const
Returns true if PhysReg cannot be written to in inline asm statements.
Definition: TargetRegisterInfo.h:545
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetRegisterInfo::lookThruSingleUseCopyChain
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
Definition: TargetRegisterInfo.cpp:616
llvm::BitMaskClassIterator::operator++
void operator++()
Advance iterator to the next entry.
Definition: TargetRegisterInfo.h:1242
llvm::TargetRegisterInfo::shouldRewriteCopySrc
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Definition: TargetRegisterInfo.cpp:411
llvm::TargetRegisterClass::getNumRegs
unsigned getNumRegs() const
Return the number of registers in this class.
Definition: TargetRegisterInfo.h:77
llvm::TargetRegisterInfo::shouldUseDeferredSpillingForVirtReg
virtual bool shouldUseDeferredSpillingForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Deferred spilling delays the spill insertion of a virtual register after every other allocation.
Definition: TargetRegisterInfo.h:1069
llvm::TargetRegisterClass::begin
iterator begin() const
begin/end - Return all of the registers in this class.
Definition: TargetRegisterInfo.h:73
llvm::TargetRegisterInfo::lookThruCopyLike
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Definition: TargetRegisterInfo.cpp:594
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:274
uint16_t
llvm::TargetRegisterClass::getRegister
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
Definition: TargetRegisterInfo.h:85
llvm::TargetRegisterClass::getSuperClasses
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
Definition: TargetRegisterInfo.h:174
llvm::TargetRegisterInfo::getCustomEHPadPreservedMask
virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...
Definition: TargetRegisterInfo.h:500
llvm::TargetRegisterInfo::isDivergentRegClass
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
Definition: TargetRegisterInfo.h:555
llvm::TargetRegisterInfo::composeSubRegIndexLaneMask
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
Definition: TargetRegisterInfo.h:644
llvm::TargetRegisterClass::getSuperRegIndices
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
Definition: TargetRegisterInfo.h:167
llvm::TargetRegisterInfo::getFrameIndexInstrOffset
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
Definition: TargetRegisterInfo.h:946
llvm::TargetRegisterInfo::getRegPressureSetScore
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
Definition: TargetRegisterInfo.h:803
llvm::TargetRegisterClass::sc_iterator
const TargetRegisterClass *const * sc_iterator
Definition: TargetRegisterInfo.h:50
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::TargetRegisterInfo::RegClassInfo::VTList
vt_iterator VTList
Definition: TargetRegisterInfo.h:237
llvm::TargetRegisterClass::contains
bool contains(Register Reg1, Register Reg2) const
Return true if both registers are in this class.
Definition: TargetRegisterInfo.h:100
llvm::TargetRegisterClass::MC
const MCRegisterClass * MC
Definition: TargetRegisterInfo.h:53
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:737
llvm::TargetRegisterInfo::getNoPreservedMask
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
Definition: TargetRegisterInfo.h:505
llvm::TargetRegisterInfo::regclass_iterator
const TargetRegisterClass *const * regclass_iterator
Definition: TargetRegisterInfo.h:233
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:474
llvm::TargetRegisterInfo::hasStackRealignment
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
Definition: TargetRegisterInfo.h:940
llvm::TargetRegisterInfo::materializeFrameBaseRegister
virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for a pointer to FrameIdx before insertion point I.
Definition: TargetRegisterInfo.h:961
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:677
llvm::TargetRegisterClass::hasSubClass
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:119
llvm::TargetRegisterInfo::requiresRegisterScavenging
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger.
Definition: TargetRegisterInfo.h:887
SmallVector.h
llvm::TargetRegisterInfo::getCoveringLanes
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
Definition: TargetRegisterInfo.h:418
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::SuperRegClassIterator::getMask
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
Definition: TargetRegisterInfo.h:1146
llvm::TargetRegisterInfo::getRegClassWeight
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
LaneBitmask.h
llvm::TargetRegisterInfoDesc
Extra information, not in MCRegisterDesc, about registers.
Definition: TargetRegisterInfo.h:211
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:194
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::TargetRegisterInfo::RegClassInfo::SpillSize
unsigned SpillSize
Definition: TargetRegisterInfo.h:236
llvm::MVT::Untyped
@ Untyped
Definition: MachineValueType.h:253
llvm::SmallVectorImpl< unsigned >
llvm::MCRegisterClass::isAllocatable
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
Definition: MCRegisterInfo.h:95
llvm::BitMaskClassIterator
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
Definition: TargetRegisterInfo.h:1165
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1098
llvm::TargetRegisterInfo::checkAllSuperRegsMarked
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
Definition: TargetRegisterInfo.cpp:85
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:124
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::TargetRegisterInfo::getSpillAlignment
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:286
llvm::TargetRegisterInfo::isFrameOffsetLegal
virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index.
Definition: TargetRegisterInfo.h:977
llvm::TargetRegisterInfo::adjustStackMapLiveOutMask
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
Definition: TargetRegisterInfo.h:577
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:371
llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMask
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
Definition: TargetRegisterInfo.h:658
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::TargetRegisterInfo::RegClassInfo::SpillAlignment
unsigned SpillAlignment
Definition: TargetRegisterInfo.h:236
llvm::TargetRegisterInfo::hasReservedSpillSlot
virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
Definition: TargetRegisterInfo.h:922
llvm::TargetRegisterClass::end
iterator end() const
Definition: TargetRegisterInfo.h:74
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:491
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:80
llvm::BitMaskClassIterator::getID
unsigned getID() const
Returns the current register class ID.
Definition: TargetRegisterInfo.h:1239
llvm::TargetRegisterInfo::prependOffsetExpression
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
Definition: TargetRegisterInfo.cpp:648
llvm::TargetRegisterInfo::getRegMasks
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
llvm::TargetRegisterInfo::getRegPressureLimit
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
Definition: TargetRegisterInfo.h:794
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::TargetRegisterInfo::legalclasstypes_begin
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
Definition: TargetRegisterInfo.h:319
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::TargetRegisterInfo::requiresFrameIndexReplacementScavenging
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
Definition: TargetRegisterInfo.h:905
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40
llvm::LLT
Definition: LowLevelTypeImpl.h:40