LLVM 18.0.0git
TargetRegisterInfo.h
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1//==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes an abstract interface used to get information about a
10// target machines register file. This information is used for a variety of
11// purposed, especially register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16#define LLVM_CODEGEN_TARGETREGISTERINFO_H
17
18#include "llvm/ADT/ArrayRef.h"
20#include "llvm/ADT/StringRef.h"
24#include "llvm/IR/CallingConv.h"
25#include "llvm/MC/LaneBitmask.h"
30#include <cassert>
31#include <cstdint>
32
33namespace llvm {
34
35class BitVector;
36class DIExpression;
37class LiveRegMatrix;
38class MachineFunction;
39class MachineInstr;
40class RegScavenger;
41class VirtRegMap;
42class LiveIntervals;
43class LiveInterval;
44
46public:
47 using iterator = const MCPhysReg *;
48 using const_iterator = const MCPhysReg *;
49 using sc_iterator = const TargetRegisterClass* const *;
50
51 // Instance variables filled by tablegen, do not use!
56 /// Classes with a higher priority value are assigned first by register
57 /// allocators using a greedy heuristic. The value is in the range [0,31].
58 const uint8_t AllocationPriority;
59
60 // Change allocation priority heuristic used by greedy.
61 const bool GlobalPriority;
62
63 /// Configurable target specific flags.
64 const uint8_t TSFlags;
65 /// Whether the class supports two (or more) disjunct subregister indices.
67 /// Whether a combination of subregisters can cover every register in the
68 /// class. See also the CoveredBySubRegs description in Target.td.
69 const bool CoveredBySubRegs;
72
73 /// Return the register class ID number.
74 unsigned getID() const { return MC->getID(); }
75
76 /// begin/end - Return all of the registers in this class.
77 ///
78 iterator begin() const { return MC->begin(); }
79 iterator end() const { return MC->end(); }
80
81 /// Return the number of registers in this class.
82 unsigned getNumRegs() const { return MC->getNumRegs(); }
83
85 getRegisters() const {
86 return make_range(MC->begin(), MC->end());
87 }
88
89 /// Return the specified register in the class.
90 MCRegister getRegister(unsigned i) const {
91 return MC->getRegister(i);
92 }
93
94 /// Return true if the specified register is included in this register class.
95 /// This does not include virtual registers.
96 bool contains(Register Reg) const {
97 /// FIXME: Historically this function has returned false when given vregs
98 /// but it should probably only receive physical registers
99 if (!Reg.isPhysical())
100 return false;
101 return MC->contains(Reg.asMCReg());
102 }
103
104 /// Return true if both registers are in this class.
105 bool contains(Register Reg1, Register Reg2) const {
106 /// FIXME: Historically this function has returned false when given a vregs
107 /// but it should probably only receive physical registers
108 if (!Reg1.isPhysical() || !Reg2.isPhysical())
109 return false;
110 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg());
111 }
112
113 /// Return the cost of copying a value between two registers in this class.
114 /// A negative number means the register class is very expensive
115 /// to copy e.g. status flag register classes.
116 int getCopyCost() const { return MC->getCopyCost(); }
117
118 /// Return true if this register class may be used to create virtual
119 /// registers.
120 bool isAllocatable() const { return MC->isAllocatable(); }
121
122 /// Return true if the specified TargetRegisterClass
123 /// is a proper sub-class of this TargetRegisterClass.
124 bool hasSubClass(const TargetRegisterClass *RC) const {
125 return RC != this && hasSubClassEq(RC);
126 }
127
128 /// Returns true if RC is a sub-class of or equal to this class.
129 bool hasSubClassEq(const TargetRegisterClass *RC) const {
130 unsigned ID = RC->getID();
131 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
132 }
133
134 /// Return true if the specified TargetRegisterClass is a
135 /// proper super-class of this TargetRegisterClass.
136 bool hasSuperClass(const TargetRegisterClass *RC) const {
137 return RC->hasSubClass(this);
138 }
139
140 /// Returns true if RC is a super-class of or equal to this class.
141 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
142 return RC->hasSubClassEq(this);
143 }
144
145 /// Returns a bit vector of subclasses, including this one.
146 /// The vector is indexed by class IDs.
147 ///
148 /// To use it, consider the returned array as a chunk of memory that
149 /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
150 /// contains a bitset of the ID of the subclasses in big-endian style.
151
152 /// I.e., the representation of the memory from left to right at the
153 /// bit level looks like:
154 /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
155 /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
156 /// Where the number represents the class ID and XXX bits that
157 /// should be ignored.
158 ///
159 /// See the implementation of hasSubClassEq for an example of how it
160 /// can be used.
161 const uint32_t *getSubClassMask() const {
162 return SubClassMask;
163 }
164
165 /// Returns a 0-terminated list of sub-register indices that project some
166 /// super-register class into this register class. The list has an entry for
167 /// each Idx such that:
168 ///
169 /// There exists SuperRC where:
170 /// For all Reg in SuperRC:
171 /// this->contains(Reg:Idx)
173 return SuperRegIndices;
174 }
175
176 /// Returns a NULL-terminated list of super-classes. The
177 /// classes are ordered by ID which is also a topological ordering from large
178 /// to small classes. The list does NOT include the current class.
180 return SuperClasses;
181 }
182
183 /// Return true if this TargetRegisterClass is a subset
184 /// class of at least one other TargetRegisterClass.
185 bool isASubClass() const {
186 return SuperClasses[0] != nullptr;
187 }
188
189 /// Returns the preferred order for allocating registers from this register
190 /// class in MF. The raw order comes directly from the .td file and may
191 /// include reserved registers that are not allocatable.
192 /// Register allocators should also make sure to allocate
193 /// callee-saved registers only after all the volatiles are used. The
194 /// RegisterClassInfo class provides filtered allocation orders with
195 /// callee-saved registers moved to the end.
196 ///
197 /// The MachineFunction argument can be used to tune the allocatable
198 /// registers based on the characteristics of the function, subtarget, or
199 /// other criteria.
200 ///
201 /// By default, this method returns all registers in the class.
203 return OrderFunc ? OrderFunc(MF) : ArrayRef(begin(), getNumRegs());
204 }
205
206 /// Returns the combination of all lane masks of register in this class.
207 /// The lane masks of the registers are the combination of all lane masks
208 /// of their subregisters. Returns 1 if there are no subregisters.
210 return LaneMask;
211 }
212};
213
214/// Extra information, not in MCRegisterDesc, about registers.
215/// These are used by codegen, not by MC.
217 const uint8_t *CostPerUse; // Extra cost of instructions using register.
218 unsigned NumCosts; // Number of cost values associated with each register.
219 const bool
220 *InAllocatableClass; // Register belongs to an allocatable regclass.
221};
222
223/// Each TargetRegisterClass has a per register weight, and weight
224/// limit which must be less than the limits of its pressure sets.
226 unsigned RegWeight;
227 unsigned WeightLimit;
228};
229
230/// TargetRegisterInfo base class - We assume that the target defines a static
231/// array of TargetRegisterDesc objects that represent all of the machine
232/// registers that the target has. As such, we simply have to track a pointer
233/// to this array so that we can turn register number into a register
234/// descriptor.
235///
237public:
238 using regclass_iterator = const TargetRegisterClass * const *;
242 unsigned VTListOffset;
243 };
244private:
245 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
246 const char *const *SubRegIndexNames; // Names of subreg indexes.
247 // Pointer to array of lane masks, one per sub-reg index.
248 const LaneBitmask *SubRegIndexLaneMasks;
249
250 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
251 LaneBitmask CoveringLanes;
252 const RegClassInfo *const RCInfos;
253 const MVT::SimpleValueType *const RCVTLists;
254 unsigned HwMode;
255
256protected:
260 const char *const *SRINames,
261 const LaneBitmask *SRILaneMasks,
262 LaneBitmask CoveringLanes,
263 const RegClassInfo *const RCIs,
264 const MVT::SimpleValueType *const RCVTLists,
265 unsigned Mode = 0);
267
268public:
269 // Register numbers can represent physical registers, virtual registers, and
270 // sometimes stack slots. The unsigned values are divided into these ranges:
271 //
272 // 0 Not a register, can be used as a sentinel.
273 // [1;2^30) Physical registers assigned by TableGen.
274 // [2^30;2^31) Stack slots. (Rarely used.)
275 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
276 //
277 // Further sentinels can be allocated from the small negative integers.
278 // DenseMapInfo<unsigned> uses -1u and -2u.
279
280 /// Return the size in bits of a register from class RC.
281 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
282 return getRegClassInfo(RC).RegSize;
283 }
284
285 /// Return the size in bytes of the stack slot allocated to hold a spilled
286 /// copy of a register from class RC.
287 unsigned getSpillSize(const TargetRegisterClass &RC) const {
288 return getRegClassInfo(RC).SpillSize / 8;
289 }
290
291 /// Return the minimum required alignment in bytes for a spill slot for
292 /// a register of this class.
294 return Align(getRegClassInfo(RC).SpillAlignment / 8);
295 }
296
297 /// Return true if the given TargetRegisterClass has the ValueType T.
299 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
300 if (MVT(*I) == T)
301 return true;
302 return false;
303 }
304
305 /// Return true if the given TargetRegisterClass is compatible with LLT T.
307 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) {
308 MVT VT(*I);
309 if (VT == MVT::Untyped)
310 return true;
311
312 if (LLT(VT) == T)
313 return true;
314 }
315 return false;
316 }
317
318 /// Loop over all of the value types that can be represented by values
319 /// in the given register class.
321 return &RCVTLists[getRegClassInfo(RC).VTListOffset];
322 }
323
326 while (*I != MVT::Other)
327 ++I;
328 return I;
329 }
330
331 /// Returns the Register Class of a physical register of the given type,
332 /// picking the most sub register class of the right type that contains this
333 /// physreg.
335 MVT VT = MVT::Other) const;
336
337 /// Returns the Register Class of a physical register of the given type,
338 /// picking the most sub register class of the right type that contains this
339 /// physreg. If there is no register class compatible with the given type,
340 /// returns nullptr.
342 LLT Ty = LLT()) const;
343
344 /// Return the maximal subclass of the given register class that is
345 /// allocatable or NULL.
346 const TargetRegisterClass *
348
349 /// Returns a bitset indexed by register number indicating if a register is
350 /// allocatable or not. If a register class is specified, returns the subset
351 /// for the class.
353 const TargetRegisterClass *RC = nullptr) const;
354
355 /// Get a list of cost values for all registers that correspond to the index
356 /// returned by RegisterCostTableIndex.
358 unsigned Idx = getRegisterCostTableIndex(MF);
359 unsigned NumRegs = getNumRegs();
360 assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds");
361
362 return ArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
363 }
364
365 /// Return true if the register is in the allocation of any register class.
367 return InfoDesc->InAllocatableClass[RegNo];
368 }
369
370 /// Return the human-readable symbolic target-specific
371 /// name for the specified SubRegIndex.
372 const char *getSubRegIndexName(unsigned SubIdx) const {
373 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
374 "This is not a subregister index");
375 return SubRegIndexNames[SubIdx-1];
376 }
377
378 /// Return a bitmask representing the parts of a register that are covered by
379 /// SubIdx \see LaneBitmask.
380 ///
381 /// SubIdx == 0 is allowed, it has the lane mask ~0u.
382 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
383 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
384 return SubRegIndexLaneMasks[SubIdx];
385 }
386
387 /// Try to find one or more subregister indexes to cover \p LaneMask.
388 ///
389 /// If this is possible, returns true and appends the best matching set of
390 /// indexes to \p Indexes. If this is not possible, returns false.
392 const TargetRegisterClass *RC,
393 LaneBitmask LaneMask,
394 SmallVectorImpl<unsigned> &Indexes) const;
395
396 /// The lane masks returned by getSubRegIndexLaneMask() above can only be
397 /// used to determine if sub-registers overlap - they can't be used to
398 /// determine if a set of sub-registers completely cover another
399 /// sub-register.
400 ///
401 /// The X86 general purpose registers have two lanes corresponding to the
402 /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
403 /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
404 /// sub_32bit sub-register.
405 ///
406 /// On the other hand, the ARM NEON lanes fully cover their registers: The
407 /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
408 /// This is related to the CoveredBySubRegs property on register definitions.
409 ///
410 /// This function returns a bit mask of lanes that completely cover their
411 /// sub-registers. More precisely, given:
412 ///
413 /// Covering = getCoveringLanes();
414 /// MaskA = getSubRegIndexLaneMask(SubA);
415 /// MaskB = getSubRegIndexLaneMask(SubB);
416 ///
417 /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
418 /// SubB.
419 LaneBitmask getCoveringLanes() const { return CoveringLanes; }
420
421 /// Returns true if the two registers are equal or alias each other.
422 /// The registers may be virtual registers.
423 bool regsOverlap(Register RegA, Register RegB) const {
424 if (RegA == RegB)
425 return true;
426 if (RegA.isPhysical() && RegB.isPhysical())
427 return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg());
428 return false;
429 }
430
431 /// Returns true if Reg contains RegUnit.
432 bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
433 for (MCRegUnit Unit : regunits(Reg))
434 if (Register(Unit) == RegUnit)
435 return true;
436 return false;
437 }
438
439 /// Returns the original SrcReg unless it is the target of a copy-like
440 /// operation, in which case we chain backwards through all such operations
441 /// to the ultimate source register. If a physical register is encountered,
442 /// we stop the search.
443 virtual Register lookThruCopyLike(Register SrcReg,
444 const MachineRegisterInfo *MRI) const;
445
446 /// Find the original SrcReg unless it is the target of a copy-like operation,
447 /// in which case we chain backwards through all such operations to the
448 /// ultimate source register. If a physical register is encountered, we stop
449 /// the search.
450 /// Return the original SrcReg if all the definitions in the chain only have
451 /// one user and not a physical register.
452 virtual Register
454 const MachineRegisterInfo *MRI) const;
455
456 /// Return a null-terminated list of all of the callee-saved registers on
457 /// this target. The register should be in the order of desired callee-save
458 /// stack frame offset. The first register is closest to the incoming stack
459 /// pointer if stack grows down, and vice versa.
460 /// Notice: This function does not take into account disabled CSRs.
461 /// In most cases you will want to use instead the function
462 /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
463 virtual const MCPhysReg*
465
466 /// Return a mask of call-preserved registers for the given calling convention
467 /// on the current function. The mask should include all call-preserved
468 /// aliases. This is used by the register allocator to determine which
469 /// registers can be live across a call.
470 ///
471 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
472 /// A set bit indicates that all bits of the corresponding register are
473 /// preserved across the function call. The bit mask is expected to be
474 /// sub-register complete, i.e. if A is preserved, so are all its
475 /// sub-registers.
476 ///
477 /// Bits are numbered from the LSB, so the bit for physical register Reg can
478 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
479 ///
480 /// A NULL pointer means that no register mask will be used, and call
481 /// instructions should use implicit-def operands to indicate call clobbered
482 /// registers.
483 ///
485 CallingConv::ID) const {
486 // The default mask clobbers everything. All targets should override.
487 return nullptr;
488 }
489
490 /// Return a register mask for the registers preserved by the unwinder,
491 /// or nullptr if no custom mask is needed.
492 virtual const uint32_t *
494 return nullptr;
495 }
496
497 /// Return a register mask that clobbers everything.
498 virtual const uint32_t *getNoPreservedMask() const {
499 llvm_unreachable("target does not provide no preserved mask");
500 }
501
502 /// Return a list of all of the registers which are clobbered "inside" a call
503 /// to the given function. For example, these might be needed for PLT
504 /// sequences of long-branch veneers.
505 virtual ArrayRef<MCPhysReg>
507 return {};
508 }
509
510 /// Return true if all bits that are set in mask \p mask0 are also set in
511 /// \p mask1.
512 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
513
514 /// Return all the call-preserved register masks defined for this target.
517
518 /// Returns a bitset indexed by physical register number indicating if a
519 /// register is a special register that has particular uses and should be
520 /// considered unavailable at all times, e.g. stack pointer, return address.
521 /// A reserved register:
522 /// - is not allocatable
523 /// - is considered always live
524 /// - is ignored by liveness tracking
525 /// It is often necessary to reserve the super registers of a reserved
526 /// register as well, to avoid them getting allocated indirectly. You may use
527 /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
528 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
529
530 /// Returns either a string explaining why the given register is reserved for
531 /// this function, or an empty optional if no explanation has been written.
532 /// The absence of an explanation does not mean that the register is not
533 /// reserved (meaning, you should check that PhysReg is in fact reserved
534 /// before calling this).
535 virtual std::optional<std::string>
537 return {};
538 }
539
540 /// Returns false if we can't guarantee that Physreg, specified as an IR asm
541 /// clobber constraint, will be preserved across the statement.
542 virtual bool isAsmClobberable(const MachineFunction &MF,
543 MCRegister PhysReg) const {
544 return true;
545 }
546
547 /// Returns true if PhysReg cannot be written to in inline asm statements.
549 unsigned PhysReg) const {
550 return false;
551 }
552
553 /// Returns true if PhysReg is unallocatable and constant throughout the
554 /// function. Used by MachineRegisterInfo::isConstantPhysReg().
555 virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }
556
557 /// Returns true if the register class is considered divergent.
558 virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
559 return false;
560 }
561
562 /// Returns true if the register is considered uniform.
564 const RegisterBankInfo &RBI, Register Reg) const {
565 return false;
566 }
567
568 /// Physical registers that may be modified within a function but are
569 /// guaranteed to be restored before any uses. This is useful for targets that
570 /// have call sequences where a GOT register may be updated by the caller
571 /// prior to a call and is guaranteed to be restored (also by the caller)
572 /// after the call.
574 const MachineFunction &MF) const {
575 return false;
576 }
577
578 /// This is a wrapper around getCallPreservedMask().
579 /// Return true if the register is preserved after the call.
580 virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
581 const MachineFunction &MF) const;
582
583 /// Returns true if PhysReg can be used as an argument to a function.
584 virtual bool isArgumentRegister(const MachineFunction &MF,
585 MCRegister PhysReg) const {
586 return false;
587 }
588
589 /// Returns true if PhysReg is a fixed register.
590 virtual bool isFixedRegister(const MachineFunction &MF,
591 MCRegister PhysReg) const {
592 return false;
593 }
594
595 /// Returns true if PhysReg is a general purpose register.
597 MCRegister PhysReg) const {
598 return false;
599 }
600
601 /// Prior to adding the live-out mask to a stackmap or patchpoint
602 /// instruction, provide the target the opportunity to adjust it (mainly to
603 /// remove pseudo-registers that should be ignored).
604 virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
605
606 /// Return a super-register of the specified register
607 /// Reg so its sub-register of index SubIdx is Reg.
609 const TargetRegisterClass *RC) const {
610 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
611 }
612
613 /// Return a subclass of the specified register
614 /// class A so that each register in it has a sub-register of the
615 /// specified sub-register index which is in the specified register class B.
616 ///
617 /// TableGen will synthesize missing A sub-classes.
618 virtual const TargetRegisterClass *
620 const TargetRegisterClass *B, unsigned Idx) const;
621
622 // For a copy-like instruction that defines a register of class DefRC with
623 // subreg index DefSubReg, reading from another source with class SrcRC and
624 // subregister SrcSubReg return true if this is a preferable copy
625 // instruction or an earlier use should be used.
626 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
627 unsigned DefSubReg,
628 const TargetRegisterClass *SrcRC,
629 unsigned SrcSubReg) const;
630
631 /// Returns the largest legal sub-class of RC that
632 /// supports the sub-register index Idx.
633 /// If no such sub-class exists, return NULL.
634 /// If all registers in RC already have an Idx sub-register, return RC.
635 ///
636 /// TableGen generates a version of this function that is good enough in most
637 /// cases. Targets can override if they have constraints that TableGen
638 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
639 /// supported by the full GR32 register class in 64-bit mode, but only by the
640 /// GR32_ABCD regiister class in 32-bit mode.
641 ///
642 /// TableGen will synthesize missing RC sub-classes.
643 virtual const TargetRegisterClass *
644 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
645 assert(Idx == 0 && "Target has no sub-registers");
646 return RC;
647 }
648
649 /// Return a register class that can be used for a subregister copy from/into
650 /// \p SuperRC at \p SubRegIdx.
651 virtual const TargetRegisterClass *
653 unsigned SubRegIdx) const {
654 return nullptr;
655 }
656
657 /// Return the subregister index you get from composing
658 /// two subregister indices.
659 ///
660 /// The special null sub-register index composes as the identity.
661 ///
662 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
663 /// returns c. Note that composeSubRegIndices does not tell you about illegal
664 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
665 /// b, composeSubRegIndices doesn't tell you.
666 ///
667 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
668 /// ssub_0:S0 - ssub_3:S3 subregs.
669 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
670 unsigned composeSubRegIndices(unsigned a, unsigned b) const {
671 if (!a) return b;
672 if (!b) return a;
673 return composeSubRegIndicesImpl(a, b);
674 }
675
676 /// Transforms a LaneMask computed for one subregister to the lanemask that
677 /// would have been computed when composing the subsubregisters with IdxA
678 /// first. @sa composeSubRegIndices()
680 LaneBitmask Mask) const {
681 if (!IdxA)
682 return Mask;
683 return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
684 }
685
686 /// Transform a lanemask given for a virtual register to the corresponding
687 /// lanemask before using subregister with index \p IdxA.
688 /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
689 /// valie lane mask (no invalid bits set) the following holds:
690 /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
691 /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
692 /// => X1 == Mask
694 LaneBitmask LaneMask) const {
695 if (!IdxA)
696 return LaneMask;
697 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
698 }
699
700 /// Debugging helper: dump register in human readable form to dbgs() stream.
701 static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
702 const TargetRegisterInfo *TRI = nullptr);
703
704 /// Return target defined base register class for a physical register.
705 /// This is the register class with the lowest BaseClassOrder containing the
706 /// register.
707 /// Will be nullptr if the register is not in any base register class.
709 return nullptr;
710 }
711
712protected:
713 /// Overridden by TableGen in targets that have sub-registers.
714 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
715 llvm_unreachable("Target has no sub-registers");
716 }
717
718 /// Overridden by TableGen in targets that have sub-registers.
719 virtual LaneBitmask
721 llvm_unreachable("Target has no sub-registers");
722 }
723
725 LaneBitmask) const {
726 llvm_unreachable("Target has no sub-registers");
727 }
728
729 /// Return the register cost table index. This implementation is sufficient
730 /// for most architectures and can be overriden by targets in case there are
731 /// multiple cost values associated with each register.
732 virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const {
733 return 0;
734 }
735
736public:
737 /// Find a common super-register class if it exists.
738 ///
739 /// Find a register class, SuperRC and two sub-register indices, PreA and
740 /// PreB, such that:
741 ///
742 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
743 ///
744 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
745 ///
746 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
747 ///
748 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
749 /// requirements, and there is no register class with a smaller spill size
750 /// that satisfies the requirements.
751 ///
752 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
753 ///
754 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
755 /// that case, the returned register class will be a sub-class of the
756 /// corresponding argument register class.
757 ///
758 /// The function returns NULL if no register class can be found.
760 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
761 const TargetRegisterClass *RCB, unsigned SubB,
762 unsigned &PreA, unsigned &PreB) const;
763
764 //===--------------------------------------------------------------------===//
765 // Register Class Information
766 //
767protected:
769 return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
770 }
771
772public:
773 /// Register class iterators
774 regclass_iterator regclass_begin() const { return RegClassBegin; }
775 regclass_iterator regclass_end() const { return RegClassEnd; }
778 }
779
780 unsigned getNumRegClasses() const {
781 return (unsigned)(regclass_end()-regclass_begin());
782 }
783
784 /// Returns the register class associated with the enumeration value.
785 /// See class MCOperandInfo.
786 const TargetRegisterClass *getRegClass(unsigned i) const {
787 assert(i < getNumRegClasses() && "Register Class ID out of range");
788 return RegClassBegin[i];
789 }
790
791 /// Returns the name of the register class.
792 const char *getRegClassName(const TargetRegisterClass *Class) const {
793 return MCRegisterInfo::getRegClassName(Class->MC);
794 }
795
796 /// Find the largest common subclass of A and B.
797 /// Return NULL if there is no common subclass.
798 const TargetRegisterClass *
800 const TargetRegisterClass *B) const;
801
802 /// Returns a TargetRegisterClass used for pointer values.
803 /// If a target supports multiple different pointer register classes,
804 /// kind specifies which one is indicated.
805 virtual const TargetRegisterClass *
806 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
807 llvm_unreachable("Target didn't implement getPointerRegClass!");
808 }
809
810 /// Returns a legal register class to copy a register in the specified class
811 /// to or from. If it is possible to copy the register directly without using
812 /// a cross register class copy, return the specified RC. Returns NULL if it
813 /// is not possible to copy between two registers of the specified class.
814 virtual const TargetRegisterClass *
816 return RC;
817 }
818
819 /// Returns the largest super class of RC that is legal to use in the current
820 /// sub-target and has the same spill size.
821 /// The returned register class can be used to create virtual registers which
822 /// means that all its registers can be copied and spilled.
823 virtual const TargetRegisterClass *
825 const MachineFunction &) const {
826 /// The default implementation is very conservative and doesn't allow the
827 /// register allocator to inflate register classes.
828 return RC;
829 }
830
831 /// Return the register pressure "high water mark" for the specific register
832 /// class. The scheduler is in high register pressure mode (for the specific
833 /// register class) if it goes over the limit.
834 ///
835 /// Note: this is the old register pressure model that relies on a manually
836 /// specified representative register class per value type.
837 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
838 MachineFunction &MF) const {
839 return 0;
840 }
841
842 /// Return a heuristic for the machine scheduler to compare the profitability
843 /// of increasing one register pressure set versus another. The scheduler
844 /// will prefer increasing the register pressure of the set which returns
845 /// the largest value for this function.
846 virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
847 unsigned PSetID) const {
848 return PSetID;
849 }
850
851 /// Get the weight in units of pressure for this register class.
853 const TargetRegisterClass *RC) const = 0;
854
855 /// Returns size in bits of a phys/virtual/generic register.
856 unsigned getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
857
858 /// Get the weight in units of pressure for this register unit.
859 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
860
861 /// Get the number of dimensions of register pressure.
862 virtual unsigned getNumRegPressureSets() const = 0;
863
864 /// Get the name of this register unit pressure set.
865 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
866
867 /// Get the register unit pressure limit for this dimension.
868 /// This limit must be adjusted dynamically for reserved registers.
869 virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
870 unsigned Idx) const = 0;
871
872 /// Get the dimensions of register pressure impacted by this register class.
873 /// Returns a -1 terminated array of pressure set IDs.
874 virtual const int *getRegClassPressureSets(
875 const TargetRegisterClass *RC) const = 0;
876
877 /// Get the dimensions of register pressure impacted by this register unit.
878 /// Returns a -1 terminated array of pressure set IDs.
879 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
880
881 /// Get a list of 'hint' registers that the register allocator should try
882 /// first when allocating a physical register for the virtual register
883 /// VirtReg. These registers are effectively moved to the front of the
884 /// allocation order. If true is returned, regalloc will try to only use
885 /// hints to the greatest extent possible even if it means spilling.
886 ///
887 /// The Order argument is the allocation order for VirtReg's register class
888 /// as returned from RegisterClassInfo::getOrder(). The hint registers must
889 /// come from Order, and they must not be reserved.
890 ///
891 /// The default implementation of this function will only add target
892 /// independent register allocation hints. Targets that override this
893 /// function should typically call this default implementation as well and
894 /// expect to see generic copy hints added.
895 virtual bool
898 const MachineFunction &MF,
899 const VirtRegMap *VRM = nullptr,
900 const LiveRegMatrix *Matrix = nullptr) const;
901
902 /// A callback to allow target a chance to update register allocation hints
903 /// when a register is "changed" (e.g. coalesced) to another register.
904 /// e.g. On ARM, some virtual registers should target register pairs,
905 /// if one of pair is coalesced to another register, the allocation hint of
906 /// the other half of the pair should be changed to point to the new register.
908 MachineFunction &MF) const {
909 // Do nothing.
910 }
911
912 /// Allow the target to reverse allocation order of local live ranges. This
913 /// will generally allocate shorter local live ranges first. For targets with
914 /// many registers, this could reduce regalloc compile time by a large
915 /// factor. It is disabled by default for three reasons:
916 /// (1) Top-down allocation is simpler and easier to debug for targets that
917 /// don't benefit from reversing the order.
918 /// (2) Bottom-up allocation could result in poor evicition decisions on some
919 /// targets affecting the performance of compiled code.
920 /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
921 virtual bool reverseLocalAssignment() const { return false; }
922
923 /// Allow the target to override the cost of using a callee-saved register for
924 /// the first time. Default value of 0 means we will use a callee-saved
925 /// register if it is available.
926 virtual unsigned getCSRFirstUseCost() const { return 0; }
927
928 /// Returns true if the target requires (and can make use of) the register
929 /// scavenger.
930 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
931 return false;
932 }
933
934 /// Returns true if the target wants to use frame pointer based accesses to
935 /// spill to the scavenger emergency spill slot.
936 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
937 return true;
938 }
939
940 /// Returns true if the target requires post PEI scavenging of registers for
941 /// materializing frame index constants.
942 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
943 return false;
944 }
945
946 /// Returns true if the target requires using the RegScavenger directly for
947 /// frame elimination despite using requiresFrameIndexScavenging.
949 const MachineFunction &MF) const {
950 return false;
951 }
952
953 /// Returns true if the target wants the LocalStackAllocation pass to be run
954 /// and virtual base registers used for more efficient stack access.
955 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
956 return false;
957 }
958
959 /// Return true if target has reserved a spill slot in the stack frame of
960 /// the given function for the specified register. e.g. On x86, if the frame
961 /// register is required, the first fixed stack object is reserved as its
962 /// spill slot. This tells PEI not to create a new stack frame
963 /// object for the given register. It should be called only after
964 /// determineCalleeSaves().
966 int &FrameIdx) const {
967 return false;
968 }
969
970 /// Returns true if the live-ins should be tracked after register allocation.
971 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
972 return true;
973 }
974
975 /// True if the stack can be realigned for the target.
976 virtual bool canRealignStack(const MachineFunction &MF) const;
977
978 /// True if storage within the function requires the stack pointer to be
979 /// aligned more than the normal calling convention calls for.
980 virtual bool shouldRealignStack(const MachineFunction &MF) const;
981
982 /// True if stack realignment is required and still possible.
983 bool hasStackRealignment(const MachineFunction &MF) const {
984 return shouldRealignStack(MF) && canRealignStack(MF);
985 }
986
987 /// Get the offset from the referenced frame index in the instruction,
988 /// if there is one.
990 int Idx) const {
991 return 0;
992 }
993
994 /// Returns true if the instruction's frame index reference would be better
995 /// served by a base register other than FP or SP.
996 /// Used by LocalStackFrameAllocation to determine which frame index
997 /// references it should create new base registers for.
998 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
999 return false;
1000 }
1001
1002 /// Insert defining instruction(s) for a pointer to FrameIdx before
1003 /// insertion point I. Return materialized frame pointer.
1005 int FrameIdx,
1006 int64_t Offset) const {
1007 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
1008 "target");
1009 }
1010
1011 /// Resolve a frame index operand of an instruction
1012 /// to reference the indicated base register plus offset instead.
1014 int64_t Offset) const {
1015 llvm_unreachable("resolveFrameIndex does not exist on this target");
1016 }
1017
1018 /// Determine whether a given base register plus offset immediate is
1019 /// encodable to resolve a frame index.
1020 virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
1021 int64_t Offset) const {
1022 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
1023 }
1024
1025 /// Gets the DWARF expression opcodes for \p Offset.
1026 virtual void getOffsetOpcodes(const StackOffset &Offset,
1027 SmallVectorImpl<uint64_t> &Ops) const;
1028
1029 /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
1030 DIExpression *
1031 prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
1032 const StackOffset &Offset) const;
1033
1034 /// Spill the register so it can be used by the register scavenger.
1035 /// Return true if the register was spilled, false otherwise.
1036 /// If this function does not spill the register, the scavenger
1037 /// will instead spill it to the emergency spill slot.
1041 const TargetRegisterClass *RC,
1042 Register Reg) const {
1043 return false;
1044 }
1045
1046 /// Process frame indices in reverse block order. This changes the behavior of
1047 /// the RegScavenger passed to eliminateFrameIndex. If this is true targets
1048 /// should scavengeRegisterBackwards in eliminateFrameIndex. New targets
1049 /// should prefer reverse scavenging behavior.
1050 /// TODO: Remove this when all targets return true.
1051 virtual bool eliminateFrameIndicesBackwards() const { return true; }
1052
1053 /// This method must be overriden to eliminate abstract frame indices from
1054 /// instructions which may use them. The instruction referenced by the
1055 /// iterator contains an MO_FrameIndex operand which must be eliminated by
1056 /// this method. This method may modify or replace the specified instruction,
1057 /// as long as it keeps the iterator pointing at the finished product.
1058 /// SPAdj is the SP adjustment due to call frame setup instruction.
1059 /// FIOperandNum is the FI operand number.
1060 /// Returns true if the current instruction was removed and the iterator
1061 /// is not longer valid
1063 int SPAdj, unsigned FIOperandNum,
1064 RegScavenger *RS = nullptr) const = 0;
1065
1066 /// Return the assembly name for \p Reg.
1068 // FIXME: We are assuming that the assembly name is equal to the TableGen
1069 // name converted to lower case
1070 //
1071 // The TableGen name is the name of the definition for this register in the
1072 // target's tablegen files. For example, the TableGen name of
1073 // def EAX : Register <...>; is "EAX"
1074 return StringRef(getName(Reg));
1075 }
1076
1077 //===--------------------------------------------------------------------===//
1078 /// Subtarget Hooks
1079
1080 /// SrcRC and DstRC will be morphed into NewRC if this returns true.
1082 const TargetRegisterClass *SrcRC,
1083 unsigned SubReg,
1084 const TargetRegisterClass *DstRC,
1085 unsigned DstSubReg,
1086 const TargetRegisterClass *NewRC,
1087 LiveIntervals &LIS) const
1088 { return true; }
1089
1090 /// Region split has a high compile time cost especially for large live range.
1091 /// This method is used to decide whether or not \p VirtReg should
1092 /// go through this expensive splitting heuristic.
1093 virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF,
1094 const LiveInterval &VirtReg) const;
1095
1096 /// Last chance recoloring has a high compile time cost especially for
1097 /// targets with a lot of registers.
1098 /// This method is used to decide whether or not \p VirtReg should
1099 /// go through this expensive heuristic.
1100 /// When this target hook is hit, by returning false, there is a high
1101 /// chance that the register allocation will fail altogether (usually with
1102 /// "ran out of registers").
1103 /// That said, this error usually points to another problem in the
1104 /// optimization pipeline.
1105 virtual bool
1107 const LiveInterval &VirtReg) const {
1108 return true;
1109 }
1110
1111 /// Deferred spilling delays the spill insertion of a virtual register
1112 /// after every other allocation. By deferring the spilling, it is
1113 /// sometimes possible to eliminate that spilling altogether because
1114 /// something else could have been eliminated, thus leaving some space
1115 /// for the virtual register.
1116 /// However, this comes with a compile time impact because it adds one
1117 /// more stage to the greedy register allocator.
1118 /// This method is used to decide whether \p VirtReg should use the deferred
1119 /// spilling stage instead of being spilled right away.
1120 virtual bool
1122 const LiveInterval &VirtReg) const {
1123 return false;
1124 }
1125
1126 /// When prioritizing live ranges in register allocation, if this hook returns
1127 /// true then the AllocationPriority of the register class will be treated as
1128 /// more important than whether the range is local to a basic block or global.
1129 virtual bool
1131 return false;
1132 }
1133
1134 //===--------------------------------------------------------------------===//
1135 /// Debug information queries.
1136
1137 /// getFrameRegister - This method should return the register used as a base
1138 /// for values allocated in the current stack frame.
1139 virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
1140
1141 /// Mark a register and all its aliases as reserved in the given set.
1142 void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const;
1143
1144 /// Returns true if for every register in the set all super registers are part
1145 /// of the set as well.
1146 bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
1147 ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1148
1149 virtual const TargetRegisterClass *
1151 const MachineRegisterInfo &MRI) const {
1152 return nullptr;
1153 }
1154
1155 /// Returns the physical register number of sub-register "Index"
1156 /// for physical register RegNo. Return zero if the sub-register does not
1157 /// exist.
1158 inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
1159 return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx);
1160 }
1161
1162 /// Some targets have non-allocatable registers that aren't technically part
1163 /// of the explicit callee saved register list, but should be handled as such
1164 /// in certain cases.
1166 return false;
1167 }
1168};
1169
1170//===----------------------------------------------------------------------===//
1171// SuperRegClassIterator
1172//===----------------------------------------------------------------------===//
1173//
1174// Iterate over the possible super-registers for a given register class. The
1175// iterator will visit a list of pairs (Idx, Mask) corresponding to the
1176// possible classes of super-registers.
1177//
1178// Each bit mask will have at least one set bit, and each set bit in Mask
1179// corresponds to a SuperRC such that:
1180//
1181// For all Reg in SuperRC: Reg:Idx is in RC.
1182//
1183// The iterator can include (O, RC->getSubClassMask()) as the first entry which
1184// also satisfies the above requirement, assuming Reg:0 == Reg.
1185//
1187 const unsigned RCMaskWords;
1188 unsigned SubReg = 0;
1189 const uint16_t *Idx;
1190 const uint32_t *Mask;
1191
1192public:
1193 /// Create a SuperRegClassIterator that visits all the super-register classes
1194 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1196 const TargetRegisterInfo *TRI,
1197 bool IncludeSelf = false)
1198 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1199 Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1200 if (!IncludeSelf)
1201 ++*this;
1202 }
1203
1204 /// Returns true if this iterator is still pointing at a valid entry.
1205 bool isValid() const { return Idx; }
1206
1207 /// Returns the current sub-register index.
1208 unsigned getSubReg() const { return SubReg; }
1209
1210 /// Returns the bit mask of register classes that getSubReg() projects into
1211 /// RC.
1212 /// See TargetRegisterClass::getSubClassMask() for how to use it.
1213 const uint32_t *getMask() const { return Mask; }
1214
1215 /// Advance iterator to the next entry.
1216 void operator++() {
1217 assert(isValid() && "Cannot move iterator past end.");
1218 Mask += RCMaskWords;
1219 SubReg = *Idx++;
1220 if (!SubReg)
1221 Idx = nullptr;
1222 }
1223};
1224
1225//===----------------------------------------------------------------------===//
1226// BitMaskClassIterator
1227//===----------------------------------------------------------------------===//
1228/// This class encapuslates the logic to iterate over bitmask returned by
1229/// the various RegClass related APIs.
1230/// E.g., this class can be used to iterate over the subclasses provided by
1231/// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1233 /// Total number of register classes.
1234 const unsigned NumRegClasses;
1235 /// Base index of CurrentChunk.
1236 /// In other words, the number of bit we read to get at the
1237 /// beginning of that chunck.
1238 unsigned Base = 0;
1239 /// Adjust base index of CurrentChunk.
1240 /// Base index + how many bit we read within CurrentChunk.
1241 unsigned Idx = 0;
1242 /// Current register class ID.
1243 unsigned ID = 0;
1244 /// Mask we are iterating over.
1245 const uint32_t *Mask;
1246 /// Current chunk of the Mask we are traversing.
1247 uint32_t CurrentChunk;
1248
1249 /// Move ID to the next set bit.
1250 void moveToNextID() {
1251 // If the current chunk of memory is empty, move to the next one,
1252 // while making sure we do not go pass the number of register
1253 // classes.
1254 while (!CurrentChunk) {
1255 // Move to the next chunk.
1256 Base += 32;
1257 if (Base >= NumRegClasses) {
1258 ID = NumRegClasses;
1259 return;
1260 }
1261 CurrentChunk = *++Mask;
1262 Idx = Base;
1263 }
1264 // Otherwise look for the first bit set from the right
1265 // (representation of the class ID is big endian).
1266 // See getSubClassMask for more details on the representation.
1267 unsigned Offset = llvm::countr_zero(CurrentChunk);
1268 // Add the Offset to the adjusted base number of this chunk: Idx.
1269 // This is the ID of the register class.
1270 ID = Idx + Offset;
1271
1272 // Consume the zeros, if any, and the bit we just read
1273 // so that we are at the right spot for the next call.
1274 // Do not do Offset + 1 because Offset may be 31 and 32
1275 // will be UB for the shift, though in that case we could
1276 // have make the chunk being equal to 0, but that would
1277 // have introduced a if statement.
1278 moveNBits(Offset);
1279 moveNBits(1);
1280 }
1281
1282 /// Move \p NumBits Bits forward in CurrentChunk.
1283 void moveNBits(unsigned NumBits) {
1284 assert(NumBits < 32 && "Undefined behavior spotted!");
1285 // Consume the bit we read for the next call.
1286 CurrentChunk >>= NumBits;
1287 // Adjust the base for the chunk.
1288 Idx += NumBits;
1289 }
1290
1291public:
1292 /// Create a BitMaskClassIterator that visits all the register classes
1293 /// represented by \p Mask.
1294 ///
1295 /// \pre \p Mask != nullptr
1297 : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1298 // Move to the first ID.
1299 moveToNextID();
1300 }
1301
1302 /// Returns true if this iterator is still pointing at a valid entry.
1303 bool isValid() const { return getID() != NumRegClasses; }
1304
1305 /// Returns the current register class ID.
1306 unsigned getID() const { return ID; }
1307
1308 /// Advance iterator to the next entry.
1309 void operator++() {
1310 assert(isValid() && "Cannot move iterator past end.");
1311 moveToNextID();
1312 }
1313};
1314
1315// This is useful when building IndexedMaps keyed on virtual registers
1318 unsigned operator()(Register Reg) const {
1320 }
1321};
1322
1323/// Prints virtual and physical registers with or without a TRI instance.
1324///
1325/// The format is:
1326/// %noreg - NoRegister
1327/// %5 - a virtual register.
1328/// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1329/// %eax - a physical register
1330/// %physreg17 - a physical register when no TRI instance given.
1331///
1332/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1333Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
1334 unsigned SubIdx = 0,
1335 const MachineRegisterInfo *MRI = nullptr);
1336
1337/// Create Printable object to print register units on a \ref raw_ostream.
1338///
1339/// Register units are named after their root registers:
1340///
1341/// al - Single root.
1342/// fp0~st7 - Dual roots.
1343///
1344/// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1345Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1346
1347/// Create Printable object to print virtual registers and physical
1348/// registers on a \ref raw_ostream.
1349Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1350
1351/// Create Printable object to print register classes or register banks
1352/// on a \ref raw_ostream.
1353Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
1354 const TargetRegisterInfo *TRI);
1355
1356} // end namespace llvm
1357
1358#endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineBasicBlock & MBB
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
A common definition of LaneBitmask for use in TableGen and CodeGen.
Live Register Matrix
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
void operator++()
Advance iterator to the next entry.
unsigned getID() const
Returns the current register class ID.
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
DWARF expression.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getID() const
getID() - Return the register class ID number.
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
iterator begin() const
begin/end - Return all of the registers in this class.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
iterator end() const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
const char * getRegClassName(const MCRegisterClass *Class) const
iterator_range< MCRegUnitIterator > regunits(MCRegister Reg) const
Returns an iterator range over all regunits for Reg.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
Definition: Register.h:110
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:36
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
void operator++()
Advance iterator to the next entry.
unsigned getSubReg() const
Returns the current sub-register index.
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
const TargetRegisterClass *const * sc_iterator
unsigned getNumRegs() const
Return the number of registers in this class.
const uint8_t TSFlags
Configurable target specific flags.
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
unsigned getID() const
Return the register class ID number.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
const sc_iterator SuperClasses
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &)
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
const uint16_t * SuperRegIndices
const MCRegisterClass * MC
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
bool contains(Register Reg1, Register Reg2) const
Return true if both registers are in this class.
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
iterator begin() const
begin/end - Return all of the registers in this class.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
const TargetRegisterClass *const * regclass_iterator
virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index.
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const
Return true if the given TargetRegisterClass is compatible with LLT T.
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
virtual bool shouldUseDeferredSpillingForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Deferred spilling delays the spill insertion of a virtual register after every other allocation.
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
iterator_range< regclass_iterator > regclasses() const
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
virtual const TargetRegisterClass * getPhysRegBaseClass(MCRegister Reg) const
Return target defined base register class for a physical register.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const
Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint,...
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
virtual bool shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Last chance recoloring has a high compile time cost especially for targets with a lot of registers.
virtual bool eliminateFrameIndicesBackwards() const
Process frame indices in reverse block order.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time.
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) const
Returns true if PhysReg cannot be written to in inline asm statements.
virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...
virtual bool isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const
Returns true if the register is considered uniform.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
virtual std::optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const
Returns either a string explaining why the given register is reserved for this function,...
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
virtual bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a general purpose register.
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
regclass_iterator regclass_begin() const
Register class iterators.
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
unsigned getNumRegClasses() const
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
virtual ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const
Return a list of all of the registers which are clobbered "inside" a call to the given function.
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const
Some targets have non-allocatable registers that aren't technically part of the explicit callee saved...
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
const RegClassInfo & getRegClassInfo(const TargetRegisterClass &RC) const
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
virtual bool isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg can be used as an argument to a function.
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
virtual const TargetRegisterClass * getSubRegisterClass(const TargetRegisterClass *SuperRC, unsigned SubRegIdx) const
Return a register class that can be used for a subregister copy from/into SuperRC at SubRegIdx.
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
virtual bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
regclass_iterator regclass_end() const
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for a pointer to FrameIdx before insertion point I.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
virtual ArrayRef< const char * > getRegMaskNames() const =0
virtual bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a fixed register.
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
virtual StringRef getRegAsmName(MCRegister Reg) const
Return the assembly name for Reg.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const
Return the register cost table index.
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction's frame index reference would be better served by a base register oth...
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
virtual bool regClassPriorityTrumpsGlobalness(const MachineFunction &MF) const
When prioritizing live ranges in register allocation, if this hook returns true then the AllocationPr...
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
virtual void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: bit.h:179
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
Extra information, not in MCRegisterDesc, about registers.
unsigned operator()(Register Reg) const