LLVM  14.0.0git
TargetRegisterInfo.h
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1 //==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes an abstract interface used to get information about a
10 // target machines register file. This information is used for a variety of
11 // purposed, especially register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16 #define LLVM_CODEGEN_TARGETREGISTERINFO_H
17 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/MC/LaneBitmask.h"
25 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/Support/Printable.h"
30 #include <cassert>
31 #include <cstdint>
32 #include <functional>
33 
34 namespace llvm {
35 
36 class BitVector;
37 class DIExpression;
38 class LiveRegMatrix;
39 class MachineFunction;
40 class MachineInstr;
41 class RegScavenger;
42 class VirtRegMap;
43 class LiveIntervals;
44 class LiveInterval;
45 
47 public:
48  using iterator = const MCPhysReg *;
49  using const_iterator = const MCPhysReg *;
50  using sc_iterator = const TargetRegisterClass* const *;
51 
52  // Instance variables filled by tablegen, do not use!
57  /// Classes with a higher priority value are assigned first by register
58  /// allocators using a greedy heuristic. The value is in the range [0,63].
59  const uint8_t AllocationPriority;
60  /// Whether the class supports two (or more) disjunct subregister indices.
61  const bool HasDisjunctSubRegs;
62  /// Whether a combination of subregisters can cover every register in the
63  /// class. See also the CoveredBySubRegs description in Target.td.
64  const bool CoveredBySubRegs;
67 
68  /// Return the register class ID number.
69  unsigned getID() const { return MC->getID(); }
70 
71  /// begin/end - Return all of the registers in this class.
72  ///
73  iterator begin() const { return MC->begin(); }
74  iterator end() const { return MC->end(); }
75 
76  /// Return the number of registers in this class.
77  unsigned getNumRegs() const { return MC->getNumRegs(); }
78 
80  getRegisters() const {
81  return make_range(MC->begin(), MC->end());
82  }
83 
84  /// Return the specified register in the class.
85  MCRegister getRegister(unsigned i) const {
86  return MC->getRegister(i);
87  }
88 
89  /// Return true if the specified register is included in this register class.
90  /// This does not include virtual registers.
91  bool contains(Register Reg) const {
92  /// FIXME: Historically this function has returned false when given vregs
93  /// but it should probably only receive physical registers
94  if (!Reg.isPhysical())
95  return false;
96  return MC->contains(Reg.asMCReg());
97  }
98 
99  /// Return true if both registers are in this class.
100  bool contains(Register Reg1, Register Reg2) const {
101  /// FIXME: Historically this function has returned false when given a vregs
102  /// but it should probably only receive physical registers
103  if (!Reg1.isPhysical() || !Reg2.isPhysical())
104  return false;
105  return MC->contains(Reg1.asMCReg(), Reg2.asMCReg());
106  }
107 
108  /// Return the cost of copying a value between two registers in this class.
109  /// A negative number means the register class is very expensive
110  /// to copy e.g. status flag register classes.
111  int getCopyCost() const { return MC->getCopyCost(); }
112 
113  /// Return true if this register class may be used to create virtual
114  /// registers.
115  bool isAllocatable() const { return MC->isAllocatable(); }
116 
117  /// Return true if the specified TargetRegisterClass
118  /// is a proper sub-class of this TargetRegisterClass.
119  bool hasSubClass(const TargetRegisterClass *RC) const {
120  return RC != this && hasSubClassEq(RC);
121  }
122 
123  /// Returns true if RC is a sub-class of or equal to this class.
124  bool hasSubClassEq(const TargetRegisterClass *RC) const {
125  unsigned ID = RC->getID();
126  return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
127  }
128 
129  /// Return true if the specified TargetRegisterClass is a
130  /// proper super-class of this TargetRegisterClass.
131  bool hasSuperClass(const TargetRegisterClass *RC) const {
132  return RC->hasSubClass(this);
133  }
134 
135  /// Returns true if RC is a super-class of or equal to this class.
136  bool hasSuperClassEq(const TargetRegisterClass *RC) const {
137  return RC->hasSubClassEq(this);
138  }
139 
140  /// Returns a bit vector of subclasses, including this one.
141  /// The vector is indexed by class IDs.
142  ///
143  /// To use it, consider the returned array as a chunk of memory that
144  /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
145  /// contains a bitset of the ID of the subclasses in big-endian style.
146 
147  /// I.e., the representation of the memory from left to right at the
148  /// bit level looks like:
149  /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
150  /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
151  /// Where the number represents the class ID and XXX bits that
152  /// should be ignored.
153  ///
154  /// See the implementation of hasSubClassEq for an example of how it
155  /// can be used.
156  const uint32_t *getSubClassMask() const {
157  return SubClassMask;
158  }
159 
160  /// Returns a 0-terminated list of sub-register indices that project some
161  /// super-register class into this register class. The list has an entry for
162  /// each Idx such that:
163  ///
164  /// There exists SuperRC where:
165  /// For all Reg in SuperRC:
166  /// this->contains(Reg:Idx)
167  const uint16_t *getSuperRegIndices() const {
168  return SuperRegIndices;
169  }
170 
171  /// Returns a NULL-terminated list of super-classes. The
172  /// classes are ordered by ID which is also a topological ordering from large
173  /// to small classes. The list does NOT include the current class.
175  return SuperClasses;
176  }
177 
178  /// Return true if this TargetRegisterClass is a subset
179  /// class of at least one other TargetRegisterClass.
180  bool isASubClass() const {
181  return SuperClasses[0] != nullptr;
182  }
183 
184  /// Returns the preferred order for allocating registers from this register
185  /// class in MF. The raw order comes directly from the .td file and may
186  /// include reserved registers that are not allocatable.
187  /// Register allocators should also make sure to allocate
188  /// callee-saved registers only after all the volatiles are used. The
189  /// RegisterClassInfo class provides filtered allocation orders with
190  /// callee-saved registers moved to the end.
191  ///
192  /// The MachineFunction argument can be used to tune the allocatable
193  /// registers based on the characteristics of the function, subtarget, or
194  /// other criteria.
195  ///
196  /// By default, this method returns all registers in the class.
198  return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
199  }
200 
201  /// Returns the combination of all lane masks of register in this class.
202  /// The lane masks of the registers are the combination of all lane masks
203  /// of their subregisters. Returns 1 if there are no subregisters.
205  return LaneMask;
206  }
207 };
208 
209 /// Extra information, not in MCRegisterDesc, about registers.
210 /// These are used by codegen, not by MC.
212  const uint8_t *CostPerUse; // Extra cost of instructions using register.
213  unsigned NumCosts; // Number of cost values associated with each register.
214  const bool
215  *InAllocatableClass; // Register belongs to an allocatable regclass.
216 };
217 
218 /// Each TargetRegisterClass has a per register weight, and weight
219 /// limit which must be less than the limits of its pressure sets.
221  unsigned RegWeight;
222  unsigned WeightLimit;
223 };
224 
225 /// TargetRegisterInfo base class - We assume that the target defines a static
226 /// array of TargetRegisterDesc objects that represent all of the machine
227 /// registers that the target has. As such, we simply have to track a pointer
228 /// to this array so that we can turn register number into a register
229 /// descriptor.
230 ///
232 public:
233  using regclass_iterator = const TargetRegisterClass * const *;
235  struct RegClassInfo {
238  };
239 private:
240  const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
241  const char *const *SubRegIndexNames; // Names of subreg indexes.
242  // Pointer to array of lane masks, one per sub-reg index.
243  const LaneBitmask *SubRegIndexLaneMasks;
244 
245  regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
246  LaneBitmask CoveringLanes;
247  const RegClassInfo *const RCInfos;
248  unsigned HwMode;
249 
250 protected:
252  regclass_iterator RCB,
253  regclass_iterator RCE,
254  const char *const *SRINames,
255  const LaneBitmask *SRILaneMasks,
256  LaneBitmask CoveringLanes,
257  const RegClassInfo *const RCIs,
258  unsigned Mode = 0);
259  virtual ~TargetRegisterInfo();
260 
261 public:
262  // Register numbers can represent physical registers, virtual registers, and
263  // sometimes stack slots. The unsigned values are divided into these ranges:
264  //
265  // 0 Not a register, can be used as a sentinel.
266  // [1;2^30) Physical registers assigned by TableGen.
267  // [2^30;2^31) Stack slots. (Rarely used.)
268  // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
269  //
270  // Further sentinels can be allocated from the small negative integers.
271  // DenseMapInfo<unsigned> uses -1u and -2u.
272 
273  /// Return the size in bits of a register from class RC.
274  unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
275  return getRegClassInfo(RC).RegSize;
276  }
277 
278  /// Return the size in bytes of the stack slot allocated to hold a spilled
279  /// copy of a register from class RC.
280  unsigned getSpillSize(const TargetRegisterClass &RC) const {
281  return getRegClassInfo(RC).SpillSize / 8;
282  }
283 
284  /// Return the minimum required alignment in bytes for a spill slot for
285  /// a register of this class.
287  return Align(getRegClassInfo(RC).SpillAlignment / 8);
288  }
289 
290  /// Return true if the given TargetRegisterClass has the ValueType T.
291  bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
292  for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
293  if (MVT(*I) == T)
294  return true;
295  return false;
296  }
297 
298  /// Return true if the given TargetRegisterClass is compatible with LLT T.
299  bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const {
300  for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) {
301  MVT VT(*I);
302  if (VT == MVT::Untyped)
303  return true;
304 
305  if (LLT(VT) == T)
306  return true;
307  }
308  return false;
309  }
310 
311  /// Loop over all of the value types that can be represented by values
312  /// in the given register class.
314  return getRegClassInfo(RC).VTList;
315  }
316 
319  while (*I != MVT::Other)
320  ++I;
321  return I;
322  }
323 
324  /// Returns the Register Class of a physical register of the given type,
325  /// picking the most sub register class of the right type that contains this
326  /// physreg.
328  MVT VT = MVT::Other) const;
329 
330  /// Returns the Register Class of a physical register of the given type,
331  /// picking the most sub register class of the right type that contains this
332  /// physreg. If there is no register class compatible with the given type,
333  /// returns nullptr.
335  LLT Ty = LLT()) const;
336 
337  /// Return the maximal subclass of the given register class that is
338  /// allocatable or NULL.
339  const TargetRegisterClass *
340  getAllocatableClass(const TargetRegisterClass *RC) const;
341 
342  /// Returns a bitset indexed by register number indicating if a register is
343  /// allocatable or not. If a register class is specified, returns the subset
344  /// for the class.
346  const TargetRegisterClass *RC = nullptr) const;
347 
348  /// Get a list of cost values for all registers that correspond to the index
349  /// returned by RegisterCostTableIndex.
351  unsigned Idx = getRegisterCostTableIndex(MF);
352  unsigned NumRegs = getNumRegs();
353  assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds");
354 
355  return makeArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
356  }
357 
358  /// Return true if the register is in the allocation of any register class.
359  bool isInAllocatableClass(MCRegister RegNo) const {
360  return InfoDesc->InAllocatableClass[RegNo];
361  }
362 
363  /// Return the human-readable symbolic target-specific
364  /// name for the specified SubRegIndex.
365  const char *getSubRegIndexName(unsigned SubIdx) const {
366  assert(SubIdx && SubIdx < getNumSubRegIndices() &&
367  "This is not a subregister index");
368  return SubRegIndexNames[SubIdx-1];
369  }
370 
371  /// Return a bitmask representing the parts of a register that are covered by
372  /// SubIdx \see LaneBitmask.
373  ///
374  /// SubIdx == 0 is allowed, it has the lane mask ~0u.
375  LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
376  assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
377  return SubRegIndexLaneMasks[SubIdx];
378  }
379 
380  /// Try to find one or more subregister indexes to cover \p LaneMask.
381  ///
382  /// If this is possible, returns true and appends the best matching set of
383  /// indexes to \p Indexes. If this is not possible, returns false.
385  const TargetRegisterClass *RC,
386  LaneBitmask LaneMask,
387  SmallVectorImpl<unsigned> &Indexes) const;
388 
389  /// The lane masks returned by getSubRegIndexLaneMask() above can only be
390  /// used to determine if sub-registers overlap - they can't be used to
391  /// determine if a set of sub-registers completely cover another
392  /// sub-register.
393  ///
394  /// The X86 general purpose registers have two lanes corresponding to the
395  /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
396  /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
397  /// sub_32bit sub-register.
398  ///
399  /// On the other hand, the ARM NEON lanes fully cover their registers: The
400  /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
401  /// This is related to the CoveredBySubRegs property on register definitions.
402  ///
403  /// This function returns a bit mask of lanes that completely cover their
404  /// sub-registers. More precisely, given:
405  ///
406  /// Covering = getCoveringLanes();
407  /// MaskA = getSubRegIndexLaneMask(SubA);
408  /// MaskB = getSubRegIndexLaneMask(SubB);
409  ///
410  /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
411  /// SubB.
412  LaneBitmask getCoveringLanes() const { return CoveringLanes; }
413 
414  /// Returns true if the two registers are equal or alias each other.
415  /// The registers may be virtual registers.
416  bool regsOverlap(Register regA, Register regB) const {
417  if (regA == regB) return true;
418  if (!regA.isPhysical() || !regB.isPhysical())
419  return false;
420 
421  // Regunits are numerically ordered. Find a common unit.
422  MCRegUnitIterator RUA(regA.asMCReg(), this);
423  MCRegUnitIterator RUB(regB.asMCReg(), this);
424  do {
425  if (*RUA == *RUB) return true;
426  if (*RUA < *RUB) ++RUA;
427  else ++RUB;
428  } while (RUA.isValid() && RUB.isValid());
429  return false;
430  }
431 
432  /// Returns true if Reg contains RegUnit.
433  bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
434  for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
435  if (Register(*Units) == RegUnit)
436  return true;
437  return false;
438  }
439 
440  /// Returns the original SrcReg unless it is the target of a copy-like
441  /// operation, in which case we chain backwards through all such operations
442  /// to the ultimate source register. If a physical register is encountered,
443  /// we stop the search.
444  virtual Register lookThruCopyLike(Register SrcReg,
445  const MachineRegisterInfo *MRI) const;
446 
447  /// Find the original SrcReg unless it is the target of a copy-like operation,
448  /// in which case we chain backwards through all such operations to the
449  /// ultimate source register. If a physical register is encountered, we stop
450  /// the search.
451  /// Return the original SrcReg if all the definitions in the chain only have
452  /// one user and not a physical register.
453  virtual Register
455  const MachineRegisterInfo *MRI) const;
456 
457  /// Return a null-terminated list of all of the callee-saved registers on
458  /// this target. The register should be in the order of desired callee-save
459  /// stack frame offset. The first register is closest to the incoming stack
460  /// pointer if stack grows down, and vice versa.
461  /// Notice: This function does not take into account disabled CSRs.
462  /// In most cases you will want to use instead the function
463  /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
464  virtual const MCPhysReg*
465  getCalleeSavedRegs(const MachineFunction *MF) const = 0;
466 
467  /// Return a mask of call-preserved registers for the given calling convention
468  /// on the current function. The mask should include all call-preserved
469  /// aliases. This is used by the register allocator to determine which
470  /// registers can be live across a call.
471  ///
472  /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
473  /// A set bit indicates that all bits of the corresponding register are
474  /// preserved across the function call. The bit mask is expected to be
475  /// sub-register complete, i.e. if A is preserved, so are all its
476  /// sub-registers.
477  ///
478  /// Bits are numbered from the LSB, so the bit for physical register Reg can
479  /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
480  ///
481  /// A NULL pointer means that no register mask will be used, and call
482  /// instructions should use implicit-def operands to indicate call clobbered
483  /// registers.
484  ///
486  CallingConv::ID) const {
487  // The default mask clobbers everything. All targets should override.
488  return nullptr;
489  }
490 
491  /// Return a register mask for the registers preserved by the unwinder,
492  /// or nullptr if no custom mask is needed.
493  virtual const uint32_t *
495  return nullptr;
496  }
497 
498  /// Return a register mask that clobbers everything.
499  virtual const uint32_t *getNoPreservedMask() const {
500  llvm_unreachable("target does not provide no preserved mask");
501  }
502 
503  /// Return a list of all of the registers which are clobbered "inside" a call
504  /// to the given function. For example, these might be needed for PLT
505  /// sequences of long-branch veneers.
506  virtual ArrayRef<MCPhysReg>
508  return {};
509  }
510 
511  /// Return true if all bits that are set in mask \p mask0 are also set in
512  /// \p mask1.
513  bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
514 
515  /// Return all the call-preserved register masks defined for this target.
516  virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
517  virtual ArrayRef<const char *> getRegMaskNames() const = 0;
518 
519  /// Returns a bitset indexed by physical register number indicating if a
520  /// register is a special register that has particular uses and should be
521  /// considered unavailable at all times, e.g. stack pointer, return address.
522  /// A reserved register:
523  /// - is not allocatable
524  /// - is considered always live
525  /// - is ignored by liveness tracking
526  /// It is often necessary to reserve the super registers of a reserved
527  /// register as well, to avoid them getting allocated indirectly. You may use
528  /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
529  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
530 
531  /// Returns false if we can't guarantee that Physreg, specified as an IR asm
532  /// clobber constraint, will be preserved across the statement.
533  virtual bool isAsmClobberable(const MachineFunction &MF,
534  MCRegister PhysReg) const {
535  return true;
536  }
537 
538  /// Returns true if PhysReg cannot be written to in inline asm statements.
539  virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF,
540  unsigned PhysReg) const {
541  return false;
542  }
543 
544  /// Returns true if PhysReg is unallocatable and constant throughout the
545  /// function. Used by MachineRegisterInfo::isConstantPhysReg().
546  virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }
547 
548  /// Returns true if the register class is considered divergent.
549  virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
550  return false;
551  }
552 
553  /// Physical registers that may be modified within a function but are
554  /// guaranteed to be restored before any uses. This is useful for targets that
555  /// have call sequences where a GOT register may be updated by the caller
556  /// prior to a call and is guaranteed to be restored (also by the caller)
557  /// after the call.
558  virtual bool isCallerPreservedPhysReg(MCRegister PhysReg,
559  const MachineFunction &MF) const {
560  return false;
561  }
562 
563  /// This is a wrapper around getCallPreservedMask().
564  /// Return true if the register is preserved after the call.
565  virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
566  const MachineFunction &MF) const;
567 
568  /// Prior to adding the live-out mask to a stackmap or patchpoint
569  /// instruction, provide the target the opportunity to adjust it (mainly to
570  /// remove pseudo-registers that should be ignored).
571  virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
572 
573  /// Return a super-register of the specified register
574  /// Reg so its sub-register of index SubIdx is Reg.
576  const TargetRegisterClass *RC) const {
577  return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
578  }
579 
580  /// Return a subclass of the specified register
581  /// class A so that each register in it has a sub-register of the
582  /// specified sub-register index which is in the specified register class B.
583  ///
584  /// TableGen will synthesize missing A sub-classes.
585  virtual const TargetRegisterClass *
587  const TargetRegisterClass *B, unsigned Idx) const;
588 
589  // For a copy-like instruction that defines a register of class DefRC with
590  // subreg index DefSubReg, reading from another source with class SrcRC and
591  // subregister SrcSubReg return true if this is a preferable copy
592  // instruction or an earlier use should be used.
593  virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
594  unsigned DefSubReg,
595  const TargetRegisterClass *SrcRC,
596  unsigned SrcSubReg) const;
597 
598  /// Returns the largest legal sub-class of RC that
599  /// supports the sub-register index Idx.
600  /// If no such sub-class exists, return NULL.
601  /// If all registers in RC already have an Idx sub-register, return RC.
602  ///
603  /// TableGen generates a version of this function that is good enough in most
604  /// cases. Targets can override if they have constraints that TableGen
605  /// doesn't understand. For example, the x86 sub_8bit sub-register index is
606  /// supported by the full GR32 register class in 64-bit mode, but only by the
607  /// GR32_ABCD regiister class in 32-bit mode.
608  ///
609  /// TableGen will synthesize missing RC sub-classes.
610  virtual const TargetRegisterClass *
611  getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
612  assert(Idx == 0 && "Target has no sub-registers");
613  return RC;
614  }
615 
616  /// Return the subregister index you get from composing
617  /// two subregister indices.
618  ///
619  /// The special null sub-register index composes as the identity.
620  ///
621  /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
622  /// returns c. Note that composeSubRegIndices does not tell you about illegal
623  /// compositions. If R does not have a subreg a, or R:a does not have a subreg
624  /// b, composeSubRegIndices doesn't tell you.
625  ///
626  /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
627  /// ssub_0:S0 - ssub_3:S3 subregs.
628  /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
629  unsigned composeSubRegIndices(unsigned a, unsigned b) const {
630  if (!a) return b;
631  if (!b) return a;
632  return composeSubRegIndicesImpl(a, b);
633  }
634 
635  /// Transforms a LaneMask computed for one subregister to the lanemask that
636  /// would have been computed when composing the subsubregisters with IdxA
637  /// first. @sa composeSubRegIndices()
639  LaneBitmask Mask) const {
640  if (!IdxA)
641  return Mask;
642  return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
643  }
644 
645  /// Transform a lanemask given for a virtual register to the corresponding
646  /// lanemask before using subregister with index \p IdxA.
647  /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
648  /// valie lane mask (no invalid bits set) the following holds:
649  /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
650  /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
651  /// => X1 == Mask
653  LaneBitmask LaneMask) const {
654  if (!IdxA)
655  return LaneMask;
656  return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
657  }
658 
659  /// Debugging helper: dump register in human readable form to dbgs() stream.
660  static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
661  const TargetRegisterInfo *TRI = nullptr);
662 
663 protected:
664  /// Overridden by TableGen in targets that have sub-registers.
665  virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
666  llvm_unreachable("Target has no sub-registers");
667  }
668 
669  /// Overridden by TableGen in targets that have sub-registers.
670  virtual LaneBitmask
672  llvm_unreachable("Target has no sub-registers");
673  }
674 
676  LaneBitmask) const {
677  llvm_unreachable("Target has no sub-registers");
678  }
679 
680  /// Return the register cost table index. This implementation is sufficient
681  /// for most architectures and can be overriden by targets in case there are
682  /// multiple cost values associated with each register.
683  virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const {
684  return 0;
685  }
686 
687 public:
688  /// Find a common super-register class if it exists.
689  ///
690  /// Find a register class, SuperRC and two sub-register indices, PreA and
691  /// PreB, such that:
692  ///
693  /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
694  ///
695  /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
696  ///
697  /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
698  ///
699  /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
700  /// requirements, and there is no register class with a smaller spill size
701  /// that satisfies the requirements.
702  ///
703  /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
704  ///
705  /// Either of the PreA and PreB sub-register indices may be returned as 0. In
706  /// that case, the returned register class will be a sub-class of the
707  /// corresponding argument register class.
708  ///
709  /// The function returns NULL if no register class can be found.
710  const TargetRegisterClass*
711  getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
712  const TargetRegisterClass *RCB, unsigned SubB,
713  unsigned &PreA, unsigned &PreB) const;
714 
715  //===--------------------------------------------------------------------===//
716  // Register Class Information
717  //
718 protected:
720  return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
721  }
722 
723 public:
724  /// Register class iterators
725  regclass_iterator regclass_begin() const { return RegClassBegin; }
726  regclass_iterator regclass_end() const { return RegClassEnd; }
729  }
730 
731  unsigned getNumRegClasses() const {
732  return (unsigned)(regclass_end()-regclass_begin());
733  }
734 
735  /// Returns the register class associated with the enumeration value.
736  /// See class MCOperandInfo.
737  const TargetRegisterClass *getRegClass(unsigned i) const {
738  assert(i < getNumRegClasses() && "Register Class ID out of range");
739  return RegClassBegin[i];
740  }
741 
742  /// Returns the name of the register class.
743  const char *getRegClassName(const TargetRegisterClass *Class) const {
744  return MCRegisterInfo::getRegClassName(Class->MC);
745  }
746 
747  /// Find the largest common subclass of A and B.
748  /// Return NULL if there is no common subclass.
749  const TargetRegisterClass *
751  const TargetRegisterClass *B) const;
752 
753  /// Returns a TargetRegisterClass used for pointer values.
754  /// If a target supports multiple different pointer register classes,
755  /// kind specifies which one is indicated.
756  virtual const TargetRegisterClass *
757  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
758  llvm_unreachable("Target didn't implement getPointerRegClass!");
759  }
760 
761  /// Returns a legal register class to copy a register in the specified class
762  /// to or from. If it is possible to copy the register directly without using
763  /// a cross register class copy, return the specified RC. Returns NULL if it
764  /// is not possible to copy between two registers of the specified class.
765  virtual const TargetRegisterClass *
767  return RC;
768  }
769 
770  /// Returns the largest super class of RC that is legal to use in the current
771  /// sub-target and has the same spill size.
772  /// The returned register class can be used to create virtual registers which
773  /// means that all its registers can be copied and spilled.
774  virtual const TargetRegisterClass *
776  const MachineFunction &) const {
777  /// The default implementation is very conservative and doesn't allow the
778  /// register allocator to inflate register classes.
779  return RC;
780  }
781 
782  /// Return the register pressure "high water mark" for the specific register
783  /// class. The scheduler is in high register pressure mode (for the specific
784  /// register class) if it goes over the limit.
785  ///
786  /// Note: this is the old register pressure model that relies on a manually
787  /// specified representative register class per value type.
788  virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
789  MachineFunction &MF) const {
790  return 0;
791  }
792 
793  /// Return a heuristic for the machine scheduler to compare the profitability
794  /// of increasing one register pressure set versus another. The scheduler
795  /// will prefer increasing the register pressure of the set which returns
796  /// the largest value for this function.
797  virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
798  unsigned PSetID) const {
799  return PSetID;
800  }
801 
802  /// Get the weight in units of pressure for this register class.
803  virtual const RegClassWeight &getRegClassWeight(
804  const TargetRegisterClass *RC) const = 0;
805 
806  /// Returns size in bits of a phys/virtual/generic register.
807  unsigned getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
808 
809  /// Get the weight in units of pressure for this register unit.
810  virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
811 
812  /// Get the number of dimensions of register pressure.
813  virtual unsigned getNumRegPressureSets() const = 0;
814 
815  /// Get the name of this register unit pressure set.
816  virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
817 
818  /// Get the register unit pressure limit for this dimension.
819  /// This limit must be adjusted dynamically for reserved registers.
820  virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
821  unsigned Idx) const = 0;
822 
823  /// Get the dimensions of register pressure impacted by this register class.
824  /// Returns a -1 terminated array of pressure set IDs.
825  virtual const int *getRegClassPressureSets(
826  const TargetRegisterClass *RC) const = 0;
827 
828  /// Get the dimensions of register pressure impacted by this register unit.
829  /// Returns a -1 terminated array of pressure set IDs.
830  virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
831 
832  /// Get a list of 'hint' registers that the register allocator should try
833  /// first when allocating a physical register for the virtual register
834  /// VirtReg. These registers are effectively moved to the front of the
835  /// allocation order. If true is returned, regalloc will try to only use
836  /// hints to the greatest extent possible even if it means spilling.
837  ///
838  /// The Order argument is the allocation order for VirtReg's register class
839  /// as returned from RegisterClassInfo::getOrder(). The hint registers must
840  /// come from Order, and they must not be reserved.
841  ///
842  /// The default implementation of this function will only add target
843  /// independent register allocation hints. Targets that override this
844  /// function should typically call this default implementation as well and
845  /// expect to see generic copy hints added.
846  virtual bool
849  const MachineFunction &MF,
850  const VirtRegMap *VRM = nullptr,
851  const LiveRegMatrix *Matrix = nullptr) const;
852 
853  /// A callback to allow target a chance to update register allocation hints
854  /// when a register is "changed" (e.g. coalesced) to another register.
855  /// e.g. On ARM, some virtual registers should target register pairs,
856  /// if one of pair is coalesced to another register, the allocation hint of
857  /// the other half of the pair should be changed to point to the new register.
858  virtual void updateRegAllocHint(Register Reg, Register NewReg,
859  MachineFunction &MF) const {
860  // Do nothing.
861  }
862 
863  /// Allow the target to reverse allocation order of local live ranges. This
864  /// will generally allocate shorter local live ranges first. For targets with
865  /// many registers, this could reduce regalloc compile time by a large
866  /// factor. It is disabled by default for three reasons:
867  /// (1) Top-down allocation is simpler and easier to debug for targets that
868  /// don't benefit from reversing the order.
869  /// (2) Bottom-up allocation could result in poor evicition decisions on some
870  /// targets affecting the performance of compiled code.
871  /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
872  virtual bool reverseLocalAssignment() const { return false; }
873 
874  /// Add the allocation priority to global and split ranges as well as the
875  /// local ranges when registers are added to the queue.
876  virtual bool addAllocPriorityToGlobalRanges() const { return false; }
877 
878  /// Allow the target to override the cost of using a callee-saved register for
879  /// the first time. Default value of 0 means we will use a callee-saved
880  /// register if it is available.
881  virtual unsigned getCSRFirstUseCost() const { return 0; }
882 
883  /// Returns true if the target requires (and can make use of) the register
884  /// scavenger.
885  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
886  return false;
887  }
888 
889  /// Returns true if the target wants to use frame pointer based accesses to
890  /// spill to the scavenger emergency spill slot.
891  virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
892  return true;
893  }
894 
895  /// Returns true if the target requires post PEI scavenging of registers for
896  /// materializing frame index constants.
897  virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
898  return false;
899  }
900 
901  /// Returns true if the target requires using the RegScavenger directly for
902  /// frame elimination despite using requiresFrameIndexScavenging.
904  const MachineFunction &MF) const {
905  return false;
906  }
907 
908  /// Returns true if the target wants the LocalStackAllocation pass to be run
909  /// and virtual base registers used for more efficient stack access.
910  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
911  return false;
912  }
913 
914  /// Return true if target has reserved a spill slot in the stack frame of
915  /// the given function for the specified register. e.g. On x86, if the frame
916  /// register is required, the first fixed stack object is reserved as its
917  /// spill slot. This tells PEI not to create a new stack frame
918  /// object for the given register. It should be called only after
919  /// determineCalleeSaves().
921  int &FrameIdx) const {
922  return false;
923  }
924 
925  /// Returns true if the live-ins should be tracked after register allocation.
926  virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
927  return true;
928  }
929 
930  /// True if the stack can be realigned for the target.
931  virtual bool canRealignStack(const MachineFunction &MF) const;
932 
933  /// True if storage within the function requires the stack pointer to be
934  /// aligned more than the normal calling convention calls for.
935  virtual bool shouldRealignStack(const MachineFunction &MF) const;
936 
937  /// True if stack realignment is required and still possible.
938  bool hasStackRealignment(const MachineFunction &MF) const {
939  return shouldRealignStack(MF) && canRealignStack(MF);
940  }
941 
942  /// Get the offset from the referenced frame index in the instruction,
943  /// if there is one.
944  virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
945  int Idx) const {
946  return 0;
947  }
948 
949  /// Returns true if the instruction's frame index reference would be better
950  /// served by a base register other than FP or SP.
951  /// Used by LocalStackFrameAllocation to determine which frame index
952  /// references it should create new base registers for.
953  virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
954  return false;
955  }
956 
957  /// Insert defining instruction(s) for a pointer to FrameIdx before
958  /// insertion point I. Return materialized frame pointer.
960  int FrameIdx,
961  int64_t Offset) const {
962  llvm_unreachable("materializeFrameBaseRegister does not exist on this "
963  "target");
964  }
965 
966  /// Resolve a frame index operand of an instruction
967  /// to reference the indicated base register plus offset instead.
968  virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
969  int64_t Offset) const {
970  llvm_unreachable("resolveFrameIndex does not exist on this target");
971  }
972 
973  /// Determine whether a given base register plus offset immediate is
974  /// encodable to resolve a frame index.
975  virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
976  int64_t Offset) const {
977  llvm_unreachable("isFrameOffsetLegal does not exist on this target");
978  }
979 
980  /// Gets the DWARF expression opcodes for \p Offset.
981  virtual void getOffsetOpcodes(const StackOffset &Offset,
982  SmallVectorImpl<uint64_t> &Ops) const;
983 
984  /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
985  DIExpression *
986  prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
987  const StackOffset &Offset) const;
988 
989  /// Spill the register so it can be used by the register scavenger.
990  /// Return true if the register was spilled, false otherwise.
991  /// If this function does not spill the register, the scavenger
992  /// will instead spill it to the emergency spill slot.
996  const TargetRegisterClass *RC,
997  Register Reg) const {
998  return false;
999  }
1000 
1001  /// This method must be overriden to eliminate abstract frame indices from
1002  /// instructions which may use them. The instruction referenced by the
1003  /// iterator contains an MO_FrameIndex operand which must be eliminated by
1004  /// this method. This method may modify or replace the specified instruction,
1005  /// as long as it keeps the iterator pointing at the finished product.
1006  /// SPAdj is the SP adjustment due to call frame setup instruction.
1007  /// FIOperandNum is the FI operand number.
1009  int SPAdj, unsigned FIOperandNum,
1010  RegScavenger *RS = nullptr) const = 0;
1011 
1012  /// Return the assembly name for \p Reg.
1014  // FIXME: We are assuming that the assembly name is equal to the TableGen
1015  // name converted to lower case
1016  //
1017  // The TableGen name is the name of the definition for this register in the
1018  // target's tablegen files. For example, the TableGen name of
1019  // def EAX : Register <...>; is "EAX"
1020  return StringRef(getName(Reg));
1021  }
1022 
1023  //===--------------------------------------------------------------------===//
1024  /// Subtarget Hooks
1025 
1026  /// SrcRC and DstRC will be morphed into NewRC if this returns true.
1028  const TargetRegisterClass *SrcRC,
1029  unsigned SubReg,
1030  const TargetRegisterClass *DstRC,
1031  unsigned DstSubReg,
1032  const TargetRegisterClass *NewRC,
1033  LiveIntervals &LIS) const
1034  { return true; }
1035 
1036  /// Region split has a high compile time cost especially for large live range.
1037  /// This method is used to decide whether or not \p VirtReg should
1038  /// go through this expensive splitting heuristic.
1039  virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF,
1040  const LiveInterval &VirtReg) const;
1041 
1042  /// Last chance recoloring has a high compile time cost especially for
1043  /// targets with a lot of registers.
1044  /// This method is used to decide whether or not \p VirtReg should
1045  /// go through this expensive heuristic.
1046  /// When this target hook is hit, by returning false, there is a high
1047  /// chance that the register allocation will fail altogether (usually with
1048  /// "ran out of registers").
1049  /// That said, this error usually points to another problem in the
1050  /// optimization pipeline.
1051  virtual bool
1053  const LiveInterval &VirtReg) const {
1054  return true;
1055  }
1056 
1057  /// Deferred spilling delays the spill insertion of a virtual register
1058  /// after every other allocation. By deferring the spilling, it is
1059  /// sometimes possible to eliminate that spilling altogether because
1060  /// something else could have been eliminated, thus leaving some space
1061  /// for the virtual register.
1062  /// However, this comes with a compile time impact because it adds one
1063  /// more stage to the greedy register allocator.
1064  /// This method is used to decide whether \p VirtReg should use the deferred
1065  /// spilling stage instead of being spilled right away.
1066  virtual bool
1068  const LiveInterval &VirtReg) const {
1069  return false;
1070  }
1071 
1072  //===--------------------------------------------------------------------===//
1073  /// Debug information queries.
1074 
1075  /// getFrameRegister - This method should return the register used as a base
1076  /// for values allocated in the current stack frame.
1077  virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
1078 
1079  /// Mark a register and all its aliases as reserved in the given set.
1081 
1082  /// Returns true if for every register in the set all super registers are part
1083  /// of the set as well.
1085  ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1086 
1087  virtual const TargetRegisterClass *
1089  const MachineRegisterInfo &MRI) const {
1090  return nullptr;
1091  }
1092 
1093  /// Returns the physical register number of sub-register "Index"
1094  /// for physical register RegNo. Return zero if the sub-register does not
1095  /// exist.
1096  inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
1097  return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx);
1098  }
1099 };
1100 
1101 //===----------------------------------------------------------------------===//
1102 // SuperRegClassIterator
1103 //===----------------------------------------------------------------------===//
1104 //
1105 // Iterate over the possible super-registers for a given register class. The
1106 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
1107 // possible classes of super-registers.
1108 //
1109 // Each bit mask will have at least one set bit, and each set bit in Mask
1110 // corresponds to a SuperRC such that:
1111 //
1112 // For all Reg in SuperRC: Reg:Idx is in RC.
1113 //
1114 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
1115 // also satisfies the above requirement, assuming Reg:0 == Reg.
1116 //
1118  const unsigned RCMaskWords;
1119  unsigned SubReg = 0;
1120  const uint16_t *Idx;
1121  const uint32_t *Mask;
1122 
1123 public:
1124  /// Create a SuperRegClassIterator that visits all the super-register classes
1125  /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1127  const TargetRegisterInfo *TRI,
1128  bool IncludeSelf = false)
1129  : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1130  Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1131  if (!IncludeSelf)
1132  ++*this;
1133  }
1134 
1135  /// Returns true if this iterator is still pointing at a valid entry.
1136  bool isValid() const { return Idx; }
1137 
1138  /// Returns the current sub-register index.
1139  unsigned getSubReg() const { return SubReg; }
1140 
1141  /// Returns the bit mask of register classes that getSubReg() projects into
1142  /// RC.
1143  /// See TargetRegisterClass::getSubClassMask() for how to use it.
1144  const uint32_t *getMask() const { return Mask; }
1145 
1146  /// Advance iterator to the next entry.
1147  void operator++() {
1148  assert(isValid() && "Cannot move iterator past end.");
1149  Mask += RCMaskWords;
1150  SubReg = *Idx++;
1151  if (!SubReg)
1152  Idx = nullptr;
1153  }
1154 };
1155 
1156 //===----------------------------------------------------------------------===//
1157 // BitMaskClassIterator
1158 //===----------------------------------------------------------------------===//
1159 /// This class encapuslates the logic to iterate over bitmask returned by
1160 /// the various RegClass related APIs.
1161 /// E.g., this class can be used to iterate over the subclasses provided by
1162 /// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1164  /// Total number of register classes.
1165  const unsigned NumRegClasses;
1166  /// Base index of CurrentChunk.
1167  /// In other words, the number of bit we read to get at the
1168  /// beginning of that chunck.
1169  unsigned Base = 0;
1170  /// Adjust base index of CurrentChunk.
1171  /// Base index + how many bit we read within CurrentChunk.
1172  unsigned Idx = 0;
1173  /// Current register class ID.
1174  unsigned ID = 0;
1175  /// Mask we are iterating over.
1176  const uint32_t *Mask;
1177  /// Current chunk of the Mask we are traversing.
1178  uint32_t CurrentChunk;
1179 
1180  /// Move ID to the next set bit.
1181  void moveToNextID() {
1182  // If the current chunk of memory is empty, move to the next one,
1183  // while making sure we do not go pass the number of register
1184  // classes.
1185  while (!CurrentChunk) {
1186  // Move to the next chunk.
1187  Base += 32;
1188  if (Base >= NumRegClasses) {
1189  ID = NumRegClasses;
1190  return;
1191  }
1192  CurrentChunk = *++Mask;
1193  Idx = Base;
1194  }
1195  // Otherwise look for the first bit set from the right
1196  // (representation of the class ID is big endian).
1197  // See getSubClassMask for more details on the representation.
1198  unsigned Offset = countTrailingZeros(CurrentChunk);
1199  // Add the Offset to the adjusted base number of this chunk: Idx.
1200  // This is the ID of the register class.
1201  ID = Idx + Offset;
1202 
1203  // Consume the zeros, if any, and the bit we just read
1204  // so that we are at the right spot for the next call.
1205  // Do not do Offset + 1 because Offset may be 31 and 32
1206  // will be UB for the shift, though in that case we could
1207  // have make the chunk being equal to 0, but that would
1208  // have introduced a if statement.
1209  moveNBits(Offset);
1210  moveNBits(1);
1211  }
1212 
1213  /// Move \p NumBits Bits forward in CurrentChunk.
1214  void moveNBits(unsigned NumBits) {
1215  assert(NumBits < 32 && "Undefined behavior spotted!");
1216  // Consume the bit we read for the next call.
1217  CurrentChunk >>= NumBits;
1218  // Adjust the base for the chunk.
1219  Idx += NumBits;
1220  }
1221 
1222 public:
1223  /// Create a BitMaskClassIterator that visits all the register classes
1224  /// represented by \p Mask.
1225  ///
1226  /// \pre \p Mask != nullptr
1228  : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1229  // Move to the first ID.
1230  moveToNextID();
1231  }
1232 
1233  /// Returns true if this iterator is still pointing at a valid entry.
1234  bool isValid() const { return getID() != NumRegClasses; }
1235 
1236  /// Returns the current register class ID.
1237  unsigned getID() const { return ID; }
1238 
1239  /// Advance iterator to the next entry.
1240  void operator++() {
1241  assert(isValid() && "Cannot move iterator past end.");
1242  moveToNextID();
1243  }
1244 };
1245 
1246 // This is useful when building IndexedMaps keyed on virtual registers
1249  unsigned operator()(Register Reg) const {
1250  return Register::virtReg2Index(Reg);
1251  }
1252 };
1253 
1254 /// Prints virtual and physical registers with or without a TRI instance.
1255 ///
1256 /// The format is:
1257 /// %noreg - NoRegister
1258 /// %5 - a virtual register.
1259 /// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1260 /// %eax - a physical register
1261 /// %physreg17 - a physical register when no TRI instance given.
1262 ///
1263 /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1264 Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
1265  unsigned SubIdx = 0,
1266  const MachineRegisterInfo *MRI = nullptr);
1267 
1268 /// Create Printable object to print register units on a \ref raw_ostream.
1269 ///
1270 /// Register units are named after their root registers:
1271 ///
1272 /// al - Single root.
1273 /// fp0~st7 - Dual roots.
1274 ///
1275 /// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1276 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1277 
1278 /// Create Printable object to print virtual registers and physical
1279 /// registers on a \ref raw_ostream.
1280 Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1281 
1282 /// Create Printable object to print register classes or register banks
1283 /// on a \ref raw_ostream.
1284 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
1285  const TargetRegisterInfo *TRI);
1286 
1287 } // end namespace llvm
1288 
1289 #endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
llvm::TargetRegisterInfo::trackLivenessAfterRegAlloc
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
Definition: TargetRegisterInfo.h:926
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::TargetRegisterInfo::getRegAsmName
virtual StringRef getRegAsmName(MCRegister Reg) const
Return the assembly name for Reg.
Definition: TargetRegisterInfo.h:1013
i
i
Definition: README.txt:29
llvm::TargetRegisterInfoDesc::InAllocatableClass
const bool * InAllocatableClass
Definition: TargetRegisterInfo.h:215
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:611
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:775
llvm::TargetRegisterInfo::getConstrainedRegClassForOperand
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
Definition: TargetRegisterInfo.h:1088
llvm::TargetRegisterInfo::shouldRegionSplitForVirtReg
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
Definition: TargetRegisterInfo.cpp:68
llvm::TargetRegisterInfo::~TargetRegisterInfo
virtual ~TargetRegisterInfo()
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
MathExtras.h
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:69
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::TargetRegisterInfo::shouldUseLastChanceRecoloringForVirtReg
virtual bool shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Last chance recoloring has a high compile time cost especially for targets with a lot of registers.
Definition: TargetRegisterInfo.h:1052
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::SuperRegClassIterator::getSubReg
unsigned getSubReg() const
Returns the current sub-register index.
Definition: TargetRegisterInfo.h:1139
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::TargetRegisterInfo::getCrossCopyRegClass
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
Definition: TargetRegisterInfo.h:766
llvm::TargetRegisterClass::isASubClass
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
Definition: TargetRegisterInfo.h:180
llvm::TargetRegisterInfo::getIntraCallClobberedRegs
virtual ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const
Return a list of all of the registers which are clobbered "inside" a call to the given function.
Definition: TargetRegisterInfo.h:507
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::TargetRegisterInfo::resolveFrameIndex
virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...
Definition: TargetRegisterInfo.h:968
llvm::TargetRegisterClass::getLaneMask
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
Definition: TargetRegisterInfo.h:204
llvm::printVRegOrUnit
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Definition: TargetRegisterInfo.cpp:164
llvm::MCRegisterClass::end
iterator end() const
Definition: MCRegisterInfo.h:53
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:115
llvm::VirtReg2IndexFunctor
Definition: TargetRegisterInfo.h:1247
llvm::MCRegisterClass::getNumRegs
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
Definition: MCRegisterInfo.h:57
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
Printable.h
StringRef.h
llvm::TargetRegisterInfo::dumpReg
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
Definition: TargetRegisterInfo.cpp:669
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
llvm::TargetRegisterInfo::getRegMaskNames
virtual ArrayRef< const char * > getRegMaskNames() const =0
llvm::TargetRegisterInfo::getRegisterCosts
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
Definition: TargetRegisterInfo.h:350
llvm::TargetRegisterInfo::getMinimalPhysRegClassLLT
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:229
llvm::TargetRegisterInfo::isInAllocatableClass
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition: TargetRegisterInfo.h:359
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1136
llvm::TargetRegisterInfo::isConstantPhysReg
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: TargetRegisterInfo.h:546
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:255
llvm::TargetRegisterInfo::getOffsetOpcodes
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
Definition: TargetRegisterInfo.cpp:642
llvm::TargetRegisterInfo::isAsmClobberable
virtual bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const
Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint,...
Definition: TargetRegisterInfo.h:533
llvm::TargetRegisterInfo::shouldRealignStack
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
Definition: TargetRegisterInfo.cpp:482
llvm::TargetRegisterInfo::updateRegAllocHint
virtual void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
Definition: TargetRegisterInfo.h:858
MachineBasicBlock.h
llvm::TargetRegisterInfoDesc::NumCosts
unsigned NumCosts
Definition: TargetRegisterInfo.h:213
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::TargetRegisterClass::getCopyCost
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Definition: TargetRegisterInfo.h:111
llvm::TargetRegisterInfo::markSuperRegs
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
Definition: TargetRegisterInfo.cpp:79
llvm::TargetRegisterInfo::getRegisterCostTableIndex
virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const
Return the register cost table index.
Definition: TargetRegisterInfo.h:683
llvm::TargetRegisterInfo::regclass_begin
regclass_iterator regclass_begin() const
Register class iterators.
Definition: TargetRegisterInfo.h:725
llvm::TargetRegisterInfo::requiresFrameIndexScavenging
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
Definition: TargetRegisterInfo.h:897
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::TargetRegisterInfo::getCSRFirstUseCost
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time.
Definition: TargetRegisterInfo.h:881
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::TargetRegisterInfo::isCalleeSavedPhysReg
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
Definition: TargetRegisterInfo.cpp:464
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2557
llvm::TargetRegisterInfo::getRegPressureSetLimit
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
llvm::TargetRegisterInfo::RegClassInfo
Definition: TargetRegisterInfo.h:235
llvm::TargetRegisterInfo::getRegClassInfo
const RegClassInfo & getRegClassInfo(const TargetRegisterClass &RC) const
Definition: TargetRegisterInfo.h:719
RegisterSet
SmallSet< unsigned, 4 > RegisterSet
Definition: Thumb2ITBlockPass.cpp:39
llvm::TargetRegisterInfo::useFPForScavengingIndex
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
Definition: TargetRegisterInfo.h:891
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::TargetRegisterClass::SubClassMask
const uint32_t * SubClassMask
Definition: TargetRegisterInfo.h:54
llvm::MCRegisterInfo::getNumSubRegIndices
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
Definition: MCRegisterInfo.h:498
llvm::TargetRegisterClass::getSubClassMask
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
Definition: TargetRegisterInfo.h:156
llvm::TargetRegisterInfo::legalclasstypes_end
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
Definition: TargetRegisterInfo.h:317
llvm::BitMaskClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1234
llvm::MCRegisterClass::getCopyCost
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
Definition: MCRegisterInfo.h:91
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:33
llvm::TargetRegisterInfo::getCalleeSavedRegs
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
llvm::TargetRegisterInfo::RegClassInfo::RegSize
unsigned RegSize
Definition: TargetRegisterInfo.h:236
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::SuperRegClassIterator::SuperRegClassIterator
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
Definition: TargetRegisterInfo.h:1126
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:91
llvm::TargetRegisterInfo::getRegUnitWeight
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:478
llvm::TargetRegisterInfoDesc::CostPerUse
const uint8_t * CostPerUse
Definition: TargetRegisterInfo.h:212
llvm::TargetRegisterInfo::getRegUnitPressureSets
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:375
llvm::TargetRegisterClass::SuperRegIndices
const uint16_t * SuperRegIndices
Definition: TargetRegisterInfo.h:55
llvm::TargetRegisterClass::CoveredBySubRegs
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
Definition: TargetRegisterInfo.h:64
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:197
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const
Return true if the given TargetRegisterClass is compatible with LLT T.
Definition: TargetRegisterInfo.h:299
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetRegisterInfo::hasRegUnit
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
Definition: TargetRegisterInfo.h:433
llvm::TargetRegisterInfo::getRegClassPressureSets
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
b
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Definition: README.txt:418
llvm::TargetRegisterClass::AllocationPriority
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
Definition: TargetRegisterInfo.h:59
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::TargetRegisterInfo::composeSubRegIndicesImpl
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
Definition: TargetRegisterInfo.h:665
llvm::MCRegisterClass::getRegister
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
Definition: MCRegisterInfo.h:61
llvm::TargetRegisterInfo::requiresVirtualBaseRegisters
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
Definition: TargetRegisterInfo.h:910
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:136
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:416
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:302
llvm::BitVector
Definition: BitVector.h:74
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::TargetRegisterClass::hasSuperClass
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:131
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::TargetRegisterClass::OrderFunc
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &)
Definition: TargetRegisterInfo.h:66
llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Definition: TargetRegisterInfo.h:675
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1117
llvm::TargetRegisterInfo::isCallerPreservedPhysReg
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
Definition: TargetRegisterInfo.h:558
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:141
llvm::MCRegisterClass::begin
iterator begin() const
begin/end - Return all of the registers in this class.
Definition: MCRegisterInfo.h:52
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:757
llvm::TargetRegisterInfo::regclasses
iterator_range< regclass_iterator > regclasses() const
Definition: TargetRegisterInfo.h:727
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:491
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:286
llvm::RegClassWeight
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
Definition: TargetRegisterInfo.h:220
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:280
llvm::TargetRegisterClass::LaneMask
const LaneBitmask LaneMask
Definition: TargetRegisterInfo.h:56
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:737
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::TargetRegisterInfo::saveScavengerRegister
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
Definition: TargetRegisterInfo.h:993
llvm::VirtReg2IndexFunctor::operator()
unsigned operator()(Register Reg) const
Definition: TargetRegisterInfo.h:1249
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:743
llvm::TargetRegisterInfo::getCommonSuperRegClass
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
Definition: TargetRegisterInfo.cpp:318
llvm::SuperRegClassIterator::operator++
void operator++()
Advance iterator to the next entry.
Definition: TargetRegisterInfo.h:1147
llvm::TargetRegisterClass::SuperClasses
const sc_iterator SuperClasses
Definition: TargetRegisterInfo.h:65
llvm::TargetRegisterInfo::getFrameRegister
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:575
llvm::TargetRegisterClass::HasDisjunctSubRegs
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
Definition: TargetRegisterInfo.h:61
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetRegisterInfo::getNumRegPressureSets
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:421
llvm::TargetRegisterInfo::eliminateFrameIndex
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
llvm::TargetRegisterInfo::reverseLocalAssignment
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
Definition: TargetRegisterInfo.h:872
MCRegisterInfo.h
llvm::TargetRegisterInfo::regclass_end
regclass_iterator regclass_end() const
Definition: TargetRegisterInfo.h:726
ArrayRef.h
llvm::TargetRegisterInfo::getRegPressureSetName
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetRegisterInfo::composeSubRegIndexLaneMaskImpl
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
Definition: TargetRegisterInfo.h:671
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:288
iterator_range.h
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::Register::asMCReg
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
Definition: Register.h:120
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::TargetRegisterInfo::needsFrameBaseReg
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction's frame index reference would be better served by a base register oth...
Definition: TargetRegisterInfo.h:953
llvm::RegClassWeight::RegWeight
unsigned RegWeight
Definition: TargetRegisterInfo.h:221
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:174
llvm::TargetRegisterInfo::TargetRegisterInfo
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0)
Definition: TargetRegisterInfo.cpp:52
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::BitMaskClassIterator::BitMaskClassIterator
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask.
Definition: TargetRegisterInfo.h:1227
llvm::TargetRegisterInfo::shouldCoalesce
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
Definition: TargetRegisterInfo.h:1027
RegInfo
Definition: AMDGPUAsmParser.cpp:2366
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:629
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::TargetRegisterInfo::getCoveringSubRegIndexes
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
Definition: TargetRegisterInfo.cpp:523
llvm::MCRegisterClass::getID
unsigned getID() const
getID() - Return the register class ID number.
Definition: MCRegisterInfo.h:48
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:291
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::RegClassWeight::WeightLimit
unsigned WeightLimit
Definition: TargetRegisterInfo.h:222
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCRegisterInfo::getRegClassName
const char * getRegClassName(const MCRegisterClass *Class) const
Definition: MCRegisterInfo.h:548
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetRegisterInfo::isInlineAsmReadOnlyReg
virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) const
Returns true if PhysReg cannot be written to in inline asm statements.
Definition: TargetRegisterInfo.h:539
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetRegisterInfo::lookThruSingleUseCopyChain
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
Definition: TargetRegisterInfo.cpp:617
llvm::BitMaskClassIterator::operator++
void operator++()
Advance iterator to the next entry.
Definition: TargetRegisterInfo.h:1240
llvm::TargetRegisterInfo::shouldRewriteCopySrc
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Definition: TargetRegisterInfo.cpp:412
llvm::TargetRegisterClass::getNumRegs
unsigned getNumRegs() const
Return the number of registers in this class.
Definition: TargetRegisterInfo.h:77
llvm::TargetRegisterInfo::shouldUseDeferredSpillingForVirtReg
virtual bool shouldUseDeferredSpillingForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Deferred spilling delays the spill insertion of a virtual register after every other allocation.
Definition: TargetRegisterInfo.h:1067
llvm::TargetRegisterClass::begin
iterator begin() const
begin/end - Return all of the registers in this class.
Definition: TargetRegisterInfo.h:73
llvm::TargetRegisterInfo::lookThruCopyLike
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Definition: TargetRegisterInfo.cpp:595
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:274
uint16_t
llvm::TargetRegisterClass::getRegister
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
Definition: TargetRegisterInfo.h:85
llvm::TargetRegisterClass::getSuperClasses
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
Definition: TargetRegisterInfo.h:174
llvm::TargetRegisterInfo::getCustomEHPadPreservedMask
virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...
Definition: TargetRegisterInfo.h:494
llvm::TargetRegisterInfo::isDivergentRegClass
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
Definition: TargetRegisterInfo.h:549
llvm::TargetRegisterInfo::composeSubRegIndexLaneMask
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
Definition: TargetRegisterInfo.h:638
llvm::TargetRegisterClass::getSuperRegIndices
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
Definition: TargetRegisterInfo.h:167
llvm::TargetRegisterInfo::getFrameIndexInstrOffset
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
Definition: TargetRegisterInfo.h:944
llvm::TargetRegisterInfo::getRegPressureSetScore
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
Definition: TargetRegisterInfo.h:797
llvm::TargetRegisterClass::sc_iterator
const TargetRegisterClass *const * sc_iterator
Definition: TargetRegisterInfo.h:50
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::TargetRegisterInfo::RegClassInfo::VTList
vt_iterator VTList
Definition: TargetRegisterInfo.h:237
llvm::TargetRegisterClass::contains
bool contains(Register Reg1, Register Reg2) const
Return true if both registers are in this class.
Definition: TargetRegisterInfo.h:100
llvm::TargetRegisterClass::MC
const MCRegisterClass * MC
Definition: TargetRegisterInfo.h:53
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:731
llvm::TargetRegisterInfo::getNoPreservedMask
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
Definition: TargetRegisterInfo.h:499
llvm::TargetRegisterInfo::regclass_iterator
const TargetRegisterClass *const * regclass_iterator
Definition: TargetRegisterInfo.h:233
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:476
llvm::TargetRegisterInfo::hasStackRealignment
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
Definition: TargetRegisterInfo.h:938
llvm::TargetRegisterInfo::materializeFrameBaseRegister
virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for a pointer to FrameIdx before insertion point I.
Definition: TargetRegisterInfo.h:959
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:677
llvm::TargetRegisterClass::hasSubClass
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:119
llvm::TargetRegisterInfo::addAllocPriorityToGlobalRanges
virtual bool addAllocPriorityToGlobalRanges() const
Add the allocation priority to global and split ranges as well as the local ranges when registers are...
Definition: TargetRegisterInfo.h:876
llvm::TargetRegisterInfo::requiresRegisterScavenging
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger.
Definition: TargetRegisterInfo.h:885
SmallVector.h
llvm::TargetRegisterInfo::getCoveringLanes
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
Definition: TargetRegisterInfo.h:412
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::SuperRegClassIterator::getMask
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
Definition: TargetRegisterInfo.h:1144
llvm::TargetRegisterInfo::getRegClassWeight
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
LaneBitmask.h
llvm::TargetRegisterInfoDesc
Extra information, not in MCRegisterDesc, about registers.
Definition: TargetRegisterInfo.h:211
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:194
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::TargetRegisterInfo::RegClassInfo::SpillSize
unsigned SpillSize
Definition: TargetRegisterInfo.h:236
llvm::MVT::Untyped
@ Untyped
Definition: MachineValueType.h:266
llvm::SmallVectorImpl< unsigned >
llvm::MCRegisterClass::isAllocatable
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
Definition: MCRegisterInfo.h:95
llvm::BitMaskClassIterator
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
Definition: TargetRegisterInfo.h:1163
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1096
llvm::TargetRegisterInfo::checkAllSuperRegsMarked
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
Definition: TargetRegisterInfo.cpp:85
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:124
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::TargetRegisterInfo::isFrameOffsetLegal
virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index.
Definition: TargetRegisterInfo.h:975
llvm::TargetRegisterInfo::adjustStackMapLiveOutMask
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
Definition: TargetRegisterInfo.h:571
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:365
llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMask
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
Definition: TargetRegisterInfo.h:652
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::TargetRegisterInfo::RegClassInfo::SpillAlignment
unsigned SpillAlignment
Definition: TargetRegisterInfo.h:236
llvm::TargetRegisterInfo::hasReservedSpillSlot
virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
Definition: TargetRegisterInfo.h:920
llvm::TargetRegisterClass::end
iterator end() const
Definition: TargetRegisterInfo.h:74
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:485
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:80
llvm::BitMaskClassIterator::getID
unsigned getID() const
Returns the current register class ID.
Definition: TargetRegisterInfo.h:1237
llvm::TargetRegisterInfo::prependOffsetExpression
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
Definition: TargetRegisterInfo.cpp:649
llvm::TargetRegisterInfo::getRegMasks
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
llvm::TargetRegisterInfo::getRegPressureLimit
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
Definition: TargetRegisterInfo.h:788
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::TargetRegisterInfo::legalclasstypes_begin
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
Definition: TargetRegisterInfo.h:313
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::TargetRegisterInfo::requiresFrameIndexReplacementScavenging
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
Definition: TargetRegisterInfo.h:903
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40
llvm::LLT
Definition: LowLevelTypeImpl.h:40