LLVM 22.0.0git
NVVMIntrinsicUtils.h
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1//===--- NVVMIntrinsicUtils.h -----------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file contains the definitions of the enumerations and flags
11/// associated with NVVM Intrinsics, along with some helper functions.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_IR_NVVMINTRINSICUTILS_H
16#define LLVM_IR_NVVMINTRINSICUTILS_H
17
18#include <stdint.h>
19
20#include "llvm/ADT/APFloat.h"
21#include "llvm/IR/Intrinsics.h"
22#include "llvm/IR/IntrinsicsNVPTX.h"
23
24namespace llvm {
25namespace nvvm {
26
27// Reduction Ops supported with TMA Copy from Shared
28// to Global Memory for the "cp.reduce.async.bulk.tensor.*"
29// family of PTX instructions.
30enum class TMAReductionOp : uint8_t {
31 ADD = 0,
32 MIN = 1,
33 MAX = 2,
34 INC = 3,
35 DEC = 4,
36 AND = 5,
37 OR = 6,
38 XOR = 7,
39};
40
41// Enum to represent the cta_group::1 and
42// cta_group::2 variants in TMA/TCGEN05 family of
43// PTX instructions.
44enum class CTAGroupKind : uint8_t {
45 CG_NONE = 0, // default with no cta_group modifier
46 CG_1 = 1, // cta_group::1 modifier
47 CG_2 = 2, // cta_group::2 modifier
48};
49
50enum class Tcgen05MMAKind : uint8_t { F16 = 0, TF32 = 1, F8F6F4 = 2, I8 = 3 };
51
52enum class Tcgen05CollectorUsageOp : uint8_t {
53 DISCARD = 0,
54 LASTUSE = 1,
55 FILL = 2,
56 USE = 3,
57};
58
59inline bool FPToIntegerIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID) {
60 switch (IntrinsicID) {
61 case Intrinsic::nvvm_f2i_rm_ftz:
62 case Intrinsic::nvvm_f2i_rn_ftz:
63 case Intrinsic::nvvm_f2i_rp_ftz:
64 case Intrinsic::nvvm_f2i_rz_ftz:
65
66 case Intrinsic::nvvm_f2ui_rm_ftz:
67 case Intrinsic::nvvm_f2ui_rn_ftz:
68 case Intrinsic::nvvm_f2ui_rp_ftz:
69 case Intrinsic::nvvm_f2ui_rz_ftz:
70
71 case Intrinsic::nvvm_f2ll_rm_ftz:
72 case Intrinsic::nvvm_f2ll_rn_ftz:
73 case Intrinsic::nvvm_f2ll_rp_ftz:
74 case Intrinsic::nvvm_f2ll_rz_ftz:
75
76 case Intrinsic::nvvm_f2ull_rm_ftz:
77 case Intrinsic::nvvm_f2ull_rn_ftz:
78 case Intrinsic::nvvm_f2ull_rp_ftz:
79 case Intrinsic::nvvm_f2ull_rz_ftz:
80 return true;
81
82 case Intrinsic::nvvm_f2i_rm:
83 case Intrinsic::nvvm_f2i_rn:
84 case Intrinsic::nvvm_f2i_rp:
85 case Intrinsic::nvvm_f2i_rz:
86
87 case Intrinsic::nvvm_f2ui_rm:
88 case Intrinsic::nvvm_f2ui_rn:
89 case Intrinsic::nvvm_f2ui_rp:
90 case Intrinsic::nvvm_f2ui_rz:
91
92 case Intrinsic::nvvm_d2i_rm:
93 case Intrinsic::nvvm_d2i_rn:
94 case Intrinsic::nvvm_d2i_rp:
95 case Intrinsic::nvvm_d2i_rz:
96
97 case Intrinsic::nvvm_d2ui_rm:
98 case Intrinsic::nvvm_d2ui_rn:
99 case Intrinsic::nvvm_d2ui_rp:
100 case Intrinsic::nvvm_d2ui_rz:
101
102 case Intrinsic::nvvm_f2ll_rm:
103 case Intrinsic::nvvm_f2ll_rn:
104 case Intrinsic::nvvm_f2ll_rp:
105 case Intrinsic::nvvm_f2ll_rz:
106
107 case Intrinsic::nvvm_f2ull_rm:
108 case Intrinsic::nvvm_f2ull_rn:
109 case Intrinsic::nvvm_f2ull_rp:
110 case Intrinsic::nvvm_f2ull_rz:
111
112 case Intrinsic::nvvm_d2ll_rm:
113 case Intrinsic::nvvm_d2ll_rn:
114 case Intrinsic::nvvm_d2ll_rp:
115 case Intrinsic::nvvm_d2ll_rz:
116
117 case Intrinsic::nvvm_d2ull_rm:
118 case Intrinsic::nvvm_d2ull_rn:
119 case Intrinsic::nvvm_d2ull_rp:
120 case Intrinsic::nvvm_d2ull_rz:
121 return false;
122 }
123 llvm_unreachable("Checking FTZ flag for invalid f2i/d2i intrinsic");
124}
125
126inline bool FPToIntegerIntrinsicResultIsSigned(Intrinsic::ID IntrinsicID) {
127 switch (IntrinsicID) {
128 // f2i
129 case Intrinsic::nvvm_f2i_rm:
130 case Intrinsic::nvvm_f2i_rm_ftz:
131 case Intrinsic::nvvm_f2i_rn:
132 case Intrinsic::nvvm_f2i_rn_ftz:
133 case Intrinsic::nvvm_f2i_rp:
134 case Intrinsic::nvvm_f2i_rp_ftz:
135 case Intrinsic::nvvm_f2i_rz:
136 case Intrinsic::nvvm_f2i_rz_ftz:
137 // d2i
138 case Intrinsic::nvvm_d2i_rm:
139 case Intrinsic::nvvm_d2i_rn:
140 case Intrinsic::nvvm_d2i_rp:
141 case Intrinsic::nvvm_d2i_rz:
142 // f2ll
143 case Intrinsic::nvvm_f2ll_rm:
144 case Intrinsic::nvvm_f2ll_rm_ftz:
145 case Intrinsic::nvvm_f2ll_rn:
146 case Intrinsic::nvvm_f2ll_rn_ftz:
147 case Intrinsic::nvvm_f2ll_rp:
148 case Intrinsic::nvvm_f2ll_rp_ftz:
149 case Intrinsic::nvvm_f2ll_rz:
150 case Intrinsic::nvvm_f2ll_rz_ftz:
151 // d2ll
152 case Intrinsic::nvvm_d2ll_rm:
153 case Intrinsic::nvvm_d2ll_rn:
154 case Intrinsic::nvvm_d2ll_rp:
155 case Intrinsic::nvvm_d2ll_rz:
156 return true;
157
158 // f2ui
159 case Intrinsic::nvvm_f2ui_rm:
160 case Intrinsic::nvvm_f2ui_rm_ftz:
161 case Intrinsic::nvvm_f2ui_rn:
162 case Intrinsic::nvvm_f2ui_rn_ftz:
163 case Intrinsic::nvvm_f2ui_rp:
164 case Intrinsic::nvvm_f2ui_rp_ftz:
165 case Intrinsic::nvvm_f2ui_rz:
166 case Intrinsic::nvvm_f2ui_rz_ftz:
167 // d2ui
168 case Intrinsic::nvvm_d2ui_rm:
169 case Intrinsic::nvvm_d2ui_rn:
170 case Intrinsic::nvvm_d2ui_rp:
171 case Intrinsic::nvvm_d2ui_rz:
172 // f2ull
173 case Intrinsic::nvvm_f2ull_rm:
174 case Intrinsic::nvvm_f2ull_rm_ftz:
175 case Intrinsic::nvvm_f2ull_rn:
176 case Intrinsic::nvvm_f2ull_rn_ftz:
177 case Intrinsic::nvvm_f2ull_rp:
178 case Intrinsic::nvvm_f2ull_rp_ftz:
179 case Intrinsic::nvvm_f2ull_rz:
180 case Intrinsic::nvvm_f2ull_rz_ftz:
181 // d2ull
182 case Intrinsic::nvvm_d2ull_rm:
183 case Intrinsic::nvvm_d2ull_rn:
184 case Intrinsic::nvvm_d2ull_rp:
185 case Intrinsic::nvvm_d2ull_rz:
186 return false;
187 }
188 llvm_unreachable(
189 "Checking invalid f2i/d2i intrinsic for signed int conversion");
190}
191
192inline bool FPToIntegerIntrinsicNaNZero(Intrinsic::ID IntrinsicID) {
193 switch (IntrinsicID) {
194 // f2i
195 case Intrinsic::nvvm_f2i_rm:
196 case Intrinsic::nvvm_f2i_rn:
197 case Intrinsic::nvvm_f2i_rp:
198 case Intrinsic::nvvm_f2i_rz:
199 case Intrinsic::nvvm_f2i_rm_ftz:
200 case Intrinsic::nvvm_f2i_rn_ftz:
201 case Intrinsic::nvvm_f2i_rp_ftz:
202 case Intrinsic::nvvm_f2i_rz_ftz:
203 // f2ui
204 case Intrinsic::nvvm_f2ui_rm:
205 case Intrinsic::nvvm_f2ui_rn:
206 case Intrinsic::nvvm_f2ui_rp:
207 case Intrinsic::nvvm_f2ui_rz:
208 case Intrinsic::nvvm_f2ui_rm_ftz:
209 case Intrinsic::nvvm_f2ui_rn_ftz:
210 case Intrinsic::nvvm_f2ui_rp_ftz:
211 case Intrinsic::nvvm_f2ui_rz_ftz:
212 return true;
213 // d2i
214 case Intrinsic::nvvm_d2i_rm:
215 case Intrinsic::nvvm_d2i_rn:
216 case Intrinsic::nvvm_d2i_rp:
217 case Intrinsic::nvvm_d2i_rz:
218 // d2ui
219 case Intrinsic::nvvm_d2ui_rm:
220 case Intrinsic::nvvm_d2ui_rn:
221 case Intrinsic::nvvm_d2ui_rp:
222 case Intrinsic::nvvm_d2ui_rz:
223 // f2ll
224 case Intrinsic::nvvm_f2ll_rm:
225 case Intrinsic::nvvm_f2ll_rn:
226 case Intrinsic::nvvm_f2ll_rp:
227 case Intrinsic::nvvm_f2ll_rz:
228 case Intrinsic::nvvm_f2ll_rm_ftz:
229 case Intrinsic::nvvm_f2ll_rn_ftz:
230 case Intrinsic::nvvm_f2ll_rp_ftz:
231 case Intrinsic::nvvm_f2ll_rz_ftz:
232 // f2ull
233 case Intrinsic::nvvm_f2ull_rm:
234 case Intrinsic::nvvm_f2ull_rn:
235 case Intrinsic::nvvm_f2ull_rp:
236 case Intrinsic::nvvm_f2ull_rz:
237 case Intrinsic::nvvm_f2ull_rm_ftz:
238 case Intrinsic::nvvm_f2ull_rn_ftz:
239 case Intrinsic::nvvm_f2ull_rp_ftz:
240 case Intrinsic::nvvm_f2ull_rz_ftz:
241 // d2ll
242 case Intrinsic::nvvm_d2ll_rm:
243 case Intrinsic::nvvm_d2ll_rn:
244 case Intrinsic::nvvm_d2ll_rp:
245 case Intrinsic::nvvm_d2ll_rz:
246 // d2ull
247 case Intrinsic::nvvm_d2ull_rm:
248 case Intrinsic::nvvm_d2ull_rn:
249 case Intrinsic::nvvm_d2ull_rp:
250 case Intrinsic::nvvm_d2ull_rz:
251 return false;
252 }
253 llvm_unreachable("Checking NaN result for invalid f2i/d2i intrinsic");
254}
255
256inline APFloat::roundingMode
257GetFPToIntegerRoundingMode(Intrinsic::ID IntrinsicID) {
258 switch (IntrinsicID) {
259 // RM:
260 case Intrinsic::nvvm_f2i_rm:
261 case Intrinsic::nvvm_f2ui_rm:
262 case Intrinsic::nvvm_f2i_rm_ftz:
263 case Intrinsic::nvvm_f2ui_rm_ftz:
264 case Intrinsic::nvvm_d2i_rm:
265 case Intrinsic::nvvm_d2ui_rm:
266
267 case Intrinsic::nvvm_f2ll_rm:
268 case Intrinsic::nvvm_f2ull_rm:
269 case Intrinsic::nvvm_f2ll_rm_ftz:
270 case Intrinsic::nvvm_f2ull_rm_ftz:
271 case Intrinsic::nvvm_d2ll_rm:
272 case Intrinsic::nvvm_d2ull_rm:
273 return APFloat::rmTowardNegative;
274
275 // RN:
276 case Intrinsic::nvvm_f2i_rn:
277 case Intrinsic::nvvm_f2ui_rn:
278 case Intrinsic::nvvm_f2i_rn_ftz:
279 case Intrinsic::nvvm_f2ui_rn_ftz:
280 case Intrinsic::nvvm_d2i_rn:
281 case Intrinsic::nvvm_d2ui_rn:
282
283 case Intrinsic::nvvm_f2ll_rn:
284 case Intrinsic::nvvm_f2ull_rn:
285 case Intrinsic::nvvm_f2ll_rn_ftz:
286 case Intrinsic::nvvm_f2ull_rn_ftz:
287 case Intrinsic::nvvm_d2ll_rn:
288 case Intrinsic::nvvm_d2ull_rn:
289 return APFloat::rmNearestTiesToEven;
290
291 // RP:
292 case Intrinsic::nvvm_f2i_rp:
293 case Intrinsic::nvvm_f2ui_rp:
294 case Intrinsic::nvvm_f2i_rp_ftz:
295 case Intrinsic::nvvm_f2ui_rp_ftz:
296 case Intrinsic::nvvm_d2i_rp:
297 case Intrinsic::nvvm_d2ui_rp:
298
299 case Intrinsic::nvvm_f2ll_rp:
300 case Intrinsic::nvvm_f2ull_rp:
301 case Intrinsic::nvvm_f2ll_rp_ftz:
302 case Intrinsic::nvvm_f2ull_rp_ftz:
303 case Intrinsic::nvvm_d2ll_rp:
304 case Intrinsic::nvvm_d2ull_rp:
305 return APFloat::rmTowardPositive;
306
307 // RZ:
308 case Intrinsic::nvvm_f2i_rz:
309 case Intrinsic::nvvm_f2ui_rz:
310 case Intrinsic::nvvm_f2i_rz_ftz:
311 case Intrinsic::nvvm_f2ui_rz_ftz:
312 case Intrinsic::nvvm_d2i_rz:
313 case Intrinsic::nvvm_d2ui_rz:
314
315 case Intrinsic::nvvm_f2ll_rz:
316 case Intrinsic::nvvm_f2ull_rz:
317 case Intrinsic::nvvm_f2ll_rz_ftz:
318 case Intrinsic::nvvm_f2ull_rz_ftz:
319 case Intrinsic::nvvm_d2ll_rz:
320 case Intrinsic::nvvm_d2ull_rz:
321 return APFloat::rmTowardZero;
322 }
323 llvm_unreachable("Checking rounding mode for invalid f2i/d2i intrinsic");
324}
325
326inline bool FMinFMaxShouldFTZ(Intrinsic::ID IntrinsicID) {
327 switch (IntrinsicID) {
328 case Intrinsic::nvvm_fmax_ftz_f:
329 case Intrinsic::nvvm_fmax_ftz_nan_f:
330 case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
331 case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
332
333 case Intrinsic::nvvm_fmin_ftz_f:
334 case Intrinsic::nvvm_fmin_ftz_nan_f:
335 case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
336 case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
337 return true;
338
339 case Intrinsic::nvvm_fmax_d:
340 case Intrinsic::nvvm_fmax_f:
341 case Intrinsic::nvvm_fmax_nan_f:
342 case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
343 case Intrinsic::nvvm_fmax_xorsign_abs_f:
344
345 case Intrinsic::nvvm_fmin_d:
346 case Intrinsic::nvvm_fmin_f:
347 case Intrinsic::nvvm_fmin_nan_f:
348 case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
349 case Intrinsic::nvvm_fmin_xorsign_abs_f:
350 return false;
351 }
352 llvm_unreachable("Checking FTZ flag for invalid fmin/fmax intrinsic");
353}
354
355inline bool FMinFMaxPropagatesNaNs(Intrinsic::ID IntrinsicID) {
356 switch (IntrinsicID) {
357 case Intrinsic::nvvm_fmax_ftz_nan_f:
358 case Intrinsic::nvvm_fmax_nan_f:
359 case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
360 case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
361
362 case Intrinsic::nvvm_fmin_ftz_nan_f:
363 case Intrinsic::nvvm_fmin_nan_f:
364 case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
365 case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
366 return true;
367
368 case Intrinsic::nvvm_fmax_d:
369 case Intrinsic::nvvm_fmax_f:
370 case Intrinsic::nvvm_fmax_ftz_f:
371 case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
372 case Intrinsic::nvvm_fmax_xorsign_abs_f:
373
374 case Intrinsic::nvvm_fmin_d:
375 case Intrinsic::nvvm_fmin_f:
376 case Intrinsic::nvvm_fmin_ftz_f:
377 case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
378 case Intrinsic::nvvm_fmin_xorsign_abs_f:
379 return false;
380 }
381 llvm_unreachable("Checking NaN flag for invalid fmin/fmax intrinsic");
382}
383
384inline bool FMinFMaxIsXorSignAbs(Intrinsic::ID IntrinsicID) {
385 switch (IntrinsicID) {
386 case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
387 case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
388 case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
389 case Intrinsic::nvvm_fmax_xorsign_abs_f:
390
391 case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
392 case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
393 case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
394 case Intrinsic::nvvm_fmin_xorsign_abs_f:
395 return true;
396
397 case Intrinsic::nvvm_fmax_d:
398 case Intrinsic::nvvm_fmax_f:
399 case Intrinsic::nvvm_fmax_ftz_f:
400 case Intrinsic::nvvm_fmax_ftz_nan_f:
401 case Intrinsic::nvvm_fmax_nan_f:
402
403 case Intrinsic::nvvm_fmin_d:
404 case Intrinsic::nvvm_fmin_f:
405 case Intrinsic::nvvm_fmin_ftz_f:
406 case Intrinsic::nvvm_fmin_ftz_nan_f:
407 case Intrinsic::nvvm_fmin_nan_f:
408 return false;
409 }
410 llvm_unreachable("Checking XorSignAbs flag for invalid fmin/fmax intrinsic");
411}
412
413inline bool UnaryMathIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID) {
414 switch (IntrinsicID) {
415 case Intrinsic::nvvm_ceil_ftz_f:
416 case Intrinsic::nvvm_fabs_ftz:
417 case Intrinsic::nvvm_floor_ftz_f:
418 case Intrinsic::nvvm_round_ftz_f:
419 case Intrinsic::nvvm_saturate_ftz_f:
420 case Intrinsic::nvvm_sqrt_rn_ftz_f:
421 return true;
422 case Intrinsic::nvvm_ceil_f:
423 case Intrinsic::nvvm_ceil_d:
424 case Intrinsic::nvvm_fabs:
425 case Intrinsic::nvvm_floor_f:
426 case Intrinsic::nvvm_floor_d:
427 case Intrinsic::nvvm_round_f:
428 case Intrinsic::nvvm_round_d:
429 case Intrinsic::nvvm_saturate_d:
430 case Intrinsic::nvvm_saturate_f:
431 case Intrinsic::nvvm_sqrt_f:
432 case Intrinsic::nvvm_sqrt_rn_d:
433 case Intrinsic::nvvm_sqrt_rn_f:
434 return false;
435 }
436 llvm_unreachable("Checking FTZ flag for invalid unary intrinsic");
437}
438
439inline bool RCPShouldFTZ(Intrinsic::ID IntrinsicID) {
440 switch (IntrinsicID) {
441 case Intrinsic::nvvm_rcp_rm_ftz_f:
442 case Intrinsic::nvvm_rcp_rn_ftz_f:
443 case Intrinsic::nvvm_rcp_rp_ftz_f:
444 case Intrinsic::nvvm_rcp_rz_ftz_f:
445 return true;
446 case Intrinsic::nvvm_rcp_rm_d:
447 case Intrinsic::nvvm_rcp_rm_f:
448 case Intrinsic::nvvm_rcp_rn_d:
449 case Intrinsic::nvvm_rcp_rn_f:
450 case Intrinsic::nvvm_rcp_rp_d:
451 case Intrinsic::nvvm_rcp_rp_f:
452 case Intrinsic::nvvm_rcp_rz_d:
453 case Intrinsic::nvvm_rcp_rz_f:
454 return false;
455 }
456 llvm_unreachable("Checking FTZ flag for invalid rcp intrinsic");
457}
458
459inline APFloat::roundingMode GetRCPRoundingMode(Intrinsic::ID IntrinsicID) {
460 switch (IntrinsicID) {
461 case Intrinsic::nvvm_rcp_rm_f:
462 case Intrinsic::nvvm_rcp_rm_d:
463 case Intrinsic::nvvm_rcp_rm_ftz_f:
464 return APFloat::rmTowardNegative;
465
466 case Intrinsic::nvvm_rcp_rn_f:
467 case Intrinsic::nvvm_rcp_rn_d:
468 case Intrinsic::nvvm_rcp_rn_ftz_f:
469 return APFloat::rmNearestTiesToEven;
470
471 case Intrinsic::nvvm_rcp_rp_f:
472 case Intrinsic::nvvm_rcp_rp_d:
473 case Intrinsic::nvvm_rcp_rp_ftz_f:
474 return APFloat::rmTowardPositive;
475
476 case Intrinsic::nvvm_rcp_rz_f:
477 case Intrinsic::nvvm_rcp_rz_d:
478 case Intrinsic::nvvm_rcp_rz_ftz_f:
479 return APFloat::rmTowardZero;
480 }
481 llvm_unreachable("Checking rounding mode for invalid rcp intrinsic");
482}
483
484inline DenormalMode GetNVVMDenormMode(bool ShouldFTZ) {
485 if (ShouldFTZ)
486 return DenormalMode::getPreserveSign();
487 return DenormalMode::getIEEE();
488}
489
490inline bool FAddShouldFTZ(Intrinsic::ID IntrinsicID) {
491 switch (IntrinsicID) {
492 case Intrinsic::nvvm_add_rm_ftz_f:
493 case Intrinsic::nvvm_add_rn_ftz_f:
494 case Intrinsic::nvvm_add_rp_ftz_f:
495 case Intrinsic::nvvm_add_rz_ftz_f:
496 return true;
497
498 case Intrinsic::nvvm_add_rm_f:
499 case Intrinsic::nvvm_add_rn_f:
500 case Intrinsic::nvvm_add_rp_f:
501 case Intrinsic::nvvm_add_rz_f:
502 case Intrinsic::nvvm_add_rm_d:
503 case Intrinsic::nvvm_add_rn_d:
504 case Intrinsic::nvvm_add_rp_d:
505 case Intrinsic::nvvm_add_rz_d:
506 return false;
507 }
508 llvm_unreachable("Checking FTZ flag for invalid NVVM add intrinsic");
509}
510
511inline APFloat::roundingMode GetFAddRoundingMode(Intrinsic::ID IntrinsicID) {
512 switch (IntrinsicID) {
513 case Intrinsic::nvvm_add_rm_f:
514 case Intrinsic::nvvm_add_rm_d:
515 case Intrinsic::nvvm_add_rm_ftz_f:
516 return APFloat::rmTowardNegative;
517 case Intrinsic::nvvm_add_rn_f:
518 case Intrinsic::nvvm_add_rn_d:
519 case Intrinsic::nvvm_add_rn_ftz_f:
520 return APFloat::rmNearestTiesToEven;
521 case Intrinsic::nvvm_add_rp_f:
522 case Intrinsic::nvvm_add_rp_d:
523 case Intrinsic::nvvm_add_rp_ftz_f:
524 return APFloat::rmTowardPositive;
525 case Intrinsic::nvvm_add_rz_f:
526 case Intrinsic::nvvm_add_rz_d:
527 case Intrinsic::nvvm_add_rz_ftz_f:
528 return APFloat::rmTowardZero;
529 }
530 llvm_unreachable("Invalid FP instrinsic rounding mode for NVVM add");
531}
532
533inline bool FMulShouldFTZ(Intrinsic::ID IntrinsicID) {
534 switch (IntrinsicID) {
535 case Intrinsic::nvvm_mul_rm_ftz_f:
536 case Intrinsic::nvvm_mul_rn_ftz_f:
537 case Intrinsic::nvvm_mul_rp_ftz_f:
538 case Intrinsic::nvvm_mul_rz_ftz_f:
539 return true;
540
541 case Intrinsic::nvvm_mul_rm_f:
542 case Intrinsic::nvvm_mul_rn_f:
543 case Intrinsic::nvvm_mul_rp_f:
544 case Intrinsic::nvvm_mul_rz_f:
545 case Intrinsic::nvvm_mul_rm_d:
546 case Intrinsic::nvvm_mul_rn_d:
547 case Intrinsic::nvvm_mul_rp_d:
548 case Intrinsic::nvvm_mul_rz_d:
549 return false;
550 }
551 llvm_unreachable("Checking FTZ flag for invalid NVVM mul intrinsic");
552}
553
554inline APFloat::roundingMode GetFMulRoundingMode(Intrinsic::ID IntrinsicID) {
555 switch (IntrinsicID) {
556 case Intrinsic::nvvm_mul_rm_f:
557 case Intrinsic::nvvm_mul_rm_d:
558 case Intrinsic::nvvm_mul_rm_ftz_f:
559 return APFloat::rmTowardNegative;
560 case Intrinsic::nvvm_mul_rn_f:
561 case Intrinsic::nvvm_mul_rn_d:
562 case Intrinsic::nvvm_mul_rn_ftz_f:
563 return APFloat::rmNearestTiesToEven;
564 case Intrinsic::nvvm_mul_rp_f:
565 case Intrinsic::nvvm_mul_rp_d:
566 case Intrinsic::nvvm_mul_rp_ftz_f:
567 return APFloat::rmTowardPositive;
568 case Intrinsic::nvvm_mul_rz_f:
569 case Intrinsic::nvvm_mul_rz_d:
570 case Intrinsic::nvvm_mul_rz_ftz_f:
571 return APFloat::rmTowardZero;
572 }
573 llvm_unreachable("Invalid FP instrinsic rounding mode for NVVM mul");
574}
575
576inline bool FDivShouldFTZ(Intrinsic::ID IntrinsicID) {
577 switch (IntrinsicID) {
578 case Intrinsic::nvvm_div_rm_ftz_f:
579 case Intrinsic::nvvm_div_rn_ftz_f:
580 case Intrinsic::nvvm_div_rp_ftz_f:
581 case Intrinsic::nvvm_div_rz_ftz_f:
582 return true;
583
584 case Intrinsic::nvvm_div_rm_f:
585 case Intrinsic::nvvm_div_rn_f:
586 case Intrinsic::nvvm_div_rp_f:
587 case Intrinsic::nvvm_div_rz_f:
588 case Intrinsic::nvvm_div_rm_d:
589 case Intrinsic::nvvm_div_rn_d:
590 case Intrinsic::nvvm_div_rp_d:
591 case Intrinsic::nvvm_div_rz_d:
592 return false;
593 }
594 llvm_unreachable("Checking FTZ flag for invalid NVVM div intrinsic");
595}
596
597inline APFloat::roundingMode GetFDivRoundingMode(Intrinsic::ID IntrinsicID) {
598 switch (IntrinsicID) {
599 case Intrinsic::nvvm_div_rm_f:
600 case Intrinsic::nvvm_div_rm_d:
601 case Intrinsic::nvvm_div_rm_ftz_f:
602 return APFloat::rmTowardNegative;
603 case Intrinsic::nvvm_div_rn_f:
604 case Intrinsic::nvvm_div_rn_d:
605 case Intrinsic::nvvm_div_rn_ftz_f:
606 return APFloat::rmNearestTiesToEven;
607 case Intrinsic::nvvm_div_rp_f:
608 case Intrinsic::nvvm_div_rp_d:
609 case Intrinsic::nvvm_div_rp_ftz_f:
610 return APFloat::rmTowardPositive;
611 case Intrinsic::nvvm_div_rz_f:
612 case Intrinsic::nvvm_div_rz_d:
613 case Intrinsic::nvvm_div_rz_ftz_f:
614 return APFloat::rmTowardZero;
615 }
616 llvm_unreachable("Invalid FP instrinsic rounding mode for NVVM div");
617}
618
619inline bool FMAShouldFTZ(Intrinsic::ID IntrinsicID) {
620 switch (IntrinsicID) {
621 case Intrinsic::nvvm_fma_rm_ftz_f:
622 case Intrinsic::nvvm_fma_rn_ftz_f:
623 case Intrinsic::nvvm_fma_rp_ftz_f:
624 case Intrinsic::nvvm_fma_rz_ftz_f:
625 return true;
626
627 case Intrinsic::nvvm_fma_rm_f:
628 case Intrinsic::nvvm_fma_rn_f:
629 case Intrinsic::nvvm_fma_rp_f:
630 case Intrinsic::nvvm_fma_rz_f:
631 case Intrinsic::nvvm_fma_rm_d:
632 case Intrinsic::nvvm_fma_rn_d:
633 case Intrinsic::nvvm_fma_rp_d:
634 case Intrinsic::nvvm_fma_rz_d:
635 return false;
636 }
637 llvm_unreachable("Checking FTZ flag for invalid NVVM fma intrinsic");
638}
639
640inline APFloat::roundingMode GetFMARoundingMode(Intrinsic::ID IntrinsicID) {
641 switch (IntrinsicID) {
642 case Intrinsic::nvvm_fma_rm_f:
643 case Intrinsic::nvvm_fma_rm_d:
644 case Intrinsic::nvvm_fma_rm_ftz_f:
645 return APFloat::rmTowardNegative;
646 case Intrinsic::nvvm_fma_rn_f:
647 case Intrinsic::nvvm_fma_rn_d:
648 case Intrinsic::nvvm_fma_rn_ftz_f:
649 return APFloat::rmNearestTiesToEven;
650 case Intrinsic::nvvm_fma_rp_f:
651 case Intrinsic::nvvm_fma_rp_d:
652 case Intrinsic::nvvm_fma_rp_ftz_f:
653 return APFloat::rmTowardPositive;
654 case Intrinsic::nvvm_fma_rz_f:
655 case Intrinsic::nvvm_fma_rz_d:
656 case Intrinsic::nvvm_fma_rz_ftz_f:
657 return APFloat::rmTowardZero;
658 }
659 llvm_unreachable("Invalid FP instrinsic rounding mode for NVVM fma");
660}
661
662} // namespace nvvm
663} // namespace llvm
664#endif // LLVM_IR_NVVMINTRINSICUTILS_H
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::APFloatBase::rmTowardNegative
static constexpr roundingMode rmTowardNegative
Definition APFloat.h:347
llvm::APFloatBase::roundingMode
llvm::RoundingMode roundingMode
IEEE-754R 4.3: Rounding-direction attributes.
Definition APFloat.h:342
llvm::APFloatBase::rmNearestTiesToEven
static constexpr roundingMode rmNearestTiesToEven
Definition APFloat.h:344
llvm::APFloatBase::rmTowardZero
static constexpr roundingMode rmTowardZero
Definition APFloat.h:348
llvm::APFloatBase::rmTowardPositive
static constexpr roundingMode rmTowardPositive
Definition APFloat.h:346
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::nvvm::GetFMARoundingMode
APFloat::roundingMode GetFMARoundingMode(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:640
llvm::nvvm::GetNVVMDenormMode
DenormalMode GetNVVMDenormMode(bool ShouldFTZ)
Definition NVVMIntrinsicUtils.h:484
llvm::nvvm::FPToIntegerIntrinsicNaNZero
bool FPToIntegerIntrinsicNaNZero(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:192
llvm::nvvm::GetFDivRoundingMode
APFloat::roundingMode GetFDivRoundingMode(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:597
llvm::nvvm::FPToIntegerIntrinsicResultIsSigned
bool FPToIntegerIntrinsicResultIsSigned(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:126
llvm::nvvm::GetFPToIntegerRoundingMode
APFloat::roundingMode GetFPToIntegerRoundingMode(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:257
llvm::nvvm::RCPShouldFTZ
bool RCPShouldFTZ(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:439
llvm::nvvm::FPToIntegerIntrinsicShouldFTZ
bool FPToIntegerIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:59
llvm::nvvm::FDivShouldFTZ
bool FDivShouldFTZ(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:576
llvm::nvvm::FAddShouldFTZ
bool FAddShouldFTZ(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:490
llvm::nvvm::FMinFMaxIsXorSignAbs
bool FMinFMaxIsXorSignAbs(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:384
llvm::nvvm::GetFMulRoundingMode
APFloat::roundingMode GetFMulRoundingMode(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:554
llvm::nvvm::UnaryMathIntrinsicShouldFTZ
bool UnaryMathIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:413
llvm::nvvm::FMinFMaxShouldFTZ
bool FMinFMaxShouldFTZ(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:326
llvm::nvvm::GetFAddRoundingMode
APFloat::roundingMode GetFAddRoundingMode(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:511
llvm::nvvm::FMAShouldFTZ
bool FMAShouldFTZ(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:619
llvm::nvvm::FMulShouldFTZ
bool FMulShouldFTZ(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:533
llvm::nvvm::GetRCPRoundingMode
APFloat::roundingMode GetRCPRoundingMode(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:459
llvm::nvvm::FMinFMaxPropagatesNaNs
bool FMinFMaxPropagatesNaNs(Intrinsic::ID IntrinsicID)
Definition NVVMIntrinsicUtils.h:355
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition FloatingPointMode.h:71
llvm::DenormalMode::getPreserveSign
static constexpr DenormalMode getPreserveSign()
Definition FloatingPointMode.h:119
llvm::DenormalMode::getIEEE
static constexpr DenormalMode getIEEE()
Definition FloatingPointMode.h:115
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