#include "RISCVBaseInfo.h"#include "llvm/ADT/ArrayRef.h"#include "llvm/ADT/Triple.h"#include "llvm/MC/MCInst.h"#include "llvm/MC/MCRegisterInfo.h"#include "llvm/MC/MCSubtargetInfo.h"#include "llvm/Support/RISCVISAInfo.h"#include "llvm/Support/TargetParser.h"#include "llvm/Support/raw_ostream.h"#include "RISCVGenSearchableTables.inc"#include "RISCVGenCompressInstEmitter.inc"
Include dependency graph for RISCVBaseInfo.cpp:
Go to the source code of this file.
Namespaces | |
| namespace | llvm |
| This is an optimization pass for GlobalISel generic memory operations. | |
| namespace | llvm::RISCVSysReg |
| namespace | llvm::RISCVInsnOpcode |
| namespace | llvm::RISCVABI |
| namespace | llvm::RISCVFeatures |
Macros | |
| #define | GET_SysRegsList_IMPL |
| #define | GET_RISCVOpcodesList_IMPL |
| #define | GEN_UNCOMPRESS_INSTR |
| #define | GEN_COMPRESS_INSTR |
Functions | |
| ABI | llvm::RISCVABI::computeTargetABI (const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName) |
| ABI | llvm::RISCVABI::getTargetABI (StringRef ABIName) |
| MCRegister | llvm::RISCVABI::getBPReg () |
| MCRegister | llvm::RISCVABI::getSCSPReg () |
| void | llvm::RISCVFeatures::validate (const Triple &TT, const FeatureBitset &FeatureBits) |
| llvm::Expected< std::unique_ptr< RISCVISAInfo > > | llvm::RISCVFeatures::parseFeatureBits (bool IsRV64, const FeatureBitset &FeatureBits) |
Macro Definition Documentation
◆ GEN_COMPRESS_INSTR
| #define GEN_COMPRESS_INSTR |
Definition at line 204 of file RISCVBaseInfo.cpp.
◆ GEN_UNCOMPRESS_INSTR
| #define GEN_UNCOMPRESS_INSTR |
Definition at line 203 of file RISCVBaseInfo.cpp.
◆ GET_RISCVOpcodesList_IMPL
| #define GET_RISCVOpcodesList_IMPL |
Definition at line 34 of file RISCVBaseInfo.cpp.
◆ GET_SysRegsList_IMPL
| #define GET_SysRegsList_IMPL |
Definition at line 29 of file RISCVBaseInfo.cpp.
