LLVM 19.0.0git
RISCVBaseInfo.cpp
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1//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCVBaseInfo.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/MC/MCInst.h"
23
24namespace llvm {
25
26extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
27
28namespace RISCVSysReg {
29#define GET_SysRegsList_IMPL
30#include "RISCVGenSearchableTables.inc"
31} // namespace RISCVSysReg
32
33namespace RISCVInsnOpcode {
34#define GET_RISCVOpcodesList_IMPL
35#include "RISCVGenSearchableTables.inc"
36} // namespace RISCVInsnOpcode
37
38namespace RISCVABI {
39ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
40 StringRef ABIName) {
41 auto TargetABI = getTargetABI(ABIName);
42 bool IsRV64 = TT.isArch64Bit();
43 bool IsRVE = FeatureBits[RISCV::FeatureRVE];
44
45 if (!ABIName.empty() && TargetABI == ABI_Unknown) {
46 errs()
47 << "'" << ABIName
48 << "' is not a recognized ABI for this target (ignoring target-abi)\n";
49 } else if (ABIName.starts_with("ilp32") && IsRV64) {
50 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
51 "target-abi)\n";
52 TargetABI = ABI_Unknown;
53 } else if (ABIName.starts_with("lp64") && !IsRV64) {
54 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
55 "target-abi)\n";
56 TargetABI = ABI_Unknown;
57 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E &&
58 TargetABI != ABI_Unknown) {
59 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
60 errs()
61 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
62 TargetABI = ABI_Unknown;
63 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&
64 TargetABI != ABI_Unknown) {
65 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
66 errs()
67 << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";
68 TargetABI = ABI_Unknown;
69 }
70
71 if ((TargetABI == RISCVABI::ABI::ABI_ILP32E ||
72 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
73 FeatureBits[RISCV::FeatureStdExtD])
74 report_fatal_error("ILP32E cannot be used with the D ISA extension");
75
76 if (TargetABI != ABI_Unknown)
77 return TargetABI;
78
79 // If no explicit ABI is given, try to compute the default ABI.
80 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
81 if (!ISAInfo)
82 report_fatal_error(ISAInfo.takeError());
83 return getTargetABI((*ISAInfo)->computeDefaultABI());
84}
85
87 auto TargetABI = StringSwitch<ABI>(ABIName)
88 .Case("ilp32", ABI_ILP32)
89 .Case("ilp32f", ABI_ILP32F)
90 .Case("ilp32d", ABI_ILP32D)
91 .Case("ilp32e", ABI_ILP32E)
92 .Case("lp64", ABI_LP64)
93 .Case("lp64f", ABI_LP64F)
94 .Case("lp64d", ABI_LP64D)
95 .Case("lp64e", ABI_LP64E)
97 return TargetABI;
98}
99
100// To avoid the BP value clobbered by a function call, we need to choose a
101// callee saved register to save the value. RV32E only has X8 and X9 as callee
102// saved registers and X8 will be used as fp. So we choose X9 as bp.
103MCRegister getBPReg() { return RISCV::X9; }
104
105// Returns the register holding shadow call stack pointer.
106MCRegister getSCSPReg() { return RISCV::X3; }
107
108} // namespace RISCVABI
109
110namespace RISCVFeatures {
111
112void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
113 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
114 report_fatal_error("RV64 target requires an RV64 CPU");
115 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
116 report_fatal_error("RV32 target requires an RV32 CPU");
117 if (FeatureBits[RISCV::Feature32Bit] &&
118 FeatureBits[RISCV::Feature64Bit])
119 report_fatal_error("RV32 and RV64 can't be combined");
120}
121
123parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
124 unsigned XLen = IsRV64 ? 64 : 32;
125 std::vector<std::string> FeatureVector;
126 // Convert FeatureBitset to FeatureVector.
127 for (auto Feature : RISCVFeatureKV) {
128 if (FeatureBits[Feature.Value] &&
130 FeatureVector.push_back(std::string("+") + Feature.Key);
131 }
132 return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
133}
134
135} // namespace RISCVFeatures
136
137// Encode VTYPE into the binary format used by the the VSETVLI instruction which
138// is used by our MC layer representation.
139//
140// Bits | Name | Description
141// -----+------------+------------------------------------------------
142// 7 | vma | Vector mask agnostic
143// 6 | vta | Vector tail agnostic
144// 5:3 | vsew[2:0] | Standard element width (SEW) setting
145// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
146unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW,
147 bool TailAgnostic, bool MaskAgnostic) {
148 assert(isValidSEW(SEW) && "Invalid SEW");
149 unsigned VLMULBits = static_cast<unsigned>(VLMUL);
150 unsigned VSEWBits = encodeSEW(SEW);
151 unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
152 if (TailAgnostic)
153 VTypeI |= 0x40;
154 if (MaskAgnostic)
155 VTypeI |= 0x80;
156
157 return VTypeI;
158}
159
160std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
161 switch (VLMUL) {
162 default:
163 llvm_unreachable("Unexpected LMUL value!");
168 return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
172 return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
173 }
174}
175
176void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
177 unsigned Sew = getSEW(VType);
178 OS << "e" << Sew;
179
180 unsigned LMul;
181 bool Fractional;
182 std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
183
184 if (Fractional)
185 OS << ", mf";
186 else
187 OS << ", m";
188 OS << LMul;
189
190 if (isTailAgnostic(VType))
191 OS << ", ta";
192 else
193 OS << ", tu";
194
195 if (isMaskAgnostic(VType))
196 OS << ", ma";
197 else
198 OS << ", mu";
199}
200
201unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
202 unsigned LMul;
203 bool Fractional;
204 std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
205
206 // Convert LMul to a fixed point value with 3 fractional bits.
207 LMul = Fractional ? (8 / LMul) : (LMul * 8);
208
209 assert(SEW >= 8 && "Unexpected SEW value");
210 return (SEW * 8) / LMul;
211}
212
213std::optional<RISCVII::VLMUL>
214RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) {
215 unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
216 unsigned EMULFixedPoint = (EEW * 8) / Ratio;
217 bool Fractional = EMULFixedPoint < 8;
218 unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
219 if (!isValidLMUL(EMUL, Fractional))
220 return std::nullopt;
221 return RISCVVType::encodeLMUL(EMUL, Fractional);
222}
223
224// Include the auto-generated portion of the compress emitter.
225#define GEN_UNCOMPRESS_INSTR
226#define GEN_COMPRESS_INSTR
227#include "RISCVGenCompressInstEmitter.inc"
228
229bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI,
230 const MCSubtargetInfo &STI) {
231 return compressInst(OutInst, MI, STI);
232}
233
234bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI,
235 const MCSubtargetInfo &STI) {
236 return uncompressInst(OutInst, MI, STI);
237}
238
239// Lookup table for fli.s for entries 2-31.
240static constexpr std::pair<uint8_t, uint8_t> LoadFP32ImmArr[] = {
241 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},
242 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},
243 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},
244 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},
245 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},
246 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},
247 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},
248 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},
249 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},
250 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},
251};
252
254 assert((&FPImm.getSemantics() == &APFloat::IEEEsingle() ||
255 &FPImm.getSemantics() == &APFloat::IEEEdouble() ||
256 &FPImm.getSemantics() == &APFloat::IEEEhalf()) &&
257 "Unexpected semantics");
258
259 // Handle the minimum normalized value which is different for each type.
260 if (FPImm.isSmallestNormalized() && !FPImm.isNegative())
261 return 1;
262
263 // Convert to single precision to use its lookup table.
264 bool LosesInfo;
267 if (Status != APFloat::opOK || LosesInfo)
268 return -1;
269
270 APInt Imm = FPImm.bitcastToAPInt();
271
272 if (Imm.extractBitsAsZExtValue(21, 0) != 0)
273 return -1;
274
275 bool Sign = Imm.extractBitsAsZExtValue(1, 31);
276 uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21);
277 uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23);
278
279 auto EMI = llvm::lower_bound(LoadFP32ImmArr, std::make_pair(Exp, Mantissa));
280 if (EMI == std::end(LoadFP32ImmArr) || EMI->first != Exp ||
281 EMI->second != Mantissa)
282 return -1;
283
284 // Table doesn't have entry 0 or 1.
285 int Entry = std::distance(std::begin(LoadFP32ImmArr), EMI) + 2;
286
287 // The only legal negative value is -1.0(entry 0). 1.0 is entry 16.
288 if (Sign) {
289 if (Entry == 16)
290 return 0;
291 return -1;
292 }
293
294 return Entry;
295}
296
297float RISCVLoadFPImm::getFPImm(unsigned Imm) {
298 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate");
299
300 // Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
301 uint32_t Sign = 0;
302 if (Imm == 0) {
303 Sign = 0b1;
304 Imm = 16;
305 }
306
307 uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
308 uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
309
310 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
311 return bit_cast<float>(I);
312}
313
314void RISCVZC::printRlist(unsigned SlistEncode, raw_ostream &OS) {
315 OS << "{ra";
316 if (SlistEncode > 4) {
317 OS << ", s0";
318 if (SlistEncode == 15)
319 OS << "-s11";
320 else if (SlistEncode > 5 && SlistEncode <= 14)
321 OS << "-s" << (SlistEncode - 5);
322 }
323 OS << "}";
324}
325
326void RISCVZC::printSpimm(int64_t Spimm, raw_ostream &OS) { OS << Spimm; }
327
328} // namespace llvm
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:5196
bool isNegative() const
Definition: APFloat.h:1295
const fltSemantics & getSemantics() const
Definition: APFloat.h:1303
APInt bitcastToAPInt() const
Definition: APFloat.h:1210
bool isSmallestNormalized() const
Definition: APFloat.h:1315
Class for arbitrary precision integers.
Definition: APInt.h:76
Tagged union holding either a T or a Error.
Definition: Error.h:474
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
static bool isSupportedExtensionFeature(StringRef Ext)
static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatures(unsigned XLen, const std::vector< std::string > &Features)
Parse RISC-V ISA info from feature vector.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:257
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ABI getTargetABI(StringRef ABIName)
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
MCRegister getBPReg()
MCRegister getSCSPReg()
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
int getLoadFPImm(APFloat FPImm)
getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
float getFPImm(unsigned Imm)
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
void printVType(unsigned VType, raw_ostream &OS)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
std::optional< RISCVII::VLMUL > getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW)
void printRlist(unsigned SlistEncode, raw_ostream &OS)
void printSpimm(int64_t Spimm, raw_ostream &OS)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static constexpr std::pair< uint8_t, uint8_t > LoadFP32ImmArr[]
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1950
const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]
static const fltSemantics & IEEEsingle() LLVM_READNONE
Definition: APFloat.cpp:249
static constexpr roundingMode rmNearestTiesToEven
Definition: APFloat.h:230
static const fltSemantics & IEEEdouble() LLVM_READNONE
Definition: APFloat.cpp:250
static const fltSemantics & IEEEhalf() LLVM_READNONE
Definition: APFloat.cpp:247
opStatus
IEEE-754R 7: Default exception handling.
Definition: APFloat.h:246
Used to provide key value pairs for feature and CPU bit flags.