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26 namespace RISCVSysReg {
27 #define GET_SysRegsList_IMPL
28 #include "RISCVGenSearchableTables.inc"
31 namespace RISCVInsnOpcode {
32 #define GET_RISCVOpcodesList_IMPL
33 #include "RISCVGenSearchableTables.inc"
40 bool IsRV64 = TT.isArch64Bit();
41 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
46 <<
"' is not a recognized ABI for this target (ignoring target-abi)\n";
47 }
else if (ABIName.
startswith(
"ilp32") && IsRV64) {
48 errs() <<
"32-bit ABIs are not supported for 64-bit targets (ignoring "
51 }
else if (ABIName.
startswith(
"lp64") && !IsRV64) {
52 errs() <<
"64-bit ABIs are not supported for 32-bit targets (ignoring "
58 <<
"Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
95 namespace RISCVFeatures {
98 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
100 if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit])
102 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
108 unsigned XLen = IsRV64 ? 64 : 32;
109 std::vector<std::string> FeatureVector;
112 if (FeatureBits[Feature.Value] &&
114 FeatureVector.push_back(std::string(
"+") + Feature.Key);
131 bool TailAgnostic,
bool MaskAgnostic) {
133 unsigned VLMULBits =
static_cast<unsigned>(
VLMUL);
135 unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
152 return std::make_pair(1 <<
static_cast<unsigned>(
VLMUL),
false);
156 return std::make_pair(1 << (8 -
static_cast<unsigned>(
VLMUL)),
true);
161 unsigned Sew =
getSEW(VType);
StringSwitch & Case(StringLiteral S, T Value)
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
This is an optimization pass for GlobalISel generic memory operations.
ABI getTargetABI(StringRef ABIName)
LLVM_NODISCARD R Default(T Value)
Triple - Helper class for working with autoconf configuration names.
static bool isValidSEW(unsigned SEW)
static bool isTailAgnostic(unsigned VType)
Container class for subtarget features.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Tagged union holding either a T or a Error.
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
static unsigned getSEW(unsigned VType)
static unsigned encodeSEW(unsigned SEW)
static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatures(unsigned XLen, const std::vector< std::string > &Features)
Parse RISCV ISA info from feature vector.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class implements an extremely fast bulk output stream that can only output to a stream.
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
Used to provide key value pairs for feature and CPU bit flags.
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printVType(unsigned VType, raw_ostream &OS)
static RISCVII::VLMUL getVLMUL(unsigned VType)
static bool isMaskAgnostic(unsigned VType)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
static bool isSupportedExtensionFeature(StringRef Ext)
A switch()-like statement whose cases are string literals.
const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]
Wrapper class representing physical registers. Should be passed by value.