LLVM  13.0.0git
RISCVBaseInfo.cpp
Go to the documentation of this file.
1 //===-- RISCVBaseInfo.cpp - Top level definitions for RISCV MC ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCVBaseInfo.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/Triple.h"
18 
19 namespace llvm {
20 namespace RISCVSysReg {
21 #define GET_SysRegsList_IMPL
22 #include "RISCVGenSearchableTables.inc"
23 } // namespace RISCVSysReg
24 
25 namespace RISCVABI {
26 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
27  StringRef ABIName) {
28  auto TargetABI = getTargetABI(ABIName);
29  bool IsRV64 = TT.isArch64Bit();
30  bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
31 
32  if (!ABIName.empty() && TargetABI == ABI_Unknown) {
33  errs()
34  << "'" << ABIName
35  << "' is not a recognized ABI for this target (ignoring target-abi)\n";
36  } else if (ABIName.startswith("ilp32") && IsRV64) {
37  errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
38  "target-abi)\n";
39  TargetABI = ABI_Unknown;
40  } else if (ABIName.startswith("lp64") && !IsRV64) {
41  errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
42  "target-abi)\n";
43  TargetABI = ABI_Unknown;
44  } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) {
45  // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
46  errs()
47  << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
48  TargetABI = ABI_Unknown;
49  }
50 
51  if (TargetABI != ABI_Unknown)
52  return TargetABI;
53 
54  // For now, default to the ilp32/ilp32e/lp64 ABI if no explicit ABI is given
55  // or an invalid/unrecognised string is given. In the future, it might be
56  // worth changing this to default to ilp32f/lp64f and ilp32d/lp64d when
57  // hardware support for floating point is present.
58  if (IsRV32E)
59  return ABI_ILP32E;
60  if (IsRV64)
61  return ABI_LP64;
62  return ABI_ILP32;
63 }
64 
66  auto TargetABI = StringSwitch<ABI>(ABIName)
67  .Case("ilp32", ABI_ILP32)
68  .Case("ilp32f", ABI_ILP32F)
69  .Case("ilp32d", ABI_ILP32D)
70  .Case("ilp32e", ABI_ILP32E)
71  .Case("lp64", ABI_LP64)
72  .Case("lp64f", ABI_LP64F)
73  .Case("lp64d", ABI_LP64D)
75  return TargetABI;
76 }
77 
78 // To avoid the BP value clobbered by a function call, we need to choose a
79 // callee saved register to save the value. RV32E only has X8 and X9 as callee
80 // saved registers and X8 will be used as fp. So we choose X9 as bp.
81 MCRegister getBPReg() { return RISCV::X9; }
82 
83 // Returns the register holding shadow call stack pointer.
84 MCRegister getSCSPReg() { return RISCV::X18; }
85 
86 } // namespace RISCVABI
87 
88 namespace RISCVFeatures {
89 
90 void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
91  if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
92  report_fatal_error("RV64 target requires an RV64 CPU");
93  if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit])
94  report_fatal_error("RV32 target requires an RV32 CPU");
95  if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
96  report_fatal_error("RV32E can't be enabled for an RV64 target");
97 }
98 
99 } // namespace RISCVFeatures
100 
101 void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
102  RISCVVSEW VSEW = getVSEW(VType);
103  RISCVVLMUL VLMUL = getVLMUL(VType);
104 
105  unsigned Sew = 1 << (static_cast<unsigned>(VSEW) + 3);
106  OS << "e" << Sew;
107 
108  switch (VLMUL) {
110  llvm_unreachable("Unexpected LMUL value!");
111  case RISCVVLMUL::LMUL_1:
112  case RISCVVLMUL::LMUL_2:
113  case RISCVVLMUL::LMUL_4:
114  case RISCVVLMUL::LMUL_8: {
115  unsigned LMul = 1 << static_cast<unsigned>(VLMUL);
116  OS << ",m" << LMul;
117  break;
118  }
119  case RISCVVLMUL::LMUL_F2:
120  case RISCVVLMUL::LMUL_F4:
121  case RISCVVLMUL::LMUL_F8: {
122  unsigned LMul = 1 << (8 - static_cast<unsigned>(VLMUL));
123  OS << ",mf" << LMul;
124  break;
125  }
126  }
127 
128  if (isTailAgnostic(VType))
129  OS << ",ta";
130  else
131  OS << ",tu";
132 
133  if (isMaskAgnostic(VType))
134  OS << ",ma";
135  else
136  OS << ",mu";
137 }
138 
139 } // namespace llvm
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::RISCVABI::ABI_LP64F
@ ABI_LP64F
Definition: RISCVBaseInfo.h:235
llvm::StringRef::startswith
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:289
llvm
Definition: AllocatorList.h:23
llvm::RISCVVLMUL::LMUL_1
@ LMUL_1
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:156
llvm::RISCVVType::getVSEW
static RISCVVSEW getVSEW(unsigned VType)
Definition: RISCVBaseInfo.h:323
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:65
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::RISCVVType::isTailAgnostic
static bool isTailAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:328
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:892
llvm::RISCVVLMUL::LMUL_F8
@ LMUL_F8
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:90
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:81
llvm::RISCVVType::getVLMUL
static RISCVVLMUL getVLMUL(unsigned VType)
Definition: RISCVBaseInfo.h:318
llvm::RISCVABI::ABI_ILP32
@ ABI_ILP32
Definition: RISCVBaseInfo.h:230
llvm::RISCVVLMUL::LMUL_2
@ LMUL_2
llvm::RISCVABI::ABI_LP64
@ ABI_LP64
Definition: RISCVBaseInfo.h:234
llvm::RISCVVSEW
RISCVVSEW
Definition: RISCVBaseInfo.h:263
llvm::RISCVABI::ABI_ILP32D
@ ABI_ILP32D
Definition: RISCVBaseInfo.h:232
llvm::RISCVVLMUL::LMUL_F2
@ LMUL_F2
llvm::RISCVABI::ABI_ILP32E
@ ABI_ILP32E
Definition: RISCVBaseInfo.h:233
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:84
llvm::RISCVVLMUL::LMUL_4
@ LMUL_4
llvm::RISCVVLMUL::LMUL_F4
@ LMUL_F4
ArrayRef.h
llvm::RISCVVLMUL::LMUL_8
@ LMUL_8
Triple.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::RISCVVType::printVType
void printVType(unsigned VType, raw_ostream &OS)
Definition: RISCVBaseInfo.cpp:101
llvm::RISCVABI::ABI_LP64D
@ ABI_LP64D
Definition: RISCVBaseInfo.h:236
llvm::RISCVVType::isMaskAgnostic
static bool isMaskAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:330
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:26
RISCVBaseInfo.h
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:237
llvm::RISCVVLMUL
RISCVVLMUL
Definition: RISCVBaseInfo.h:274
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::RISCVABI::ABI_ILP32F
@ ABI_ILP32F
Definition: RISCVBaseInfo.h:231
raw_ostream.h
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:229
llvm::RISCVVLMUL::LMUL_RESERVED
@ LMUL_RESERVED
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22