LLVM 18.0.0git
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Classes | |
struct | CPUInfo |
struct | RISCVMaskedPseudoInfo |
struct | VLEPseudo |
struct | VLSEGPseudo |
struct | VLX_VSXPseudo |
struct | VLXSEGPseudo |
struct | VSEPseudo |
struct | VSSEGPseudo |
struct | VSXSEGPseudo |
Enumerations | |
enum | PartialMappingIdx { PMI_GPR32 = 0 , PMI_GPR64 = 1 } |
enum | ValueMappingsIdx { InvalidIdx = 0 , GPR32Idx = 1 , GPR64Idx = 4 } |
enum | Fixups { fixup_riscv_hi20 = FirstTargetFixupKind , fixup_riscv_lo12_i , fixup_riscv_12_i , fixup_riscv_lo12_s , fixup_riscv_pcrel_hi20 , fixup_riscv_pcrel_lo12_i , fixup_riscv_pcrel_lo12_s , fixup_riscv_got_hi20 , fixup_riscv_tprel_hi20 , fixup_riscv_tprel_lo12_i , fixup_riscv_tprel_lo12_s , fixup_riscv_tprel_add , fixup_riscv_tls_got_hi20 , fixup_riscv_tls_gd_hi20 , fixup_riscv_jal , fixup_riscv_branch , fixup_riscv_rvc_jump , fixup_riscv_rvc_branch , fixup_riscv_call , fixup_riscv_call_plt , fixup_riscv_relax , fixup_riscv_align , fixup_riscv_invalid , NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind } |
enum | CPUKind : unsigned |
Variables | |
static constexpr unsigned | RVVBitsPerBlock = 64 |
RegisterBankInfo::PartialMapping | PartMappings [] |
RegisterBankInfo::ValueMapping | ValueMappings [] |
static constexpr int64_t | VLMaxSentinel = -1LL |
static constexpr unsigned | FPMASK_Negative_Infinity = 0x001 |
static constexpr unsigned | FPMASK_Negative_Normal = 0x002 |
static constexpr unsigned | FPMASK_Negative_Subnormal = 0x004 |
static constexpr unsigned | FPMASK_Negative_Zero = 0x008 |
static constexpr unsigned | FPMASK_Positive_Zero = 0x010 |
static constexpr unsigned | FPMASK_Positive_Subnormal = 0x020 |
static constexpr unsigned | FPMASK_Positive_Normal = 0x040 |
static constexpr unsigned | FPMASK_Positive_Infinity = 0x080 |
static constexpr unsigned | FPMASK_Signaling_NaN = 0x100 |
static constexpr unsigned | FPMASK_Quiet_NaN = 0x200 |
constexpr CPUInfo | RISCVCPUInfo [] |
enum llvm::RISCV::CPUKind : unsigned |
Definition at line 22 of file RISCVTargetParser.cpp.
enum llvm::RISCV::Fixups |
Definition at line 19 of file RISCVFixupKinds.h.
Enumerator | |
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PMI_GPR32 | |
PMI_GPR64 |
Definition at line 32 of file RISCVRegisterBankInfo.cpp.
Enumerator | |
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InvalidIdx | |
GPR32Idx | |
GPR64Idx |
Definition at line 50 of file RISCVRegisterBankInfo.cpp.
bool llvm::RISCV::CC_RISCV | ( | const DataLayout & | DL, |
RISCVABI::ABI | ABI, | ||
unsigned | ValNo, | ||
MVT | ValVT, | ||
MVT | LocVT, | ||
CCValAssign::LocInfo | LocInfo, | ||
ISD::ArgFlagsTy | ArgFlags, | ||
CCState & | State, | ||
bool | IsFixed, | ||
bool | IsRet, | ||
Type * | OrigTy, | ||
const RISCVTargetLowering & | TLI, | ||
std::optional< unsigned > | FirstMaskArgument | ||
) |
Definition at line 15903 of file RISCVISelLowering.cpp.
References llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32D, llvm::RISCVABI::ABI_ILP32F, llvm::RISCVABI::ABI_LP64, llvm::RISCVABI::ABI_LP64D, llvm::RISCVABI::ABI_LP64F, llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), ArgFPR16s, ArgFPR32s, ArgFPR64s, ArgGPRs, assert(), llvm::CCValAssign::BCvt, CC_RISCVAssign2XLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::CCValAssign::Full, llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCState::getFirstUnallocated(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCState::getPendingArgFlags(), llvm::CCState::getPendingLocs(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::hasVInstructions(), llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::ISD::ArgFlagsTy::isNest(), llvm::MVT::isScalableVector(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm::MVT::isVector(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), and llvm::MaybeAlign::valueOrOne().
Referenced by llvm::RISCVTargetLowering::CanLowerReturn(), llvm::RISCVCallLowering::lowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVCallLowering::lowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::RISCVTargetLowering::LowerReturn().
bool llvm::RISCV::CC_RISCV_FastCC | ( | const DataLayout & | DL, |
RISCVABI::ABI | ABI, | ||
unsigned | ValNo, | ||
MVT | ValVT, | ||
MVT | LocVT, | ||
CCValAssign::LocInfo | LocInfo, | ||
ISD::ArgFlagsTy | ArgFlags, | ||
CCState & | State, | ||
bool | IsFixed, | ||
bool | IsRet, | ||
Type * | OrigTy, | ||
const RISCVTargetLowering & | TLI, | ||
std::optional< unsigned > | FirstMaskArgument | ||
) |
Definition at line 16358 of file RISCVISelLowering.cpp.
References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), allocateRVVReg(), llvm::CCState::AllocateStack(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCValAssign::getMem(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::getXLenVT(), llvm::CCValAssign::Indirect, llvm::RISCVSubtarget::is64Bit(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), and llvm::MaybeAlign::valueOrOne().
Referenced by llvm::RISCVCallLowering::lowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVCallLowering::lowerFormalArguments(), and llvm::RISCVTargetLowering::LowerFormalArguments().
bool llvm::RISCV::CC_RISCV_GHC | ( | unsigned | ValNo, |
MVT | ValVT, | ||
MVT | LocVT, | ||
CCValAssign::LocInfo | LocInfo, | ||
ISD::ArgFlagsTy | ArgFlags, | ||
CCState & | State | ||
) |
Definition at line 16481 of file RISCVISelLowering.cpp.
References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::getMachineFunction(), llvm::CCValAssign::getReg(), llvm::MachineFunction::getSubtarget(), llvm::RISCVSubtarget::is64Bit(), llvm::ISD::ArgFlagsTy::isNest(), and llvm::report_fatal_error().
Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().
void llvm::RISCV::fillValidCPUArchList | ( | SmallVectorImpl< StringRef > & | Values, |
bool | IsRV64 | ||
) |
Definition at line 76 of file RISCVTargetParser.cpp.
References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.
void llvm::RISCV::fillValidTuneCPUArchList | ( | SmallVectorImpl< StringRef > & | Values, |
bool | IsRV64 | ||
) |
Definition at line 83 of file RISCVTargetParser.cpp.
References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.
Definition at line 40 of file RISCVTargetParser.cpp.
References llvm::CallingConv::C, and RISCVCPUInfo.
Referenced by getMArchFromMcpu(), and parseCPU().
Definition at line 69 of file RISCVTargetParser.cpp.
References getCPUInfoByName(), and Info.
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inlinestatic |
Definition at line 81 of file RISCVFixupKinds.h.
References llvm::FirstLiteralRelocationKind, llvm_unreachable, and Size.
Referenced by llvm::RISCVAsmBackend::relaxDwarfLineAddr().
bool llvm::RISCV::hasEqualFRM | ( | const MachineInstr & | MI1, |
const MachineInstr & | MI2 | ||
) |
Definition at line 2839 of file RISCVInstrInfo.cpp.
References llvm::MachineOperand::getImm(), getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().
Referenced by canCombineFPFusedMultiply(), and llvm::RISCVInstrInfo::hasReassociableSibling().
bool llvm::RISCV::isFaultFirstLoad | ( | const MachineInstr & | MI | ) |
Definition at line 2834 of file RISCVInstrInfo.cpp.
References MI.
Referenced by lowerRISCVVMachineInstrToMCInst().
bool llvm::RISCV::isRVVSpill | ( | const MachineInstr & | MI | ) |
Definition at line 2783 of file RISCVInstrInfo.cpp.
References isRVVSpillForZvlsseg(), isRVVWholeLoadStore(), and MI.
Referenced by llvm::RISCVRegisterInfo::eliminateFrameIndex(), and getScavSlotsNumForRVV().
std::optional< std::pair< unsigned, unsigned > > llvm::RISCV::isRVVSpillForZvlsseg | ( | unsigned | Opcode | ) |
Definition at line 2794 of file RISCVInstrInfo.cpp.
Referenced by isRVVSpill(), llvm::RISCVRegisterInfo::lowerVRELOAD(), and llvm::RISCVRegisterInfo::lowerVSPILL().
bool llvm::RISCV::isSEXT_W | ( | const MachineInstr & | MI | ) |
Definition at line 2738 of file RISCVInstrInfo.cpp.
References MI.
Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().
bool llvm::RISCV::isZEXT_B | ( | const MachineInstr & | MI | ) |
Definition at line 2750 of file RISCVInstrInfo.cpp.
References MI.
Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().
bool llvm::RISCV::isZEXT_W | ( | const MachineInstr & | MI | ) |
Definition at line 2744 of file RISCVInstrInfo.cpp.
References MI.
Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().
Definition at line 47 of file RISCVTargetParser.cpp.
References getCPUInfoByName(), and Info.
Referenced by parseTuneCPU().
Definition at line 55 of file RISCVTargetParser.cpp.
References parseCPU(), and TUNE_PROC.
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staticconstexpr |
Definition at line 272 of file RISCVInstrInfo.h.
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staticconstexpr |
Definition at line 273 of file RISCVInstrInfo.h.
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staticconstexpr |
Definition at line 274 of file RISCVInstrInfo.h.
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staticconstexpr |
Definition at line 275 of file RISCVInstrInfo.h.
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staticconstexpr |
Definition at line 279 of file RISCVInstrInfo.h.
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staticconstexpr |
Definition at line 278 of file RISCVInstrInfo.h.
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staticconstexpr |
Definition at line 277 of file RISCVInstrInfo.h.
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staticconstexpr |
Definition at line 276 of file RISCVInstrInfo.h.
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staticconstexpr |
Definition at line 281 of file RISCVInstrInfo.h.
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staticconstexpr |
Definition at line 280 of file RISCVInstrInfo.h.
RegisterBankInfo::PartialMapping llvm::RISCV::PartMappings[] |
Definition at line 27 of file RISCVRegisterBankInfo.cpp.
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constexpr |
Definition at line 34 of file RISCVTargetParser.cpp.
Referenced by fillValidCPUArchList(), fillValidTuneCPUArchList(), and getCPUInfoByName().
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staticconstexpr |
Definition at line 27 of file RISCVTargetParser.h.
Referenced by llvm::RISCVTargetLowering::computeVLMAX(), getContainerForFixedLengthVector(), getLMUL1VT(), llvm::RISCVTTIImpl::getMaxVScale(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetMachine::getSubtargetImpl(), llvm::RISCVTTIImpl::getVScaleForTuning(), isValidEGW(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), lowerGetVectorLength(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::RISCVTargetLowering::RISCVTargetLowering().
RegisterBankInfo::ValueMapping llvm::RISCV::ValueMappings[] |
Definition at line 37 of file RISCVRegisterBankInfo.cpp.
Referenced by llvm::RISCVRegisterBankInfo::getInstrMapping().
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staticconstexpr |
Definition at line 269 of file RISCVInstrInfo.h.
Referenced by if(), llvm::RISCVDAGToDAGISel::selectLow8BitsVSplat(), and llvm::RISCVDAGToDAGISel::selectVLOp().