LLVM  14.0.0git
Classes | Enumerations | Functions | Variables
llvm::RISCV Namespace Reference

Classes

struct  CPUInfo
 
struct  VLEPseudo
 
struct  VLSEGPseudo
 
struct  VLX_VSXPseudo
 
struct  VLXSEGPseudo
 
struct  VSEPseudo
 
struct  VSSEGPseudo
 
struct  VSXSEGPseudo
 

Enumerations

enum  CPUKind : unsigned
 
enum  FeatureKind : unsigned {
  FK_INVALID = 0, FK_NONE = 1, FK_STDEXTM = 1 << 2, FK_STDEXTA = 1 << 3,
  FK_STDEXTF = 1 << 4, FK_STDEXTD = 1 << 5, FK_STDEXTC = 1 << 6, FK_64BIT = 1 << 7
}
 
enum  Fixups {
  fixup_riscv_hi20 = FirstTargetFixupKind, fixup_riscv_lo12_i, fixup_riscv_lo12_s, fixup_riscv_pcrel_hi20,
  fixup_riscv_pcrel_lo12_i, fixup_riscv_pcrel_lo12_s, fixup_riscv_got_hi20, fixup_riscv_tprel_hi20,
  fixup_riscv_tprel_lo12_i, fixup_riscv_tprel_lo12_s, fixup_riscv_tprel_add, fixup_riscv_tls_got_hi20,
  fixup_riscv_tls_gd_hi20, fixup_riscv_jal, fixup_riscv_branch, fixup_riscv_rvc_jump,
  fixup_riscv_rvc_branch, fixup_riscv_call, fixup_riscv_call_plt, fixup_riscv_relax,
  fixup_riscv_align, fixup_riscv_set_8, fixup_riscv_add_8, fixup_riscv_sub_8,
  fixup_riscv_set_16, fixup_riscv_add_16, fixup_riscv_sub_16, fixup_riscv_set_32,
  fixup_riscv_add_32, fixup_riscv_sub_32, fixup_riscv_add_64, fixup_riscv_sub_64,
  fixup_riscv_set_6b, fixup_riscv_sub_6b, fixup_riscv_invalid, NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind
}
 

Functions

bool checkCPUKind (CPUKind Kind, bool IsRV64)
 
bool checkTuneCPUKind (CPUKind Kind, bool IsRV64)
 
CPUKind parseCPUKind (StringRef CPU)
 
CPUKind parseTuneCPUKind (StringRef CPU, bool IsRV64)
 
StringRef getMArchFromMcpu (StringRef CPU)
 
void fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
 Provide a list of valid CPU names. More...
 
void fillValidTuneCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
 
bool getCPUFeaturesExceptStdExt (CPUKind Kind, std::vector< StringRef > &Features)
 
StringRef resolveTuneCPUAlias (StringRef TuneCPU, bool IsRV64)
 

Variables

constexpr CPUInfo RISCVCPUInfo []
 
static constexpr int64_t VLMaxSentinel = -1LL
 
static constexpr unsigned RVVBitsPerBlock = 64
 

Enumeration Type Documentation

◆ CPUKind

enum llvm::RISCV::CPUKind : unsigned

Definition at line 152 of file TargetParser.h.

◆ FeatureKind

enum llvm::RISCV::FeatureKind : unsigned
Enumerator
FK_INVALID 
FK_NONE 
FK_STDEXTM 
FK_STDEXTA 
FK_STDEXTF 
FK_STDEXTD 
FK_STDEXTC 
FK_64BIT 

Definition at line 157 of file TargetParser.h.

◆ Fixups

Enumerator
fixup_riscv_hi20 
fixup_riscv_lo12_i 
fixup_riscv_lo12_s 
fixup_riscv_pcrel_hi20 
fixup_riscv_pcrel_lo12_i 
fixup_riscv_pcrel_lo12_s 
fixup_riscv_got_hi20 
fixup_riscv_tprel_hi20 
fixup_riscv_tprel_lo12_i 
fixup_riscv_tprel_lo12_s 
fixup_riscv_tprel_add 
fixup_riscv_tls_got_hi20 
fixup_riscv_tls_gd_hi20 
fixup_riscv_jal 
fixup_riscv_branch 
fixup_riscv_rvc_jump 
fixup_riscv_rvc_branch 
fixup_riscv_call 
fixup_riscv_call_plt 
fixup_riscv_relax 
fixup_riscv_align 
fixup_riscv_set_8 
fixup_riscv_add_8 
fixup_riscv_sub_8 
fixup_riscv_set_16 
fixup_riscv_add_16 
fixup_riscv_sub_16 
fixup_riscv_set_32 
fixup_riscv_add_32 
fixup_riscv_sub_32 
fixup_riscv_add_64 
fixup_riscv_sub_64 
fixup_riscv_set_6b 
fixup_riscv_sub_6b 
fixup_riscv_invalid 
NumTargetFixupKinds 

Definition at line 18 of file RISCVFixupKinds.h.

Function Documentation

◆ checkCPUKind()

bool llvm::RISCV::checkCPUKind ( CPUKind  Kind,
bool  IsRV64 
)

Definition at line 262 of file TargetParser.cpp.

References is64Bit(), and RISCVCPUInfo.

◆ checkTuneCPUKind()

bool llvm::RISCV::checkTuneCPUKind ( CPUKind  Kind,
bool  IsRV64 
)

Definition at line 268 of file TargetParser.cpp.

References is64Bit(), and RISCVCPUInfo.

◆ fillValidCPUArchList()

void llvm::RISCV::fillValidCPUArchList ( SmallVectorImpl< StringRef > &  Values,
bool  IsRV64 
)

Provide a list of valid CPU names.

If Only64Bit is true, the list will only contain 64-bit capable CPUs.

Definition at line 302 of file TargetParser.cpp.

References llvm::SmallVectorImpl< T >::emplace_back(), P, Processors, and RISCVCPUInfo.

◆ fillValidTuneCPUArchList()

void llvm::RISCV::fillValidTuneCPUArchList ( SmallVectorImpl< StringRef > &  Values,
bool  IsRV64 
)

Definition at line 309 of file TargetParser.cpp.

References llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

◆ getCPUFeaturesExceptStdExt()

bool llvm::RISCV::getCPUFeaturesExceptStdExt ( CPUKind  Kind,
std::vector< StringRef > &  Features 
)

Definition at line 319 of file TargetParser.cpp.

References FK_64BIT, FK_INVALID, and RISCVCPUInfo.

◆ getMArchFromMcpu()

StringRef llvm::RISCV::getMArchFromMcpu ( StringRef  CPU)

Definition at line 297 of file TargetParser.cpp.

References parseCPUKind(), and RISCVCPUInfo.

◆ parseCPUKind()

CPUKind llvm::RISCV::parseCPUKind ( StringRef  CPU)

Definition at line 274 of file TargetParser.cpp.

References llvm::StringSwitch< T, R >::Default().

Referenced by getMArchFromMcpu().

◆ parseTuneCPUKind()

CPUKind llvm::RISCV::parseTuneCPUKind ( StringRef  CPU,
bool  IsRV64 
)

◆ resolveTuneCPUAlias()

StringRef llvm::RISCV::resolveTuneCPUAlias ( StringRef  TuneCPU,
bool  IsRV64 
)

Definition at line 281 of file TargetParser.cpp.

References llvm::StringSwitch< T, R >::Default().

Referenced by parseTuneCPUKind().

Variable Documentation

◆ RISCVCPUInfo

constexpr CPUInfo llvm::RISCV::RISCVCPUInfo[]
constexpr
Initial value:
= {
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)
}

Definition at line 256 of file TargetParser.cpp.

Referenced by checkCPUKind(), checkTuneCPUKind(), fillValidCPUArchList(), fillValidTuneCPUArchList(), getCPUFeaturesExceptStdExt(), and getMArchFromMcpu().

◆ RVVBitsPerBlock

constexpr unsigned llvm::RISCV::RVVBitsPerBlock = 64
staticconstexpr

◆ VLMaxSentinel

constexpr int64_t llvm::RISCV::VLMaxSentinel = -1LL
staticconstexpr

Definition at line 185 of file RISCVInstrInfo.h.

Referenced by getDefaultVLOps().