LLVM 17.0.0git
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Classes | |
struct | CPUInfo |
struct | RISCVMaskedPseudoInfo |
struct | VLEPseudo |
struct | VLSEGPseudo |
struct | VLX_VSXPseudo |
struct | VLXSEGPseudo |
struct | VSEPseudo |
struct | VSSEGPseudo |
struct | VSXSEGPseudo |
Enumerations | |
enum | CPUKind : unsigned |
enum | Fixups { fixup_riscv_hi20 = FirstTargetFixupKind , fixup_riscv_lo12_i , fixup_riscv_lo12_s , fixup_riscv_pcrel_hi20 , fixup_riscv_pcrel_lo12_i , fixup_riscv_pcrel_lo12_s , fixup_riscv_got_hi20 , fixup_riscv_tprel_hi20 , fixup_riscv_tprel_lo12_i , fixup_riscv_tprel_lo12_s , fixup_riscv_tprel_add , fixup_riscv_tls_got_hi20 , fixup_riscv_tls_gd_hi20 , fixup_riscv_jal , fixup_riscv_branch , fixup_riscv_rvc_jump , fixup_riscv_rvc_branch , fixup_riscv_call , fixup_riscv_call_plt , fixup_riscv_relax , fixup_riscv_align , fixup_riscv_set_8 , fixup_riscv_add_8 , fixup_riscv_sub_8 , fixup_riscv_set_16 , fixup_riscv_add_16 , fixup_riscv_sub_16 , fixup_riscv_set_32 , fixup_riscv_add_32 , fixup_riscv_sub_32 , fixup_riscv_add_64 , fixup_riscv_sub_64 , fixup_riscv_set_6b , fixup_riscv_sub_6b , fixup_riscv_invalid , NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind } |
Variables | |
static constexpr unsigned | RVVBitsPerBlock = 64 |
static constexpr int64_t | VLMaxSentinel = -1LL |
constexpr CPUInfo | RISCVCPUInfo [] |
enum llvm::RISCV::CPUKind : unsigned |
Definition at line 29 of file RISCVTargetParser.h.
enum llvm::RISCV::Fixups |
Definition at line 18 of file RISCVFixupKinds.h.
Definition at line 36 of file RISCVTargetParser.cpp.
References is64Bit(), and RISCVCPUInfo.
Definition at line 42 of file RISCVTargetParser.cpp.
References is64Bit(), and RISCVCPUInfo.
void llvm::RISCV::fillValidCPUArchList | ( | SmallVectorImpl< StringRef > & | Values, |
bool | IsRV64 | ||
) |
Definition at line 72 of file RISCVTargetParser.cpp.
References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.
void llvm::RISCV::fillValidTuneCPUArchList | ( | SmallVectorImpl< StringRef > & | Values, |
bool | IsRV64 | ||
) |
Definition at line 79 of file RISCVTargetParser.cpp.
References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.
Definition at line 89 of file RISCVTargetParser.cpp.
References Info, and RISCVCPUInfo.
Definition at line 67 of file RISCVTargetParser.cpp.
References parseCPUKind(), and RISCVCPUInfo.
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inlinestatic |
Definition at line 114 of file RISCVFixupKinds.h.
References fixup_riscv_add_16, fixup_riscv_add_32, fixup_riscv_add_64, fixup_riscv_add_8, fixup_riscv_sub_16, fixup_riscv_sub_32, fixup_riscv_sub_64, fixup_riscv_sub_8, llvm_unreachable, and Size.
Referenced by RISCVELFStreamer::emitValueImpl(), and llvm::RISCVAsmBackend::relaxDwarfLineAddr().
bool llvm::RISCV::hasEqualFRM | ( | const MachineInstr & | MI1, |
const MachineInstr & | MI2 | ||
) |
Definition at line 2937 of file RISCVInstrInfo.cpp.
References llvm::MachineOperand::getImm(), getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().
Referenced by canCombineFPFusedMultiply(), and llvm::RISCVInstrInfo::hasReassociableSibling().
bool llvm::RISCV::isFaultFirstLoad | ( | const MachineInstr & | MI | ) |
Definition at line 2932 of file RISCVInstrInfo.cpp.
References MI.
Referenced by lowerRISCVVMachineInstrToMCInst().
bool llvm::RISCV::isRVVSpill | ( | const MachineInstr & | MI | ) |
Definition at line 2881 of file RISCVInstrInfo.cpp.
References isRVVSpillForZvlsseg(), isRVVWholeLoadStore(), and MI.
Referenced by llvm::RISCVRegisterInfo::eliminateFrameIndex(), and getScavSlotsNumForRVV().
std::optional< std::pair< unsigned, unsigned > > llvm::RISCV::isRVVSpillForZvlsseg | ( | unsigned | Opcode | ) |
Definition at line 2892 of file RISCVInstrInfo.cpp.
Referenced by isRVVSpill(), llvm::RISCVRegisterInfo::lowerVRELOAD(), and llvm::RISCVRegisterInfo::lowerVSPILL().
bool llvm::RISCV::isSEXT_W | ( | const MachineInstr & | MI | ) |
Definition at line 2836 of file RISCVInstrInfo.cpp.
References MI.
Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().
Definition at line 104 of file RISCVTargetParser.cpp.
Referenced by llvm::RISCVSubtarget::RISCVSubtarget().
bool llvm::RISCV::isZEXT_B | ( | const MachineInstr & | MI | ) |
Definition at line 2848 of file RISCVInstrInfo.cpp.
References MI.
Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().
bool llvm::RISCV::isZEXT_W | ( | const MachineInstr & | MI | ) |
Definition at line 2842 of file RISCVInstrInfo.cpp.
References MI.
Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().
Definition at line 52 of file RISCVTargetParser.cpp.
References llvm::StringSwitch< T, R >::Default().
Referenced by getMArchFromMcpu().
Definition at line 59 of file RISCVTargetParser.cpp.
References llvm::StringSwitch< T, R >::Default().
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constexpr |
Definition at line 30 of file RISCVTargetParser.cpp.
Referenced by checkCPUKind(), checkTuneCPUKind(), fillValidCPUArchList(), fillValidTuneCPUArchList(), getCPUFeaturesExceptStdExt(), and getMArchFromMcpu().
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staticconstexpr |
Definition at line 27 of file RISCVTargetParser.h.
Referenced by llvm::RISCVTargetLowering::computeVLMAX(), getContainerForFixedLengthVector(), getLMUL1VT(), llvm::RISCVTTIImpl::getMaxVScale(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetMachine::getSubtargetImpl(), llvm::RISCVTTIImpl::getVScaleForTuning(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::RISCVTargetLowering::RISCVTargetLowering().
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staticconstexpr |
Definition at line 269 of file RISCVInstrInfo.h.
Referenced by if(), and llvm::RISCVDAGToDAGISel::selectVLOp().