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13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
20 #define GET_INSTRINFO_HEADER
21 #define GET_INSTRINFO_OPERAND_ENUM
22 #include "RISCVGenInstrInfo.inc"
59 bool KillSrc)
const override;
82 bool AllowModify)
const override;
87 int *BytesAdded =
nullptr)
const override;
95 int *BytesRemoved =
nullptr)
const override;
103 int64_t BrOffset)
const override;
115 int64_t &Offset,
unsigned &
Width,
122 std::pair<unsigned, unsigned>
131 bool OutlineFromLinkOnceODRs)
const override;
136 unsigned &Flags)
const override;
142 std::vector<outliner::Candidate> &RepeatedSequenceLocs)
const override;
147 unsigned Flags)
const override;
161 unsigned &SrcOpIdx2)
const override;
164 unsigned OpIdx2)
const override;
201 namespace RISCVVPseudosTable {
208 #define GET_RISCVVPseudosTable_DECL
209 #include "RISCVGenSearchableTables.inc"
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
This is an optimization pass for GlobalISel generic memory operations.
RISCVInstrInfo(RISCVSubtarget &STI)
const MCInstrDesc & getBrCond(RISCVCC::CondCode CC) const
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
CondCode getOppositeBranchCondition(CondCode)
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
InstrType
Represents how an instruction should be mapped by the outliner.
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
const RISCVSubtarget & STI
static constexpr int64_t VLMaxSentinel
Instances of this class represent a single low-level machine instruction.
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
The information necessary to create an outlined function for some class of candidate.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned const TargetRegisterInfo * TRI
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
Optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode) const
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
(vector float) vec_cmpeq(*A, *B) C
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isRVVSpill(const MachineInstr &MI, bool CheckFIs) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MCInst getNop() const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Representation of each machine instruction.
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
An individual sequence of instructions to be replaced with a call to an outlined function.
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
A Module instance is used to store all the information related to an LLVM module.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock MachineBasicBlock::iterator MBBI
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Register getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, int64_t Amount, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
Wrapper class representing virtual and physical registers.
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Wrapper class representing physical registers. Should be passed by value.