LLVM  13.0.0git
RISCVInstrInfo.h
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1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15 
16 #include "RISCVRegisterInfo.h"
18 #include "llvm/IR/DiagnosticInfo.h"
19 
20 #define GET_INSTRINFO_HEADER
21 #include "RISCVGenInstrInfo.inc"
22 
23 namespace llvm {
24 
25 class RISCVSubtarget;
26 
28 
29 public:
31 
32  MCInst getNop() const override;
33 
34  unsigned isLoadFromStackSlot(const MachineInstr &MI,
35  int &FrameIndex) const override;
36  unsigned isStoreToStackSlot(const MachineInstr &MI,
37  int &FrameIndex) const override;
38 
40  const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
41  bool KillSrc) const override;
42 
45  bool IsKill, int FrameIndex,
46  const TargetRegisterClass *RC,
47  const TargetRegisterInfo *TRI) const override;
48 
51  int FrameIndex, const TargetRegisterClass *RC,
52  const TargetRegisterInfo *TRI) const override;
53 
54  // Materializes the given integer Val into DstReg.
56  const DebugLoc &DL, Register DstReg, uint64_t Val,
58 
59  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
60 
62  MachineBasicBlock *&FBB,
64  bool AllowModify) const override;
65 
68  const DebugLoc &dl,
69  int *BytesAdded = nullptr) const override;
70 
72  MachineBasicBlock &NewDestBB,
73  const DebugLoc &DL, int64_t BrOffset,
74  RegScavenger *RS = nullptr) const override;
75 
77  int *BytesRemoved = nullptr) const override;
78 
79  bool
81 
82  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
83 
84  bool isBranchOffsetInRange(unsigned BranchOpc,
85  int64_t BrOffset) const override;
86 
87  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
88 
90  isCopyInstrImpl(const MachineInstr &MI) const override;
91 
92  bool verifyInstruction(const MachineInstr &MI,
93  StringRef &ErrInfo) const override;
94 
96  const MachineOperand *&BaseOp,
97  int64_t &Offset, unsigned &Width,
98  const TargetRegisterInfo *TRI) const;
99 
101  const MachineInstr &MIb) const override;
102 
103 
104  std::pair<unsigned, unsigned>
105  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
106 
109 
110  // Return true if the function can safely be outlined from.
111  virtual bool
113  bool OutlineFromLinkOnceODRs) const override;
114 
115  // Return true if MBB is safe to outline from, and return any target-specific
116  // information in Flags.
118  unsigned &Flags) const override;
119 
120  // Calculate target-specific information for a set of outlining candidates.
122  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
123 
124  // Return if/how a given MachineInstr should be outlined.
125  virtual outliner::InstrType
127  unsigned Flags) const override;
128 
129  // Insert a custom frame for outlined functions.
130  virtual void
132  const outliner::OutlinedFunction &OF) const override;
133 
134  // Insert a call to an outlined function into a given basic block.
138  const outliner::Candidate &C) const override;
139 
140  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
141  unsigned &SrcOpIdx2) const override;
143  unsigned OpIdx1,
144  unsigned OpIdx2) const override;
145 
148  const DebugLoc &DL, int64_t Amount) const;
149 
151  isRVVSpillForZvlsseg(unsigned Opcode) const;
152 
153 protected:
155 };
156 
157 namespace RISCVVPseudosTable {
158 
159 struct PseudoInfo {
162 };
163 
164 #define GET_RISCVVPseudosTable_DECL
165 #include "RISCVGenSearchableTables.inc"
166 
167 } // end namespace RISCVVPseudosTable
168 
169 } // end namespace llvm
170 #endif
llvm::RISCVInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: RISCVInstrInfo.cpp:674
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: RISCVInstrInfo.cpp:959
llvm
Definition: AllocatorList.h:23
llvm::RISCVInstrInfo::RISCVInstrInfo
RISCVInstrInfo(RISCVSubtarget &STI)
Definition: RISCVInstrInfo.cpp:49
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::RISCVInstrInfo::getOutliningType
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
Definition: RISCVInstrInfo.cpp:1046
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:34
TargetInstrInfo.h
llvm::RISCVInstrInfo::insertIndirectBranch
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
Definition: RISCVInstrInfo.cpp:638
llvm::RISCVInstrInfo::STI
const RISCVSubtarget & STI
Definition: RISCVInstrInfo.h:154
llvm::Optional
Definition: APInt.h:33
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::RISCVVPseudosTable::PseudoInfo
Definition: RISCVInstrInfo.h:159
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:183
llvm::RISCVInstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: RISCVInstrInfo.cpp:682
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:164
llvm::RISCVInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: RISCVInstrInfo.cpp:62
llvm::RISCVInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: RISCVInstrInfo.cpp:689
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
RISCVGenInstrInfo
llvm::RISCVInstrInfo::isRVVSpillForZvlsseg
Optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode) const
Definition: RISCVInstrInfo.cpp:1398
llvm::RISCVVPseudosTable::PseudoInfo::BaseInstr
uint16_t BaseInstr
Definition: RISCVInstrInfo.h:161
llvm::RISCVInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: RISCVInstrInfo.cpp:1153
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::RISCVInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: RISCVInstrInfo.cpp:499
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::RISCVInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: RISCVInstrInfo.cpp:953
llvm::RISCVInstrInfo::insertOutlinedCall
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
Definition: RISCVInstrInfo.cpp:1122
llvm::RISCVInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: RISCVInstrInfo.cpp:567
llvm::RISCVInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: RISCVInstrInfo.cpp:242
llvm::RISCVInstrInfo::getNop
MCInst getNop() const override
Definition: RISCVInstrInfo.cpp:53
llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: RISCVInstrInfo.cpp:921
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::RISCVInstrInfo::isFunctionSafeToOutlineFrom
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
Definition: RISCVInstrInfo.cpp:976
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:38
llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Definition: RISCVInstrInfo.cpp:898
llvm::RISCVInstrInfo::isMBBSafeToOutlineFrom
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Definition: RISCVInstrInfo.cpp:993
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:81
llvm::RISCVInstrInfo::isCopyInstrImpl
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
Definition: RISCVInstrInfo.cpp:824
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:80
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:27
llvm::RISCVInstrInfo::getVLENFactoredAmount
Register getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, int64_t Amount) const
Definition: RISCVInstrInfo.cpp:1356
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:167
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::RISCVInstrInfo::movImm
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
Definition: RISCVInstrInfo.cpp:428
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RISCVInstrInfo::buildOutlinedFrame
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Definition: RISCVInstrInfo.cpp:1094
llvm::RISCVInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
Definition: RISCVInstrInfo.cpp:601
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::RISCVInstrInfo::getOutliningCandidateInfo
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Definition: RISCVInstrInfo.cpp:1004
uint16_t
DiagnosticInfo.h
llvm::RISCVInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: RISCVInstrInfo.cpp:89
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::RISCVInstrInfo::isAsCheapAsAMove
bool isAsCheapAsAMove(const MachineInstr &MI) const override
Definition: RISCVInstrInfo.cpp:803
llvm::RISCVInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Definition: RISCVInstrInfo.cpp:1268
llvm::RISCVVPseudosTable::PseudoInfo::Pseudo
uint16_t Pseudo
Definition: RISCVInstrInfo.h:160
llvm::RISCVInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: RISCVInstrInfo.cpp:336
llvm::RISCVInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
Definition: RISCVInstrInfo.cpp:120
llvm::RISCVInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: RISCVInstrInfo.cpp:847
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::RISCVInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: RISCVInstrInfo.cpp:713
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
RISCVRegisterInfo.h