LLVM 17.0.0git
RISCVInstrInfo.h
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1//===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISCV implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15
16#include "RISCVRegisterInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#define GET_INSTRINFO_OPERAND_ENUM
22#include "RISCVGenInstrInfo.inc"
23
24namespace llvm {
25
26class RISCVSubtarget;
27
28namespace RISCVCC {
29
38};
39
41
42} // end of namespace RISCVCC
43
45
46public:
48
49 MCInst getNop() const override;
51
52 unsigned isLoadFromStackSlot(const MachineInstr &MI,
53 int &FrameIndex) const override;
54 unsigned isStoreToStackSlot(const MachineInstr &MI,
55 int &FrameIndex) const override;
56
58 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
59 bool KillSrc) const override;
60
63 bool IsKill, int FrameIndex,
64 const TargetRegisterClass *RC,
66 Register VReg) const override;
67
70 int FrameIndex, const TargetRegisterClass *RC,
72 Register VReg) const override;
73
78 int FrameIndex,
79 LiveIntervals *LIS = nullptr,
80 VirtRegMap *VRM = nullptr) const override;
81
82 // Materializes the given integer Val into DstReg.
84 const DebugLoc &DL, Register DstReg, uint64_t Val,
86
87 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
88
92 bool AllowModify) const override;
93
96 const DebugLoc &dl,
97 int *BytesAdded = nullptr) const override;
98
100 MachineBasicBlock &NewDestBB,
101 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
102 int64_t BrOffset, RegScavenger *RS) const override;
103
105 int *BytesRemoved = nullptr) const override;
106
107 bool
109
110 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
111
112 bool isBranchOffsetInRange(unsigned BranchOpc,
113 int64_t BrOffset) const override;
114
115 bool analyzeSelect(const MachineInstr &MI,
116 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
117 unsigned &FalseOp, bool &Optimizable) const override;
118
121 bool) const override;
122
123 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
124
125 std::optional<DestSourcePair>
126 isCopyInstrImpl(const MachineInstr &MI) const override;
127
129 StringRef &ErrInfo) const override;
130
132 const MachineOperand *&BaseOp,
133 int64_t &Offset, unsigned &Width,
134 const TargetRegisterInfo *TRI) const;
135
137 const MachineInstr &MIb) const override;
138
139
140 std::pair<unsigned, unsigned>
141 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
142
145
146 // Return true if the function can safely be outlined from.
148 bool OutlineFromLinkOnceODRs) const override;
149
150 // Return true if MBB is safe to outline from, and return any target-specific
151 // information in Flags.
153 unsigned &Flags) const override;
154
156
157 // Calculate target-specific information for a set of outlining candidates.
159 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
160
161 // Return if/how a given MachineInstr should be outlined.
163 unsigned Flags) const override;
164
165 // Insert a custom frame for outlined functions.
167 const outliner::OutlinedFunction &OF) const override;
168
169 // Insert a call to an outlined function into a given basic block.
173 outliner::Candidate &C) const override;
174
175 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
176 unsigned &SrcOpIdx2) const override;
178 unsigned OpIdx1,
179 unsigned OpIdx2) const override;
180
182 LiveIntervals *LIS) const override;
183
184 // MIR printer helper function to annotate Operands with a comment.
185 std::string
187 unsigned OpIdx,
188 const TargetRegisterInfo *TRI) const override;
189
193 int64_t Amount, MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
194
195 bool useMachineCombiner() const override { return true; }
196
197 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
198 MachineInstr &NewMI1,
199 MachineInstr &NewMI2) const override;
200 bool
203 bool DoRegPressureReduce) const override;
204
205 void
207 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
208
213 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
214
215 bool hasReassociableSibling(const MachineInstr &Inst,
216 bool &Commuted) const override;
217
219 bool Invert) const override;
220
221 std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override;
222
223 // Returns true if all uses of OrigMI only depend on the lower \p NBits bits
224 // of its output.
226 unsigned NBits) const;
227 // Returns true if all uses of OrigMI only depend on the lower word of its
228 // output, so we can transform OrigMI to the corresponding W-version.
230 const MachineRegisterInfo &MRI) const {
231 return hasAllNBitUsers(MI, MRI, 32);
232 }
233
234protected:
236};
237
238namespace RISCV {
239
240// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
241bool isSEXT_W(const MachineInstr &MI);
242bool isZEXT_W(const MachineInstr &MI);
243bool isZEXT_B(const MachineInstr &MI);
244
245// Returns true if the given MI is an RVV instruction opcode for which we may
246// expect to see a FrameIndex operand.
247bool isRVVSpill(const MachineInstr &MI);
248
249std::optional<std::pair<unsigned, unsigned>>
250isRVVSpillForZvlsseg(unsigned Opcode);
251
252bool isFaultFirstLoad(const MachineInstr &MI);
253
254// Implemented in RISCVGenInstrInfo.inc
255int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
256
257// Return true if both input instructions have equal rounding mode. If at least
258// one of the instructions does not have rounding mode, false will be returned.
259bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
260
261// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
262static constexpr int64_t VLMaxSentinel = -1LL;
263
264} // namespace RISCV
265
266namespace RISCVVPseudosTable {
267
271};
272
273#define GET_RISCVVPseudosTable_DECL
274#include "RISCVGenSearchableTables.inc"
275
276} // end namespace RISCVVPseudosTable
277
278} // end namespace llvm
279#endif
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
SmallVector< MachineOperand, 4 > Cond
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
#define P(N)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool hasAllNBitUsers(const MachineInstr &MI, const MachineRegisterInfo &MRI, unsigned NBits) const
const MCInstrDesc & getBrCond(RISCVCC::CondCode CC) const
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const override
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool hasAllWUsers(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
const RISCVSubtarget & STI
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
bool useMachineCombiner() const override
std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MCInst getNop() const override
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
void getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, int64_t Amount, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
CondCode getOppositeBranchCondition(CondCode)
bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2)
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
bool isSEXT_W(const MachineInstr &MI)
bool isFaultFirstLoad(const MachineInstr &MI)
std::optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode)
bool isZEXT_B(const MachineInstr &MI)
bool isRVVSpill(const MachineInstr &MI)
static constexpr int64_t VLMaxSentinel
bool isZEXT_W(const MachineInstr &MI)
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.