LLVM 17.0.0git
RISCVInstrInfo.h
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1//===-- RISCVInstrInfo.h - RISC-V Instruction Information -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15
16#include "RISCVRegisterInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#define GET_INSTRINFO_OPERAND_ENUM
22#include "RISCVGenInstrInfo.inc"
23
24namespace llvm {
25
26class RISCVSubtarget;
27
32
33namespace RISCVCC {
34
43};
44
46
47} // end of namespace RISCVCC
48
50
51public:
53
54 MCInst getNop() const override;
56
57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
58 int &FrameIndex) const override;
59 unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
60 unsigned &MemBytes) const override;
61 unsigned isStoreToStackSlot(const MachineInstr &MI,
62 int &FrameIndex) const override;
63 unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
64 unsigned &MemBytes) const override;
65
67 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
68 bool KillSrc) const override;
69
72 bool IsKill, int FrameIndex,
73 const TargetRegisterClass *RC,
75 Register VReg) const override;
76
79 int FrameIndex, const TargetRegisterClass *RC,
81 Register VReg) const override;
82
87 int FrameIndex,
88 LiveIntervals *LIS = nullptr,
89 VirtRegMap *VRM = nullptr) const override;
90
91 // Materializes the given integer Val into DstReg.
93 const DebugLoc &DL, Register DstReg, uint64_t Val,
95
96 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
97
101 bool AllowModify) const override;
102
105 const DebugLoc &dl,
106 int *BytesAdded = nullptr) const override;
107
109 MachineBasicBlock &NewDestBB,
110 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
111 int64_t BrOffset, RegScavenger *RS) const override;
112
114 int *BytesRemoved = nullptr) const override;
115
116 bool
118
119 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
120
121 bool isBranchOffsetInRange(unsigned BranchOpc,
122 int64_t BrOffset) const override;
123
124 bool analyzeSelect(const MachineInstr &MI,
125 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
126 unsigned &FalseOp, bool &Optimizable) const override;
127
130 bool) const override;
131
132 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
133
134 std::optional<DestSourcePair>
135 isCopyInstrImpl(const MachineInstr &MI) const override;
136
138 StringRef &ErrInfo) const override;
139
141 const MachineOperand *&BaseOp,
142 int64_t &Offset, unsigned &Width,
143 const TargetRegisterInfo *TRI) const;
144
146 const MachineInstr &MIb) const override;
147
148
149 std::pair<unsigned, unsigned>
150 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
151
154
155 // Return true if the function can safely be outlined from.
157 bool OutlineFromLinkOnceODRs) const override;
158
159 // Return true if MBB is safe to outline from, and return any target-specific
160 // information in Flags.
162 unsigned &Flags) const override;
163
165
166 // Calculate target-specific information for a set of outlining candidates.
167 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
168 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
169
170 // Return if/how a given MachineInstr should be outlined.
171 virtual outliner::InstrType
173 unsigned Flags) const override;
174
175 // Insert a custom frame for outlined functions.
177 const outliner::OutlinedFunction &OF) const override;
178
179 // Insert a call to an outlined function into a given basic block.
183 outliner::Candidate &C) const override;
184
185 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
186 unsigned &SrcOpIdx2) const override;
188 unsigned OpIdx1,
189 unsigned OpIdx2) const override;
190
192 LiveIntervals *LIS) const override;
193
194 // MIR printer helper function to annotate Operands with a comment.
195 std::string
197 unsigned OpIdx,
198 const TargetRegisterInfo *TRI) const override;
199
203 int64_t Amount, MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
204
205 bool useMachineCombiner() const override { return true; }
206
208
209 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
210 MachineInstr &NewMI1,
211 MachineInstr &NewMI2) const override;
212 bool
215 bool DoRegPressureReduce) const override;
216
217 void
219 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
220
225 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
226
227 bool hasReassociableSibling(const MachineInstr &Inst,
228 bool &Commuted) const override;
229
231 bool Invert) const override;
232
233 std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override;
234
237
238protected:
240};
241
242namespace RISCV {
243
244// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
245bool isSEXT_W(const MachineInstr &MI);
246bool isZEXT_W(const MachineInstr &MI);
247bool isZEXT_B(const MachineInstr &MI);
248
249// Returns true if the given MI is an RVV instruction opcode for which we may
250// expect to see a FrameIndex operand.
251bool isRVVSpill(const MachineInstr &MI);
252
253std::optional<std::pair<unsigned, unsigned>>
254isRVVSpillForZvlsseg(unsigned Opcode);
255
256bool isFaultFirstLoad(const MachineInstr &MI);
257
258// Implemented in RISCVGenInstrInfo.inc
259int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
260
261// Return true if both input instructions have equal rounding mode. If at least
262// one of the instructions does not have rounding mode, false will be returned.
263bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
264
265// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
266static constexpr int64_t VLMaxSentinel = -1LL;
267
268// Mask assignments for floating-point
269static constexpr unsigned FPMASK_Negative_Infinity = 0x001;
270static constexpr unsigned FPMASK_Negative_Normal = 0x002;
271static constexpr unsigned FPMASK_Negative_Subnormal = 0x004;
272static constexpr unsigned FPMASK_Negative_Zero = 0x008;
273static constexpr unsigned FPMASK_Positive_Zero = 0x010;
274static constexpr unsigned FPMASK_Positive_Subnormal = 0x020;
275static constexpr unsigned FPMASK_Positive_Normal = 0x040;
276static constexpr unsigned FPMASK_Positive_Infinity = 0x080;
277static constexpr unsigned FPMASK_Signaling_NaN = 0x100;
278static constexpr unsigned FPMASK_Quiet_NaN = 0x200;
279} // namespace RISCV
280
281namespace RISCVVPseudosTable {
282
286};
287
288#define GET_RISCVVPseudosTable_DECL
289#include "RISCVGenSearchableTables.inc"
290
291} // end namespace RISCVVPseudosTable
292
293} // end namespace llvm
294#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
SmallVector< MachineOperand, 4 > Cond
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
#define P(N)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
@ Flags
Definition: TextStubV5.cpp:93
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MCInstrDesc & getBrCond(RISCVCC::CondCode CC) const
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const override
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
const RISCVSubtarget & STI
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
bool useMachineCombiner() const override
std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
MachineTraceStrategy getMachineCombinerTraceStrategy() const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
virtual outliner::InstrType getOutliningTypeImpl(MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
MCInst getNop() const override
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
void getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, int64_t Amount, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
CondCode getOppositeBranchCondition(CondCode)
static constexpr unsigned FPMASK_Negative_Zero
static constexpr unsigned FPMASK_Positive_Subnormal
bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2)
static constexpr unsigned FPMASK_Positive_Normal
static constexpr unsigned FPMASK_Negative_Subnormal
static constexpr unsigned FPMASK_Negative_Normal
static constexpr unsigned FPMASK_Positive_Infinity
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
static constexpr unsigned FPMASK_Negative_Infinity
static constexpr unsigned FPMASK_Quiet_NaN
bool isSEXT_W(const MachineInstr &MI)
bool isFaultFirstLoad(const MachineInstr &MI)
std::optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode)
static constexpr unsigned FPMASK_Signaling_NaN
bool isZEXT_B(const MachineInstr &MI)
static constexpr unsigned FPMASK_Positive_Zero
bool isRVVSpill(const MachineInstr &MI)
static constexpr int64_t VLMaxSentinel
bool isZEXT_W(const MachineInstr &MI)
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
MachineTraceStrategy
Strategies for selecting traces.
static const MachineMemOperand::Flags MONontemporalBit1
static const MachineMemOperand::Flags MONontemporalBit0
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.