LLVM 18.0.0git
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#include "RISCV.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include <queue>
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "riscv-insert-vsetvli" |
#define | RISCV_INSERT_VSETVLI_NAME "RISC-V Insert VSETVLI pass" |
Functions | |
INITIALIZE_PASS (RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME, false, false) static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI | |
if (!hasUndefinedMergeOp(MI, *MRI)) | |
assert (RISCVVType::isValidSEW(SEW) &&"Unexpected SEW") | |
if (RISCVII::hasVLOp(TSFlags)) | |
InstrInfo | setAVLReg (RISCV::NoRegister) |
if (std::optional< unsigned > EEW=getEEWForLoadStore(MI)) | |
InstrInfo | setVTYPE (VLMul, SEW, TailAgnostic, MaskAgnostic) |
static VSETVLIInfo | getInfoForVSETVLI (const MachineInstr &MI) |
static bool | isLMUL1OrSmaller (RISCVII::VLMUL LMUL) |
static bool | hasFixedResult (const VSETVLIInfo &Info, const RISCVSubtarget &ST) |
Return true if the VL value configured must be equal to the requested one. | |
static void | doUnion (DemandedFields &A, DemandedFields B) |
static bool | isNonZeroAVL (const MachineOperand &MO) |
static bool | canMutatePriorConfig (const MachineInstr &PrevMI, const MachineInstr &MI, const DemandedFields &Used) |
Variables | |
static cl::opt< bool > | DisableInsertVSETVLPHIOpt ("riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, cl::desc("Disable looking through phis when inserting vsetvlis.")) |
static cl::opt< bool > | UseStrictAsserts ("riscv-insert-vsetvl-strict-asserts", cl::init(true), cl::Hidden, cl::desc("Enable strict assertion checking for the dataflow algorithm")) |
uint64_t | TSFlags |
uint64_t const MachineRegisterInfo * | MRI |
bool | TailAgnostic = true |
bool | MaskAgnostic = true |
RISCVII::VLMUL | VLMul = RISCVII::getLMul(TSFlags) |
unsigned | Log2SEW = MI.getOperand(getSEWOpNum(MI)).getImm() |
unsigned | SEW = Log2SEW ? 1 << Log2SEW : 8 |
else | |
return | InstrInfo |
#define DEBUG_TYPE "riscv-insert-vsetvli" |
Definition at line 34 of file RISCVInsertVSETVLI.cpp.
#define RISCV_INSERT_VSETVLI_NAME "RISC-V Insert VSETVLI pass" |
Definition at line 35 of file RISCVInsertVSETVLI.cpp.
assert | ( | RISCVVType::isValidSEW(SEW) &&"Unexpected SEW" | ) |
Referenced by getInfoForVSETVLI(), if(), and isNonZeroAVL().
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Definition at line 1431 of file RISCVInsertVSETVLI.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), isNonZeroAVL(), and MI.
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Definition at line 1412 of file RISCVInsertVSETVLI.cpp.
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Definition at line 845 of file RISCVInsertVSETVLI.cpp.
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Return true if the VL value configured must be equal to the requested one.
Definition at line 1304 of file RISCVInsertVSETVLI.cpp.
References llvm::RISCVVType::decodeVLMUL(), Info, and SEW.
if | ( | ! | hasUndefinedMergeOpMI, *MRI | ) |
Definition at line 779 of file RISCVInsertVSETVLI.cpp.
References assert(), llvm::RISCVII::doesForceTailAgnostic(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVII::MASK_AGNOSTIC, MaskAgnostic, MI, llvm::RISCVII::TAIL_AGNOSTIC, TailAgnostic, TSFlags, and llvm::RISCVII::usesMaskPolicy().
if | ( | RISCVII::hasVLOp(TSFlags) | ) |
Definition at line 810 of file RISCVInsertVSETVLI.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), InstrInfo, llvm::MachineOperand::isImm(), MI, and llvm::RISCV::VLMaxSentinel.
Definition at line 827 of file RISCVInsertVSETVLI.cpp.
INITIALIZE_PASS | ( | RISCVInsertVSETVLI | , |
DEBUG_TYPE | , | ||
RISCV_INSERT_VSETVLI_NAME | , | ||
false | , | ||
false | |||
) | const & |
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Definition at line 946 of file RISCVInsertVSETVLI.cpp.
References llvm::RISCVVType::decodeVLMUL().
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Definition at line 1422 of file RISCVInsertVSETVLI.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
Referenced by canMutatePriorConfig(), combineBinOpToReduce(), and lowerReductionSeq().
InstrInfo setAVLReg | ( | RISCV::NoRegister | ) |
InstrInfo setVTYPE | ( | VLMul | , |
SEW | , | ||
TailAgnostic | , | ||
MaskAgnostic | |||
) |
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else |
Definition at line 822 of file RISCVInsertVSETVLI.cpp.
return InstrInfo |
Definition at line 833 of file RISCVInsertVSETVLI.cpp.
Referenced by llvm::AArch64Subtarget::AArch64Subtarget(), llvm::ARCSubtarget::ARCSubtarget(), llvm::ARMSubtarget::ARMSubtarget(), llvm::AVRSubtarget::AVRSubtarget(), llvm::createLanaiMCCodeEmitter(), llvm::CSKYSubtarget::CSKYSubtarget(), llvm::GCNSubtarget::GCNSubtarget(), llvm::GCNSubtarget::getInstrInfo(), llvm::R600Subtarget::getInstrInfo(), llvm::ARCSubtarget::getInstrInfo(), llvm::BPFSubtarget::getInstrInfo(), llvm::CSKYSubtarget::getInstrInfo(), llvm::DirectXSubtarget::getInstrInfo(), llvm::HexagonSubtarget::getInstrInfo(), llvm::LoongArchSubtarget::getInstrInfo(), llvm::MipsSubtarget::getInstrInfo(), llvm::MSP430Subtarget::getInstrInfo(), llvm::NVPTXSubtarget::getInstrInfo(), llvm::RISCVSubtarget::getInstrInfo(), llvm::SparcSubtarget::getInstrInfo(), llvm::SPIRVSubtarget::getInstrInfo(), llvm::SystemZSubtarget::getInstrInfo(), llvm::VESubtarget::getInstrInfo(), llvm::WebAssemblySubtarget::getInstrInfo(), llvm::X86Subtarget::getInstrInfo(), llvm::XCoreSubtarget::getInstrInfo(), llvm::GCNSubtarget::getRegisterInfo(), llvm::R600Subtarget::getRegisterInfo(), llvm::ARCSubtarget::getRegisterInfo(), llvm::BPFSubtarget::getRegisterInfo(), llvm::MipsSubtarget::getRegisterInfo(), llvm::NVPTXSubtarget::getRegisterInfo(), llvm::SparcSubtarget::getRegisterInfo(), llvm::SPIRVSubtarget::getRegisterInfo(), llvm::SystemZSubtarget::getRegisterInfo(), llvm::VESubtarget::getRegisterInfo(), llvm::XCoreSubtarget::getRegisterInfo(), llvm::AMDGPU::getVOPDInstInfo(), llvm::HexagonSubtarget::HexagonSubtarget(), if(), llvm::GenericUniformityAnalysisImpl< ContextT >::initialize(), llvm::LoongArchSubtarget::LoongArchSubtarget(), llvm::M68kSubtarget::M68kSubtarget(), llvm::MipsSubtarget::MipsSubtarget(), llvm::MSP430Subtarget::MSP430Subtarget(), llvm::PerTargetMIParsingState::parseInstrName(), llvm::PPCSubtarget::PPCSubtarget(), llvm::R600Subtarget::R600Subtarget(), llvm::PPCRegisterInfo::requiresFrameIndexScavenging(), llvm::RISCVSubtarget::RISCVSubtarget(), llvm::SparcSubtarget::SparcSubtarget(), llvm::SPIRVSubtarget::SPIRVSubtarget(), llvm::SystemZSubtarget::SystemZSubtarget(), llvm::VESubtarget::VESubtarget(), llvm::WebAssemblySubtarget::WebAssemblySubtarget(), and llvm::X86Subtarget::X86Subtarget().
Definition at line 805 of file RISCVInsertVSETVLI.cpp.
Referenced by llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), llvm::RISCVInstrInfo::createMIROperandComment(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLSEG(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), and llvm::RISCVInstrInfo::verifyInstruction().
Definition at line 778 of file RISCVInsertVSETVLI.cpp.
Referenced by llvm::RISCVVType::encodeVTYPE(), and if().
Definition at line 774 of file RISCVInsertVSETVLI.cpp.
Definition at line 807 of file RISCVInsertVSETVLI.cpp.
Referenced by llvm::mca::RISCVInstrumentManager::createInstruments(), llvm::RISCVInstrInfo::createMIROperandComment(), llvm::RISCVVType::encodeSEW(), llvm::RISCVVType::encodeVTYPE(), llvm::mca::RISCVInstrumentManager::getSchedClassID(), llvm::RISCVVType::getSEWLMULRatio(), hasFixedResult(), if(), llvm::RISCVVType::isValidSEW(), lowerVectorIntrinsicScalars(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), and llvm::RISCVInstrInfo::verifyInstruction().
Definition at line 777 of file RISCVInsertVSETVLI.cpp.
Referenced by llvm::RISCVVType::encodeVTYPE(), and if().
uint64_t TSFlags |
Definition at line 773 of file RISCVInsertVSETVLI.cpp.
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::RISCVInstrInfo::createMIROperandComment(), decodeOperand_AVLdSt_Any(), llvm::RISCVII::doesForceTailAgnostic(), getBaseOffset(), llvm::X86II::getBaseOpcodeFor(), llvm::getFMA3Group(), llvm::RISCVII::getFormat(), llvm::RISCVII::getFRMOpNum(), getImmFixupKind(), llvm::RISCVII::getLMul(), llvm::X86II::getMemoryOperandNo(), llvm::RISCVII::getSEWOpNum(), llvm::X86II::getSizeOfImm(), getThreeSrcCommuteCase(), llvm::RISCVII::getVLOpNum(), llvm::RISCVII::getVXRMOpNum(), llvm::X86II::hasImm(), llvm::RISCVII::hasRoundModeOp(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVII::hasVLOp(), if(), isConvertibleToVMV_V_V(), isDispOrCDisp8(), llvm::R600InstrInfo::isExport(), llvm::X86II::isImmPCRel(), llvm::X86II::isImmSigned(), llvm::X86II::isKMasked(), llvm::X86II::isKMergeMasked(), llvm::X86II::isPrefix(), llvm::X86II::isPseudo(), isRIPRelative(), llvm::RISCVII::isRVVWideningReduction(), isSignExtendingOpW(), llvm::RISCVII::isTiedPseudo(), lowerRISCVVMachineInstrToMCInst(), llvm::X86_MC::needsAddressSizeOverride(), llvm::X86::optimizeInstFromVEX3ToVEX2(), llvm::X86InstPrinterCommon::printInstFlags(), printMasking(), llvm::CSKYInstPrinter::printOperand(), llvm::SIInstrInfo::pseudoToMCOpcode(), llvm::RISCVII::usesMaskPolicy(), llvm::RISCVII::usesVXRM(), and llvm::RISCVInstrInfo::verifyInstruction().
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RISCVII::VLMUL VLMul = RISCVII::getLMul(TSFlags) |
Definition at line 803 of file RISCVInsertVSETVLI.cpp.
Referenced by llvm::RISCVVType::getSEWLMULRatio(), and llvm::RISCVDAGToDAGISel::selectVSETVLI().