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19 #ifndef LLVM_CODEGEN_LIVEINTERVALS_H
20 #define LLVM_CODEGEN_LIVEINTERVALS_H
43 class LiveIntervalCalc;
44 class MachineBlockFrequencyInfo;
45 class MachineDominatorTree;
46 class MachineFunction;
48 class MachineRegisterInfo;
50 class TargetInstrInfo;
114 return *VirtRegIntervals[
Reg.id()];
125 VirtRegIntervals[
Reg.id()];
131 VirtRegIntervals.
grow(
Reg.id());
132 VirtRegIntervals[
Reg.id()] = createInterval(
Reg);
133 return *VirtRegIntervals[
Reg.id()];
138 computeVirtRegInterval(LI);
144 delete VirtRegIntervals[
Reg];
145 VirtRegIntervals[
Reg] =
nullptr;
206 "Use pruneValue on the main LiveRange and on each subrange");
255 assert(
unsigned(
MBB->getNumber()) == RegMaskBlocks.size() &&
256 "Blocks must be added in order.");
257 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
316 bool UpdateFlags =
false);
350 std::pair<unsigned, unsigned>
P = RegMaskBlocks[MBBNum];
361 std::pair<unsigned, unsigned>
P = RegMaskBlocks[MBBNum];
393 computeRegUnitRange(*LR, Unit);
401 return RegUnitRanges[Unit];
405 return RegUnitRanges[Unit];
411 delete RegUnitRanges[Unit];
412 RegUnitRanges[Unit] =
nullptr;
444 void computeVirtRegs();
447 void computeRegMasks();
462 void dumpInstrs()
const;
464 void computeLiveInRegUnits();
465 void computeRegUnitRange(
LiveRange&,
unsigned Unit);
469 void extendSegmentsToUses(
LiveRange &Segments,
LiveInterval::Segment addSegmentToEndOfBlock(Register Reg, MachineInstr &startInst)
Given a register and an instruction, adds a live segment from that instruction to the end of its MBB.
void insertMBBInMaps(MachineBasicBlock *mbb)
Add the given MachineBasicBlock into the maps.
This is an optimization pass for GlobalISel generic memory operations.
SlotIndexes * getSlotIndexes() const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const
Returns a sorted array of slot indices of all instructions with register mask operands in the basic b...
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Reg
All possible values of the reg field in the ModR/M byte.
This represents a simple continuous liveness interval for a value.
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
If LI is confined to a single basic block, return a pointer to that block.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void addKillFlags(const VirtRegMap *)
Add kill flags to any instruction that kills a virtual register.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void removeAllRegUnitsForPhysReg(MCRegister Reg)
Remove associated live ranges for the register units associated with Reg.
void removeInterval(Register Reg)
Interval removal.
ArrayRef< SlotIndex > getRegMaskSlots() const
Returns a sorted array of slot indices of all instructions with register mask operands.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
const LiveInterval & getInterval(Register Reg) const
#define LLVM_ATTRIBUTE_UNUSED
unsigned const TargetRegisterInfo * TRI
void removeRegUnit(unsigned Unit)
Remove computed live range for register unit Unit.
LiveInterval & createAndComputeVirtRegInterval(Register Reg)
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
TargetInstrInfo - Interface to description of machine instruction set.
bool liveAt(SlotIndex index) const
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices)
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const
Returns true if VNI is killed by any PHI-def values in LI.
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
bool runOnMachineFunction(MachineFunction &) override
Pass entry point; Calculates LiveIntervals.
Represent the analysis usage information of a pass.
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)
If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
This class implements an extremely fast bulk output stream that can only output to a stream.
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
LiveInterval - This class represents the liveness of a register, or stack slot.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
SlotIndex - An opaque wrapper around machine indexes.
void handleMoveIntoNewBundle(MachineInstr &BundleStart, bool UpdateFlags=false)
Update intervals of operands of all instructions in the newly created bundle specified by BundleStart...
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
void insertMBBInMaps(MachineBasicBlock *MBB)
void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
Representation of each machine instruction.
ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const
Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBBNum).
This class represents the liveness of a register, stack slot, etc.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
SlotIndex replaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in maps used by register allocat...
Allocate memory in an ever growing pool, as if by bump-pointer.
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
bool checkRegMaskInterference(const LiveInterval &LI, BitVector &UsableRegs)
Test if LI is live across any register mask instructions, and compute a bit mask of physical register...
A Module instance is used to store all the information related to an LLVM module.
SI Optimize VGPR LiveRange
LiveInterval & getInterval(Register Reg)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
const LiveRange * getCachedRegUnit(unsigned Unit) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
LiveInterval & createEmptyInterval(Register Reg)
Interval creation.
A live range for subregisters.
Wrapper class representing virtual and physical registers.
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &MI)
Calculate the spill weight to assign to a single instruction.
LLVM_ATTRIBUTE_UNUSED void pruneValue(LiveInterval &, SlotIndex, SmallVectorImpl< SlotIndex > *)
This function should not be used.
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)
Extend the live range LR to reach all points in Indices.
~LiveIntervals() override
VNInfo - Value Number Information.
ArrayRef< const uint32_t * > getRegMaskBits() const
Returns an array of register mask pointers corresponding to getRegMaskSlots().
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range.
@ Kill
The last use of a register.
cl::opt< bool > UseSegmentSetForPhysRegs
bool inBounds(IndexT n) const
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B, MachineBasicBlock::iterator E)
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)
Update live intervals for instructions in a range of iterators.
bool hasInterval(Register Reg) const
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
void removeMachineInstrFromMaps(MachineInstr &MI, bool AllowBundled=false)
Removes machine instruction (bundle) MI from the mapping.
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos.
static constexpr LaneBitmask getAll()
VNInfo::Allocator & getVNInfoAllocator()
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
Wrapper class representing physical registers. Should be passed by value.