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LiveIntervals.h
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1 //===- LiveIntervals.h - Live Interval Analysis -----------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LiveInterval analysis pass. Given some
10 /// numbering of each the machine instructions (in this implemention depth-first
11 /// order) an interval [i, j) is said to be a live interval for register v if
12 /// there is no instruction with number j' > j such that v is live at j' and
13 /// there is no instruction with number i' < i such that v is live at i'. In
14 /// this implementation intervals can have holes, i.e. an interval might look
15 /// like [1,20), [50,65), [1000,1001).
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #ifndef LLVM_CODEGEN_LIVEINTERVALS_H
20 #define LLVM_CODEGEN_LIVEINTERVALS_H
21 
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/IndexedMap.h"
24 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/MC/LaneBitmask.h"
32 #include "llvm/Support/Compiler.h"
34 #include <cassert>
35 #include <cstdint>
36 #include <utility>
37 
38 namespace llvm {
39 
40 extern cl::opt<bool> UseSegmentSetForPhysRegs;
41 
42 class BitVector;
43 class LiveIntervalCalc;
44 class MachineBlockFrequencyInfo;
45 class MachineDominatorTree;
46 class MachineFunction;
47 class MachineInstr;
48 class MachineRegisterInfo;
49 class raw_ostream;
50 class TargetInstrInfo;
51 class VirtRegMap;
52 
54  MachineFunction* MF;
56  const TargetRegisterInfo* TRI;
57  const TargetInstrInfo *TII;
58  SlotIndexes* Indexes;
59  MachineDominatorTree *DomTree = nullptr;
60  LiveIntervalCalc *LICalc = nullptr;
61 
62  /// Special pool allocator for VNInfo's (LiveInterval val#).
63  VNInfo::Allocator VNInfoAllocator;
64 
65  /// Live interval pointers for all the virtual registers.
67 
68  /// Sorted list of instructions with register mask operands. Always use the
69  /// 'r' slot, RegMasks are normal clobbers, not early clobbers.
70  SmallVector<SlotIndex, 8> RegMaskSlots;
71 
72  /// This vector is parallel to RegMaskSlots, it holds a pointer to the
73  /// corresponding register mask. This pointer can be recomputed as:
74  ///
75  /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
76  /// unsigned OpNum = findRegMaskOperand(MI);
77  /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
78  ///
79  /// This is kept in a separate vector partly because some standard
80  /// libraries don't support lower_bound() with mixed objects, partly to
81  /// improve locality when searching in RegMaskSlots.
82  /// Also see the comment in LiveInterval::find().
84 
85  /// For each basic block number, keep (begin, size) pairs indexing into the
86  /// RegMaskSlots and RegMaskBits arrays.
87  /// Note that basic block numbers may not be layout contiguous, that's why
88  /// we can't just keep track of the first register mask in each basic
89  /// block.
91 
92  /// Keeps a live range set for each register unit to track fixed physreg
93  /// interference.
94  SmallVector<LiveRange*, 0> RegUnitRanges;
95 
96  public:
97  static char ID;
98 
99  LiveIntervals();
100  ~LiveIntervals() override;
101 
102  /// Calculate the spill weight to assign to a single instruction.
103  static float getSpillWeight(bool isDef, bool isUse,
104  const MachineBlockFrequencyInfo *MBFI,
105  const MachineInstr &MI);
106 
107  /// Calculate the spill weight to assign to a single instruction.
108  static float getSpillWeight(bool isDef, bool isUse,
109  const MachineBlockFrequencyInfo *MBFI,
110  const MachineBasicBlock *MBB);
111 
113  if (hasInterval(Reg))
114  return *VirtRegIntervals[Reg.id()];
115 
117  }
118 
120  return const_cast<LiveIntervals*>(this)->getInterval(Reg);
121  }
122 
123  bool hasInterval(Register Reg) const {
124  return VirtRegIntervals.inBounds(Reg.id()) &&
125  VirtRegIntervals[Reg.id()];
126  }
127 
128  /// Interval creation.
130  assert(!hasInterval(Reg) && "Interval already exists!");
131  VirtRegIntervals.grow(Reg.id());
132  VirtRegIntervals[Reg.id()] = createInterval(Reg);
133  return *VirtRegIntervals[Reg.id()];
134  }
135 
138  computeVirtRegInterval(LI);
139  return LI;
140  }
141 
142  /// Interval removal.
144  delete VirtRegIntervals[Reg];
145  VirtRegIntervals[Reg] = nullptr;
146  }
147 
148  /// Given a register and an instruction, adds a live segment from that
149  /// instruction to the end of its MBB.
151  MachineInstr &startInst);
152 
153  /// After removing some uses of a register, shrink its live range to just
154  /// the remaining uses. This method does not compute reaching defs for new
155  /// uses, and it doesn't remove dead defs.
156  /// Dead PHIDef values are marked as unused. New dead machine instructions
157  /// are added to the dead vector. Returns true if the interval may have been
158  /// separated into multiple connected components.
159  bool shrinkToUses(LiveInterval *li,
160  SmallVectorImpl<MachineInstr*> *dead = nullptr);
161 
162  /// Specialized version of
163  /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead)
164  /// that works on a subregister live range and only looks at uses matching
165  /// the lane mask of the subregister range.
166  /// This may leave the subrange empty which needs to be cleaned up with
167  /// LiveInterval::removeEmptySubranges() afterwards.
169 
170  /// Extend the live range \p LR to reach all points in \p Indices. The
171  /// points in the \p Indices array must be jointly dominated by the union
172  /// of the existing defs in \p LR and points in \p Undefs.
173  ///
174  /// PHI-defs are added as needed to maintain SSA form.
175  ///
176  /// If a SlotIndex in \p Indices is the end index of a basic block, \p LR
177  /// will be extended to be live out of the basic block.
178  /// If a SlotIndex in \p Indices is jointy dominated only by points in
179  /// \p Undefs, the live range will not be extended to that point.
180  ///
181  /// See also LiveRangeCalc::extend().
183  ArrayRef<SlotIndex> Undefs);
184 
186  extendToIndices(LR, Indices, /*Undefs=*/{});
187  }
188 
189  /// If \p LR has a live value at \p Kill, prune its live range by removing
190  /// any liveness reachable from Kill. Add live range end points to
191  /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
192  /// value's live range.
193  ///
194  /// Calling pruneValue() and extendToIndices() can be used to reconstruct
195  /// SSA form after adding defs to a virtual register.
197  SmallVectorImpl<SlotIndex> *EndPoints);
198 
199  /// This function should not be used. Its intent is to tell you that you are
200  /// doing something wrong if you call pruneValue directly on a
201  /// LiveInterval. Indeed, you are supposed to call pruneValue on the main
202  /// LiveRange and all the LiveRanges of the subranges if any.
206  "Use pruneValue on the main LiveRange and on each subrange");
207  }
208 
210  return Indexes;
211  }
212 
213  /// Returns true if the specified machine instr has been removed or was
214  /// never entered in the map.
215  bool isNotInMIMap(const MachineInstr &Instr) const {
216  return !Indexes->hasIndex(Instr);
217  }
218 
219  /// Returns the base index of the given instruction.
221  return Indexes->getInstructionIndex(Instr);
222  }
223 
224  /// Returns the instruction associated with the given index.
226  return Indexes->getInstructionFromIndex(index);
227  }
228 
229  /// Return the first index in the given basic block.
231  return Indexes->getMBBStartIdx(mbb);
232  }
233 
234  /// Return the last index in the given basic block.
236  return Indexes->getMBBEndIdx(mbb);
237  }
238 
239  bool isLiveInToMBB(const LiveRange &LR,
240  const MachineBasicBlock *mbb) const {
241  return LR.liveAt(getMBBStartIdx(mbb));
242  }
243 
244  bool isLiveOutOfMBB(const LiveRange &LR,
245  const MachineBasicBlock *mbb) const {
246  return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
247  }
248 
250  return Indexes->getMBBFromIndex(index);
251  }
252 
254  Indexes->insertMBBInMaps(MBB);
255  assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
256  "Blocks must be added in order.");
257  RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
258  }
259 
261  return Indexes->insertMachineInstrInMaps(MI);
262  }
263 
266  for (MachineBasicBlock::iterator I = B; I != E; ++I)
267  Indexes->insertMachineInstrInMaps(*I);
268  }
269 
271  Indexes->removeMachineInstrFromMaps(MI);
272  }
273 
275  return Indexes->replaceMachineInstrInMaps(MI, NewMI);
276  }
277 
278  VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
279 
280  void getAnalysisUsage(AnalysisUsage &AU) const override;
281  void releaseMemory() override;
282 
283  /// Pass entry point; Calculates LiveIntervals.
284  bool runOnMachineFunction(MachineFunction&) override;
285 
286  /// Implement the dump method.
287  void print(raw_ostream &O, const Module* = nullptr) const override;
288 
289  /// If LI is confined to a single basic block, return a pointer to that
290  /// block. If LI is live in to or out of any block, return NULL.
292 
293  /// Returns true if VNI is killed by any PHI-def values in LI.
294  /// This may conservatively return true to avoid expensive computations.
295  bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
296 
297  /// Add kill flags to any instruction that kills a virtual register.
298  void addKillFlags(const VirtRegMap*);
299 
300  /// Call this method to notify LiveIntervals that instruction \p MI has been
301  /// moved within a basic block. This will update the live intervals for all
302  /// operands of \p MI. Moves between basic blocks are not supported.
303  ///
304  /// \param UpdateFlags Update live intervals for nonallocatable physregs.
305  void handleMove(MachineInstr &MI, bool UpdateFlags = false);
306 
307  /// Update intervals of operands of all instructions in the newly
308  /// created bundle specified by \p BundleStart.
309  ///
310  /// \param UpdateFlags Update live intervals for nonallocatable physregs.
311  ///
312  /// Assumes existing liveness is accurate.
313  /// \pre BundleStart should be the first instruction in the Bundle.
314  /// \pre BundleStart should not have a have SlotIndex as one will be assigned.
315  void handleMoveIntoNewBundle(MachineInstr &BundleStart,
316  bool UpdateFlags = false);
317 
318  /// Update live intervals for instructions in a range of iterators. It is
319  /// intended for use after target hooks that may insert or remove
320  /// instructions, and is only efficient for a small number of instructions.
321  ///
322  /// OrigRegs is a vector of registers that were originally used by the
323  /// instructions in the range between the two iterators.
324  ///
325  /// Currently, the only only changes that are supported are simple removal
326  /// and addition of uses.
330  ArrayRef<Register> OrigRegs);
331 
332  // Register mask functions.
333  //
334  // Machine instructions may use a register mask operand to indicate that a
335  // large number of registers are clobbered by the instruction. This is
336  // typically used for calls.
337  //
338  // For compile time performance reasons, these clobbers are not recorded in
339  // the live intervals for individual physical registers. Instead,
340  // LiveIntervalAnalysis maintains a sorted list of instructions with
341  // register mask operands.
342 
343  /// Returns a sorted array of slot indices of all instructions with
344  /// register mask operands.
345  ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
346 
347  /// Returns a sorted array of slot indices of all instructions with register
348  /// mask operands in the basic block numbered \p MBBNum.
350  std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
351  return getRegMaskSlots().slice(P.first, P.second);
352  }
353 
354  /// Returns an array of register mask pointers corresponding to
355  /// getRegMaskSlots().
356  ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
357 
358  /// Returns an array of mask pointers corresponding to
359  /// getRegMaskSlotsInBlock(MBBNum).
361  std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
362  return getRegMaskBits().slice(P.first, P.second);
363  }
364 
365  /// Test if \p LI is live across any register mask instructions, and
366  /// compute a bit mask of physical registers that are not clobbered by any
367  /// of them.
368  ///
369  /// Returns false if \p LI doesn't cross any register mask instructions. In
370  /// that case, the bit vector is not filled in.
371  bool checkRegMaskInterference(const LiveInterval &LI,
372  BitVector &UsableRegs);
373 
374  // Register unit functions.
375  //
376  // Fixed interference occurs when MachineInstrs use physregs directly
377  // instead of virtual registers. This typically happens when passing
378  // arguments to a function call, or when instructions require operands in
379  // fixed registers.
380  //
381  // Each physreg has one or more register units, see MCRegisterInfo. We
382  // track liveness per register unit to handle aliasing registers more
383  // efficiently.
384 
385  /// Return the live range for register unit \p Unit. It will be computed if
386  /// it doesn't exist.
387  LiveRange &getRegUnit(unsigned Unit) {
388  LiveRange *LR = RegUnitRanges[Unit];
389  if (!LR) {
390  // Compute missing ranges on demand.
391  // Use segment set to speed-up initial computation of the live range.
392  RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
393  computeRegUnitRange(*LR, Unit);
394  }
395  return *LR;
396  }
397 
398  /// Return the live range for register unit \p Unit if it has already been
399  /// computed, or nullptr if it hasn't been computed yet.
400  LiveRange *getCachedRegUnit(unsigned Unit) {
401  return RegUnitRanges[Unit];
402  }
403 
404  const LiveRange *getCachedRegUnit(unsigned Unit) const {
405  return RegUnitRanges[Unit];
406  }
407 
408  /// Remove computed live range for register unit \p Unit. Subsequent uses
409  /// should rely on on-demand recomputation.
410  void removeRegUnit(unsigned Unit) {
411  delete RegUnitRanges[Unit];
412  RegUnitRanges[Unit] = nullptr;
413  }
414 
415  /// Remove associated live ranges for the register units associated with \p
416  /// Reg. Subsequent uses should rely on on-demand recomputation. \note This
417  /// method can result in inconsistent liveness tracking if multiple phyical
418  /// registers share a regunit, and should be used cautiously.
420  for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
421  removeRegUnit(*Units);
422  }
423 
424  /// Remove value numbers and related live segments starting at position
425  /// \p Pos that are part of any liverange of physical register \p Reg or one
426  /// of its subregisters.
428 
429  /// Remove value number and related live segments of \p LI and its subranges
430  /// that start at position \p Pos.
431  void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos);
432 
433  /// Split separate components in LiveInterval \p LI into separate intervals.
436 
437  /// For live interval \p LI with correct SubRanges construct matching
438  /// information for the main live range. Expects the main live range to not
439  /// have any segments or value numbers.
441 
442  private:
443  /// Compute live intervals for all virtual registers.
444  void computeVirtRegs();
445 
446  /// Compute RegMaskSlots and RegMaskBits.
447  void computeRegMasks();
448 
449  /// Walk the values in \p LI and check for dead values:
450  /// - Dead PHIDef values are marked as unused.
451  /// - Dead operands are marked as such.
452  /// - Completely dead machine instructions are added to the \p dead vector
453  /// if it is not nullptr.
454  /// Returns true if any PHI value numbers have been removed which may
455  /// have separated the interval into multiple connected components.
456  bool computeDeadValues(LiveInterval &LI,
458 
459  static LiveInterval *createInterval(Register Reg);
460 
461  void printInstrs(raw_ostream &O) const;
462  void dumpInstrs() const;
463 
464  void computeLiveInRegUnits();
465  void computeRegUnitRange(LiveRange&, unsigned Unit);
466  bool computeVirtRegInterval(LiveInterval&);
467 
468  using ShrinkToUsesWorkList = SmallVector<std::pair<SlotIndex, VNInfo*>, 16>;
469  void extendSegmentsToUses(LiveRange &Segments,
470  ShrinkToUsesWorkList &WorkList, Register Reg,
471  LaneBitmask LaneMask);
472 
473  /// Helper function for repairIntervalsInRange(), walks backwards and
474  /// creates/modifies live segments in \p LR to match the operands found.
475  /// Only full operands or operands with subregisters matching \p LaneMask
476  /// are considered.
477  void repairOldRegInRange(MachineBasicBlock::iterator Begin,
479  const SlotIndex endIdx, LiveRange &LR,
480  Register Reg,
481  LaneBitmask LaneMask = LaneBitmask::getAll());
482 
483  class HMEditor;
484  };
485 
486 } // end namespace llvm
487 
488 #endif
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::LiveIntervals::addSegmentToEndOfBlock
LiveInterval::Segment addSegmentToEndOfBlock(Register Reg, MachineInstr &startInst)
Given a register and an instruction, adds a live segment from that instruction to the end of its MBB.
Definition: LiveIntervals.cpp:872
IndexedMap.h
llvm::SlotIndexes::insertMBBInMaps
void insertMBBInMaps(MachineBasicBlock *mbb)
Add the given MachineBasicBlock into the maps.
Definition: SlotIndexes.h:615
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::LiveIntervals::getSlotIndexes
SlotIndexes * getSlotIndexes() const
Definition: LiveIntervals.h:209
llvm::LiveIntervals::isLiveInToMBB
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
Definition: LiveIntervals.h:239
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::LiveIntervals::isNotInMIMap
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
Definition: LiveIntervals.h:215
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1182
llvm::LiveIntervals::getRegMaskSlotsInBlock
ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const
Returns a sorted array of slot indices of all instructions with register mask operands in the basic b...
Definition: LiveIntervals.h:349
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:225
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::LiveRange::Segment
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
llvm::LiveIntervals::intervalIsInOneMBB
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
If LI is confined to a single basic block, return a pointer to that block.
Definition: LiveIntervals.cpp:818
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::LiveIntervals::addKillFlags
void addKillFlags(const VirtRegMap *)
Add kill flags to any instruction that kills a virtual register.
Definition: LiveIntervals.cpp:693
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::LiveIntervals::removeAllRegUnitsForPhysReg
void removeAllRegUnitsForPhysReg(MCRegister Reg)
Remove associated live ranges for the register units associated with Reg.
Definition: LiveIntervals.h:419
llvm::LiveIntervals::removeInterval
void removeInterval(Register Reg)
Interval removal.
Definition: LiveIntervals.h:143
llvm::LiveIntervals::getRegMaskSlots
ArrayRef< SlotIndex > getRegMaskSlots() const
Returns a sorted array of slot indices of all instructions with register mask operands.
Definition: LiveIntervals.h:345
llvm::SlotIndexes::getMBBEndIdx
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:481
llvm::LiveIntervals::getInterval
const LiveInterval & getInterval(Register Reg) const
Definition: LiveIntervals.h:119
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:172
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::LiveIntervals::removeRegUnit
void removeRegUnit(unsigned Unit)
Remove computed live range for register unit Unit.
Definition: LiveIntervals.h:410
llvm::LiveIntervals::createAndComputeVirtRegInterval
LiveInterval & createAndComputeVirtRegInterval(Register Reg)
Definition: LiveIntervals.h:136
llvm::LiveIntervals::getMBBFromIndex
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Definition: LiveIntervals.h:249
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:220
llvm::LiveIntervals::handleMove
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.
Definition: LiveIntervals.cpp:1508
llvm::LiveIntervals::print
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Definition: LiveIntervals.cpp:148
CommandLine.h
llvm::SlotIndexes::hasIndex
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:385
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::LiveRange::liveAt
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
llvm::LiveIntervals::extendToIndices
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices)
Definition: LiveIntervals.h:185
llvm::LiveIntervalCalc
Definition: LiveIntervalCalc.h:28
llvm::MachineBlockFrequencyInfo
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
Definition: MachineBlockFrequencyInfo.h:33
llvm::LiveIntervals::getMBBStartIdx
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
Definition: LiveIntervals.h:230
llvm::LiveIntervals::getCachedRegUnit
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
Definition: LiveIntervals.h:400
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::LiveIntervals::ID
static char ID
Definition: LiveIntervals.h:97
llvm::LiveIntervals::hasPHIKill
bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const
Returns true if VNI is killed by any PHI-def values in LI.
Definition: LiveIntervals.cpp:844
llvm::LiveIntervals::InsertMachineInstrInMaps
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
Definition: LiveIntervals.h:260
llvm::LiveIntervals::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &) override
Pass entry point; Calculates LiveIntervals.
Definition: LiveIntervals.cpp:120
llvm::IndexedMap
Definition: IndexedMap.h:30
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::LiveIntervals::isLiveOutOfMBB
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
Definition: LiveIntervals.h:244
llvm::LiveIntervals::pruneValue
void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)
If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill.
Definition: LiveIntervals.cpp:631
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::SlotIndexes::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:390
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:319
llvm::BitVector
Definition: BitVector.h:75
llvm::LiveIntervals::LiveIntervals
LiveIntervals()
Definition: LiveIntervals.cpp:97
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
llvm::SlotIndexes::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
Definition: SlotIndexes.h:408
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::LiveIntervals::handleMoveIntoNewBundle
void handleMoveIntoNewBundle(MachineInstr &BundleStart, bool UpdateFlags=false)
Update intervals of operands of all instructions in the newly created bundle specified by BundleStart...
Definition: LiveIntervals.cpp:1524
llvm::SlotIndexes::insertMachineInstrInMaps
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:540
llvm::LiveIntervals::insertMBBInMaps
void insertMBBInMaps(MachineBasicBlock *MBB)
Definition: LiveIntervals.h:253
llvm::LiveIntervals::removePhysRegDefAt
void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
Definition: LiveIntervals.cpp:1712
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:264
llvm::SlotIndexes::getMBBStartIdx
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:471
llvm::LiveIntervals::ReplaceMachineInstrInMaps
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
Definition: LiveIntervals.h:274
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
index
splat index
Definition: README_ALTIVEC.txt:181
llvm::LiveIntervals::getRegMaskBitsInBlock
ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const
Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBBNum).
Definition: LiveIntervals.h:360
llvm::LiveRange
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
llvm::LiveIntervals::getMBBEndIdx
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
Definition: LiveIntervals.h:235
llvm::SlotIndexes::replaceMachineInstrInMaps
SlotIndex replaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in maps used by register allocat...
Definition: SlotIndexes.h:597
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:63
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::LiveIntervals::releaseMemory
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
Definition: LiveIntervals.cpp:103
ArrayRef.h
MachineFunctionPass.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SlotIndexes::getMBBFromIndex
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
Definition: SlotIndexes.h:519
llvm::LiveIntervals::shrinkToUses
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
Definition: LiveIntervals.cpp:449
llvm::LiveIntervals::checkRegMaskInterference
bool checkRegMaskInterference(const LiveInterval &LI, BitVector &UsableRegs)
Test if LI is live across any register mask instructions, and compute a bit mask of physical register...
Definition: LiveIntervals.cpp:905
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
LiveRange
SI Optimize VGPR LiveRange
Definition: SIOptimizeVGPRLiveRange.cpp:616
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:112
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::IndexedMap::grow
void grow(IndexT n)
Definition: IndexedMap.h:68
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LiveIntervals::getCachedRegUnit
const LiveRange * getCachedRegUnit(unsigned Unit) const
Definition: LiveIntervals.h:404
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
Compiler.h
llvm::LiveIntervals::createEmptyInterval
LiveInterval & createEmptyInterval(Register Reg)
Interval creation.
Definition: LiveIntervals.h:129
llvm::LiveInterval::SubRange
A live range for subregisters.
Definition: LiveInterval.h:693
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LiveIntervals::getSpillWeight
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &MI)
Calculate the spill weight to assign to a single instruction.
Definition: LiveIntervals.cpp:859
llvm::LiveIntervals::pruneValue
LLVM_ATTRIBUTE_UNUSED void pruneValue(LiveInterval &, SlotIndex, SmallVectorImpl< SlotIndex > *)
This function should not be used.
Definition: LiveIntervals.h:203
llvm::LiveIntervals::extendToIndices
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)
Extend the live range LR to reach all points in Indices.
Definition: LiveIntervals.cpp:622
llvm::LiveIntervals::~LiveIntervals
~LiveIntervals() override
Definition: LiveIntervals.cpp:101
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveIntervals::getRegMaskBits
ArrayRef< const uint32_t * > getRegMaskBits() const
Returns an array of register mask pointers corresponding to getRegMaskSlots().
Definition: LiveIntervals.h:356
llvm::LiveIntervals::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition: LiveIntervals.cpp:86
llvm::LiveIntervals::constructMainRangeFromSubranges
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range.
Definition: LiveIntervals.cpp:1755
LiveInterval.h
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:680
SmallVector.h
llvm::UseSegmentSetForPhysRegs
cl::opt< bool > UseSegmentSetForPhysRegs
llvm::IndexedMap::inBounds
bool inBounds(IndexT n) const
Definition: IndexedMap.h:74
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::LiveIntervals::RemoveMachineInstrFromMaps
void RemoveMachineInstrFromMaps(MachineInstr &MI)
Definition: LiveIntervals.h:270
llvm::LiveIntervals::splitSeparateComponents
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
Definition: LiveIntervals.cpp:1738
llvm::LiveIntervals::InsertMachineInstrRangeInMaps
void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B, MachineBasicBlock::iterator E)
Definition: LiveIntervals.h:264
LaneBitmask.h
llvm::SmallVectorImpl< MachineInstr * >
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::LiveIntervals::repairIntervalsInRange
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)
Update live intervals for instructions in a range of iterators.
Definition: LiveIntervals.cpp:1650
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:123
SlotIndexes.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SlotIndexes::removeMachineInstrFromMaps
void removeMachineInstrFromMaps(MachineInstr &MI, bool AllowBundled=false)
Removes machine instruction (bundle) MI from the mapping.
Definition: SlotIndexes.cpp:115
llvm::LiveIntervals::removeVRegDefAt
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos.
Definition: LiveIntervals.cpp:1720
TargetRegisterInfo.h
llvm::LaneBitmask::getAll
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:84
llvm::LiveIntervals::getVNInfoAllocator
VNInfo::Allocator & getVNInfoAllocator()
Definition: LiveIntervals.h:278
llvm::LiveIntervals::getRegUnit
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
Definition: LiveIntervals.h:387
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24