LLVM 17.0.0git
RISCVTargetParser.cpp
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1//===-- RISCVTargetParser.cpp - Parser for target features ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise hardware features
10// FOR RISC-V CPUS.
11//
12//===----------------------------------------------------------------------===//
13
18
19namespace llvm {
20namespace RISCV {
21
22struct CPUInfo {
26 bool isInvalid() const { return DefaultMarch.empty(); }
27 bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
28};
29
30constexpr CPUInfo RISCVCPUInfo[] = {
31#define PROC(ENUM, NAME, DEFAULT_MARCH) \
32 {NAME, CK_##ENUM, DEFAULT_MARCH},
33#include "llvm/TargetParser/RISCVTargetParserDef.inc"
34};
35
36bool checkCPUKind(CPUKind Kind, bool IsRV64) {
37 if (Kind == CK_INVALID)
38 return false;
39 return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
40}
41
42bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) {
43 if (Kind == CK_INVALID)
44 return false;
45#define TUNE_PROC(ENUM, NAME) \
46 if (Kind == CK_##ENUM) \
47 return true;
48#include "llvm/TargetParser/RISCVTargetParserDef.inc"
49 return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
50}
51
54#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
55#include "llvm/TargetParser/RISCVTargetParserDef.inc"
56 .Default(CK_INVALID);
57}
58
59CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) {
60 return llvm::StringSwitch<CPUKind>(TuneCPU)
61#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
62#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
63#include "llvm/TargetParser/RISCVTargetParserDef.inc"
64 .Default(CK_INVALID);
65}
66
68 CPUKind Kind = parseCPUKind(CPU);
69 return RISCVCPUInfo[static_cast<unsigned>(Kind)].DefaultMarch;
70}
71
73 for (const auto &C : RISCVCPUInfo) {
74 if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
75 Values.emplace_back(C.Name);
76 }
77}
78
80 for (const auto &C : RISCVCPUInfo) {
81 if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
82 Values.emplace_back(C.Name);
83 }
84#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
85#include "llvm/TargetParser/RISCVTargetParserDef.inc"
86}
87
88// Get all features except standard extension feature
90 std::vector<StringRef> &Features) {
91 const CPUInfo &Info = RISCVCPUInfo[static_cast<unsigned>(Kind)];
92
93 if (Info.isInvalid())
94 return false;
95
96 if (Info.is64Bit())
97 Features.push_back("+64bit");
98 else
99 Features.push_back("-64bit");
100
101 return true;
102}
103
105 // X18 is reserved for the ShadowCallStack ABI (even when not enabled).
106 return TT.isOSFuchsia() || TT.isAndroid();
107}
108
109} // namespace RISCV
110} // namespace llvm
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static bool is64Bit(const char *name)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:840
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:257
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
R Default(T Value)
Definition: StringSwitch.h:182
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
void fillValidTuneCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
constexpr CPUInfo RISCVCPUInfo[]
StringRef getMArchFromMcpu(StringRef CPU)
bool isX18ReservedByDefault(const Triple &TT)
CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64)
bool checkTuneCPUKind(CPUKind Kind, bool IsRV64)
bool checkCPUKind(CPUKind Kind, bool IsRV64)
CPUKind parseCPUKind(StringRef CPU)
bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector< StringRef > &Features)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18