LLVM  15.0.0git
CSEInfo.cpp
Go to the documentation of this file.
1 //===- CSEInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
13 #include "llvm/InitializePasses.h"
14 #include "llvm/Support/Error.h"
15 
16 #define DEBUG_TYPE "cseinfo"
17 
18 using namespace llvm;
23 }
25  "Analysis containing CSE Info", false, true)
27  "Analysis containing CSE Info", false, true)
28 
29 /// -------- UniqueMachineInstr -------------//
30 
32  GISelInstProfileBuilder(ID, MI->getMF()->getRegInfo()).addNodeID(MI);
33 }
34 /// -----------------------------------------
35 
36 /// --------- CSEConfigFull ---------- ///
37 bool CSEConfigFull::shouldCSEOpc(unsigned Opc) {
38  switch (Opc) {
39  default:
40  break;
41  case TargetOpcode::G_ADD:
42  case TargetOpcode::G_AND:
43  case TargetOpcode::G_ASHR:
44  case TargetOpcode::G_LSHR:
45  case TargetOpcode::G_MUL:
46  case TargetOpcode::G_OR:
47  case TargetOpcode::G_SHL:
48  case TargetOpcode::G_SUB:
49  case TargetOpcode::G_XOR:
50  case TargetOpcode::G_UDIV:
51  case TargetOpcode::G_SDIV:
52  case TargetOpcode::G_UREM:
53  case TargetOpcode::G_SREM:
54  case TargetOpcode::G_CONSTANT:
55  case TargetOpcode::G_FCONSTANT:
56  case TargetOpcode::G_IMPLICIT_DEF:
57  case TargetOpcode::G_ZEXT:
58  case TargetOpcode::G_SEXT:
59  case TargetOpcode::G_ANYEXT:
60  case TargetOpcode::G_UNMERGE_VALUES:
61  case TargetOpcode::G_TRUNC:
62  case TargetOpcode::G_PTR_ADD:
63  case TargetOpcode::G_EXTRACT:
64  return true;
65  }
66  return false;
67 }
68 
70  return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT ||
71  Opc == TargetOpcode::G_IMPLICIT_DEF;
72 }
73 
74 std::unique_ptr<CSEConfigBase>
76  std::unique_ptr<CSEConfigBase> Config;
77  if (Level == CodeGenOpt::None)
78  Config = std::make_unique<CSEConfigConstantOnly>();
79  else
80  Config = std::make_unique<CSEConfigFull>();
81  return Config;
82 }
83 
84 /// -----------------------------------------
85 
86 /// -------- GISelCSEInfo -------------//
88  this->MF = &MF;
89  this->MRI = &MF.getRegInfo();
90 }
91 
92 GISelCSEInfo::~GISelCSEInfo() = default;
93 
94 bool GISelCSEInfo::isUniqueMachineInstValid(
95  const UniqueMachineInstr &UMI) const {
96  // Should we check here and assert that the instruction has been fully
97  // constructed?
98  // FIXME: Any other checks required to be done here? Remove this method if
99  // none.
100  return true;
101 }
102 
103 void GISelCSEInfo::invalidateUniqueMachineInstr(UniqueMachineInstr *UMI) {
104  bool Removed = CSEMap.RemoveNode(UMI);
105  (void)Removed;
106  assert(Removed && "Invalidation called on invalid UMI");
107  // FIXME: Should UMI be deallocated/destroyed?
108 }
109 
110 UniqueMachineInstr *GISelCSEInfo::getNodeIfExists(FoldingSetNodeID &ID,
112  void *&InsertPos) {
113  auto *Node = CSEMap.FindNodeOrInsertPos(ID, InsertPos);
114  if (Node) {
115  if (!isUniqueMachineInstValid(*Node)) {
116  invalidateUniqueMachineInstr(Node);
117  return nullptr;
118  }
119 
120  if (Node->MI->getParent() != MBB)
121  return nullptr;
122  }
123  return Node;
124 }
125 
126 void GISelCSEInfo::insertNode(UniqueMachineInstr *UMI, void *InsertPos) {
128  assert(UMI);
129  UniqueMachineInstr *MaybeNewNode = UMI;
130  if (InsertPos)
131  CSEMap.InsertNode(UMI, InsertPos);
132  else
133  MaybeNewNode = CSEMap.GetOrInsertNode(UMI);
134  if (MaybeNewNode != UMI) {
135  // A similar node exists in the folding set. Let's ignore this one.
136  return;
137  }
138  assert(InstrMapping.count(UMI->MI) == 0 &&
139  "This instruction should not be in the map");
140  InstrMapping[UMI->MI] = MaybeNewNode;
141 }
142 
143 UniqueMachineInstr *GISelCSEInfo::getUniqueInstrForMI(const MachineInstr *MI) {
144  assert(shouldCSE(MI->getOpcode()) && "Trying to CSE an unsupported Node");
145  auto *Node = new (UniqueInstrAllocator) UniqueMachineInstr(MI);
146  return Node;
147 }
148 
149 void GISelCSEInfo::insertInstr(MachineInstr *MI, void *InsertPos) {
150  assert(MI);
151  // If it exists in temporary insts, remove it.
152  TemporaryInsts.remove(MI);
153  auto *Node = getUniqueInstrForMI(MI);
154  insertNode(Node, InsertPos);
155 }
156 
157 MachineInstr *GISelCSEInfo::getMachineInstrIfExists(FoldingSetNodeID &ID,
159  void *&InsertPos) {
161  if (auto *Inst = getNodeIfExists(ID, MBB, InsertPos)) {
162  LLVM_DEBUG(dbgs() << "CSEInfo::Found Instr " << *Inst->MI;);
163  return const_cast<MachineInstr *>(Inst->MI);
164  }
165  return nullptr;
166 }
167 
168 void GISelCSEInfo::countOpcodeHit(unsigned Opc) {
169 #ifndef NDEBUG
170  if (OpcodeHitTable.count(Opc))
171  OpcodeHitTable[Opc] += 1;
172  else
173  OpcodeHitTable[Opc] = 1;
174 #endif
175  // Else do nothing.
176 }
177 
179  if (shouldCSE(MI->getOpcode())) {
180  TemporaryInsts.insert(MI);
181  LLVM_DEBUG(dbgs() << "CSEInfo::Recording new MI " << *MI);
182  }
183 }
184 
186  assert(shouldCSE(MI->getOpcode()) && "Invalid instruction for CSE");
187  auto *UMI = InstrMapping.lookup(MI);
188  LLVM_DEBUG(dbgs() << "CSEInfo::Handling recorded MI " << *MI);
189  if (UMI) {
190  // Invalidate this MI.
191  invalidateUniqueMachineInstr(UMI);
192  InstrMapping.erase(MI);
193  }
194  /// Now insert the new instruction.
195  if (UMI) {
196  /// We'll reuse the same UniqueMachineInstr to avoid the new
197  /// allocation.
198  *UMI = UniqueMachineInstr(MI);
199  insertNode(UMI, nullptr);
200  } else {
201  /// This is a new instruction. Allocate a new UniqueMachineInstr and
202  /// Insert.
203  insertInstr(MI);
204  }
205 }
206 
208  if (auto *UMI = InstrMapping.lookup(MI)) {
209  invalidateUniqueMachineInstr(UMI);
210  InstrMapping.erase(MI);
211  }
212  TemporaryInsts.remove(MI);
213 }
214 
216  while (!TemporaryInsts.empty()) {
217  auto *MI = TemporaryInsts.pop_back_val();
219  }
220 }
221 
222 bool GISelCSEInfo::shouldCSE(unsigned Opc) const {
223  assert(CSEOpt.get() && "CSEConfig not set");
224  return CSEOpt->shouldCSEOpc(Opc);
225 }
226 
230  // For now, perform erase, followed by insert.
231  erasingInstr(MI);
232  createdInstr(MI);
233 }
235 
237  setMF(MF);
238  for (auto &MBB : MF) {
239  if (MBB.empty())
240  continue;
241  for (MachineInstr &MI : MBB) {
242  if (!shouldCSE(MI.getOpcode()))
243  continue;
244  LLVM_DEBUG(dbgs() << "CSEInfo::Add MI: " << MI);
245  insertInstr(&MI);
246  }
247  }
248 }
249 
251  print();
252  CSEMap.clear();
253  InstrMapping.clear();
254  UniqueInstrAllocator.Reset();
255  TemporaryInsts.clear();
256  CSEOpt.reset();
257  MRI = nullptr;
258  MF = nullptr;
259 #ifndef NDEBUG
260  OpcodeHitTable.clear();
261 #endif
262 }
263 
264 #ifndef NDEBUG
265 static const char *stringify(const MachineInstr *MI, std::string &S) {
266  raw_string_ostream OS(S);
267  OS << *MI;
268  return OS.str().c_str();
269 }
270 #endif
271 
273 #ifndef NDEBUG
274  std::string S1, S2;
276  // For each instruction in map from MI -> UMI,
277  // Profile(MI) and make sure UMI is found for that profile.
278  for (auto &It : InstrMapping) {
279  FoldingSetNodeID TmpID;
280  GISelInstProfileBuilder(TmpID, *MRI).addNodeID(It.first);
281  void *InsertPos;
282  UniqueMachineInstr *FoundNode =
283  CSEMap.FindNodeOrInsertPos(TmpID, InsertPos);
284  if (FoundNode != It.second)
285  return createStringError(std::errc::not_supported,
286  "CSEMap mismatch, InstrMapping has MIs without "
287  "corresponding Nodes in CSEMap:\n%s",
288  stringify(It.second->MI, S1));
289  }
290 
291  // For every node in the CSEMap, make sure that the InstrMapping
292  // points to it.
293  for (const UniqueMachineInstr &UMI : CSEMap) {
294  if (!InstrMapping.count(UMI.MI))
295  return createStringError(std::errc::not_supported,
296  "Node in CSE without InstrMapping:\n%s",
297  stringify(UMI.MI, S1));
298 
299  if (InstrMapping[UMI.MI] != &UMI)
300  return createStringError(std::make_error_code(std::errc::not_supported),
301  "Mismatch in CSE mapping:\n%s\n%s",
302  stringify(InstrMapping[UMI.MI]->MI, S1),
303  stringify(UMI.MI, S2));
304  }
305 #endif
306  return Error::success();
307 }
308 
310  LLVM_DEBUG(for (auto &It
311  : OpcodeHitTable) {
312  dbgs() << "CSEInfo::CSE Hit for Opc " << It.first << " : " << It.second
313  << "\n";
314  };);
315 }
316 /// -----------------------------------------
317 // ---- Profiling methods for FoldingSetNode --- //
320  addNodeIDMBB(MI->getParent());
321  addNodeIDOpcode(MI->getOpcode());
322  for (auto &Op : MI->operands())
324  addNodeIDFlag(MI->getFlags());
325  return *this;
326 }
327 
330  ID.AddInteger(Opc);
331  return *this;
332 }
333 
336  uint64_t Val = Ty.getUniqueRAWLLTData();
337  ID.AddInteger(Val);
338  return *this;
339 }
340 
343  ID.AddPointer(RC);
344  return *this;
345 }
346 
349  ID.AddPointer(RB);
350  return *this;
351 }
352 
355  ID.AddInteger(Imm);
356  return *this;
357 }
358 
361  ID.AddInteger(Reg);
362  return *this;
363 }
364 
368  return *this;
369 }
370 
373  ID.AddPointer(MBB);
374  return *this;
375 }
376 
379  if (Flag)
380  ID.AddInteger(Flag);
381  return *this;
382 }
383 
386  LLT Ty = MRI.getType(Reg);
387  if (Ty.isValid())
388  addNodeIDRegType(Ty);
389 
390  if (const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg)) {
391  if (const auto *RB = RCOrRB.dyn_cast<const RegisterBank *>())
392  addNodeIDRegType(RB);
393  else if (const auto *RC = RCOrRB.dyn_cast<const TargetRegisterClass *>())
394  addNodeIDRegType(RC);
395  }
396  return *this;
397 }
398 
400  const MachineOperand &MO) const {
401  if (MO.isReg()) {
402  Register Reg = MO.getReg();
403  if (!MO.isDef())
405 
406  // Profile the register properties.
407  addNodeIDReg(Reg);
408  assert(!MO.isImplicit() && "Unhandled case");
409  } else if (MO.isImm())
410  ID.AddInteger(MO.getImm());
411  else if (MO.isCImm())
412  ID.AddPointer(MO.getCImm());
413  else if (MO.isFPImm())
414  ID.AddPointer(MO.getFPImm());
415  else if (MO.isPredicate())
416  ID.AddInteger(MO.getPredicate());
417  else
418  llvm_unreachable("Unhandled operand type");
419  // Handle other types
420  return *this;
421 }
422 
423 GISelCSEInfo &
424 GISelCSEAnalysisWrapper::get(std::unique_ptr<CSEConfigBase> CSEOpt,
425  bool Recompute) {
426  if (!AlreadyComputed || Recompute) {
427  Info.releaseMemory();
428  Info.setCSEConfig(std::move(CSEOpt));
429  Info.analyze(*MF);
430  AlreadyComputed = true;
431  }
432  return Info;
433 }
435  AU.setPreservesAll();
437 }
438 
440  releaseMemory();
441  Wrapper.setMF(MF);
442  return false;
443 }
llvm::GISelCSEAnalysisWrapperPass::releaseMemory
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
Definition: CSEInfo.h:234
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::GISelCSEInfo::handleRecordedInst
void handleRecordedInst(MachineInstr *MI)
Use this callback to inform CSE about a newly fully created instruction.
Definition: CSEInfo.cpp:185
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::GISelCSEInfo::~GISelCSEInfo
virtual ~GISelCSEInfo()
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::GISelCSEAnalysisWrapperPass
The actual analysis pass wrapper.
Definition: CSEInfo.h:220
llvm::BumpPtrAllocatorImpl::Reset
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it,...
Definition: Allocator.h:121
llvm::GISelCSEInfo::handleRemoveInst
void handleRemoveInst(MachineInstr *MI)
Remove this inst from the CSE map.
Definition: CSEInfo.cpp:207
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:632
DEBUG_TYPE
#define DEBUG_TYPE
Definition: CSEInfo.cpp:16
llvm::GISelCSEInfo
The CSE Analysis object.
Definition: CSEInfo.h:69
llvm::GISelInstProfileBuilder::addNodeIDMBB
const GISelInstProfileBuilder & addNodeIDMBB(const MachineBasicBlock *MBB) const
Definition: CSEInfo.cpp:372
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::Error::success
static ErrorSuccess success()
Create a success value.
Definition: Error.h:329
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
Error.h
llvm::GISelInstProfileBuilder::addNodeIDMachineOperand
const GISelInstProfileBuilder & addNodeIDMachineOperand(const MachineOperand &MO) const
Definition: CSEInfo.cpp:399
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1886
llvm::GISelCSEAnalysisWrapper::setMF
void setMF(MachineFunction &MFunc)
Definition: CSEInfo.h:214
llvm::GISelInstProfileBuilder::addNodeID
const GISelInstProfileBuilder & addNodeID(const MachineInstr *MI) const
Definition: CSEInfo.cpp:319
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:324
llvm::GISelCSEInfo::changedInstr
void changedInstr(MachineInstr &MI) override
This instruction was mutated in some way.
Definition: CSEInfo.cpp:234
llvm::GISelInstProfileBuilder::addNodeIDRegType
const GISelInstProfileBuilder & addNodeIDRegType(const LLT Ty) const
Definition: CSEInfo.cpp:335
llvm::GISelCSEInfo::shouldCSE
bool shouldCSE(unsigned Opc) const
Definition: CSEInfo.cpp:222
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::DenseMapBase::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:147
llvm::GISelCSEAnalysisWrapper::get
GISelCSEInfo & get(std::unique_ptr< CSEConfigBase > CSEOpt, bool ReCompute=false)
Takes a CSEConfigBase object that defines what opcodes get CSEd.
Definition: CSEInfo.cpp:424
llvm::UniqueMachineInstr
A class that wraps MachineInstrs and derives from FoldingSetNode in order to be uniqued in a CSEMap.
Definition: CSEInfo.h:29
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
llvm::GISelInstProfileBuilder::addNodeIDOpcode
const GISelInstProfileBuilder & addNodeIDOpcode(unsigned Opc) const
Definition: CSEInfo.cpp:329
llvm::initializeGISelCSEAnalysisWrapperPassPass
void initializeGISelCSEAnalysisWrapperPassPass(PassRegistry &)
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
CSEInfo.h
llvm::GISelInstProfileBuilder::addNodeIDReg
const GISelInstProfileBuilder & addNodeIDReg(Register Reg) const
Definition: CSEInfo.cpp:385
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
CSE
separate const offset from Split GEPs to a variadic base and a constant offset for better CSE
Definition: SeparateConstOffsetFromGEP.cpp:495
stringify
static const char * stringify(const MachineInstr *MI, std::string &S)
Definition: CSEInfo.cpp:265
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::GISelCSEAnalysisWrapperPass::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: CSEInfo.cpp:439
llvm::GISelCSEInfo::recordNewInstruction
void recordNewInstruction(MachineInstr *MI)
Records a newly created inst in a list and lazily insert it to the CSEMap.
Definition: CSEInfo.cpp:178
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::GISelCSEInfo::erasingInstr
void erasingInstr(MachineInstr &MI) override
An instruction is about to be erased.
Definition: CSEInfo.cpp:227
false
Definition: StackSlotColoring.cpp:141
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::GISelCSEInfo::analyze
void analyze(MachineFunction &MF)
Definition: CSEInfo.cpp:236
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::GISelInstProfileBuilder::addNodeIDRegNum
const GISelInstProfileBuilder & addNodeIDRegNum(Register Reg) const
Definition: CSEInfo.cpp:360
llvm::GISelInstProfileBuilder::addNodeIDImmediate
const GISelInstProfileBuilder & addNodeIDImmediate(int64_t Imm) const
Definition: CSEInfo.cpp:354
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::GISelCSEInfo::createdInstr
void createdInstr(MachineInstr &MI) override
An instruction has been created and inserted into the function.
Definition: CSEInfo.cpp:228
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(GISelCSEAnalysisWrapperPass, DEBUG_TYPE, "Analysis containing CSE Info", false, true) INITIALIZE_PASS_END(GISelCSEAnalysisWrapperPass
llvm::CSEConfigFull::shouldCSEOpc
virtual bool shouldCSEOpc(unsigned Opc) override
------— CSEConfigFull -------— ///
Definition: CSEInfo.cpp:37
llvm::DenseMapBase::clear
void clear()
Definition: DenseMap.h:112
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:551
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::GISelCSEAnalysisWrapperPass::GISelCSEAnalysisWrapperPass
GISelCSEAnalysisWrapperPass()
Definition: CSEInfo.cpp:20
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:556
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:597
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LLT::getUniqueRAWLLTData
uint64_t getUniqueRAWLLTData() const
Definition: LowLevelTypeImpl.h:385
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:676
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::GISelWorkList::pop_back_val
MachineInstr * pop_back_val()
Definition: GISelWorkList.h:102
llvm::GISelCSEInfo::setCSEConfig
void setCSEConfig(std::unique_ptr< CSEConfigBase > Opt)
Definition: CSEInfo.h:144
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:75
llvm::GISelCSEInfo::countOpcodeHit
void countOpcodeHit(unsigned Opc)
Definition: CSEInfo.cpp:168
llvm::GISelCSEAnalysisWrapperPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition: CSEInfo.cpp:434
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::FoldingSetNodeID
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:318
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
Profile
Load MIR Sample Profile
Definition: MIRSampleProfile.cpp:70
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::GISelWorkList::remove
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
Definition: GISelWorkList.h:83
llvm::GISelCSEInfo::handleRecordedInsts
void handleRecordedInsts()
Use this callback to insert all the recorded instructions.
Definition: CSEInfo.cpp:215
llvm::PointerUnion
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
Definition: PointerUnion.h:112
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::make_error_code
std::error_code make_error_code(BitcodeError E)
Definition: BitcodeReader.h:271
llvm::GISelWorkList::insert
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
Definition: GISelWorkList.h:74
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::GISelInstProfileBuilder::addNodeIDFlag
const GISelInstProfileBuilder & addNodeIDFlag(unsigned Flag) const
Definition: CSEInfo.cpp:378
llvm::createStringError
Error createStringError(std::error_code EC, char const *Fmt, const Ts &... Vals)
Create formatted StringError object.
Definition: Error.h:1239
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
llvm::GISelInstProfileBuilder
Definition: CSEInfo.h:167
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::GISelCSEInfo::releaseMemory
void releaseMemory()
Definition: CSEInfo.cpp:250
llvm::CSEConfigConstantOnly::shouldCSEOpc
virtual bool shouldCSEOpc(unsigned Opc) override
Definition: CSEInfo.cpp:69
llvm::GISelCSEInfo::verify
Error verify()
Definition: CSEInfo.cpp:272
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::GISelCSEInfo::setMF
void setMF(MachineFunction &MF)
-----— GISelCSEInfo ----------—//
Definition: CSEInfo.cpp:87
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::MachineOperand::isFPImm
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Definition: MachineOperand.h:326
llvm::MachineOperand::isPredicate
bool isPredicate() const
Definition: MachineOperand.h:352
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
llvm::GISelCSEInfo::print
void print()
Definition: CSEInfo.cpp:309
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:250
llvm::GISelWorkList::clear
void clear()
Definition: GISelWorkList.h:97
llvm::GISelCSEAnalysisWrapperPass::ID
static char ID
Definition: CSEInfo.h:224
llvm::raw_string_ostream::str
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:650
InitializePasses.h
llvm::GISelCSEInfo::changingInstr
void changingInstr(MachineInstr &MI) override
This instruction is about to be mutated in some way.
Definition: CSEInfo.cpp:229
llvm::GISelWorkList::empty
bool empty() const
Definition: GISelWorkList.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:39