LLVM  14.0.0git
RISCVInsertVSETVLI.cpp
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1 //===- RISCVInsertVSETVLI.cpp - Insert VSETVLI instructions ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a function pass that inserts VSETVLI instructions where
10 // needed.
11 //
12 // This pass consists of 3 phases:
13 //
14 // Phase 1 collects how each basic block affects VL/VTYPE.
15 //
16 // Phase 2 uses the information from phase 1 to do a data flow analysis to
17 // propagate the VL/VTYPE changes through the function. This gives us the
18 // VL/VTYPE at the start of each basic block.
19 //
20 // Phase 3 inserts VSETVLI instructions in each basic block. Information from
21 // phase 2 is used to prevent inserting a VSETVLI before the first vector
22 // instruction in the block if possible.
23 //
24 //===----------------------------------------------------------------------===//
25 
26 #include "RISCV.h"
27 #include "RISCVSubtarget.h"
30 #include <queue>
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "riscv-insert-vsetvli"
34 #define RISCV_INSERT_VSETVLI_NAME "RISCV Insert VSETVLI pass"
35 
37  "riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden,
38  cl::desc("Disable looking through phis when inserting vsetvlis."));
39 
40 namespace {
41 
42 class VSETVLIInfo {
43  union {
44  Register AVLReg;
45  unsigned AVLImm;
46  };
47 
48  enum : uint8_t {
49  Uninitialized,
50  AVLIsReg,
51  AVLIsImm,
52  Unknown,
53  } State = Uninitialized;
54 
55  // Fields from VTYPE.
57  uint8_t SEW = 0;
58  uint8_t TailAgnostic : 1;
59  uint8_t MaskAgnostic : 1;
60  uint8_t MaskRegOp : 1;
61  uint8_t StoreOp : 1;
62  uint8_t SEWLMULRatioOnly : 1;
63 
64 public:
65  VSETVLIInfo()
66  : AVLImm(0), TailAgnostic(false), MaskAgnostic(false), MaskRegOp(false),
67  StoreOp(false), SEWLMULRatioOnly(false) {}
68 
69  static VSETVLIInfo getUnknown() {
70  VSETVLIInfo Info;
71  Info.setUnknown();
72  return Info;
73  }
74 
75  bool isValid() const { return State != Uninitialized; }
76  void setUnknown() { State = Unknown; }
77  bool isUnknown() const { return State == Unknown; }
78 
79  void setAVLReg(Register Reg) {
80  AVLReg = Reg;
81  State = AVLIsReg;
82  }
83 
84  void setAVLImm(unsigned Imm) {
85  AVLImm = Imm;
86  State = AVLIsImm;
87  }
88 
89  bool hasAVLImm() const { return State == AVLIsImm; }
90  bool hasAVLReg() const { return State == AVLIsReg; }
91  Register getAVLReg() const {
92  assert(hasAVLReg());
93  return AVLReg;
94  }
95  unsigned getAVLImm() const {
96  assert(hasAVLImm());
97  return AVLImm;
98  }
99 
100  bool hasSameAVL(const VSETVLIInfo &Other) const {
101  assert(isValid() && Other.isValid() &&
102  "Can't compare invalid VSETVLIInfos");
103  assert(!isUnknown() && !Other.isUnknown() &&
104  "Can't compare AVL in unknown state");
105  if (hasAVLReg() && Other.hasAVLReg())
106  return getAVLReg() == Other.getAVLReg();
107 
108  if (hasAVLImm() && Other.hasAVLImm())
109  return getAVLImm() == Other.getAVLImm();
110 
111  return false;
112  }
113 
114  void setVTYPE(unsigned VType) {
115  assert(isValid() && !isUnknown() &&
116  "Can't set VTYPE for uninitialized or unknown");
117  VLMul = RISCVVType::getVLMUL(VType);
118  SEW = RISCVVType::getSEW(VType);
119  TailAgnostic = RISCVVType::isTailAgnostic(VType);
120  MaskAgnostic = RISCVVType::isMaskAgnostic(VType);
121  }
122  void setVTYPE(RISCVII::VLMUL L, unsigned S, bool TA, bool MA, bool MRO,
123  bool IsStore) {
124  assert(isValid() && !isUnknown() &&
125  "Can't set VTYPE for uninitialized or unknown");
126  VLMul = L;
127  SEW = S;
128  TailAgnostic = TA;
129  MaskAgnostic = MA;
130  MaskRegOp = MRO;
131  StoreOp = IsStore;
132  }
133 
134  unsigned encodeVTYPE() const {
135  assert(isValid() && !isUnknown() && !SEWLMULRatioOnly &&
136  "Can't encode VTYPE for uninitialized or unknown");
137  return RISCVVType::encodeVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic);
138  }
139 
140  bool hasSEWLMULRatioOnly() const { return SEWLMULRatioOnly; }
141 
142  bool hasSameVTYPE(const VSETVLIInfo &Other) const {
143  assert(isValid() && Other.isValid() &&
144  "Can't compare invalid VSETVLIInfos");
145  assert(!isUnknown() && !Other.isUnknown() &&
146  "Can't compare VTYPE in unknown state");
147  assert(!SEWLMULRatioOnly && !Other.SEWLMULRatioOnly &&
148  "Can't compare when only LMUL/SEW ratio is valid.");
149  return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) ==
150  std::tie(Other.VLMul, Other.SEW, Other.TailAgnostic,
151  Other.MaskAgnostic);
152  }
153 
154  static unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
155  unsigned LMul;
156  bool Fractional;
157  std::tie(LMul, Fractional) = RISCVVType::decodeVLMUL(VLMul);
158 
159  // Convert LMul to a fixed point value with 3 fractional bits.
160  LMul = Fractional ? (8 / LMul) : (LMul * 8);
161 
162  assert(SEW >= 8 && "Unexpected SEW value");
163  return (SEW * 8) / LMul;
164  }
165 
166  unsigned getSEWLMULRatio() const {
167  assert(isValid() && !isUnknown() &&
168  "Can't use VTYPE for uninitialized or unknown");
169  return getSEWLMULRatio(SEW, VLMul);
170  }
171 
172  // Check if the VTYPE for these two VSETVLIInfos produce the same VLMAX.
173  bool hasSameVLMAX(const VSETVLIInfo &Other) const {
174  assert(isValid() && Other.isValid() &&
175  "Can't compare invalid VSETVLIInfos");
176  assert(!isUnknown() && !Other.isUnknown() &&
177  "Can't compare VTYPE in unknown state");
178  return getSEWLMULRatio() == Other.getSEWLMULRatio();
179  }
180 
181  // Determine whether the vector instructions requirements represented by
182  // InstrInfo are compatible with the previous vsetvli instruction represented
183  // by this.
184  bool isCompatible(const VSETVLIInfo &InstrInfo) const {
185  assert(isValid() && InstrInfo.isValid() &&
186  "Can't compare invalid VSETVLIInfos");
187  assert(!InstrInfo.SEWLMULRatioOnly &&
188  "Expected a valid VTYPE for instruction!");
189  // Nothing is compatible with Unknown.
190  if (isUnknown() || InstrInfo.isUnknown())
191  return false;
192 
193  // If only our VLMAX ratio is valid, then this isn't compatible.
194  if (SEWLMULRatioOnly)
195  return false;
196 
197  // If the instruction doesn't need an AVLReg and the SEW matches, consider
198  // it compatible.
199  if (InstrInfo.hasAVLReg() && InstrInfo.AVLReg == RISCV::NoRegister) {
200  if (SEW == InstrInfo.SEW)
201  return true;
202  }
203 
204  // The AVL must match.
205  if (!hasSameAVL(InstrInfo))
206  return false;
207 
208  // Simple case, see if full VTYPE matches.
209  if (hasSameVTYPE(InstrInfo))
210  return true;
211 
212  // If this is a mask reg operation, it only cares about VLMAX.
213  // FIXME: Mask reg operations are probably ok if "this" VLMAX is larger
214  // than "InstrInfo".
215  if (InstrInfo.MaskRegOp && hasSameVLMAX(InstrInfo) &&
216  TailAgnostic == InstrInfo.TailAgnostic &&
217  MaskAgnostic == InstrInfo.MaskAgnostic)
218  return true;
219 
220  // Store instructions don't use the policy fields.
221  if (InstrInfo.StoreOp && VLMul == InstrInfo.VLMul && SEW == InstrInfo.SEW)
222  return true;
223 
224  // Anything else is not compatible.
225  return false;
226  }
227 
228  bool isCompatibleWithLoadStoreEEW(unsigned EEW,
229  const VSETVLIInfo &InstrInfo) const {
230  assert(isValid() && InstrInfo.isValid() &&
231  "Can't compare invalid VSETVLIInfos");
232  assert(!InstrInfo.SEWLMULRatioOnly &&
233  "Expected a valid VTYPE for instruction!");
234  assert(EEW == InstrInfo.SEW && "Mismatched EEW/SEW for store");
235 
236  if (isUnknown() || hasSEWLMULRatioOnly())
237  return false;
238 
239  if (!hasSameAVL(InstrInfo))
240  return false;
241 
242  // Stores can ignore the tail and mask policies.
243  if (!InstrInfo.StoreOp && (TailAgnostic != InstrInfo.TailAgnostic ||
244  MaskAgnostic != InstrInfo.MaskAgnostic))
245  return false;
246 
247  return getSEWLMULRatio() == getSEWLMULRatio(EEW, InstrInfo.VLMul);
248  }
249 
250  bool operator==(const VSETVLIInfo &Other) const {
251  // Uninitialized is only equal to another Uninitialized.
252  if (!isValid())
253  return !Other.isValid();
254  if (!Other.isValid())
255  return !isValid();
256 
257  // Unknown is only equal to another Unknown.
258  if (isUnknown())
259  return Other.isUnknown();
260  if (Other.isUnknown())
261  return isUnknown();
262 
263  if (!hasSameAVL(Other))
264  return false;
265 
266  // If only the VLMAX is valid, check that it is the same.
267  if (SEWLMULRatioOnly && Other.SEWLMULRatioOnly)
268  return hasSameVLMAX(Other);
269 
270  // If the full VTYPE is valid, check that it is the same.
271  if (!SEWLMULRatioOnly && !Other.SEWLMULRatioOnly)
272  return hasSameVTYPE(Other);
273 
274  // If the SEWLMULRatioOnly bits are different, then they aren't equal.
275  return false;
276  }
277 
278  // Calculate the VSETVLIInfo visible to a block assuming this and Other are
279  // both predecessors.
280  VSETVLIInfo intersect(const VSETVLIInfo &Other) const {
281  // If the new value isn't valid, ignore it.
282  if (!Other.isValid())
283  return *this;
284 
285  // If this value isn't valid, this must be the first predecessor, use it.
286  if (!isValid())
287  return Other;
288 
289  // If either is unknown, the result is unknown.
290  if (isUnknown() || Other.isUnknown())
291  return VSETVLIInfo::getUnknown();
292 
293  // If we have an exact, match return this.
294  if (*this == Other)
295  return *this;
296 
297  // Not an exact match, but maybe the AVL and VLMAX are the same. If so,
298  // return an SEW/LMUL ratio only value.
299  if (hasSameAVL(Other) && hasSameVLMAX(Other)) {
300  VSETVLIInfo MergeInfo = *this;
301  MergeInfo.SEWLMULRatioOnly = true;
302  return MergeInfo;
303  }
304 
305  // Otherwise the result is unknown.
306  return VSETVLIInfo::getUnknown();
307  }
308 
309  // Calculate the VSETVLIInfo visible at the end of the block assuming this
310  // is the predecessor value, and Other is change for this block.
311  VSETVLIInfo merge(const VSETVLIInfo &Other) const {
312  assert(isValid() && "Can only merge with a valid VSETVLInfo");
313 
314  // Nothing changed from the predecessor, keep it.
315  if (!Other.isValid())
316  return *this;
317 
318  // If the change is compatible with the input, we won't create a VSETVLI
319  // and should keep the predecessor.
320  if (isCompatible(Other))
321  return *this;
322 
323  // Otherwise just use whatever is in this block.
324  return Other;
325  }
326 };
327 
328 struct BlockData {
329  // The VSETVLIInfo that represents the net changes to the VL/VTYPE registers
330  // made by this block. Calculated in Phase 1.
331  VSETVLIInfo Change;
332 
333  // The VSETVLIInfo that represents the VL/VTYPE settings on exit from this
334  // block. Calculated in Phase 2.
335  VSETVLIInfo Exit;
336 
337  // The VSETVLIInfo that represents the VL/VTYPE settings from all predecessor
338  // blocks. Calculated in Phase 2, and used by Phase 3.
339  VSETVLIInfo Pred;
340 
341  // Keeps track of whether the block is already in the queue.
342  bool InQueue = false;
343 
344  BlockData() {}
345 };
346 
347 class RISCVInsertVSETVLI : public MachineFunctionPass {
348  const TargetInstrInfo *TII;
350 
351  std::vector<BlockData> BlockInfo;
352  std::queue<const MachineBasicBlock *> WorkList;
353 
354 public:
355  static char ID;
356 
357  RISCVInsertVSETVLI() : MachineFunctionPass(ID) {
359  }
360  bool runOnMachineFunction(MachineFunction &MF) override;
361 
362  void getAnalysisUsage(AnalysisUsage &AU) const override {
363  AU.setPreservesCFG();
365  }
366 
367  StringRef getPassName() const override { return RISCV_INSERT_VSETVLI_NAME; }
368 
369 private:
370  bool needVSETVLI(const VSETVLIInfo &Require, const VSETVLIInfo &CurInfo);
371  bool needVSETVLIPHI(const VSETVLIInfo &Require, const MachineBasicBlock &MBB);
372  void insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI,
373  const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo);
374 
375  bool computeVLVTYPEChanges(const MachineBasicBlock &MBB);
376  void computeIncomingVLVTYPE(const MachineBasicBlock &MBB);
377  void emitVSETVLIs(MachineBasicBlock &MBB);
378 };
379 
380 } // end anonymous namespace
381 
382 char RISCVInsertVSETVLI::ID = 0;
383 
385  false, false)
386 
387 static MachineInstr *elideCopies(MachineInstr *MI,
389  while (true) {
390  if (!MI->isFullCopy())
391  return MI;
392  if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
393  return nullptr;
394  MI = MRI->getVRegDef(MI->getOperand(1).getReg());
395  if (!MI)
396  return nullptr;
397  }
398 }
399 
400 static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
401  const MachineRegisterInfo *MRI) {
402  VSETVLIInfo InstrInfo;
403  unsigned NumOperands = MI.getNumExplicitOperands();
404  bool HasPolicy = RISCVII::hasVecPolicyOp(TSFlags);
405 
406  // Default to tail agnostic unless the destination is tied to a source.
407  // Unless the source is undef. In that case the user would have some control
408  // over the tail values. Some pseudo instructions force a tail agnostic policy
409  // despite having a tied def.
410  bool ForceTailAgnostic = RISCVII::doesForceTailAgnostic(TSFlags);
411  bool TailAgnostic = true;
412  // If the instruction has policy argument, use the argument.
413  if (HasPolicy) {
414  const MachineOperand &Op = MI.getOperand(MI.getNumExplicitOperands() - 1);
415  TailAgnostic = Op.getImm() & 0x1;
416  }
417 
418  unsigned UseOpIdx;
419  if (!(ForceTailAgnostic || (HasPolicy && TailAgnostic)) &&
420  MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
421  TailAgnostic = false;
422  // If the tied operand is an IMPLICIT_DEF we can keep TailAgnostic.
423  const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
424  MachineInstr *UseMI = MRI->getVRegDef(UseMO.getReg());
425  if (UseMI) {
426  UseMI = elideCopies(UseMI, MRI);
427  if (UseMI && UseMI->isImplicitDef())
428  TailAgnostic = true;
429  }
430  }
431 
432  // Remove the tail policy so we can find the SEW and VL.
433  if (HasPolicy)
434  --NumOperands;
435 
436  RISCVII::VLMUL VLMul = RISCVII::getLMul(TSFlags);
437 
438  unsigned Log2SEW = MI.getOperand(NumOperands - 1).getImm();
439  // A Log2SEW of 0 is an operation on mask registers only.
440  bool MaskRegOp = Log2SEW == 0;
441  unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
442  assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");
443 
444  // If there are no explicit defs, this is a store instruction which can
445  // ignore the tail and mask policies.
446  bool StoreOp = MI.getNumExplicitDefs() == 0;
447 
448  if (RISCVII::hasVLOp(TSFlags)) {
449  const MachineOperand &VLOp = MI.getOperand(NumOperands - 2);
450  if (VLOp.isImm()) {
451  int64_t Imm = VLOp.getImm();
452  // Conver the VLMax sentintel to X0 register.
453  if (Imm == RISCV::VLMaxSentinel)
454  InstrInfo.setAVLReg(RISCV::X0);
455  else
456  InstrInfo.setAVLImm(Imm);
457  } else {
458  InstrInfo.setAVLReg(VLOp.getReg());
459  }
460  } else
461  InstrInfo.setAVLReg(RISCV::NoRegister);
462  InstrInfo.setVTYPE(VLMul, SEW, /*TailAgnostic*/ TailAgnostic,
463  /*MaskAgnostic*/ false, MaskRegOp, StoreOp);
464 
465  return InstrInfo;
466 }
467 
468 void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI,
469  const VSETVLIInfo &Info,
470  const VSETVLIInfo &PrevInfo) {
471  DebugLoc DL = MI.getDebugLoc();
472 
473  // Use X0, X0 form if the AVL is the same and the SEW+LMUL gives the same
474  // VLMAX.
475  if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
476  Info.hasSameAVL(PrevInfo) && Info.hasSameVLMAX(PrevInfo)) {
477  BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoVSETVLIX0))
478  .addReg(RISCV::X0, RegState::Define | RegState::Dead)
479  .addReg(RISCV::X0, RegState::Kill)
480  .addImm(Info.encodeVTYPE())
481  .addReg(RISCV::VL, RegState::Implicit);
482  return;
483  }
484 
485  if (Info.hasAVLImm()) {
486  BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoVSETIVLI))
487  .addReg(RISCV::X0, RegState::Define | RegState::Dead)
488  .addImm(Info.getAVLImm())
489  .addImm(Info.encodeVTYPE());
490  return;
491  }
492 
493  Register AVLReg = Info.getAVLReg();
494  if (AVLReg == RISCV::NoRegister) {
495  // We can only use x0, x0 if there's no chance of the vtype change causing
496  // the previous vl to become invalid.
497  if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
498  Info.hasSameVLMAX(PrevInfo)) {
499  BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoVSETVLIX0))
500  .addReg(RISCV::X0, RegState::Define | RegState::Dead)
501  .addReg(RISCV::X0, RegState::Kill)
502  .addImm(Info.encodeVTYPE())
503  .addReg(RISCV::VL, RegState::Implicit);
504  return;
505  }
506  // Otherwise use an AVL of 0 to avoid depending on previous vl.
507  BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoVSETIVLI))
508  .addReg(RISCV::X0, RegState::Define | RegState::Dead)
509  .addImm(0)
510  .addImm(Info.encodeVTYPE());
511  return;
512  }
513 
514  if (AVLReg.isVirtual())
515  MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);
516 
517  // Use X0 as the DestReg unless AVLReg is X0. We also need to change the
518  // opcode if the AVLReg is X0 as they have different register classes for
519  // the AVL operand.
520  Register DestReg = RISCV::X0;
521  unsigned Opcode = RISCV::PseudoVSETVLI;
522  if (AVLReg == RISCV::X0) {
523  DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
524  Opcode = RISCV::PseudoVSETVLIX0;
525  }
526  BuildMI(MBB, MI, DL, TII->get(Opcode))
528  .addReg(AVLReg)
529  .addImm(Info.encodeVTYPE());
530 }
531 
532 // Return a VSETVLIInfo representing the changes made by this VSETVLI or
533 // VSETIVLI instruction.
534 static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
535  VSETVLIInfo NewInfo;
536  if (MI.getOpcode() == RISCV::PseudoVSETIVLI) {
537  NewInfo.setAVLImm(MI.getOperand(1).getImm());
538  } else {
539  assert(MI.getOpcode() == RISCV::PseudoVSETVLI ||
540  MI.getOpcode() == RISCV::PseudoVSETVLIX0);
541  Register AVLReg = MI.getOperand(1).getReg();
542  assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) &&
543  "Can't handle X0, X0 vsetvli yet");
544  NewInfo.setAVLReg(AVLReg);
545  }
546  NewInfo.setVTYPE(MI.getOperand(2).getImm());
547 
548  return NewInfo;
549 }
550 
551 bool RISCVInsertVSETVLI::needVSETVLI(const VSETVLIInfo &Require,
552  const VSETVLIInfo &CurInfo) {
553  if (CurInfo.isCompatible(Require))
554  return false;
555 
556  // We didn't find a compatible value. If our AVL is a virtual register,
557  // it might be defined by a VSET(I)VLI. If it has the same VTYPE we need
558  // and the last VL/VTYPE we observed is the same, we don't need a
559  // VSETVLI here.
560  if (!CurInfo.isUnknown() && Require.hasAVLReg() &&
561  Require.getAVLReg().isVirtual() && !CurInfo.hasSEWLMULRatioOnly() &&
562  Require.hasSameVTYPE(CurInfo)) {
563  if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
564  if (DefMI->getOpcode() == RISCV::PseudoVSETVLI ||
565  DefMI->getOpcode() == RISCV::PseudoVSETVLIX0 ||
566  DefMI->getOpcode() == RISCV::PseudoVSETIVLI) {
567  VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
568  if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVTYPE(CurInfo))
569  return false;
570  }
571  }
572  }
573 
574  return true;
575 }
576 
577 bool canSkipVSETVLIForLoadStore(const MachineInstr &MI,
578  const VSETVLIInfo &Require,
579  const VSETVLIInfo &CurInfo) {
580  unsigned EEW;
581  switch (MI.getOpcode()) {
582  default:
583  return false;
584  case RISCV::PseudoVLE8_V_M1:
585  case RISCV::PseudoVLE8_V_M1_MASK:
586  case RISCV::PseudoVLE8_V_M2:
587  case RISCV::PseudoVLE8_V_M2_MASK:
588  case RISCV::PseudoVLE8_V_M4:
589  case RISCV::PseudoVLE8_V_M4_MASK:
590  case RISCV::PseudoVLE8_V_M8:
591  case RISCV::PseudoVLE8_V_M8_MASK:
592  case RISCV::PseudoVLE8_V_MF2:
593  case RISCV::PseudoVLE8_V_MF2_MASK:
594  case RISCV::PseudoVLE8_V_MF4:
595  case RISCV::PseudoVLE8_V_MF4_MASK:
596  case RISCV::PseudoVLE8_V_MF8:
597  case RISCV::PseudoVLE8_V_MF8_MASK:
598  case RISCV::PseudoVLSE8_V_M1:
599  case RISCV::PseudoVLSE8_V_M1_MASK:
600  case RISCV::PseudoVLSE8_V_M2:
601  case RISCV::PseudoVLSE8_V_M2_MASK:
602  case RISCV::PseudoVLSE8_V_M4:
603  case RISCV::PseudoVLSE8_V_M4_MASK:
604  case RISCV::PseudoVLSE8_V_M8:
605  case RISCV::PseudoVLSE8_V_M8_MASK:
606  case RISCV::PseudoVLSE8_V_MF2:
607  case RISCV::PseudoVLSE8_V_MF2_MASK:
608  case RISCV::PseudoVLSE8_V_MF4:
609  case RISCV::PseudoVLSE8_V_MF4_MASK:
610  case RISCV::PseudoVLSE8_V_MF8:
611  case RISCV::PseudoVLSE8_V_MF8_MASK:
612  case RISCV::PseudoVSE8_V_M1:
613  case RISCV::PseudoVSE8_V_M1_MASK:
614  case RISCV::PseudoVSE8_V_M2:
615  case RISCV::PseudoVSE8_V_M2_MASK:
616  case RISCV::PseudoVSE8_V_M4:
617  case RISCV::PseudoVSE8_V_M4_MASK:
618  case RISCV::PseudoVSE8_V_M8:
619  case RISCV::PseudoVSE8_V_M8_MASK:
620  case RISCV::PseudoVSE8_V_MF2:
621  case RISCV::PseudoVSE8_V_MF2_MASK:
622  case RISCV::PseudoVSE8_V_MF4:
623  case RISCV::PseudoVSE8_V_MF4_MASK:
624  case RISCV::PseudoVSE8_V_MF8:
625  case RISCV::PseudoVSE8_V_MF8_MASK:
626  case RISCV::PseudoVSSE8_V_M1:
627  case RISCV::PseudoVSSE8_V_M1_MASK:
628  case RISCV::PseudoVSSE8_V_M2:
629  case RISCV::PseudoVSSE8_V_M2_MASK:
630  case RISCV::PseudoVSSE8_V_M4:
631  case RISCV::PseudoVSSE8_V_M4_MASK:
632  case RISCV::PseudoVSSE8_V_M8:
633  case RISCV::PseudoVSSE8_V_M8_MASK:
634  case RISCV::PseudoVSSE8_V_MF2:
635  case RISCV::PseudoVSSE8_V_MF2_MASK:
636  case RISCV::PseudoVSSE8_V_MF4:
637  case RISCV::PseudoVSSE8_V_MF4_MASK:
638  case RISCV::PseudoVSSE8_V_MF8:
639  case RISCV::PseudoVSSE8_V_MF8_MASK:
640  EEW = 8;
641  break;
642  case RISCV::PseudoVLE16_V_M1:
643  case RISCV::PseudoVLE16_V_M1_MASK:
644  case RISCV::PseudoVLE16_V_M2:
645  case RISCV::PseudoVLE16_V_M2_MASK:
646  case RISCV::PseudoVLE16_V_M4:
647  case RISCV::PseudoVLE16_V_M4_MASK:
648  case RISCV::PseudoVLE16_V_M8:
649  case RISCV::PseudoVLE16_V_M8_MASK:
650  case RISCV::PseudoVLE16_V_MF2:
651  case RISCV::PseudoVLE16_V_MF2_MASK:
652  case RISCV::PseudoVLE16_V_MF4:
653  case RISCV::PseudoVLE16_V_MF4_MASK:
654  case RISCV::PseudoVLSE16_V_M1:
655  case RISCV::PseudoVLSE16_V_M1_MASK:
656  case RISCV::PseudoVLSE16_V_M2:
657  case RISCV::PseudoVLSE16_V_M2_MASK:
658  case RISCV::PseudoVLSE16_V_M4:
659  case RISCV::PseudoVLSE16_V_M4_MASK:
660  case RISCV::PseudoVLSE16_V_M8:
661  case RISCV::PseudoVLSE16_V_M8_MASK:
662  case RISCV::PseudoVLSE16_V_MF2:
663  case RISCV::PseudoVLSE16_V_MF2_MASK:
664  case RISCV::PseudoVLSE16_V_MF4:
665  case RISCV::PseudoVLSE16_V_MF4_MASK:
666  case RISCV::PseudoVSE16_V_M1:
667  case RISCV::PseudoVSE16_V_M1_MASK:
668  case RISCV::PseudoVSE16_V_M2:
669  case RISCV::PseudoVSE16_V_M2_MASK:
670  case RISCV::PseudoVSE16_V_M4:
671  case RISCV::PseudoVSE16_V_M4_MASK:
672  case RISCV::PseudoVSE16_V_M8:
673  case RISCV::PseudoVSE16_V_M8_MASK:
674  case RISCV::PseudoVSE16_V_MF2:
675  case RISCV::PseudoVSE16_V_MF2_MASK:
676  case RISCV::PseudoVSE16_V_MF4:
677  case RISCV::PseudoVSE16_V_MF4_MASK:
678  case RISCV::PseudoVSSE16_V_M1:
679  case RISCV::PseudoVSSE16_V_M1_MASK:
680  case RISCV::PseudoVSSE16_V_M2:
681  case RISCV::PseudoVSSE16_V_M2_MASK:
682  case RISCV::PseudoVSSE16_V_M4:
683  case RISCV::PseudoVSSE16_V_M4_MASK:
684  case RISCV::PseudoVSSE16_V_M8:
685  case RISCV::PseudoVSSE16_V_M8_MASK:
686  case RISCV::PseudoVSSE16_V_MF2:
687  case RISCV::PseudoVSSE16_V_MF2_MASK:
688  case RISCV::PseudoVSSE16_V_MF4:
689  case RISCV::PseudoVSSE16_V_MF4_MASK:
690  EEW = 16;
691  break;
692  case RISCV::PseudoVLE32_V_M1:
693  case RISCV::PseudoVLE32_V_M1_MASK:
694  case RISCV::PseudoVLE32_V_M2:
695  case RISCV::PseudoVLE32_V_M2_MASK:
696  case RISCV::PseudoVLE32_V_M4:
697  case RISCV::PseudoVLE32_V_M4_MASK:
698  case RISCV::PseudoVLE32_V_M8:
699  case RISCV::PseudoVLE32_V_M8_MASK:
700  case RISCV::PseudoVLE32_V_MF2:
701  case RISCV::PseudoVLE32_V_MF2_MASK:
702  case RISCV::PseudoVLSE32_V_M1:
703  case RISCV::PseudoVLSE32_V_M1_MASK:
704  case RISCV::PseudoVLSE32_V_M2:
705  case RISCV::PseudoVLSE32_V_M2_MASK:
706  case RISCV::PseudoVLSE32_V_M4:
707  case RISCV::PseudoVLSE32_V_M4_MASK:
708  case RISCV::PseudoVLSE32_V_M8:
709  case RISCV::PseudoVLSE32_V_M8_MASK:
710  case RISCV::PseudoVLSE32_V_MF2:
711  case RISCV::PseudoVLSE32_V_MF2_MASK:
712  case RISCV::PseudoVSE32_V_M1:
713  case RISCV::PseudoVSE32_V_M1_MASK:
714  case RISCV::PseudoVSE32_V_M2:
715  case RISCV::PseudoVSE32_V_M2_MASK:
716  case RISCV::PseudoVSE32_V_M4:
717  case RISCV::PseudoVSE32_V_M4_MASK:
718  case RISCV::PseudoVSE32_V_M8:
719  case RISCV::PseudoVSE32_V_M8_MASK:
720  case RISCV::PseudoVSE32_V_MF2:
721  case RISCV::PseudoVSE32_V_MF2_MASK:
722  case RISCV::PseudoVSSE32_V_M1:
723  case RISCV::PseudoVSSE32_V_M1_MASK:
724  case RISCV::PseudoVSSE32_V_M2:
725  case RISCV::PseudoVSSE32_V_M2_MASK:
726  case RISCV::PseudoVSSE32_V_M4:
727  case RISCV::PseudoVSSE32_V_M4_MASK:
728  case RISCV::PseudoVSSE32_V_M8:
729  case RISCV::PseudoVSSE32_V_M8_MASK:
730  case RISCV::PseudoVSSE32_V_MF2:
731  case RISCV::PseudoVSSE32_V_MF2_MASK:
732  EEW = 32;
733  break;
734  case RISCV::PseudoVLE64_V_M1:
735  case RISCV::PseudoVLE64_V_M1_MASK:
736  case RISCV::PseudoVLE64_V_M2:
737  case RISCV::PseudoVLE64_V_M2_MASK:
738  case RISCV::PseudoVLE64_V_M4:
739  case RISCV::PseudoVLE64_V_M4_MASK:
740  case RISCV::PseudoVLE64_V_M8:
741  case RISCV::PseudoVLE64_V_M8_MASK:
742  case RISCV::PseudoVLSE64_V_M1:
743  case RISCV::PseudoVLSE64_V_M1_MASK:
744  case RISCV::PseudoVLSE64_V_M2:
745  case RISCV::PseudoVLSE64_V_M2_MASK:
746  case RISCV::PseudoVLSE64_V_M4:
747  case RISCV::PseudoVLSE64_V_M4_MASK:
748  case RISCV::PseudoVLSE64_V_M8:
749  case RISCV::PseudoVLSE64_V_M8_MASK:
750  case RISCV::PseudoVSE64_V_M1:
751  case RISCV::PseudoVSE64_V_M1_MASK:
752  case RISCV::PseudoVSE64_V_M2:
753  case RISCV::PseudoVSE64_V_M2_MASK:
754  case RISCV::PseudoVSE64_V_M4:
755  case RISCV::PseudoVSE64_V_M4_MASK:
756  case RISCV::PseudoVSE64_V_M8:
757  case RISCV::PseudoVSE64_V_M8_MASK:
758  case RISCV::PseudoVSSE64_V_M1:
759  case RISCV::PseudoVSSE64_V_M1_MASK:
760  case RISCV::PseudoVSSE64_V_M2:
761  case RISCV::PseudoVSSE64_V_M2_MASK:
762  case RISCV::PseudoVSSE64_V_M4:
763  case RISCV::PseudoVSSE64_V_M4_MASK:
764  case RISCV::PseudoVSSE64_V_M8:
765  case RISCV::PseudoVSSE64_V_M8_MASK:
766  EEW = 64;
767  break;
768  }
769 
770  return CurInfo.isCompatibleWithLoadStoreEEW(EEW, Require);
771 }
772 
773 bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB) {
774  bool HadVectorOp = false;
775 
776  BlockData &BBInfo = BlockInfo[MBB.getNumber()];
777  for (const MachineInstr &MI : MBB) {
778  // If this is an explicit VSETVLI or VSETIVLI, update our state.
779  if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
780  MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
781  MI.getOpcode() == RISCV::PseudoVSETIVLI) {
782  HadVectorOp = true;
783  BBInfo.Change = getInfoForVSETVLI(MI);
784  continue;
785  }
786 
787  uint64_t TSFlags = MI.getDesc().TSFlags;
788  if (RISCVII::hasSEWOp(TSFlags)) {
789  HadVectorOp = true;
790 
791  VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, MRI);
792 
793  if (!BBInfo.Change.isValid()) {
794  BBInfo.Change = NewInfo;
795  } else {
796  // If this instruction isn't compatible with the previous VL/VTYPE
797  // we need to insert a VSETVLI.
798  // If this is a unit-stride or strided load/store, we may be able to use
799  // the EMUL=(EEW/SEW)*LMUL relationship to avoid changing vtype.
800  // NOTE: We only do this if the vtype we're comparing against was
801  // created in this block. We need the first and third phase to treat
802  // the store the same way.
803  if (!canSkipVSETVLIForLoadStore(MI, NewInfo, BBInfo.Change) &&
804  needVSETVLI(NewInfo, BBInfo.Change))
805  BBInfo.Change = NewInfo;
806  }
807  }
808 
809  // If this is something that updates VL/VTYPE that we don't know about, set
810  // the state to unknown.
811  if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
812  MI.modifiesRegister(RISCV::VTYPE)) {
813  BBInfo.Change = VSETVLIInfo::getUnknown();
814  }
815  }
816 
817  // Initial exit state is whatever change we found in the block.
818  BBInfo.Exit = BBInfo.Change;
819 
820  return HadVectorOp;
821 }
822 
823 void RISCVInsertVSETVLI::computeIncomingVLVTYPE(const MachineBasicBlock &MBB) {
824  BlockData &BBInfo = BlockInfo[MBB.getNumber()];
825 
826  BBInfo.InQueue = false;
827 
828  VSETVLIInfo InInfo;
829  if (MBB.pred_empty()) {
830  // There are no predecessors, so use the default starting status.
831  InInfo.setUnknown();
832  } else {
834  InInfo = InInfo.intersect(BlockInfo[P->getNumber()].Exit);
835  }
836 
837  // If we don't have any valid predecessor value, wait until we do.
838  if (!InInfo.isValid())
839  return;
840 
841  BBInfo.Pred = InInfo;
842 
843  VSETVLIInfo TmpStatus = BBInfo.Pred.merge(BBInfo.Change);
844 
845  // If the new exit value matches the old exit value, we don't need to revisit
846  // any blocks.
847  if (BBInfo.Exit == TmpStatus)
848  return;
849 
850  BBInfo.Exit = TmpStatus;
851 
852  // Add the successors to the work list so we can propagate the changed exit
853  // status.
854  for (MachineBasicBlock *S : MBB.successors())
855  if (!BlockInfo[S->getNumber()].InQueue)
856  WorkList.push(S);
857 }
858 
859 // If we weren't able to prove a vsetvli was directly unneeded, it might still
860 // be/ unneeded if the AVL is a phi node where all incoming values are VL
861 // outputs from the last VSETVLI in their respective basic blocks.
862 bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
863  const MachineBasicBlock &MBB) {
865  return true;
866 
867  if (!Require.hasAVLReg())
868  return true;
869 
870  Register AVLReg = Require.getAVLReg();
871  if (!AVLReg.isVirtual())
872  return true;
873 
874  // We need the AVL to be produce by a PHI node in this basic block.
875  MachineInstr *PHI = MRI->getVRegDef(AVLReg);
876  if (!PHI || PHI->getOpcode() != RISCV::PHI || PHI->getParent() != &MBB)
877  return true;
878 
879  for (unsigned PHIOp = 1, NumOps = PHI->getNumOperands(); PHIOp != NumOps;
880  PHIOp += 2) {
881  Register InReg = PHI->getOperand(PHIOp).getReg();
882  MachineBasicBlock *PBB = PHI->getOperand(PHIOp + 1).getMBB();
883  const BlockData &PBBInfo = BlockInfo[PBB->getNumber()];
884  // If the exit from the predecessor has the VTYPE we are looking for
885  // we might be able to avoid a VSETVLI.
886  if (PBBInfo.Exit.isUnknown() || !PBBInfo.Exit.hasSameVTYPE(Require))
887  return true;
888 
889  // We need the PHI input to the be the output of a VSET(I)VLI.
890  MachineInstr *DefMI = MRI->getVRegDef(InReg);
891  if (!DefMI || (DefMI->getOpcode() != RISCV::PseudoVSETVLI &&
892  DefMI->getOpcode() != RISCV::PseudoVSETVLIX0 &&
893  DefMI->getOpcode() != RISCV::PseudoVSETIVLI))
894  return true;
895 
896  // We found a VSET(I)VLI make sure it matches the output of the
897  // predecessor block.
898  VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
899  if (!DefInfo.hasSameAVL(PBBInfo.Exit) ||
900  !DefInfo.hasSameVTYPE(PBBInfo.Exit))
901  return true;
902  }
903 
904  // If all the incoming values to the PHI checked out, we don't need
905  // to insert a VSETVLI.
906  return false;
907 }
908 
909 void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
910  VSETVLIInfo CurInfo;
911  // Only be set if current VSETVLIInfo is from an explicit VSET(I)VLI.
912  MachineInstr *PrevVSETVLIMI = nullptr;
913 
914  for (MachineInstr &MI : MBB) {
915  // If this is an explicit VSETVLI or VSETIVLI, update our state.
916  if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
917  MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
918  MI.getOpcode() == RISCV::PseudoVSETIVLI) {
919  // Conservatively, mark the VL and VTYPE as live.
920  assert(MI.getOperand(3).getReg() == RISCV::VL &&
921  MI.getOperand(4).getReg() == RISCV::VTYPE &&
922  "Unexpected operands where VL and VTYPE should be");
923  MI.getOperand(3).setIsDead(false);
924  MI.getOperand(4).setIsDead(false);
925  CurInfo = getInfoForVSETVLI(MI);
926  PrevVSETVLIMI = &MI;
927  continue;
928  }
929 
930  uint64_t TSFlags = MI.getDesc().TSFlags;
931  if (RISCVII::hasSEWOp(TSFlags)) {
932  VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, MRI);
933  if (RISCVII::hasVLOp(TSFlags)) {
934  unsigned Offset = 2;
935  if (RISCVII::hasVecPolicyOp(TSFlags))
936  Offset = 3;
937  MachineOperand &VLOp =
938  MI.getOperand(MI.getNumExplicitOperands() - Offset);
939  if (VLOp.isReg()) {
940  // Erase the AVL operand from the instruction.
941  VLOp.setReg(RISCV::NoRegister);
942  VLOp.setIsKill(false);
943  }
944  MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false,
945  /*isImp*/ true));
946  }
947  MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ false,
948  /*isImp*/ true));
949 
950  if (!CurInfo.isValid()) {
951  // We haven't found any vector instructions or VL/VTYPE changes yet,
952  // use the predecessor information.
953  assert(BlockInfo[MBB.getNumber()].Pred.isValid() &&
954  "Expected a valid predecessor state.");
955  if (needVSETVLI(NewInfo, BlockInfo[MBB.getNumber()].Pred) &&
956  needVSETVLIPHI(NewInfo, MBB)) {
957  insertVSETVLI(MBB, MI, NewInfo, BlockInfo[MBB.getNumber()].Pred);
958  CurInfo = NewInfo;
959  }
960  } else {
961  // If this instruction isn't compatible with the previous VL/VTYPE
962  // we need to insert a VSETVLI.
963  // If this is a unit-stride or strided load/store, we may be able to use
964  // the EMUL=(EEW/SEW)*LMUL relationship to avoid changing vtype.
965  // NOTE: We can't use predecessor information for the store. We must
966  // treat it the same as the first phase so that we produce the correct
967  // vl/vtype for succesor blocks.
968  if (!canSkipVSETVLIForLoadStore(MI, NewInfo, CurInfo) &&
969  needVSETVLI(NewInfo, CurInfo)) {
970  // If the previous VL/VTYPE is set by VSETVLI and do not use, Merge it
971  // with current VL/VTYPE.
972  bool NeedInsertVSETVLI = true;
973  if (PrevVSETVLIMI) {
974  bool HasSameAVL =
975  CurInfo.hasSameAVL(NewInfo) ||
976  (NewInfo.hasAVLReg() && NewInfo.getAVLReg().isVirtual() &&
977  NewInfo.getAVLReg() == PrevVSETVLIMI->getOperand(0).getReg());
978  // If these two VSETVLI have the same AVL and the same VLMAX,
979  // we could merge these two VSETVLI.
980  if (HasSameAVL &&
981  CurInfo.getSEWLMULRatio() == NewInfo.getSEWLMULRatio()) {
982  PrevVSETVLIMI->getOperand(2).setImm(NewInfo.encodeVTYPE());
983  NeedInsertVSETVLI = false;
984  }
985  }
986  if (NeedInsertVSETVLI)
987  insertVSETVLI(MBB, MI, NewInfo, CurInfo);
988  CurInfo = NewInfo;
989  }
990  }
991  PrevVSETVLIMI = nullptr;
992  }
993 
994  // If this is something updates VL/VTYPE that we don't know about, set
995  // the state to unknown.
996  if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
997  MI.modifiesRegister(RISCV::VTYPE)) {
998  CurInfo = VSETVLIInfo::getUnknown();
999  PrevVSETVLIMI = nullptr;
1000  }
1001  }
1002 }
1003 
1004 bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
1005  // Skip if the vector extension is not enabled.
1007  if (!ST.hasStdExtV())
1008  return false;
1009 
1010  TII = ST.getInstrInfo();
1011  MRI = &MF.getRegInfo();
1012 
1013  assert(BlockInfo.empty() && "Expect empty block infos");
1014  BlockInfo.resize(MF.getNumBlockIDs());
1015 
1016  bool HaveVectorOp = false;
1017 
1018  // Phase 1 - determine how VL/VTYPE are affected by the each block.
1019  for (const MachineBasicBlock &MBB : MF)
1020  HaveVectorOp |= computeVLVTYPEChanges(MBB);
1021 
1022  // If we didn't find any instructions that need VSETVLI, we're done.
1023  if (HaveVectorOp) {
1024  // Phase 2 - determine the exit VL/VTYPE from each block. We add all
1025  // blocks to the list here, but will also add any that need to be revisited
1026  // during Phase 2 processing.
1027  for (const MachineBasicBlock &MBB : MF) {
1028  WorkList.push(&MBB);
1029  BlockInfo[MBB.getNumber()].InQueue = true;
1030  }
1031  while (!WorkList.empty()) {
1032  const MachineBasicBlock &MBB = *WorkList.front();
1033  WorkList.pop();
1034  computeIncomingVLVTYPE(MBB);
1035  }
1036 
1037  // Phase 3 - add any vsetvli instructions needed in the block. Use the
1038  // Phase 2 information to avoid adding vsetvlis before the first vector
1039  // instruction in the block if the VL/VTYPE is satisfied by its
1040  // predecessors.
1041  for (MachineBasicBlock &MBB : MF)
1042  emitVSETVLIs(MBB);
1043  }
1044 
1045  BlockInfo.clear();
1046 
1047  return HaveVectorOp;
1048 }
1049 
1050 /// Returns an instance of the Insert VSETVLI pass.
1052  return new RISCVInsertVSETVLI();
1053 }
llvm::RISCVII::LMUL_1
@ LMUL_1
Definition: RISCVBaseInfo.h:96
intersect
static ValueLatticeElement intersect(const ValueLatticeElement &A, const ValueLatticeElement &B)
Combine two sets of facts about the same value into a single set of facts.
Definition: LazyValueInfo.cpp:96
RISCV_INSERT_VSETVLI_NAME
#define RISCV_INSERT_VSETVLI_NAME
Definition: RISCVInsertVSETVLI.cpp:34
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MachineInstr::isImplicitDef
bool isImplicitDef() const
Definition: MachineInstr.h:1260
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::createRISCVInsertVSETVLIPass
FunctionPass * createRISCVInsertVSETVLIPass()
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:500
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineFunction::getNumBlockIDs
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
Definition: MachineFunction.h:753
llvm::RISCVVType::isValidSEW
static bool isValidSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:331
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:655
llvm::RISCVII::hasSEWOp
static bool hasSEWOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:138
llvm::X86II::TA
@ TA
Definition: X86BaseInfo.h:803
llvm::RISCVVType::isTailAgnostic
static bool isTailAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:361
BlockData::BlockData
BlockData()
Definition: SIModeRegister.cpp:104
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::RISCV::VLMaxSentinel
static constexpr int64_t VLMaxSentinel
Definition: RISCVInstrInfo.h:185
llvm::RISCVII::hasVecPolicyOp
static bool hasVecPolicyOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:146
llvm::RISCVVType::getSEW
static unsigned getSEW(unsigned VType)
Definition: RISCVBaseInfo.h:356
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
DisableInsertVSETVLPHIOpt
static cl::opt< bool > DisableInsertVSETVLPHIOpt("riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, cl::desc("Disable looking through phis when inserting vsetvlis."))
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
merge
static LoopDeletionResult merge(LoopDeletionResult A, LoopDeletionResult B)
Definition: LoopDeletion.cpp:51
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::RISCVII::hasVLOp
static bool hasVLOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:142
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::cl::opt< bool >
llvm::RISCVVType::decodeVLMUL
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
Definition: RISCVBaseInfo.cpp:124
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::pdb::Unknown
@ Unknown
Definition: PDBTypes.h:395
LiveIntervals.h
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
MachineFunctionPass.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::operator==
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1974
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineBasicBlock::predecessors
iterator_range< pred_iterator > predecessors()
Definition: MachineBasicBlock.h:349
INITIALIZE_PASS
INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME, false, false) static MachineInstr *elideCopies(MachineInstr *MI
RISCV.h
llvm::MachineBasicBlock::pred_empty
bool pred_empty() const
Definition: MachineBasicBlock.h:331
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1056
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:355
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVII::doesForceTailAgnostic
static bool doesForceTailAgnostic(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:130
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::RISCVVType::getVLMUL
static RISCVII::VLMUL getVLMUL(unsigned VType)
Definition: RISCVBaseInfo.h:343
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::RISCVVType::isMaskAgnostic
static bool isMaskAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:363
llvm::RISCVVType::encodeVTYPE
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
Definition: RISCVBaseInfo.cpp:110
llvm::RISCVII::getLMul
static VLMUL getLMul(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:122
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:247
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
RISCVSubtarget.h
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
llvm::initializeRISCVInsertVSETVLIPass
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:216
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
DEBUG_TYPE
#define DEBUG_TYPE
Definition: RISCVInsertVSETVLI.cpp:33
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:95
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:414
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1175
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37