34#define DEBUG_TYPE "riscv-insert-vsetvli"
35#define RISCV_INSERT_VSETVLI_NAME "RISC-V Insert VSETVLI pass"
39 cl::desc(
"Disable looking through phis when inserting vsetvlis."));
43 cl::desc(
"Enable strict assertion checking for the dataflow algorithm"));
56 return MI.getOpcode() == RISCV::PseudoVSETVLI ||
57 MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
58 MI.getOpcode() == RISCV::PseudoVSETIVLI;
64 if (
MI.getOpcode() != RISCV::PseudoVSETVLIX0)
66 assert(RISCV::X0 ==
MI.getOperand(1).getReg());
67 return RISCV::X0 ==
MI.getOperand(0).getReg();
72 RISCVVPseudosTable::getPseudoInfo(RVVPseudoOpcode);
78static bool isFloatScalarMoveOrScalarSplatInstr(
const MachineInstr &
MI) {
79 switch (getRVVMCOpcode(
MI.getOpcode())) {
89 switch (getRVVMCOpcode(
MI.getOpcode())) {
99 switch (getRVVMCOpcode(
MI.getOpcode())) {
103 case RISCV::VFMV_S_F:
109 switch (getRVVMCOpcode(
MI.getOpcode())) {
114 case RISCV::VFMV_V_F:
120 switch (getRVVMCOpcode(
MI.getOpcode())) {
123 case RISCV::VSLIDEDOWN_VX:
124 case RISCV::VSLIDEDOWN_VI:
125 case RISCV::VSLIDEUP_VX:
126 case RISCV::VSLIDEUP_VI:
133static std::optional<unsigned> getEEWForLoadStore(
const MachineInstr &
MI) {
134 switch (getRVVMCOpcode(
MI.getOpcode())) {
143 case RISCV::VLSE16_V:
145 case RISCV::VSSE16_V:
148 case RISCV::VLSE32_V:
150 case RISCV::VSSE32_V:
153 case RISCV::VLSE64_V:
155 case RISCV::VSSE64_V:
165 const unsigned Log2SEW =
MI.getOperand(getSEWOpNum(
MI)).getImm();
178 if (!
MI.isRegTiedToUseOperand(0, &UseOpIdx))
187 if (UseMO.
getReg() == RISCV::NoRegister)
207struct DemandedFields {
212 bool VLZeroness =
false;
216 SEWGreaterThanOrEqual = 2,
218 SEWGreaterThanOrEqualAndLessThan64 =
225 bool SEWLMULRatio =
false;
226 bool TailPolicy =
false;
227 bool MaskPolicy =
false;
230 bool usedVTYPE()
const {
231 return SEW ||
LMUL || SEWLMULRatio || TailPolicy || MaskPolicy;
236 return VLAny || VLZeroness;
254#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
264 OS <<
"VLAny=" << VLAny <<
", ";
265 OS <<
"VLZeroness=" << VLZeroness <<
", ";
271 case SEWGreaterThanOrEqual:
272 OS <<
"SEWGreaterThanOrEqual";
274 case SEWGreaterThanOrEqualAndLessThan64:
275 OS <<
"SEWGreaterThanOrEqualAndLessThan64";
282 OS <<
"LMUL=" <<
LMUL <<
", ";
283 OS <<
"SEWLMULRatio=" << SEWLMULRatio <<
", ";
284 OS <<
"TailPolicy=" << TailPolicy <<
", ";
285 OS <<
"MaskPolicy=" << MaskPolicy;
291#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
303 const DemandedFields &Used) {
304 if (
Used.SEW == DemandedFields::SEWEqual &&
308 if (
Used.SEW == DemandedFields::SEWGreaterThanOrEqual &&
312 if (
Used.SEW == DemandedFields::SEWGreaterThanOrEqualAndLessThan64 &&
321 if (
Used.SEWLMULRatio) {
326 if (Ratio1 != Ratio2)
346 bool HasVInstructionsF64 =
352 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.readsRegister(RISCV::VL))
354 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.readsRegister(RISCV::VTYPE))
365 Res.MaskPolicy =
false;
374 if (getEEWForLoadStore(
MI)) {
375 Res.SEW = DemandedFields::SEWNone;
381 Res.TailPolicy =
false;
382 Res.MaskPolicy =
false;
389 if (isMaskRegOp(
MI)) {
390 Res.SEW = DemandedFields::SEWNone;
395 if (isScalarInsertInstr(
MI)) {
397 Res.SEWLMULRatio =
false;
405 if (hasUndefinedMergeOp(
MI, *
MRI)) {
406 if (isFloatScalarMoveOrScalarSplatInstr(
MI) && !HasVInstructionsF64)
407 Res.SEW = DemandedFields::SEWGreaterThanOrEqualAndLessThan64;
409 Res.SEW = DemandedFields::SEWGreaterThanOrEqual;
410 Res.TailPolicy =
false;
415 if (isScalarExtractInstr(
MI)) {
418 Res.SEWLMULRatio =
false;
419 Res.TailPolicy =
false;
420 Res.MaskPolicy =
false;
446 uint8_t SEWLMULRatioOnly : 1;
451 SEWLMULRatioOnly(
false) {}
453 static VSETVLIInfo getUnknown() {
460 void setUnknown() { State =
Unknown; }
461 bool isUnknown()
const {
return State ==
Unknown; }
468 void setAVLImm(
unsigned Imm) {
473 bool hasAVLImm()
const {
return State == AVLIsImm; }
474 bool hasAVLReg()
const {
return State == AVLIsReg; }
479 unsigned getAVLImm()
const {
484 unsigned getSEW()
const {
return SEW; }
489 return getAVLImm() > 0;
491 if (getAVLReg() == RISCV::X0)
494 MI &&
MI->getOpcode() == RISCV::ADDI &&
495 MI->getOperand(1).isReg() &&
MI->getOperand(2).isImm() &&
496 MI->getOperand(1).getReg() == RISCV::X0 &&
497 MI->getOperand(2).getImm() != 0)
504 bool hasEquallyZeroAVL(
const VSETVLIInfo &
Other,
506 if (hasSameAVL(
Other))
508 return (hasNonZeroAVL(
MRI) &&
Other.hasNonZeroAVL(
MRI));
511 bool hasSameAVL(
const VSETVLIInfo &
Other)
const {
512 if (hasAVLReg() &&
Other.hasAVLReg())
513 return getAVLReg() ==
Other.getAVLReg();
515 if (hasAVLImm() &&
Other.hasAVLImm())
516 return getAVLImm() ==
Other.getAVLImm();
523 "Can't set VTYPE for uninitialized or unknown");
531 "Can't set VTYPE for uninitialized or unknown");
540 "Can't encode VTYPE for uninitialized or unknown");
544 bool hasSEWLMULRatioOnly()
const {
return SEWLMULRatioOnly; }
546 bool hasSameVTYPE(
const VSETVLIInfo &
Other)
const {
548 "Can't compare invalid VSETVLIInfos");
550 "Can't compare VTYPE in unknown state");
551 assert(!SEWLMULRatioOnly && !
Other.SEWLMULRatioOnly &&
552 "Can't compare when only LMUL/SEW ratio is valid.");
553 return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) ==
560 "Can't use VTYPE for uninitialized or unknown");
568 bool hasSameVLMAX(
const VSETVLIInfo &
Other)
const {
570 "Can't compare invalid VSETVLIInfos");
572 "Can't compare VTYPE in unknown state");
576 bool hasCompatibleVTYPE(
const DemandedFields &Used,
577 const VSETVLIInfo &Require)
const {
578 return areCompatibleVTYPEs(Require.encodeVTYPE(),
encodeVTYPE(), Used);
584 bool isCompatible(
const DemandedFields &Used,
const VSETVLIInfo &Require,
587 "Can't compare invalid VSETVLIInfos");
588 assert(!Require.SEWLMULRatioOnly &&
589 "Expected a valid VTYPE for instruction!");
591 if (isUnknown() || Require.isUnknown())
595 if (SEWLMULRatioOnly)
598 if (
Used.VLAny && !hasSameAVL(Require))
601 if (
Used.VLZeroness && !hasEquallyZeroAVL(Require,
MRI))
604 return hasCompatibleVTYPE(Used, Require);
610 return !
Other.isValid();
611 if (!
Other.isValid())
616 return Other.isUnknown();
617 if (
Other.isUnknown())
620 if (!hasSameAVL(
Other))
624 if (SEWLMULRatioOnly !=
Other.SEWLMULRatioOnly)
628 if (SEWLMULRatioOnly)
629 return hasSameVLMAX(
Other);
632 return hasSameVTYPE(
Other);
636 return !(*
this ==
Other);
643 if (!
Other.isValid())
651 if (isUnknown() ||
Other.isUnknown())
652 return VSETVLIInfo::getUnknown();
660 if (hasSameAVL(
Other) && hasSameVLMAX(
Other)) {
661 VSETVLIInfo MergeInfo = *
this;
662 MergeInfo.SEWLMULRatioOnly =
true;
667 return VSETVLIInfo::getUnknown();
670#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
682 OS <<
"Uninitialized";
688 OS <<
"AVLImm=" << (
unsigned)AVLImm;
690 <<
"VLMul=" << (
unsigned)VLMul <<
", "
691 <<
"SEW=" << (
unsigned)
SEW <<
", "
692 <<
"TailAgnostic=" << (
bool)TailAgnostic <<
", "
694 <<
"SEWLMULRatioOnly=" << (
bool)SEWLMULRatioOnly <<
"}";
699#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
717 bool InQueue =
false;
726 std::vector<BlockData> BlockInfo;
727 std::queue<const MachineBasicBlock *> WorkList;
745 bool needVSETVLI(
const MachineInstr &
MI,
const VSETVLIInfo &Require,
746 const VSETVLIInfo &CurInfo)
const;
747 bool needVSETVLIPHI(
const VSETVLIInfo &Require,
750 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo);
753 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo);
755 void transferBefore(VSETVLIInfo &Info,
const MachineInstr &
MI)
const;
756 void transferAfter(VSETVLIInfo &Info,
const MachineInstr &
MI)
const;
758 VSETVLIInfo &Info)
const;
768char RISCVInsertVSETVLI::ID = 0;
779 if (!hasUndefinedMergeOp(
MI, *
MRI)) {
789 "Invalid Policy Value");
813 int64_t Imm = VLOp.
getImm();
827 if (std::optional<unsigned> EEW = getEEWForLoadStore(
MI)) {
828 assert(
SEW == EEW &&
"Initial SEW doesn't match expected EEW");
837 const VSETVLIInfo &Info,
838 const VSETVLIInfo &PrevInfo) {
847 if (
MI.getOpcode() == RISCV::PseudoVSETIVLI) {
848 NewInfo.setAVLImm(
MI.getOperand(1).getImm());
850 assert(
MI.getOpcode() == RISCV::PseudoVSETVLI ||
851 MI.getOpcode() == RISCV::PseudoVSETVLIX0);
853 assert((AVLReg != RISCV::X0 ||
MI.getOperand(0).getReg() != RISCV::X0) &&
854 "Can't handle X0, X0 vsetvli yet");
855 NewInfo.setAVLReg(AVLReg);
857 NewInfo.setVTYPE(
MI.getOperand(2).getImm());
864 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo) {
866 if (PrevInfo.isValid() && !PrevInfo.isUnknown()) {
869 if (
Info.hasSameAVL(PrevInfo) &&
Info.hasSameVLMAX(PrevInfo)) {
881 if (
Info.hasSameVLMAX(PrevInfo) &&
Info.hasAVLReg() &&
882 Info.getAVLReg().isVirtual()) {
884 if (isVectorConfigInstr(*
DefMI)) {
886 if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
899 if (
Info.hasAVLImm()) {
908 if (AVLReg == RISCV::NoRegister) {
911 if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
912 Info.hasSameVLMAX(PrevInfo)) {
929 MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);
935 unsigned Opcode = RISCV::PseudoVSETVLI;
936 if (AVLReg == RISCV::X0) {
937 DestReg =
MRI->createVirtualRegister(&RISCV::GPRRegClass);
938 Opcode = RISCV::PseudoVSETVLIX0;
948 return Fractional || LMul == 1;
954 const VSETVLIInfo &Require,
955 const VSETVLIInfo &CurInfo)
const {
956 assert(Require == computeInfoForInstr(
MI,
MI.getDesc().TSFlags,
MRI));
958 if (!CurInfo.isValid() || CurInfo.isUnknown() || CurInfo.hasSEWLMULRatioOnly())
961 DemandedFields
Used = getDemanded(
MI,
MRI);
962 bool HasVInstructionsF64 =
973 if (isVSlideInstr(
MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
976 Used.VLZeroness =
true;
978 Used.TailPolicy =
false;
986 if (isScalarSplatInstr(
MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
989 Used.SEWLMULRatio =
false;
991 if (isFloatScalarMoveOrScalarSplatInstr(
MI) && !HasVInstructionsF64)
992 Used.SEW = DemandedFields::SEWGreaterThanOrEqualAndLessThan64;
994 Used.SEW = DemandedFields::SEWGreaterThanOrEqual;
995 Used.TailPolicy =
false;
998 if (CurInfo.isCompatible(Used, Require, *
MRI))
1005 if (Require.hasAVLReg() && Require.getAVLReg().isVirtual() &&
1006 CurInfo.hasCompatibleVTYPE(Used, Require)) {
1008 if (isVectorConfigInstr(*
DefMI)) {
1010 if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
1022void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
1028 const VSETVLIInfo NewInfo = computeInfoForInstr(
MI,
TSFlags,
MRI);
1029 if (
Info.isValid() && !needVSETVLI(
MI, NewInfo, Info))
1032 const VSETVLIInfo PrevInfo =
Info;
1046 if (isScalarInsertInstr(
MI) && PrevInfo.isValid() &&
1047 PrevInfo.hasEquallyZeroAVL(Info, *
MRI) &&
1048 Info.hasSameVLMAX(PrevInfo)) {
1049 if (PrevInfo.hasAVLImm())
1050 Info.setAVLImm(PrevInfo.getAVLImm());
1052 Info.setAVLReg(PrevInfo.getAVLReg());
1060 if (!
Info.hasAVLReg() || !
Info.getAVLReg().isVirtual())
1067 if (DefInfo.hasSameVLMAX(Info) &&
1068 (DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) {
1069 if (DefInfo.hasAVLImm())
1070 Info.setAVLImm(DefInfo.getAVLImm());
1072 Info.setAVLReg(DefInfo.getAVLReg());
1080void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
1082 if (isVectorConfigInstr(
MI)) {
1089 Info.setAVLReg(
MI.getOperand(1).getReg());
1095 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.modifiesRegister(RISCV::VL) ||
1096 MI.modifiesRegister(RISCV::VTYPE))
1097 Info = VSETVLIInfo::getUnknown();
1101 VSETVLIInfo &Info)
const {
1102 bool HadVectorOp =
false;
1106 transferBefore(Info,
MI);
1111 transferAfter(Info,
MI);
1121 BBInfo.InQueue =
false;
1125 VSETVLIInfo InInfo = BBInfo.
Pred;
1128 InInfo.setUnknown();
1131 InInfo = InInfo.
intersect(BlockInfo[
P->getNumber()].Exit);
1135 if (!InInfo.isValid())
1139 if (InInfo == BBInfo.
Pred)
1142 BBInfo.
Pred = InInfo;
1144 <<
" changed to " << BBInfo.
Pred <<
"\n");
1150 VSETVLIInfo TmpStatus;
1151 computeVLVTYPEChanges(
MBB, TmpStatus);
1155 if (BBInfo.
Exit == TmpStatus)
1158 BBInfo.
Exit = TmpStatus;
1160 <<
" changed to " << BBInfo.
Exit <<
"\n");
1165 if (!BlockInfo[S->getNumber()].InQueue) {
1166 BlockInfo[S->getNumber()].InQueue =
true;
1174bool RISCVInsertVSETVLI::needVSETVLIPHI(
const VSETVLIInfo &Require,
1179 if (!Require.hasAVLReg())
1182 Register AVLReg = Require.getAVLReg();
1188 if (!
PHI ||
PHI->getOpcode() != RISCV::PHI ||
PHI->getParent() != &
MBB)
1191 for (
unsigned PHIOp = 1, NumOps =
PHI->getNumOperands(); PHIOp != NumOps;
1198 if (PBBInfo.
Exit.isUnknown() || !PBBInfo.
Exit.hasSameVTYPE(Require))
1209 if (!DefInfo.hasSameAVL(PBBInfo.
Exit) ||
1210 !DefInfo.hasSameVTYPE(PBBInfo.
Exit))
1223 bool PrefixTransparent =
true;
1225 const VSETVLIInfo PrevInfo = CurInfo;
1226 transferBefore(CurInfo,
MI);
1229 if (isVectorConfigInstr(
MI)) {
1231 assert(
MI.getOperand(3).getReg() == RISCV::VL &&
1232 MI.getOperand(4).getReg() == RISCV::VTYPE &&
1233 "Unexpected operands where VL and VTYPE should be");
1234 MI.getOperand(3).setIsDead(
false);
1235 MI.getOperand(4).setIsDead(
false);
1236 PrefixTransparent =
false;
1241 if (PrevInfo != CurInfo) {
1249 if (!PrefixTransparent || needVSETVLIPHI(CurInfo,
MBB))
1250 insertVSETVLI(
MBB,
MI, CurInfo, PrevInfo);
1251 PrefixTransparent =
false;
1258 VLOp.
setReg(RISCV::NoRegister);
1268 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.modifiesRegister(RISCV::VL) ||
1269 MI.modifiesRegister(RISCV::VTYPE))
1270 PrefixTransparent =
false;
1272 transferAfter(CurInfo,
MI);
1278 const VSETVLIInfo &ExitInfo = BlockInfo[
MBB.
getNumber()].Exit;
1279 if (CurInfo.isValid() && ExitInfo.isValid() && !ExitInfo.isUnknown() &&
1280 CurInfo != ExitInfo) {
1292 if (CurInfo !=
Info.Exit) {
1299 "InsertVSETVLI dataflow invariant violated");
1305 if (!
Info.hasAVLImm())
1309 return RISCV::X0 ==
Info.getAVLReg();
1311 unsigned AVL =
Info.getAVLImm();
1313 unsigned AVLInBits = AVL *
SEW;
1320 return ST.getRealMinVLen() / LMul >= AVLInBits;
1321 return ST.getRealMinVLen() * LMul >= AVLInBits;
1337 VSETVLIInfo AvailableInfo;
1339 const VSETVLIInfo &PredInfo = BlockInfo[
P->getNumber()].Exit;
1340 if (PredInfo.isUnknown()) {
1341 if (UnavailablePred)
1343 UnavailablePred =
P;
1344 }
else if (!AvailableInfo.isValid()) {
1345 AvailableInfo = PredInfo;
1346 }
else if (AvailableInfo != PredInfo) {
1353 if (!UnavailablePred || !AvailableInfo.isValid())
1373 VSETVLIInfo CurInfo = AvailableInfo;
1374 int TransitionsRemoved = 0;
1376 const VSETVLIInfo LastInfo = CurInfo;
1377 const VSETVLIInfo LastOldInfo = OldInfo;
1378 transferBefore(CurInfo,
MI);
1379 transferBefore(OldInfo,
MI);
1380 if (CurInfo == LastInfo)
1381 TransitionsRemoved++;
1382 if (LastOldInfo == OldInfo)
1383 TransitionsRemoved--;
1384 transferAfter(CurInfo,
MI);
1385 transferAfter(OldInfo,
MI);
1386 if (CurInfo == OldInfo)
1390 if (CurInfo != OldInfo || TransitionsRemoved <= 0)
1397 auto OldExit = BlockInfo[UnavailablePred->
getNumber()].Exit;
1399 << UnavailablePred->
getName() <<
" with state "
1400 << AvailableInfo <<
"\n");
1401 BlockInfo[UnavailablePred->
getNumber()].Exit = AvailableInfo;
1407 insertVSETVLI(*UnavailablePred, InsertPt,
1409 AvailableInfo, OldExit);
1414 A.VLZeroness |=
B.VLZeroness;
1415 A.SEW = std::max(
A.SEW,
B.SEW);
1417 A.SEWLMULRatio |=
B.SEWLMULRatio;
1418 A.TailPolicy |=
B.TailPolicy;
1419 A.MaskPolicy |=
B.MaskPolicy;
1424 return RISCV::X0 == MO.
getReg();
1433 const DemandedFields &Used) {
1437 if (!isVLPreservingConfig(
MI)) {
1443 if (Used.VLZeroness) {
1444 if (isVLPreservingConfig(PrevMI))
1453 if (
MI.getOperand(1).isReg() &&
1454 RISCV::X0 !=
MI.getOperand(1).getReg())
1462 auto VType =
MI.getOperand(2).getImm();
1463 return areCompatibleVTYPEs(PriorVType, VType, Used);
1470 DemandedFields
Used;
1476 if (!isVectorConfigInstr(
MI)) {
1481 Register VRegDef =
MI.getOperand(0).getReg();
1482 if (VRegDef != RISCV::X0 &&
1483 !(VRegDef.
isVirtual() &&
MRI->use_nodbg_empty(VRegDef)))
1487 if (!
Used.usedVL() && !
Used.usedVTYPE()) {
1492 if (!isVLPreservingConfig(*NextMI)) {
1494 MI.getOperand(0).setIsDead(
false);
1510 for (
auto *
MI : ToDelete)
1511 MI->eraseFromParent();
1518 Register VLOutput =
MI.getOperand(1).getReg();
1519 if (!
MRI->use_nodbg_empty(VLOutput))
1523 MI.getOperand(1).setReg(RISCV::X0);
1531 if (!
ST.hasVInstructions())
1536 TII =
ST.getInstrInfo();
1539 assert(BlockInfo.empty() &&
"Expect empty block infos");
1542 bool HaveVectorOp =
false;
1546 VSETVLIInfo TmpStatus;
1547 HaveVectorOp |= computeVLVTYPEChanges(
MBB, TmpStatus);
1550 BBInfo.
Exit = TmpStatus;
1552 <<
" is " << BBInfo.
Exit <<
"\n");
1557 if (!HaveVectorOp) {
1566 WorkList.push(&
MBB);
1569 while (!WorkList.empty()) {
1572 computeIncomingVLVTYPE(
MBB);
1593 doLocalPostpass(
MBB);
1601 return HaveVectorOp;
1606 return new RISCVInsertVSETVLI();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
#define LLVM_ATTRIBUTE_USED
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::optional< std::vector< StOtherPiece > > Other
const HexagonInstrInfo * TII
static ValueLatticeElement intersect(const ValueLatticeElement &A, const ValueLatticeElement &B)
Combine two sets of facts about the same value into a single set of facts.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI)
static bool isNonZeroAVL(const MachineOperand &MO)
#define RISCV_INSERT_VSETVLI_NAME
uint64_t const MachineRegisterInfo * MRI
static bool canMutatePriorConfig(const MachineInstr &PrevMI, const MachineInstr &MI, const DemandedFields &Used)
assert(RISCVVType::isValidSEW(SEW) &&"Unexpected SEW")
InstrInfo setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic)
static bool isLMUL1OrSmaller(RISCVII::VLMUL LMUL)
InstrInfo setAVLReg(RISCV::NoRegister)
static void doUnion(DemandedFields &A, DemandedFields B)
static cl::opt< bool > UseStrictAsserts("riscv-insert-vsetvl-strict-asserts", cl::init(true), cl::Hidden, cl::desc("Enable strict assertion checking for the dataflow algorithm"))
static cl::opt< bool > DisableInsertVSETVLPHIOpt("riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, cl::desc("Disable looking through phis when inserting vsetvlis."))
static bool hasFixedResult(const VSETVLIInfo &Info, const RISCVSubtarget &ST)
Return true if the VL value configured must be equal to the requested one.
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
unsigned succ_size() const
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
reverse_iterator rbegin()
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool isImplicitDef() const
unsigned getNumOperands() const
Retuns the total number of operands.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isRegSequence() const
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
This class implements an extremely fast bulk output stream that can only output to a stream.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static bool usesMaskPolicy(uint64_t TSFlags)
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool doesForceTailAgnostic(uint64_t TSFlags)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static bool hasVecPolicyOp(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static bool isMaskAgnostic(unsigned VType)
static bool isValidSEW(unsigned SEW)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static unsigned getSEW(unsigned VType)
bool isFaultFirstLoad(const MachineInstr &MI)
static constexpr int64_t VLMaxSentinel
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool operator!=(uint64_t V1, const APInt &V2)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Status intersect(const Status &S) const