34#define DEBUG_TYPE "riscv-insert-vsetvli"
35#define RISCV_INSERT_VSETVLI_NAME "RISCV Insert VSETVLI pass"
39 cl::desc(
"Disable looking through phis when inserting vsetvlis."));
43 cl::desc(
"Enable strict assertion checking for the dataflow algorithm"));
56 return MI.getOpcode() == RISCV::PseudoVSETVLI ||
57 MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
58 MI.getOpcode() == RISCV::PseudoVSETIVLI;
64 if (
MI.getOpcode() != RISCV::PseudoVSETVLIX0)
66 assert(RISCV::X0 ==
MI.getOperand(1).getReg());
67 return RISCV::X0 ==
MI.getOperand(0).getReg();
72 RISCVVPseudosTable::getPseudoInfo(RVVPseudoOpcode);
79 switch (getRVVMCOpcode(
MI.getOpcode())) {
90static std::optional<unsigned> getEEWForLoadStore(
const MachineInstr &
MI) {
91 switch (getRVVMCOpcode(
MI.getOpcode())) {
100 case RISCV::VLSE16_V:
102 case RISCV::VSSE16_V:
105 case RISCV::VLSE32_V:
107 case RISCV::VSSE32_V:
110 case RISCV::VLSE64_V:
112 case RISCV::VSSE64_V:
122 const unsigned Log2SEW =
MI.getOperand(getSEWOpNum(
MI)).getImm();
128struct DemandedFields {
133 bool VLZeroness =
false;
136 bool SEWLMULRatio =
false;
137 bool TailPolicy =
false;
138 bool MaskPolicy =
false;
141 bool usedVTYPE()
const {
142 return SEW ||
LMUL || SEWLMULRatio || TailPolicy || MaskPolicy;
147 return VLAny || VLZeroness;
165#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
175 OS <<
"VLAny=" << VLAny <<
", ";
176 OS <<
"VLZeroness=" << VLZeroness <<
", ";
177 OS <<
"SEW=" <<
SEW <<
", ";
178 OS <<
"LMUL=" <<
LMUL <<
", ";
179 OS <<
"SEWLMULRatio=" << SEWLMULRatio <<
", ";
180 OS <<
"TailPolicy=" << TailPolicy <<
", ";
181 OS <<
"MaskPolicy=" << MaskPolicy;
187#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
199static bool areCompatibleVTYPEs(
uint64_t VType1,
201 const DemandedFields &Used) {
210 if (
Used.SEWLMULRatio) {
215 if (Ratio1 != Ratio2)
219 if (
Used.TailPolicy &&
222 if (
Used.MaskPolicy &&
238 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.readsRegister(RISCV::VL))
240 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.readsRegister(RISCV::VTYPE))
251 Res.MaskPolicy =
false;
260 if (getEEWForLoadStore(
MI)) {
267 Res.TailPolicy =
false;
268 Res.MaskPolicy =
false;
275 if (isMaskRegOp(
MI)) {
281 if (isScalarMoveInstr(
MI)) {
283 Res.SEWLMULRatio =
false;
310 uint8_t SEWLMULRatioOnly : 1;
315 SEWLMULRatioOnly(
false) {}
317 static VSETVLIInfo getUnknown() {
324 void setUnknown() { State =
Unknown; }
325 bool isUnknown()
const {
return State ==
Unknown; }
332 void setAVLImm(
unsigned Imm) {
337 bool hasAVLImm()
const {
return State == AVLIsImm; }
338 bool hasAVLReg()
const {
return State == AVLIsReg; }
343 unsigned getAVLImm()
const {
348 unsigned getSEW()
const {
return SEW; }
353 return getAVLImm() > 0;
355 return getAVLReg() == RISCV::X0;
359 bool hasEquallyZeroAVL(
const VSETVLIInfo &
Other)
const {
360 if (hasSameAVL(
Other))
365 bool hasSameAVL(
const VSETVLIInfo &
Other)
const {
366 if (hasAVLReg() &&
Other.hasAVLReg())
367 return getAVLReg() ==
Other.getAVLReg();
369 if (hasAVLImm() &&
Other.hasAVLImm())
370 return getAVLImm() ==
Other.getAVLImm();
377 "Can't set VTYPE for uninitialized or unknown");
385 "Can't set VTYPE for uninitialized or unknown");
394 "Can't encode VTYPE for uninitialized or unknown");
398 bool hasSEWLMULRatioOnly()
const {
return SEWLMULRatioOnly; }
400 bool hasSameVTYPE(
const VSETVLIInfo &
Other)
const {
402 "Can't compare invalid VSETVLIInfos");
404 "Can't compare VTYPE in unknown state");
405 assert(!SEWLMULRatioOnly && !
Other.SEWLMULRatioOnly &&
406 "Can't compare when only LMUL/SEW ratio is valid.");
407 return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) ==
414 "Can't use VTYPE for uninitialized or unknown");
422 bool hasSameVLMAX(
const VSETVLIInfo &
Other)
const {
424 "Can't compare invalid VSETVLIInfos");
426 "Can't compare VTYPE in unknown state");
430 bool hasCompatibleVTYPE(
const DemandedFields &Used,
431 const VSETVLIInfo &Require)
const {
432 return areCompatibleVTYPEs(
encodeVTYPE(), Require.encodeVTYPE(), Used);
438 bool isCompatible(
const DemandedFields &Used,
const VSETVLIInfo &Require)
const {
440 "Can't compare invalid VSETVLIInfos");
441 assert(!Require.SEWLMULRatioOnly &&
442 "Expected a valid VTYPE for instruction!");
444 if (isUnknown() || Require.isUnknown())
448 if (SEWLMULRatioOnly)
453 if (Require.hasAVLReg() && Require.AVLReg == RISCV::NoRegister)
454 if (SEW == Require.SEW)
457 if (
Used.VLAny && !hasSameAVL(Require))
460 if (
Used.VLZeroness && !hasEquallyZeroAVL(Require))
463 return areCompatibleVTYPEs(
encodeVTYPE(), Require.encodeVTYPE(), Used);
469 return !
Other.isValid();
470 if (!
Other.isValid())
475 return Other.isUnknown();
476 if (
Other.isUnknown())
479 if (!hasSameAVL(
Other))
483 if (SEWLMULRatioOnly !=
Other.SEWLMULRatioOnly)
487 if (SEWLMULRatioOnly)
488 return hasSameVLMAX(
Other);
491 return hasSameVTYPE(
Other);
495 return !(*
this ==
Other);
502 if (!
Other.isValid())
510 if (isUnknown() ||
Other.isUnknown())
511 return VSETVLIInfo::getUnknown();
519 if (hasSameAVL(
Other) && hasSameVLMAX(
Other)) {
520 VSETVLIInfo MergeInfo = *
this;
521 MergeInfo.SEWLMULRatioOnly =
true;
526 return VSETVLIInfo::getUnknown();
529#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
541 OS <<
"Uninitialized";
547 OS <<
"AVLImm=" << (
unsigned)AVLImm;
549 <<
"VLMul=" << (
unsigned)VLMul <<
", "
550 <<
"SEW=" << (
unsigned)
SEW <<
", "
551 <<
"TailAgnostic=" << (
bool)TailAgnostic <<
", "
553 <<
"SEWLMULRatioOnly=" << (
bool)SEWLMULRatioOnly <<
"}";
558#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
580 bool InQueue =
false;
589 std::vector<BlockData> BlockInfo;
590 std::queue<const MachineBasicBlock *> WorkList;
608 bool needVSETVLI(
const MachineInstr &
MI,
const VSETVLIInfo &Require,
609 const VSETVLIInfo &CurInfo)
const;
610 bool needVSETVLIPHI(
const VSETVLIInfo &Require,
613 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo);
616 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo);
630char RISCVInsertVSETVLI::ID = 0;
651 "Invalid Policy Value");
689 int64_t Imm = VLOp.
getImm();
702 if (std::optional<unsigned> EEW = getEEWForLoadStore(
MI)) {
703 assert(
SEW == EEW &&
"Initial SEW doesn't match expected EEW");
712 const VSETVLIInfo &Info,
713 const VSETVLIInfo &PrevInfo) {
720 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo) {
724 if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
725 Info.hasSameAVL(PrevInfo) &&
Info.hasSameVLMAX(PrevInfo)) {
734 if (
Info.hasAVLImm()) {
743 if (AVLReg == RISCV::NoRegister) {
746 if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
747 Info.hasSameVLMAX(PrevInfo)) {
764 MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);
770 unsigned Opcode = RISCV::PseudoVSETVLI;
771 if (AVLReg == RISCV::X0) {
772 DestReg =
MRI->createVirtualRegister(&RISCV::GPRRegClass);
773 Opcode = RISCV::PseudoVSETVLIX0;
785 if (
MI.getOpcode() == RISCV::PseudoVSETIVLI) {
786 NewInfo.setAVLImm(
MI.getOperand(1).getImm());
788 assert(
MI.getOpcode() == RISCV::PseudoVSETVLI ||
789 MI.getOpcode() == RISCV::PseudoVSETVLIX0);
791 assert((AVLReg != RISCV::X0 ||
MI.getOperand(0).getReg() != RISCV::X0) &&
792 "Can't handle X0, X0 vsetvli yet");
793 NewInfo.setAVLReg(AVLReg);
795 NewInfo.setVTYPE(
MI.getOperand(2).getImm());
803 const VSETVLIInfo &Require,
804 const VSETVLIInfo &CurInfo)
const {
805 assert(Require == computeInfoForInstr(
MI,
MI.getDesc().TSFlags,
MRI));
807 if (!CurInfo.isValid() || CurInfo.isUnknown() || CurInfo.hasSEWLMULRatioOnly())
810 DemandedFields
Used = getDemanded(
MI);
812 if (isScalarMoveInstr(
MI)) {
819 auto *VRegDef =
MRI->getVRegDef(
MI.getOperand(1).getReg());
820 if (VRegDef && VRegDef->isImplicitDef() &&
821 CurInfo.getSEW() >= Require.getSEW()) {
823 Used.TailPolicy =
false;
827 if (CurInfo.isCompatible(Used, Require))
834 if (Require.hasAVLReg() && Require.getAVLReg().isVirtual() &&
835 CurInfo.hasCompatibleVTYPE(Used, Require)) {
837 if (isVectorConfigInstr(*
DefMI)) {
839 if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
851void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
const MachineInstr &
MI) {
856 const VSETVLIInfo NewInfo = computeInfoForInstr(
MI,
TSFlags,
MRI);
857 if (
Info.isValid() && !needVSETVLI(
MI, NewInfo, Info))
860 const VSETVLIInfo PrevInfo =
Info;
874 if (isScalarMoveInstr(
MI) && PrevInfo.isValid() &&
875 PrevInfo.hasEquallyZeroAVL(Info) &&
876 Info.hasSameVLMAX(PrevInfo)) {
877 if (PrevInfo.hasAVLImm())
878 Info.setAVLImm(PrevInfo.getAVLImm());
880 Info.setAVLReg(PrevInfo.getAVLReg());
888 if (!
Info.hasAVLReg() || !
Info.getAVLReg().isVirtual())
895 if (DefInfo.hasSameVLMAX(Info) &&
896 (DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) {
897 if (DefInfo.hasAVLImm())
898 Info.setAVLImm(DefInfo.getAVLImm());
900 Info.setAVLReg(DefInfo.getAVLReg());
908void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
const MachineInstr &
MI) {
909 if (isVectorConfigInstr(
MI)) {
916 Info.setAVLReg(
MI.getOperand(1).getReg());
922 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.modifiesRegister(RISCV::VL) ||
923 MI.modifiesRegister(RISCV::VTYPE))
924 Info = VSETVLIInfo::getUnknown();
928 bool HadVectorOp =
false;
948 BBInfo.InQueue =
false;
952 VSETVLIInfo InInfo = BBInfo.
Pred;
958 InInfo = InInfo.
intersect(BlockInfo[
P->getNumber()].Exit);
962 if (!InInfo.isValid())
966 if (InInfo == BBInfo.
Pred)
969 BBInfo.
Pred = InInfo;
971 <<
" changed to " << BBInfo.
Pred <<
"\n");
977 computeVLVTYPEChanges(
MBB);
978 VSETVLIInfo TmpStatus = BBInfo.
Change;
982 if (BBInfo.
Exit == TmpStatus)
985 BBInfo.
Exit = TmpStatus;
987 <<
" changed to " << BBInfo.
Exit <<
"\n");
992 if (!BlockInfo[S->getNumber()].InQueue) {
993 BlockInfo[S->getNumber()].InQueue =
true;
1001bool RISCVInsertVSETVLI::needVSETVLIPHI(
const VSETVLIInfo &Require,
1006 if (!Require.hasAVLReg())
1009 Register AVLReg = Require.getAVLReg();
1015 if (!
PHI ||
PHI->getOpcode() != RISCV::PHI ||
PHI->getParent() != &
MBB)
1018 for (
unsigned PHIOp = 1, NumOps =
PHI->getNumOperands(); PHIOp != NumOps;
1025 if (PBBInfo.
Exit.isUnknown() || !PBBInfo.
Exit.hasSameVTYPE(Require))
1036 if (!DefInfo.hasSameAVL(PBBInfo.
Exit) ||
1037 !DefInfo.hasSameVTYPE(PBBInfo.
Exit))
1050 bool PrefixTransparent =
true;
1052 const VSETVLIInfo PrevInfo = CurInfo;
1053 transferBefore(CurInfo,
MI);
1056 if (isVectorConfigInstr(
MI)) {
1058 assert(
MI.getOperand(3).getReg() == RISCV::VL &&
1059 MI.getOperand(4).getReg() == RISCV::VTYPE &&
1060 "Unexpected operands where VL and VTYPE should be");
1061 MI.getOperand(3).setIsDead(
false);
1062 MI.getOperand(4).setIsDead(
false);
1063 PrefixTransparent =
false;
1068 if (PrevInfo != CurInfo) {
1076 if (!PrefixTransparent || needVSETVLIPHI(CurInfo,
MBB))
1077 insertVSETVLI(
MBB,
MI, CurInfo, PrevInfo);
1078 PrefixTransparent =
false;
1085 VLOp.
setReg(RISCV::NoRegister);
1095 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.modifiesRegister(RISCV::VL) ||
1096 MI.modifiesRegister(RISCV::VTYPE))
1097 PrefixTransparent =
false;
1099 transferAfter(CurInfo,
MI);
1105 const VSETVLIInfo &ExitInfo = BlockInfo[
MBB.
getNumber()].Exit;
1106 if (CurInfo.isValid() && ExitInfo.isValid() && !ExitInfo.isUnknown() &&
1107 CurInfo != ExitInfo) {
1119 if (CurInfo !=
Info.Exit) {
1126 "InsertVSETVLI dataflow invariant violated");
1132 if (!
Info.hasAVLImm())
1136 return RISCV::X0 ==
Info.getAVLReg();
1138 unsigned AVL =
Info.getAVLImm();
1140 unsigned AVLInBits = AVL *
SEW;
1147 return ST.getRealMinVLen() / LMul >= AVLInBits;
1148 return ST.getRealMinVLen() * LMul >= AVLInBits;
1164 VSETVLIInfo AvailableInfo;
1166 const VSETVLIInfo &PredInfo = BlockInfo[
P->getNumber()].Exit;
1167 if (PredInfo.isUnknown()) {
1168 if (UnavailablePred)
1170 UnavailablePred =
P;
1171 }
else if (!AvailableInfo.isValid()) {
1172 AvailableInfo = PredInfo;
1173 }
else if (AvailableInfo != PredInfo) {
1180 if (!UnavailablePred || !AvailableInfo.isValid())
1200 VSETVLIInfo CurInfo = AvailableInfo;
1201 int TransitionsRemoved = 0;
1203 const VSETVLIInfo LastInfo = CurInfo;
1204 const VSETVLIInfo LastOldInfo = OldInfo;
1205 transferBefore(CurInfo,
MI);
1206 transferBefore(OldInfo,
MI);
1207 if (CurInfo == LastInfo)
1208 TransitionsRemoved++;
1209 if (LastOldInfo == OldInfo)
1210 TransitionsRemoved--;
1211 transferAfter(CurInfo,
MI);
1212 transferAfter(OldInfo,
MI);
1213 if (CurInfo == OldInfo)
1217 if (CurInfo != OldInfo || TransitionsRemoved <= 0)
1224 auto OldExit = BlockInfo[UnavailablePred->
getNumber()].Exit;
1226 << UnavailablePred->
getName() <<
" with state "
1227 << AvailableInfo <<
"\n");
1228 BlockInfo[UnavailablePred->
getNumber()].Exit = AvailableInfo;
1234 insertVSETVLI(*UnavailablePred, InsertPt,
1236 AvailableInfo, OldExit);
1241 A.VLZeroness |=
B.VLZeroness;
1244 A.SEWLMULRatio |=
B.SEWLMULRatio;
1245 A.TailPolicy |=
B.TailPolicy;
1246 A.MaskPolicy |=
B.MaskPolicy;
1251 return RISCV::X0 == MO.
getReg();
1260 const DemandedFields &Used) {
1264 if (!isVLPreservingConfig(
MI)) {
1269 if (isVLPreservingConfig(PrevMI))
1274 if (Used.VLZeroness &&
1281 if (
MI.getOperand(1).isReg() &&
1282 RISCV::X0 !=
MI.getOperand(1).getReg())
1289 MI.getOperand(1).isReg())
1297 auto VType =
MI.getOperand(2).getImm();
1298 return areCompatibleVTYPEs(PriorVType, VType, Used);
1305 DemandedFields
Used;
1311 if (!isVectorConfigInstr(
MI)) {
1316 Register VRegDef =
MI.getOperand(0).getReg();
1317 if (VRegDef != RISCV::X0 &&
1318 !(VRegDef.
isVirtual() &&
MRI->use_nodbg_empty(VRegDef)))
1322 if (!
Used.usedVL() && !
Used.usedVTYPE()) {
1327 if (!isVLPreservingConfig(*NextMI)) {
1343 for (
auto *
MI : ToDelete)
1344 MI->eraseFromParent();
1351 Register VLOutput =
MI.getOperand(1).getReg();
1352 if (!
MRI->use_nodbg_empty(VLOutput))
1356 MI.getOperand(1).setReg(RISCV::X0);
1364 if (!
ST.hasVInstructions())
1369 TII =
ST.getInstrInfo();
1372 assert(BlockInfo.empty() &&
"Expect empty block infos");
1375 bool HaveVectorOp =
false;
1379 HaveVectorOp |= computeVLVTYPEChanges(
MBB);
1384 <<
" is " << BBInfo.
Exit <<
"\n");
1389 if (!HaveVectorOp) {
1398 WorkList.push(&
MBB);
1401 while (!WorkList.empty()) {
1404 computeIncomingVLVTYPE(
MBB);
1425 doLocalPostpass(
MBB);
1434 if (
MI.getOpcode() == RISCV::PseudoVSETVLI ||
1435 MI.getOpcode() == RISCV::PseudoVSETIVLI) {
1436 Register VRegDef =
MI.getOperand(0).getReg();
1437 if (VRegDef != RISCV::X0 &&
MRI->use_nodbg_empty(VRegDef))
1438 MI.getOperand(0).setReg(RISCV::X0);
1449 return HaveVectorOp;
1454 return new RISCVInsertVSETVLI();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
#define LLVM_ATTRIBUTE_USED
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::optional< std::vector< StOtherPiece > > Other
const HexagonInstrInfo * TII
static ValueLatticeElement intersect(const ValueLatticeElement &A, const ValueLatticeElement &B)
Combine two sets of facts about the same value into a single set of facts.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static bool hasNonZeroAVL(SDValue AVL)
static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI)
static bool isNonZeroAVL(const MachineOperand &MO)
#define RISCV_INSERT_VSETVLI_NAME
uint64_t const MachineRegisterInfo * MRI
static bool canMutatePriorConfig(const MachineInstr &PrevMI, const MachineInstr &MI, const DemandedFields &Used)
assert(RISCVVType::isValidSEW(SEW) &&"Unexpected SEW")
InstrInfo setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic)
static void doUnion(DemandedFields &A, DemandedFields B)
static cl::opt< bool > UseStrictAsserts("riscv-insert-vsetvl-strict-asserts", cl::init(true), cl::Hidden, cl::desc("Enable strict assertion checking for the dataflow algorithm"))
static cl::opt< bool > DisableInsertVSETVLPHIOpt("riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, cl::desc("Disable looking through phis when inserting vsetvlis."))
static bool hasFixedResult(const VSETVLIInfo &Info, const RISCVSubtarget &ST)
Return true if the VL value configured must be equal to the requested one.
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
unsigned succ_size() const
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
reverse_iterator rbegin()
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool isImplicitDef() const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
This class implements an extremely fast bulk output stream that can only output to a stream.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static bool usesMaskPolicy(uint64_t TSFlags)
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool doesForceTailAgnostic(uint64_t TSFlags)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static bool hasVecPolicyOp(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static bool isMaskAgnostic(unsigned VType)
static bool isValidSEW(unsigned SEW)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static unsigned getSEW(unsigned VType)
bool isFaultFirstLoad(const MachineInstr &MI)
static constexpr int64_t VLMaxSentinel
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool operator!=(uint64_t V1, const APInt &V2)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Status intersect(const Status &S) const