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RISCVInsertVSETVLI.cpp
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1 //===- RISCVInsertVSETVLI.cpp - Insert VSETVLI instructions ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a function pass that inserts VSETVLI instructions where
10 // needed and expands the vl outputs of VLEFF/VLSEGFF to PseudoReadVL
11 // instructions.
12 //
13 // This pass consists of 3 phases:
14 //
15 // Phase 1 collects how each basic block affects VL/VTYPE.
16 //
17 // Phase 2 uses the information from phase 1 to do a data flow analysis to
18 // propagate the VL/VTYPE changes through the function. This gives us the
19 // VL/VTYPE at the start of each basic block.
20 //
21 // Phase 3 inserts VSETVLI instructions in each basic block. Information from
22 // phase 2 is used to prevent inserting a VSETVLI before the first vector
23 // instruction in the block if possible.
24 //
25 //===----------------------------------------------------------------------===//
26 
27 #include "RISCV.h"
28 #include "RISCVSubtarget.h"
31 #include <queue>
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "riscv-insert-vsetvli"
35 #define RISCV_INSERT_VSETVLI_NAME "RISCV Insert VSETVLI pass"
36 
38  "riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden,
39  cl::desc("Disable looking through phis when inserting vsetvlis."));
40 
42  "riscv-insert-vsetvl-strict-asserts", cl::init(true), cl::Hidden,
43  cl::desc("Enable strict assertion checking for the dataflow algorithm"));
44 
45 namespace {
46 
47 static unsigned getVLOpNum(const MachineInstr &MI) {
48  return RISCVII::getVLOpNum(MI.getDesc());
49 }
50 
51 static unsigned getSEWOpNum(const MachineInstr &MI) {
52  return RISCVII::getSEWOpNum(MI.getDesc());
53 }
54 
55 static bool isVectorConfigInstr(const MachineInstr &MI) {
56  return MI.getOpcode() == RISCV::PseudoVSETVLI ||
57  MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
58  MI.getOpcode() == RISCV::PseudoVSETIVLI;
59 }
60 
61 /// Return true if this is 'vsetvli x0, x0, vtype' which preserves
62 /// VL and only sets VTYPE.
63 static bool isVLPreservingConfig(const MachineInstr &MI) {
64  if (MI.getOpcode() != RISCV::PseudoVSETVLIX0)
65  return false;
66  assert(RISCV::X0 == MI.getOperand(1).getReg());
67  return RISCV::X0 == MI.getOperand(0).getReg();
68 }
69 
70 static uint16_t getRVVMCOpcode(uint16_t RVVPseudoOpcode) {
72  RISCVVPseudosTable::getPseudoInfo(RVVPseudoOpcode);
73  if (!RVV)
74  return 0;
75  return RVV->BaseInstr;
76 }
77 
78 static bool isScalarMoveInstr(const MachineInstr &MI) {
79  switch (getRVVMCOpcode(MI.getOpcode())) {
80  default:
81  return false;
82  case RISCV::VMV_S_X:
83  case RISCV::VFMV_S_F:
84  return true;
85  }
86 }
87 
88 /// Get the EEW for a load or store instruction. Return None if MI is not
89 /// a load or store which ignores SEW.
90 static Optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
91  switch (getRVVMCOpcode(MI.getOpcode())) {
92  default:
93  return None;
94  case RISCV::VLE8_V:
95  case RISCV::VLSE8_V:
96  case RISCV::VSE8_V:
97  case RISCV::VSSE8_V:
98  return 8;
99  case RISCV::VLE16_V:
100  case RISCV::VLSE16_V:
101  case RISCV::VSE16_V:
102  case RISCV::VSSE16_V:
103  return 16;
104  case RISCV::VLE32_V:
105  case RISCV::VLSE32_V:
106  case RISCV::VSE32_V:
107  case RISCV::VSSE32_V:
108  return 32;
109  case RISCV::VLE64_V:
110  case RISCV::VLSE64_V:
111  case RISCV::VSE64_V:
112  case RISCV::VSSE64_V:
113  return 64;
114  }
115 }
116 
117 /// Return true if this is an operation on mask registers. Note that
118 /// this includes both arithmetic/logical ops and load/store (vlm/vsm).
119 static bool isMaskRegOp(const MachineInstr &MI) {
120  if (!RISCVII::hasSEWOp(MI.getDesc().TSFlags))
121  return false;
122  const unsigned Log2SEW = MI.getOperand(getSEWOpNum(MI)).getImm();
123  // A Log2SEW of 0 is an operation on mask registers only.
124  return Log2SEW == 0;
125 }
126 
127 /// Which subfields of VL or VTYPE have values we need to preserve?
128 struct DemandedFields {
129  bool VL = false;
130  bool SEW = false;
131  bool LMUL = false;
132  bool SEWLMULRatio = false;
133  bool TailPolicy = false;
134  bool MaskPolicy = false;
135 
136  // Return true if any part of VTYPE was used
137  bool usedVTYPE() {
138  return SEW || LMUL || SEWLMULRatio || TailPolicy || MaskPolicy;
139  }
140 
141  // Mark all VTYPE subfields and properties as demanded
142  void demandVTYPE() {
143  SEW = true;
144  LMUL = true;
145  SEWLMULRatio = true;
146  TailPolicy = true;
147  MaskPolicy = true;
148  }
149 };
150 
151 /// Return true if the two values of the VTYPE register provided are
152 /// indistinguishable from the perspective of an instruction (or set of
153 /// instructions) which use only the Used subfields and properties.
154 static bool areCompatibleVTYPEs(uint64_t VType1,
155  uint64_t VType2,
156  const DemandedFields &Used) {
157  if (Used.SEW &&
158  RISCVVType::getSEW(VType1) != RISCVVType::getSEW(VType2))
159  return false;
160 
161  if (Used.LMUL &&
162  RISCVVType::getVLMUL(VType1) != RISCVVType::getVLMUL(VType2))
163  return false;
164 
165  if (Used.SEWLMULRatio) {
166  auto Ratio1 = RISCVVType::getSEWLMULRatio(RISCVVType::getSEW(VType1),
167  RISCVVType::getVLMUL(VType1));
168  auto Ratio2 = RISCVVType::getSEWLMULRatio(RISCVVType::getSEW(VType2),
169  RISCVVType::getVLMUL(VType2));
170  if (Ratio1 != Ratio2)
171  return false;
172  }
173 
174  if (Used.TailPolicy &&
176  return false;
177  if (Used.MaskPolicy &&
179  return false;
180  return true;
181 }
182 
183 /// Return the fields and properties demanded by the provided instruction.
184 static DemandedFields getDemanded(const MachineInstr &MI) {
185  // Warning: This function has to work on both the lowered (i.e. post
186  // emitVSETVLIs) and pre-lowering forms. The main implication of this is
187  // that it can't use the value of a SEW, VL, or Policy operand as they might
188  // be stale after lowering.
189 
190  // Most instructions don't use any of these subfeilds.
191  DemandedFields Res;
192  // Start conservative if registers are used
193  if (MI.isCall() || MI.isInlineAsm() || MI.readsRegister(RISCV::VL))
194  Res.VL = true;
195  if (MI.isCall() || MI.isInlineAsm() || MI.readsRegister(RISCV::VTYPE))
196  Res.demandVTYPE();
197  // Start conservative on the unlowered form too
198  uint64_t TSFlags = MI.getDesc().TSFlags;
199  if (RISCVII::hasSEWOp(TSFlags)) {
200  Res.demandVTYPE();
202  Res.VL = true;
203 
204  // Behavior is independent of mask policy.
206  Res.MaskPolicy = false;
207  }
208 
209  // Loads and stores with implicit EEW do not demand SEW or LMUL directly.
210  // They instead demand the ratio of the two which is used in computing
211  // EMUL, but which allows us the flexibility to change SEW and LMUL
212  // provided we don't change the ratio.
213  // Note: We assume that the instructions initial SEW is the EEW encoded
214  // in the opcode. This is asserted when constructing the VSETVLIInfo.
215  if (getEEWForLoadStore(MI)) {
216  Res.SEW = false;
217  Res.LMUL = false;
218  }
219 
220  // Store instructions don't use the policy fields.
221  if (RISCVII::hasSEWOp(TSFlags) && MI.getNumExplicitDefs() == 0) {
222  Res.TailPolicy = false;
223  Res.MaskPolicy = false;
224  }
225 
226  // If this is a mask reg operation, it only cares about VLMAX.
227  // TODO: Possible extensions to this logic
228  // * Probably ok if available VLMax is larger than demanded
229  // * The policy bits can probably be ignored..
230  if (isMaskRegOp(MI)) {
231  Res.SEW = false;
232  Res.LMUL = false;
233  }
234 
235  return Res;
236 }
237 
238 /// Defines the abstract state with which the forward dataflow models the
239 /// values of the VL and VTYPE registers after insertion.
240 class VSETVLIInfo {
241  union {
242  Register AVLReg;
243  unsigned AVLImm;
244  };
245 
246  enum : uint8_t {
248  AVLIsReg,
249  AVLIsImm,
250  Unknown,
251  } State = Uninitialized;
252 
253  // Fields from VTYPE.
255  uint8_t SEW = 0;
256  uint8_t TailAgnostic : 1;
257  uint8_t MaskAgnostic : 1;
258  uint8_t SEWLMULRatioOnly : 1;
259 
260 public:
261  VSETVLIInfo()
262  : AVLImm(0), TailAgnostic(false), MaskAgnostic(false),
263  SEWLMULRatioOnly(false) {}
264 
265  static VSETVLIInfo getUnknown() {
266  VSETVLIInfo Info;
267  Info.setUnknown();
268  return Info;
269  }
270 
271  bool isValid() const { return State != Uninitialized; }
272  void setUnknown() { State = Unknown; }
273  bool isUnknown() const { return State == Unknown; }
274 
275  void setAVLReg(Register Reg) {
276  AVLReg = Reg;
277  State = AVLIsReg;
278  }
279 
280  void setAVLImm(unsigned Imm) {
281  AVLImm = Imm;
282  State = AVLIsImm;
283  }
284 
285  bool hasAVLImm() const { return State == AVLIsImm; }
286  bool hasAVLReg() const { return State == AVLIsReg; }
287  Register getAVLReg() const {
288  assert(hasAVLReg());
289  return AVLReg;
290  }
291  unsigned getAVLImm() const {
292  assert(hasAVLImm());
293  return AVLImm;
294  }
295 
296  unsigned getSEW() const { return SEW; }
297  RISCVII::VLMUL getVLMUL() const { return VLMul; }
298 
299  bool hasNonZeroAVL() const {
300  if (hasAVLImm())
301  return getAVLImm() > 0;
302  if (hasAVLReg())
303  return getAVLReg() == RISCV::X0;
304  return false;
305  }
306 
307  bool hasSameAVL(const VSETVLIInfo &Other) const {
308  assert(isValid() && Other.isValid() &&
309  "Can't compare invalid VSETVLIInfos");
310  assert(!isUnknown() && !Other.isUnknown() &&
311  "Can't compare AVL in unknown state");
312  if (hasAVLReg() && Other.hasAVLReg())
313  return getAVLReg() == Other.getAVLReg();
314 
315  if (hasAVLImm() && Other.hasAVLImm())
316  return getAVLImm() == Other.getAVLImm();
317 
318  return false;
319  }
320 
321  void setVTYPE(unsigned VType) {
322  assert(isValid() && !isUnknown() &&
323  "Can't set VTYPE for uninitialized or unknown");
324  VLMul = RISCVVType::getVLMUL(VType);
325  SEW = RISCVVType::getSEW(VType);
328  }
329  void setVTYPE(RISCVII::VLMUL L, unsigned S, bool TA, bool MA) {
330  assert(isValid() && !isUnknown() &&
331  "Can't set VTYPE for uninitialized or unknown");
332  VLMul = L;
333  SEW = S;
334  TailAgnostic = TA;
335  MaskAgnostic = MA;
336  }
337 
338  unsigned encodeVTYPE() const {
339  assert(isValid() && !isUnknown() && !SEWLMULRatioOnly &&
340  "Can't encode VTYPE for uninitialized or unknown");
342  }
343 
344  bool hasSEWLMULRatioOnly() const { return SEWLMULRatioOnly; }
345 
346  bool hasSameSEW(const VSETVLIInfo &Other) const {
347  assert(isValid() && Other.isValid() &&
348  "Can't compare invalid VSETVLIInfos");
349  assert(!isUnknown() && !Other.isUnknown() &&
350  "Can't compare VTYPE in unknown state");
351  assert(!SEWLMULRatioOnly && !Other.SEWLMULRatioOnly &&
352  "Can't compare when only LMUL/SEW ratio is valid.");
353  return SEW == Other.SEW;
354  }
355 
356  bool hasSameVTYPE(const VSETVLIInfo &Other) const {
357  assert(isValid() && Other.isValid() &&
358  "Can't compare invalid VSETVLIInfos");
359  assert(!isUnknown() && !Other.isUnknown() &&
360  "Can't compare VTYPE in unknown state");
361  assert(!SEWLMULRatioOnly && !Other.SEWLMULRatioOnly &&
362  "Can't compare when only LMUL/SEW ratio is valid.");
363  return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) ==
364  std::tie(Other.VLMul, Other.SEW, Other.TailAgnostic,
365  Other.MaskAgnostic);
366  }
367 
368  unsigned getSEWLMULRatio() const {
369  assert(isValid() && !isUnknown() &&
370  "Can't use VTYPE for uninitialized or unknown");
372  }
373 
374  // Check if the VTYPE for these two VSETVLIInfos produce the same VLMAX.
375  // Note that having the same VLMAX ensures that both share the same
376  // function from AVL to VL; that is, they must produce the same VL value
377  // for any given AVL value.
378  bool hasSameVLMAX(const VSETVLIInfo &Other) const {
379  assert(isValid() && Other.isValid() &&
380  "Can't compare invalid VSETVLIInfos");
381  assert(!isUnknown() && !Other.isUnknown() &&
382  "Can't compare VTYPE in unknown state");
383  return getSEWLMULRatio() == Other.getSEWLMULRatio();
384  }
385 
386  bool hasSamePolicy(const VSETVLIInfo &Other) const {
387  assert(isValid() && Other.isValid() &&
388  "Can't compare invalid VSETVLIInfos");
389  assert(!isUnknown() && !Other.isUnknown() &&
390  "Can't compare VTYPE in unknown state");
391  return TailAgnostic == Other.TailAgnostic &&
392  MaskAgnostic == Other.MaskAgnostic;
393  }
394 
395  bool hasCompatibleVTYPE(const MachineInstr &MI,
396  const VSETVLIInfo &Require) const {
397  const DemandedFields Used = getDemanded(MI);
398  return areCompatibleVTYPEs(encodeVTYPE(), Require.encodeVTYPE(), Used);
399  }
400 
401  // Determine whether the vector instructions requirements represented by
402  // Require are compatible with the previous vsetvli instruction represented
403  // by this. MI is the instruction whose requirements we're considering.
404  bool isCompatible(const MachineInstr &MI, const VSETVLIInfo &Require) const {
405  assert(isValid() && Require.isValid() &&
406  "Can't compare invalid VSETVLIInfos");
407  assert(!Require.SEWLMULRatioOnly &&
408  "Expected a valid VTYPE for instruction!");
409  // Nothing is compatible with Unknown.
410  if (isUnknown() || Require.isUnknown())
411  return false;
412 
413  // If only our VLMAX ratio is valid, then this isn't compatible.
414  if (SEWLMULRatioOnly)
415  return false;
416 
417  // If the instruction doesn't need an AVLReg and the SEW matches, consider
418  // it compatible.
419  if (Require.hasAVLReg() && Require.AVLReg == RISCV::NoRegister)
420  if (SEW == Require.SEW)
421  return true;
422 
423  return hasSameAVL(Require) && hasCompatibleVTYPE(MI, Require);
424  }
425 
426  bool operator==(const VSETVLIInfo &Other) const {
427  // Uninitialized is only equal to another Uninitialized.
428  if (!isValid())
429  return !Other.isValid();
430  if (!Other.isValid())
431  return !isValid();
432 
433  // Unknown is only equal to another Unknown.
434  if (isUnknown())
435  return Other.isUnknown();
436  if (Other.isUnknown())
437  return isUnknown();
438 
439  if (!hasSameAVL(Other))
440  return false;
441 
442  // If the SEWLMULRatioOnly bits are different, then they aren't equal.
443  if (SEWLMULRatioOnly != Other.SEWLMULRatioOnly)
444  return false;
445 
446  // If only the VLMAX is valid, check that it is the same.
447  if (SEWLMULRatioOnly)
448  return hasSameVLMAX(Other);
449 
450  // If the full VTYPE is valid, check that it is the same.
451  return hasSameVTYPE(Other);
452  }
453 
454  bool operator!=(const VSETVLIInfo &Other) const {
455  return !(*this == Other);
456  }
457 
458  // Calculate the VSETVLIInfo visible to a block assuming this and Other are
459  // both predecessors.
460  VSETVLIInfo intersect(const VSETVLIInfo &Other) const {
461  // If the new value isn't valid, ignore it.
462  if (!Other.isValid())
463  return *this;
464 
465  // If this value isn't valid, this must be the first predecessor, use it.
466  if (!isValid())
467  return Other;
468 
469  // If either is unknown, the result is unknown.
470  if (isUnknown() || Other.isUnknown())
471  return VSETVLIInfo::getUnknown();
472 
473  // If we have an exact, match return this.
474  if (*this == Other)
475  return *this;
476 
477  // Not an exact match, but maybe the AVL and VLMAX are the same. If so,
478  // return an SEW/LMUL ratio only value.
479  if (hasSameAVL(Other) && hasSameVLMAX(Other)) {
480  VSETVLIInfo MergeInfo = *this;
481  MergeInfo.SEWLMULRatioOnly = true;
482  return MergeInfo;
483  }
484 
485  // Otherwise the result is unknown.
486  return VSETVLIInfo::getUnknown();
487  }
488 
489 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
490  /// Support for debugging, callable in GDB: V->dump()
491  LLVM_DUMP_METHOD void dump() const {
492  print(dbgs());
493  dbgs() << "\n";
494  }
495 
496  /// Implement operator<<.
497  /// @{
498  void print(raw_ostream &OS) const {
499  OS << "{";
500  if (!isValid())
501  OS << "Uninitialized";
502  if (isUnknown())
503  OS << "unknown";
504  if (hasAVLReg())
505  OS << "AVLReg=" << (unsigned)AVLReg;
506  if (hasAVLImm())
507  OS << "AVLImm=" << (unsigned)AVLImm;
508  OS << ", "
509  << "VLMul=" << (unsigned)VLMul << ", "
510  << "SEW=" << (unsigned)SEW << ", "
511  << "TailAgnostic=" << (bool)TailAgnostic << ", "
512  << "MaskAgnostic=" << (bool)MaskAgnostic << ", "
513  << "SEWLMULRatioOnly=" << (bool)SEWLMULRatioOnly << "}";
514  }
515 #endif
516 };
517 
518 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
520 inline raw_ostream &operator<<(raw_ostream &OS, const VSETVLIInfo &V) {
521  V.print(OS);
522  return OS;
523 }
524 #endif
525 
526 struct BlockData {
527  // The VSETVLIInfo that represents the net changes to the VL/VTYPE registers
528  // made by this block. Calculated in Phase 1.
529  VSETVLIInfo Change;
530 
531  // The VSETVLIInfo that represents the VL/VTYPE settings on exit from this
532  // block. Calculated in Phase 2.
533  VSETVLIInfo Exit;
534 
535  // The VSETVLIInfo that represents the VL/VTYPE settings from all predecessor
536  // blocks. Calculated in Phase 2, and used by Phase 3.
537  VSETVLIInfo Pred;
538 
539  // Keeps track of whether the block is already in the queue.
540  bool InQueue = false;
541 
542  BlockData() = default;
543 };
544 
545 class RISCVInsertVSETVLI : public MachineFunctionPass {
546  const TargetInstrInfo *TII;
548 
549  std::vector<BlockData> BlockInfo;
550  std::queue<const MachineBasicBlock *> WorkList;
551 
552 public:
553  static char ID;
554 
555  RISCVInsertVSETVLI() : MachineFunctionPass(ID) {
557  }
558  bool runOnMachineFunction(MachineFunction &MF) override;
559 
560  void getAnalysisUsage(AnalysisUsage &AU) const override {
561  AU.setPreservesCFG();
563  }
564 
565  StringRef getPassName() const override { return RISCV_INSERT_VSETVLI_NAME; }
566 
567 private:
568  bool needVSETVLI(const MachineInstr &MI, const VSETVLIInfo &Require,
569  const VSETVLIInfo &CurInfo) const;
570  bool needVSETVLIPHI(const VSETVLIInfo &Require,
571  const MachineBasicBlock &MBB) const;
572  void insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI,
573  const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo);
574  void insertVSETVLI(MachineBasicBlock &MBB,
576  const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo);
577 
578  void transferBefore(VSETVLIInfo &Info, const MachineInstr &MI);
579  void transferAfter(VSETVLIInfo &Info, const MachineInstr &MI);
580  bool computeVLVTYPEChanges(const MachineBasicBlock &MBB);
581  void computeIncomingVLVTYPE(const MachineBasicBlock &MBB);
582  void emitVSETVLIs(MachineBasicBlock &MBB);
583  void doLocalPostpass(MachineBasicBlock &MBB);
584  void doPRE(MachineBasicBlock &MBB);
585  void insertReadVL(MachineBasicBlock &MBB);
586 };
587 
588 } // end anonymous namespace
589 
590 char RISCVInsertVSETVLI::ID = 0;
591 
593  false, false)
594 
595 static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
597  VSETVLIInfo InstrInfo;
598 
600  unsigned UseOpIdx;
601  if (MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
602  // Start with undisturbed.
603  TailAgnostic = false;
604  MaskAgnostic = false;
605 
606  // If there is a policy operand, use it.
608  const MachineOperand &Op = MI.getOperand(MI.getNumExplicitOperands() - 1);
609  uint64_t Policy = Op.getImm();
611  "Invalid Policy Value");
614  }
615 
616  // If the tied operand is an IMPLICIT_DEF we can use TailAgnostic and
617  // MaskAgnostic.
618  const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
619  MachineInstr *UseMI = MRI->getVRegDef(UseMO.getReg());
620  if (UseMI && UseMI->isImplicitDef()) {
621  TailAgnostic = true;
622  MaskAgnostic = true;
623  }
624  // Some pseudo instructions force a tail agnostic policy despite having a
625  // tied def.
627  TailAgnostic = true;
628 
630  MaskAgnostic = true;
631  } else {
632  // If there is no tied operand,, there shouldn't be a policy operand.
633  assert(!RISCVII::hasVecPolicyOp(TSFlags) && "Unexpected policy operand");
634  // No tied operand use agnostic policies.
635  TailAgnostic = true;
636  MaskAgnostic = true;
637  }
638 
640 
641  unsigned Log2SEW = MI.getOperand(getSEWOpNum(MI)).getImm();
642  // A Log2SEW of 0 is an operation on mask registers only.
643  unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
644  assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");
645 
647  const MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
648  if (VLOp.isImm()) {
649  int64_t Imm = VLOp.getImm();
650  // Conver the VLMax sentintel to X0 register.
651  if (Imm == RISCV::VLMaxSentinel)
652  InstrInfo.setAVLReg(RISCV::X0);
653  else
654  InstrInfo.setAVLImm(Imm);
655  } else {
656  InstrInfo.setAVLReg(VLOp.getReg());
657  }
658  } else {
659  InstrInfo.setAVLReg(RISCV::NoRegister);
660  }
661 #ifndef NDEBUG
662  if (Optional<unsigned> EEW = getEEWForLoadStore(MI)) {
663  assert(SEW == EEW && "Initial SEW doesn't match expected EEW");
664  }
665 #endif
667 
668  return InstrInfo;
669 }
670 
671 void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI,
672  const VSETVLIInfo &Info,
673  const VSETVLIInfo &PrevInfo) {
674  DebugLoc DL = MI.getDebugLoc();
675  insertVSETVLI(MBB, MachineBasicBlock::iterator(&MI), DL, Info, PrevInfo);
676 }
677 
678 void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
680  const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo) {
681 
682  // Use X0, X0 form if the AVL is the same and the SEW+LMUL gives the same
683  // VLMAX.
684  if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
685  Info.hasSameAVL(PrevInfo) && Info.hasSameVLMAX(PrevInfo)) {
686  BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
687  .addReg(RISCV::X0, RegState::Define | RegState::Dead)
688  .addReg(RISCV::X0, RegState::Kill)
689  .addImm(Info.encodeVTYPE())
690  .addReg(RISCV::VL, RegState::Implicit);
691  return;
692  }
693 
694  if (Info.hasAVLImm()) {
695  BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETIVLI))
696  .addReg(RISCV::X0, RegState::Define | RegState::Dead)
697  .addImm(Info.getAVLImm())
698  .addImm(Info.encodeVTYPE());
699  return;
700  }
701 
702  Register AVLReg = Info.getAVLReg();
703  if (AVLReg == RISCV::NoRegister) {
704  // We can only use x0, x0 if there's no chance of the vtype change causing
705  // the previous vl to become invalid.
706  if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
707  Info.hasSameVLMAX(PrevInfo)) {
708  BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
709  .addReg(RISCV::X0, RegState::Define | RegState::Dead)
710  .addReg(RISCV::X0, RegState::Kill)
711  .addImm(Info.encodeVTYPE())
712  .addReg(RISCV::VL, RegState::Implicit);
713  return;
714  }
715  // Otherwise use an AVL of 0 to avoid depending on previous vl.
716  BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETIVLI))
717  .addReg(RISCV::X0, RegState::Define | RegState::Dead)
718  .addImm(0)
719  .addImm(Info.encodeVTYPE());
720  return;
721  }
722 
723  if (AVLReg.isVirtual())
724  MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);
725 
726  // Use X0 as the DestReg unless AVLReg is X0. We also need to change the
727  // opcode if the AVLReg is X0 as they have different register classes for
728  // the AVL operand.
729  Register DestReg = RISCV::X0;
730  unsigned Opcode = RISCV::PseudoVSETVLI;
731  if (AVLReg == RISCV::X0) {
732  DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
733  Opcode = RISCV::PseudoVSETVLIX0;
734  }
735  BuildMI(MBB, InsertPt, DL, TII->get(Opcode))
737  .addReg(AVLReg)
738  .addImm(Info.encodeVTYPE());
739 }
740 
741 // Return a VSETVLIInfo representing the changes made by this VSETVLI or
742 // VSETIVLI instruction.
743 static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
744  VSETVLIInfo NewInfo;
745  if (MI.getOpcode() == RISCV::PseudoVSETIVLI) {
746  NewInfo.setAVLImm(MI.getOperand(1).getImm());
747  } else {
748  assert(MI.getOpcode() == RISCV::PseudoVSETVLI ||
749  MI.getOpcode() == RISCV::PseudoVSETVLIX0);
750  Register AVLReg = MI.getOperand(1).getReg();
751  assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) &&
752  "Can't handle X0, X0 vsetvli yet");
753  NewInfo.setAVLReg(AVLReg);
754  }
755  NewInfo.setVTYPE(MI.getOperand(2).getImm());
756 
757  return NewInfo;
758 }
759 
760 /// Return true if a VSETVLI is required to transition from CurInfo to Require
761 /// before MI.
762 bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
763  const VSETVLIInfo &Require,
764  const VSETVLIInfo &CurInfo) const {
765  assert(Require == computeInfoForInstr(MI, MI.getDesc().TSFlags, MRI));
766 
767  if (CurInfo.isCompatible(MI, Require))
768  return false;
769 
770  if (!CurInfo.isValid() || CurInfo.isUnknown() || CurInfo.hasSEWLMULRatioOnly())
771  return true;
772 
773  // For vmv.s.x and vfmv.s.f, there is only two behaviors, VL = 0 and VL > 0.
774  // VL=0 is uninteresting (as it should have been deleted already), so it is
775  // compatible if we can prove both are non-zero. Additionally, if writing
776  // to an implicit_def operand, we don't need to preserve any other bits and
777  // are thus compatible with any larger etype, and can disregard policy bits.
778  if (isScalarMoveInstr(MI) &&
779  CurInfo.hasNonZeroAVL() && Require.hasNonZeroAVL()) {
780  auto *VRegDef = MRI->getVRegDef(MI.getOperand(1).getReg());
781  if (VRegDef && VRegDef->isImplicitDef() &&
782  CurInfo.getSEW() >= Require.getSEW())
783  return false;
784  if (CurInfo.hasSameSEW(Require) && CurInfo.hasSamePolicy(Require))
785  return false;
786  }
787 
788  // We didn't find a compatible value. If our AVL is a virtual register,
789  // it might be defined by a VSET(I)VLI. If it has the same VLMAX we need
790  // and the last VL/VTYPE we observed is the same, we don't need a
791  // VSETVLI here.
792  if (Require.hasAVLReg() && Require.getAVLReg().isVirtual() &&
793  CurInfo.hasCompatibleVTYPE(MI, Require)) {
794  if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
795  if (isVectorConfigInstr(*DefMI)) {
796  VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
797  if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
798  return false;
799  }
800  }
801  }
802 
803  return true;
804 }
805 
806 // Given an incoming state reaching MI, modifies that state so that it is minimally
807 // compatible with MI. The resulting state is guaranteed to be semantically legal
808 // for MI, but may not be the state requested by MI.
809 void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, const MachineInstr &MI) {
810  uint64_t TSFlags = MI.getDesc().TSFlags;
812  return;
813 
814  const VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, MRI);
815  if (Info.isValid() && !needVSETVLI(MI, NewInfo, Info))
816  return;
817 
818  const VSETVLIInfo PrevInfo = Info;
819  Info = NewInfo;
820 
822  return;
823 
824  // For vmv.s.x and vfmv.s.f, there are only two behaviors, VL = 0 and
825  // VL > 0. We can discard the user requested AVL and just use the last
826  // one if we can prove it equally zero. This removes a vsetvli entirely
827  // if the types match or allows use of cheaper avl preserving variant
828  // if VLMAX doesn't change. If VLMAX might change, we couldn't use
829  // the 'vsetvli x0, x0, vtype" variant, so we avoid the transform to
830  // prevent extending live range of an avl register operand.
831  // TODO: We can probably relax this for immediates.
832  if (isScalarMoveInstr(MI) && PrevInfo.isValid() &&
833  PrevInfo.hasNonZeroAVL() && Info.hasNonZeroAVL() &&
834  Info.hasSameVLMAX(PrevInfo)) {
835  if (PrevInfo.hasAVLImm())
836  Info.setAVLImm(PrevInfo.getAVLImm());
837  else
838  Info.setAVLReg(PrevInfo.getAVLReg());
839  return;
840  }
841 
842  // If AVL is defined by a vsetvli with the same VLMAX, we can
843  // replace the AVL operand with the AVL of the defining vsetvli.
844  // We avoid general register AVLs to avoid extending live ranges
845  // without being sure we can kill the original source reg entirely.
846  if (!Info.hasAVLReg() || !Info.getAVLReg().isVirtual())
847  return;
848  MachineInstr *DefMI = MRI->getVRegDef(Info.getAVLReg());
849  if (!DefMI || !isVectorConfigInstr(*DefMI))
850  return;
851 
852  VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
853  if (DefInfo.hasSameVLMAX(Info) &&
854  (DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) {
855  if (DefInfo.hasAVLImm())
856  Info.setAVLImm(DefInfo.getAVLImm());
857  else
858  Info.setAVLReg(DefInfo.getAVLReg());
859  return;
860  }
861 }
862 
863 // Given a state with which we evaluated MI (see transferBefore above for why
864 // this might be different that the state MI requested), modify the state to
865 // reflect the changes MI might make.
866 void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info, const MachineInstr &MI) {
867  if (isVectorConfigInstr(MI)) {
869  return;
870  }
871 
873  // Update AVL to vl-output of the fault first load.
874  Info.setAVLReg(MI.getOperand(1).getReg());
875  return;
876  }
877 
878  // If this is something that updates VL/VTYPE that we don't know about, set
879  // the state to unknown.
880  if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
881  MI.modifiesRegister(RISCV::VTYPE))
882  Info = VSETVLIInfo::getUnknown();
883 }
884 
885 bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB) {
886  bool HadVectorOp = false;
887 
888  BlockData &BBInfo = BlockInfo[MBB.getNumber()];
889  BBInfo.Change = BBInfo.Pred;
890  for (const MachineInstr &MI : MBB) {
891  transferBefore(BBInfo.Change, MI);
892 
893  if (isVectorConfigInstr(MI) || RISCVII::hasSEWOp(MI.getDesc().TSFlags))
894  HadVectorOp = true;
895 
896  transferAfter(BBInfo.Change, MI);
897  }
898 
899  return HadVectorOp;
900 }
901 
902 void RISCVInsertVSETVLI::computeIncomingVLVTYPE(const MachineBasicBlock &MBB) {
903 
904  BlockData &BBInfo = BlockInfo[MBB.getNumber()];
905 
906  BBInfo.InQueue = false;
907 
908  // Start with the previous entry so that we keep the most conservative state
909  // we have ever found.
910  VSETVLIInfo InInfo = BBInfo.Pred;
911  if (MBB.pred_empty()) {
912  // There are no predecessors, so use the default starting status.
913  InInfo.setUnknown();
914  } else {
916  InInfo = InInfo.intersect(BlockInfo[P->getNumber()].Exit);
917  }
918 
919  // If we don't have any valid predecessor value, wait until we do.
920  if (!InInfo.isValid())
921  return;
922 
923  // If no change, no need to rerun block
924  if (InInfo == BBInfo.Pred)
925  return;
926 
927  BBInfo.Pred = InInfo;
928  LLVM_DEBUG(dbgs() << "Entry state of " << printMBBReference(MBB)
929  << " changed to " << BBInfo.Pred << "\n");
930 
931  // Note: It's tempting to cache the state changes here, but due to the
932  // compatibility checks performed a blocks output state can change based on
933  // the input state. To cache, we'd have to add logic for finding
934  // never-compatible state changes.
935  computeVLVTYPEChanges(MBB);
936  VSETVLIInfo TmpStatus = BBInfo.Change;
937 
938  // If the new exit value matches the old exit value, we don't need to revisit
939  // any blocks.
940  if (BBInfo.Exit == TmpStatus)
941  return;
942 
943  BBInfo.Exit = TmpStatus;
944  LLVM_DEBUG(dbgs() << "Exit state of " << printMBBReference(MBB)
945  << " changed to " << BBInfo.Exit << "\n");
946 
947  // Add the successors to the work list so we can propagate the changed exit
948  // status.
949  for (MachineBasicBlock *S : MBB.successors())
950  if (!BlockInfo[S->getNumber()].InQueue) {
951  BlockInfo[S->getNumber()].InQueue = true;
952  WorkList.push(S);
953  }
954 }
955 
956 // If we weren't able to prove a vsetvli was directly unneeded, it might still
957 // be unneeded if the AVL is a phi node where all incoming values are VL
958 // outputs from the last VSETVLI in their respective basic blocks.
959 bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
960  const MachineBasicBlock &MBB) const {
962  return true;
963 
964  if (!Require.hasAVLReg())
965  return true;
966 
967  Register AVLReg = Require.getAVLReg();
968  if (!AVLReg.isVirtual())
969  return true;
970 
971  // We need the AVL to be produce by a PHI node in this basic block.
972  MachineInstr *PHI = MRI->getVRegDef(AVLReg);
973  if (!PHI || PHI->getOpcode() != RISCV::PHI || PHI->getParent() != &MBB)
974  return true;
975 
976  for (unsigned PHIOp = 1, NumOps = PHI->getNumOperands(); PHIOp != NumOps;
977  PHIOp += 2) {
978  Register InReg = PHI->getOperand(PHIOp).getReg();
979  MachineBasicBlock *PBB = PHI->getOperand(PHIOp + 1).getMBB();
980  const BlockData &PBBInfo = BlockInfo[PBB->getNumber()];
981  // If the exit from the predecessor has the VTYPE we are looking for
982  // we might be able to avoid a VSETVLI.
983  if (PBBInfo.Exit.isUnknown() || !PBBInfo.Exit.hasSameVTYPE(Require))
984  return true;
985 
986  // We need the PHI input to the be the output of a VSET(I)VLI.
987  MachineInstr *DefMI = MRI->getVRegDef(InReg);
988  if (!DefMI || !isVectorConfigInstr(*DefMI))
989  return true;
990 
991  // We found a VSET(I)VLI make sure it matches the output of the
992  // predecessor block.
993  VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
994  if (!DefInfo.hasSameAVL(PBBInfo.Exit) ||
995  !DefInfo.hasSameVTYPE(PBBInfo.Exit))
996  return true;
997  }
998 
999  // If all the incoming values to the PHI checked out, we don't need
1000  // to insert a VSETVLI.
1001  return false;
1002 }
1003 
1004 void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
1005  VSETVLIInfo CurInfo = BlockInfo[MBB.getNumber()].Pred;
1006  // Track whether the prefix of the block we've scanned is transparent
1007  // (meaning has not yet changed the abstract state).
1008  bool PrefixTransparent = true;
1009  for (MachineInstr &MI : MBB) {
1010  const VSETVLIInfo PrevInfo = CurInfo;
1011  transferBefore(CurInfo, MI);
1012 
1013  // If this is an explicit VSETVLI or VSETIVLI, update our state.
1014  if (isVectorConfigInstr(MI)) {
1015  // Conservatively, mark the VL and VTYPE as live.
1016  assert(MI.getOperand(3).getReg() == RISCV::VL &&
1017  MI.getOperand(4).getReg() == RISCV::VTYPE &&
1018  "Unexpected operands where VL and VTYPE should be");
1019  MI.getOperand(3).setIsDead(false);
1020  MI.getOperand(4).setIsDead(false);
1021  PrefixTransparent = false;
1022  }
1023 
1024  uint64_t TSFlags = MI.getDesc().TSFlags;
1025  if (RISCVII::hasSEWOp(TSFlags)) {
1026  if (PrevInfo != CurInfo) {
1027  // If this is the first implicit state change, and the state change
1028  // requested can be proven to produce the same register contents, we
1029  // can skip emitting the actual state change and continue as if we
1030  // had since we know the GPR result of the implicit state change
1031  // wouldn't be used and VL/VTYPE registers are correct. Note that
1032  // we *do* need to model the state as if it changed as while the
1033  // register contents are unchanged, the abstract model can change.
1034  if (!PrefixTransparent || needVSETVLIPHI(CurInfo, MBB))
1035  insertVSETVLI(MBB, MI, CurInfo, PrevInfo);
1036  PrefixTransparent = false;
1037  }
1038 
1039  if (RISCVII::hasVLOp(TSFlags)) {
1040  MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
1041  if (VLOp.isReg()) {
1042  // Erase the AVL operand from the instruction.
1043  VLOp.setReg(RISCV::NoRegister);
1044  VLOp.setIsKill(false);
1045  }
1046  MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false,
1047  /*isImp*/ true));
1048  }
1049  MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ false,
1050  /*isImp*/ true));
1051  }
1052 
1053  if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
1054  MI.modifiesRegister(RISCV::VTYPE))
1055  PrefixTransparent = false;
1056 
1057  transferAfter(CurInfo, MI);
1058  }
1059 
1060  // If we reach the end of the block and our current info doesn't match the
1061  // expected info, insert a vsetvli to correct.
1062  if (!UseStrictAsserts) {
1063  const VSETVLIInfo &ExitInfo = BlockInfo[MBB.getNumber()].Exit;
1064  if (CurInfo.isValid() && ExitInfo.isValid() && !ExitInfo.isUnknown() &&
1065  CurInfo != ExitInfo) {
1066  // Note there's an implicit assumption here that terminators never use
1067  // or modify VL or VTYPE. Also, fallthrough will return end().
1068  auto InsertPt = MBB.getFirstInstrTerminator();
1069  insertVSETVLI(MBB, InsertPt, MBB.findDebugLoc(InsertPt), ExitInfo,
1070  CurInfo);
1071  CurInfo = ExitInfo;
1072  }
1073  }
1074 
1075  if (UseStrictAsserts && CurInfo.isValid()) {
1076  const auto &Info = BlockInfo[MBB.getNumber()];
1077  if (CurInfo != Info.Exit) {
1078  LLVM_DEBUG(dbgs() << "in block " << printMBBReference(MBB) << "\n");
1079  LLVM_DEBUG(dbgs() << " begin state: " << Info.Pred << "\n");
1080  LLVM_DEBUG(dbgs() << " expected end state: " << Info.Exit << "\n");
1081  LLVM_DEBUG(dbgs() << " actual end state: " << CurInfo << "\n");
1082  }
1083  assert(CurInfo == Info.Exit &&
1084  "InsertVSETVLI dataflow invariant violated");
1085  }
1086 }
1087 
1088 /// Return true if the VL value configured must be equal to the requested one.
1089 static bool hasFixedResult(const VSETVLIInfo &Info, const RISCVSubtarget &ST) {
1090  if (!Info.hasAVLImm())
1091  // VLMAX is always the same value.
1092  // TODO: Could extend to other registers by looking at the associated vreg
1093  // def placement.
1094  return RISCV::X0 == Info.getAVLReg();
1095 
1096  unsigned AVL = Info.getAVLImm();
1097  unsigned SEW = Info.getSEW();
1098  unsigned AVLInBits = AVL * SEW;
1099 
1100  unsigned LMul;
1101  bool Fractional;
1102  std::tie(LMul, Fractional) = RISCVVType::decodeVLMUL(Info.getVLMUL());
1103 
1104  if (Fractional)
1105  return ST.getRealMinVLen() / LMul >= AVLInBits;
1106  return ST.getRealMinVLen() * LMul >= AVLInBits;
1107 }
1108 
1109 /// Perform simple partial redundancy elimination of the VSETVLI instructions
1110 /// we're about to insert by looking for cases where we can PRE from the
1111 /// beginning of one block to the end of one of its predecessors. Specifically,
1112 /// this is geared to catch the common case of a fixed length vsetvl in a single
1113 /// block loop when it could execute once in the preheader instead.
1114 void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
1115  const MachineFunction &MF = *MBB.getParent();
1117 
1118  if (!BlockInfo[MBB.getNumber()].Pred.isUnknown())
1119  return;
1120 
1121  MachineBasicBlock *UnavailablePred = nullptr;
1122  VSETVLIInfo AvailableInfo;
1123  for (MachineBasicBlock *P : MBB.predecessors()) {
1124  const VSETVLIInfo &PredInfo = BlockInfo[P->getNumber()].Exit;
1125  if (PredInfo.isUnknown()) {
1126  if (UnavailablePred)
1127  return;
1128  UnavailablePred = P;
1129  } else if (!AvailableInfo.isValid()) {
1130  AvailableInfo = PredInfo;
1131  } else if (AvailableInfo != PredInfo) {
1132  return;
1133  }
1134  }
1135 
1136  // Unreachable, single pred, or full redundancy. Note that FRE is handled by
1137  // phase 3.
1138  if (!UnavailablePred || !AvailableInfo.isValid())
1139  return;
1140 
1141  // Critical edge - TODO: consider splitting?
1142  if (UnavailablePred->succ_size() != 1)
1143  return;
1144 
1145  // If VL can be less than AVL, then we can't reduce the frequency of exec.
1146  if (!hasFixedResult(AvailableInfo, ST))
1147  return;
1148 
1149  // Does it actually let us remove an implicit transition in MBB?
1150  bool Found = false;
1151  for (auto &MI : MBB) {
1152  if (isVectorConfigInstr(MI))
1153  return;
1154 
1155  const uint64_t TSFlags = MI.getDesc().TSFlags;
1156  if (RISCVII::hasSEWOp(TSFlags)) {
1157  if (AvailableInfo != computeInfoForInstr(MI, TSFlags, MRI))
1158  return;
1159  Found = true;
1160  break;
1161  }
1162  }
1163  if (!Found)
1164  return;
1165 
1166  // Finally, update both data flow state and insert the actual vsetvli.
1167  // Doing both keeps the code in sync with the dataflow results, which
1168  // is critical for correctness of phase 3.
1169  auto OldInfo = BlockInfo[UnavailablePred->getNumber()].Exit;
1170  LLVM_DEBUG(dbgs() << "PRE VSETVLI from " << MBB.getName() << " to "
1171  << UnavailablePred->getName() << " with state "
1172  << AvailableInfo << "\n");
1173  BlockInfo[UnavailablePred->getNumber()].Exit = AvailableInfo;
1174  BlockInfo[MBB.getNumber()].Pred = AvailableInfo;
1175 
1176  // Note there's an implicit assumption here that terminators never use
1177  // or modify VL or VTYPE. Also, fallthrough will return end().
1178  auto InsertPt = UnavailablePred->getFirstInstrTerminator();
1179  insertVSETVLI(*UnavailablePred, InsertPt,
1180  UnavailablePred->findDebugLoc(InsertPt),
1181  AvailableInfo, OldInfo);
1182 }
1183 
1184 static void doUnion(DemandedFields &A, DemandedFields B) {
1185  A.VL |= B.VL;
1186  A.SEW |= B.SEW;
1187  A.LMUL |= B.LMUL;
1188  A.SEWLMULRatio |= B.SEWLMULRatio;
1189  A.TailPolicy |= B.TailPolicy;
1190  A.MaskPolicy |= B.MaskPolicy;
1191 }
1192 
1193 // Return true if we can mutate PrevMI's VTYPE to match MI's
1194 // without changing any the fields which have been used.
1195 // TODO: Restructure code to allow code reuse between this and isCompatible
1196 // above.
1197 static bool canMutatePriorConfig(const MachineInstr &PrevMI,
1198  const MachineInstr &MI,
1199  const DemandedFields &Used) {
1200  // TODO: Extend this to handle cases where VL does change, but VL
1201  // has not been used. (e.g. over a vmv.x.s)
1202  if (!isVLPreservingConfig(MI))
1203  // Note: `vsetvli x0, x0, vtype' is the canonical instruction
1204  // for this case. If you find yourself wanting to add other forms
1205  // to this "unused VTYPE" case, we're probably missing a
1206  // canonicalization earlier.
1207  return false;
1208 
1209  if (!PrevMI.getOperand(2).isImm() || !MI.getOperand(2).isImm())
1210  return false;
1211 
1212  auto PriorVType = PrevMI.getOperand(2).getImm();
1213  auto VType = MI.getOperand(2).getImm();
1214  return areCompatibleVTYPEs(PriorVType, VType, Used);
1215 }
1216 
1217 void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) {
1218  MachineInstr *PrevMI = nullptr;
1219  DemandedFields Used;
1220  SmallVector<MachineInstr*> ToDelete;
1221  for (MachineInstr &MI : MBB) {
1222  // Note: Must be *before* vsetvli handling to account for config cases
1223  // which only change some subfields.
1224  doUnion(Used, getDemanded(MI));
1225 
1226  if (!isVectorConfigInstr(MI))
1227  continue;
1228 
1229  if (PrevMI) {
1230  if (!Used.VL && !Used.usedVTYPE()) {
1231  ToDelete.push_back(PrevMI);
1232  // fallthrough
1233  } else if (canMutatePriorConfig(*PrevMI, MI, Used)) {
1234  PrevMI->getOperand(2).setImm(MI.getOperand(2).getImm());
1235  ToDelete.push_back(&MI);
1236  // Leave PrevMI unchanged
1237  continue;
1238  }
1239  }
1240  PrevMI = &MI;
1241  Used = getDemanded(MI);
1242  Register VRegDef = MI.getOperand(0).getReg();
1243  if (VRegDef != RISCV::X0 &&
1244  !(VRegDef.isVirtual() && MRI->use_nodbg_empty(VRegDef)))
1245  Used.VL = true;
1246  }
1247 
1248  for (auto *MI : ToDelete)
1249  MI->eraseFromParent();
1250 }
1251 
1252 void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
1253  for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
1254  MachineInstr &MI = *I++;
1255  if (RISCV::isFaultFirstLoad(MI)) {
1256  Register VLOutput = MI.getOperand(1).getReg();
1257  if (!MRI->use_nodbg_empty(VLOutput))
1258  BuildMI(MBB, I, MI.getDebugLoc(), TII->get(RISCV::PseudoReadVL),
1259  VLOutput);
1260  // We don't use the vl output of the VLEFF/VLSEGFF anymore.
1261  MI.getOperand(1).setReg(RISCV::X0);
1262  }
1263  }
1264 }
1265 
1266 bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
1267  // Skip if the vector extension is not enabled.
1269  if (!ST.hasVInstructions())
1270  return false;
1271 
1272  LLVM_DEBUG(dbgs() << "Entering InsertVSETVLI for " << MF.getName() << "\n");
1273 
1274  TII = ST.getInstrInfo();
1275  MRI = &MF.getRegInfo();
1276 
1277  assert(BlockInfo.empty() && "Expect empty block infos");
1278  BlockInfo.resize(MF.getNumBlockIDs());
1279 
1280  bool HaveVectorOp = false;
1281 
1282  // Phase 1 - determine how VL/VTYPE are affected by the each block.
1283  for (const MachineBasicBlock &MBB : MF) {
1284  HaveVectorOp |= computeVLVTYPEChanges(MBB);
1285  // Initial exit state is whatever change we found in the block.
1286  BlockData &BBInfo = BlockInfo[MBB.getNumber()];
1287  BBInfo.Exit = BBInfo.Change;
1288  LLVM_DEBUG(dbgs() << "Initial exit state of " << printMBBReference(MBB)
1289  << " is " << BBInfo.Exit << "\n");
1290 
1291  }
1292 
1293  // If we didn't find any instructions that need VSETVLI, we're done.
1294  if (!HaveVectorOp) {
1295  BlockInfo.clear();
1296  return false;
1297  }
1298 
1299  // Phase 2 - determine the exit VL/VTYPE from each block. We add all
1300  // blocks to the list here, but will also add any that need to be revisited
1301  // during Phase 2 processing.
1302  for (const MachineBasicBlock &MBB : MF) {
1303  WorkList.push(&MBB);
1304  BlockInfo[MBB.getNumber()].InQueue = true;
1305  }
1306  while (!WorkList.empty()) {
1307  const MachineBasicBlock &MBB = *WorkList.front();
1308  WorkList.pop();
1309  computeIncomingVLVTYPE(MBB);
1310  }
1311 
1312  // Perform partial redundancy elimination of vsetvli transitions.
1313  for (MachineBasicBlock &MBB : MF)
1314  doPRE(MBB);
1315 
1316  // Phase 3 - add any vsetvli instructions needed in the block. Use the
1317  // Phase 2 information to avoid adding vsetvlis before the first vector
1318  // instruction in the block if the VL/VTYPE is satisfied by its
1319  // predecessors.
1320  for (MachineBasicBlock &MBB : MF)
1321  emitVSETVLIs(MBB);
1322 
1323  // Now that all vsetvlis are explicit, go through and do block local
1324  // DSE and peephole based demanded fields based transforms. Note that
1325  // this *must* be done outside the main dataflow so long as we allow
1326  // any cross block analysis within the dataflow. We can't have both
1327  // demanded fields based mutation and non-local analysis in the
1328  // dataflow at the same time without introducing inconsistencies.
1329  for (MachineBasicBlock &MBB : MF)
1330  doLocalPostpass(MBB);
1331 
1332  // Once we're fully done rewriting all the instructions, do a final pass
1333  // through to check for VSETVLIs which write to an unused destination.
1334  // For the non X0, X0 variant, we can replace the destination register
1335  // with X0 to reduce register pressure. This is really a generic
1336  // optimization which can be applied to any dead def (TODO: generalize).
1337  for (MachineBasicBlock &MBB : MF) {
1338  for (MachineInstr &MI : MBB) {
1339  if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
1340  MI.getOpcode() == RISCV::PseudoVSETIVLI) {
1341  Register VRegDef = MI.getOperand(0).getReg();
1342  if (VRegDef != RISCV::X0 && MRI->use_nodbg_empty(VRegDef))
1343  MI.getOperand(0).setReg(RISCV::X0);
1344  }
1345  }
1346  }
1347 
1348  // Insert PseudoReadVL after VLEFF/VLSEGFF and replace it with the vl output
1349  // of VLEFF/VLSEGFF.
1350  for (MachineBasicBlock &MBB : MF)
1351  insertReadVL(MBB);
1352 
1353  BlockInfo.clear();
1354  return HaveVectorOp;
1355 }
1356 
1357 /// Returns an instance of the Insert VSETVLI pass.
1359  return new RISCVInsertVSETVLI();
1360 }
llvm::RISCVII::LMUL_1
@ LMUL_1
Definition: RISCVBaseInfo.h:109
intersect
static ValueLatticeElement intersect(const ValueLatticeElement &A, const ValueLatticeElement &B)
Combine two sets of facts about the same value into a single set of facts.
Definition: LazyValueInfo.cpp:96
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:381
LLVM_ATTRIBUTE_USED
#define LLVM_ATTRIBUTE_USED
Definition: Compiler.h:139
RISCV_INSERT_VSETVLI_NAME
#define RISCV_INSERT_VSETVLI_NAME
Definition: RISCVInsertVSETVLI.cpp:35
llvm::RISCVII::getSEWOpNum
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
Definition: RISCVBaseInfo.h:188
llvm::RISCVII::MASK_AGNOSTIC
@ MASK_AGNOSTIC
Definition: RISCVBaseInfo.h:121
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:492
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MachineInstr::isImplicitDef
bool isImplicitDef() const
Definition: MachineInstr.h:1305
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:107
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::AArch64PACKey::ID
ID
Definition: AArch64BaseInfo.h:818
llvm::RISCVII::usesMaskPolicy
static bool usesMaskPolicy(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:167
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
getInfoForVSETVLI
static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI)
Definition: RISCVInsertVSETVLI.cpp:743
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:509
llvm::SmallVector< MachineInstr * >
llvm::createRISCVInsertVSETVLIPass
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
Definition: RISCVInsertVSETVLI.cpp:1358
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:117
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::MachineFunction::getNumBlockIDs
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
Definition: MachineFunction.h:799
llvm::RISCVVType::isValidSEW
static bool isValidSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:411
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:664
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1388
llvm::RISCVII::hasSEWOp
static bool hasSEWOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:151
llvm::RISCVVType::isTailAgnostic
static bool isTailAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:452
llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::Used
@ Used
BlockData::BlockData
BlockData()
Definition: SIModeRegister.cpp:105
setVTYPE
InstrInfo setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic)
llvm::operator!=
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:2012
llvm::Optional< unsigned >
llvm::RISCVVPseudosTable::PseudoInfo
Definition: RISCVInstrInfo.h:237
canMutatePriorConfig
static bool canMutatePriorConfig(const MachineInstr &PrevMI, const MachineInstr &MI, const DemandedFields &Used)
Definition: RISCVInsertVSETVLI.cpp:1197
llvm::dump
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
Definition: SparseBitVector.h:877
llvm::RISCV::VLMaxSentinel
static constexpr int64_t VLMaxSentinel
Definition: RISCVInstrInfo.h:232
Log2SEW
unsigned Log2SEW
Definition: RISCVInsertVSETVLI.cpp:641
llvm::RISCVII::hasVecPolicyOp
static bool hasVecPolicyOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:159
llvm::RISCVVType::getSEW
static unsigned getSEW(unsigned VType)
Definition: RISCVBaseInfo.h:447
UseOpIdx
unsigned UseOpIdx
Definition: RISCVInsertVSETVLI.cpp:600
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:167
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::RISCV::isFaultFirstLoad
bool isFaultFirstLoad(const MachineInstr &MI)
Definition: RISCVInstrInfo.cpp:2449
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::RISCVVPseudosTable::PseudoInfo::BaseInstr
uint16_t BaseInstr
Definition: RISCVInstrInfo.h:239
llvm::MachineBasicBlock::getFirstInstrTerminator
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
Definition: MachineBasicBlock.cpp:248
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
InstrInfo
return InstrInfo
Definition: RISCVInsertVSETVLI.cpp:668
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
MaskAgnostic
bool MaskAgnostic
Definition: RISCVInsertVSETVLI.cpp:599
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
DisableInsertVSETVLPHIOpt
static cl::opt< bool > DisableInsertVSETVLPHIOpt("riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, cl::desc("Disable looking through phis when inserting vsetvlis."))
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::RISCVII::hasVLOp
static bool hasVLOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:155
INITIALIZE_PASS
INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME, false, false) static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:291
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
TSFlags
uint64_t TSFlags
Definition: RISCVInsertVSETVLI.cpp:595
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::cl::opt< bool >
llvm::RISCVVType::decodeVLMUL
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
Definition: RISCVBaseInfo.cpp:147
doUnion
static void doUnion(DemandedFields &A, DemandedFields B)
Definition: RISCVInsertVSETVLI.cpp:1184
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::pdb::Unknown
@ Unknown
Definition: PDBTypes.h:396
LiveIntervals.h
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::RISCVII::getVLOpNum
static unsigned getVLOpNum(const MCInstrDesc &Desc)
Definition: RISCVBaseInfo.h:177
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
MachineFunctionPass.h
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::operator==
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:2010
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineBasicBlock::predecessors
iterator_range< pred_iterator > predecessors()
Definition: MachineBasicBlock.h:386
RISCV.h
llvm::MachineBasicBlock::pred_empty
bool pred_empty() const
Definition: MachineBasicBlock.h:368
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::print
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
Definition: GCNRegPressure.cpp:138
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1115
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:392
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:265
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
assert
assert(RISCVVType::isValidSEW(SEW) &&"Unexpected SEW")
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
TailAgnostic
bool TailAgnostic
Definition: RISCVInsertVSETVLI.cpp:599
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVII::doesForceTailAgnostic
static bool doesForceTailAgnostic(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:143
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::RISCVVType::getVLMUL
static RISCVII::VLMUL getVLMUL(unsigned VType)
Definition: RISCVBaseInfo.h:423
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
uint16_t
UseStrictAsserts
static cl::opt< bool > UseStrictAsserts("riscv-insert-vsetvl-strict-asserts", cl::init(true), cl::Hidden, cl::desc("Enable strict assertion checking for the dataflow algorithm"))
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::RISCVVType::isMaskAgnostic
static bool isMaskAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:454
llvm::RISCVVType::encodeVTYPE
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
Definition: RISCVBaseInfo.cpp:133
llvm::RISCVII::getLMul
static VLMUL getLMul(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:135
llvm::AllocFnKind::Uninitialized
@ Uninitialized
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:284
llvm::XCoreISD::LMUL
@ LMUL
Definition: XCoreISelLowering.h:59
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
VLMul
RISCVII::VLMUL VLMul
Definition: RISCVInsertVSETVLI.cpp:639
MRI
uint64_t const MachineRegisterInfo * MRI
Definition: RISCVInsertVSETVLI.cpp:596
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
RISCVSubtarget.h
llvm::initializeRISCVInsertVSETVLIPass
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
llvm::X86II::TA
@ TA
Definition: X86BaseInfo.h:813
SEW
unsigned SEW
Definition: RISCVInsertVSETVLI.cpp:643
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:184
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:56
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:108
DEBUG_TYPE
#define DEBUG_TYPE
Definition: RISCVInsertVSETVLI.cpp:34
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:108
llvm::RISCVVType::getSEWLMULRatio
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
Definition: RISCVBaseInfo.cpp:188
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
hasFixedResult
static bool hasFixedResult(const VSETVLIInfo &Info, const RISCVSubtarget &ST)
Return true if the VL value configured must be equal to the requested one.
Definition: RISCVInsertVSETVLI.cpp:1089
llvm::RISCVII::TAIL_AGNOSTIC
@ TAIL_AGNOSTIC
Definition: RISCVBaseInfo.h:120
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:413
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineBasicBlock::getName
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
Definition: MachineBasicBlock.cpp:311
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1251