LLVM  17.0.0git
RISCVMatInt.h
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1 //===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H
10 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H
11 
12 #include "llvm/ADT/SmallVector.h"
14 #include <cstdint>
15 
16 namespace llvm {
17 class APInt;
18 
19 namespace RISCVMatInt {
20 
21 enum OpndKind {
22  RegImm, // ADDI/ADDIW/SLLI/SRLI/BSETI/BCLRI
23  Imm, // LUI
24  RegReg, // SH1ADD/SH2ADD/SH3ADD
25  RegX0, // ADD_UW
26 };
27 
28 class Inst {
29  unsigned Opc;
30  int32_t Imm; // The largest value we need to store is 20 bits.
31 
32 public:
33  Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) {
34  assert(I == Imm && "truncated");
35  }
36 
37  unsigned getOpcode() const { return Opc; }
38  int64_t getImm() const { return Imm; }
39 
40  OpndKind getOpndKind() const;
41 };
43 
44 // Helper to generate an instruction sequence that will materialise the given
45 // immediate value into a register. A sequence of instructions represented by a
46 // simple struct is produced rather than directly emitting the instructions in
47 // order to allow this helper to be used from both the MC layer and during
48 // instruction selection.
49 InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures);
50 
51 // Helper to estimate the number of instructions required to materialise the
52 // given immediate value into a register. This estimate does not account for
53 // `Val` possibly fitting into an immediate, and so may over-estimate.
54 //
55 // This will attempt to produce instructions to materialise `Val` as an
56 // `Size`-bit immediate.
57 //
58 // If CompressionCost is true it will use a different cost calculation if RVC is
59 // enabled. This should be used to compare two different sequences to determine
60 // which is more compressible.
61 int getIntMatCost(const APInt &Val, unsigned Size,
62  const FeatureBitset &ActiveFeatures,
63  bool CompressionCost = false);
64 } // namespace RISCVMatInt
65 } // namespace llvm
66 #endif
llvm::RISCVMatInt::getIntMatCost
int getIntMatCost(const APInt &Val, unsigned Size, const FeatureBitset &ActiveFeatures, bool CompressionCost)
Definition: RISCVMatInt.cpp:370
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RISCVMatInt::Inst::getImm
int64_t getImm() const
Definition: RISCVMatInt.h:38
llvm::RISCVMatInt::Inst::Inst
Inst(unsigned Opc, int64_t I)
Definition: RISCVMatInt.h:33
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::RISCVMatInt::generateInstSeq
InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures)
Definition: RISCVMatInt.cpp:175
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:41
SubtargetFeature.h
llvm::RISCVMatInt::Inst::getOpndKind
OpndKind getOpndKind() const
Definition: RISCVMatInt.cpp:388
llvm::RISCVMatInt::Inst::getOpcode
unsigned getOpcode() const
Definition: RISCVMatInt.h:37
I
#define I(x, y, z)
Definition: MD5.cpp:58
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RISCVMatInt::RegX0
@ RegX0
Definition: RISCVMatInt.h:25
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::RISCVMatInt::RegReg
@ RegReg
Definition: RISCVMatInt.h:24
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::RISCVMatInt::OpndKind
OpndKind
Definition: RISCVMatInt.h:21
SmallVector.h
llvm::RISCVMatInt::Inst
Definition: RISCVMatInt.h:28
llvm::RISCVMatInt::RegImm
@ RegImm
Definition: RISCVMatInt.h:22