20 for (
auto Instr : Res) {
22 bool Compressed =
false;
23 switch (Instr.getOpcode()) {
31 Compressed = isInt<6>(Instr.getImm());
50 bool IsRV64 = STI.
hasFeature(RISCV::Feature64Bit);
54 (!isInt<32>(Val) || Val == 0x800)) {
67 int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
68 int64_t Lo12 = SignExtend64<12>(Val);
73 if (Lo12 || Hi20 == 0) {
74 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
80 assert(IsRV64 &&
"Can't emit >32-bit imm for non-RV64 target");
105 int64_t Lo12 = SignExtend64<12>(Val);
112 if (!isInt<32>(Val)) {
118 if (ShiftAmount > 12 && !isInt<12>(Val)) {
119 if (isInt<32>((
uint64_t)Val << 12)) {
123 }
else if (isUInt<32>((
uint64_t)Val << 12) &&
128 Val = ((
uint64_t)Val << 12) | (0xffffffffull << 32);
138 Val = ((
uint64_t)Val) | (0xffffffffull << 32);
147 unsigned Opc =
Unsigned ? RISCV::SLLI_UW : RISCV::SLLI;
159 if (TrailingOnes > 0 && TrailingOnes < 64 &&
160 (LeadingOnes + TrailingOnes) > (64 - 12))
161 return 64 - TrailingOnes;
166 if (UpperTrailingOnes < 32 &&
167 (UpperTrailingOnes + LowerLeadingOnes) > (64 - 12))
168 return 32 - UpperTrailingOnes;
175 assert(Val > 0 &&
"Expected postive val");
182 ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros);
188 if ((TmpSeq.
size() + 1) < Res.
size() ||
195 ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
200 if ((TmpSeq.
size() + 1) < Res.
size() ||
208 if (LeadingZeros == 32 && STI.
hasFeature(RISCV::FeatureStdExtZba)) {
210 uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
215 if ((TmpSeq.
size() + 1) < Res.
size() ||
231 if ((Val & 0xfff) != 0 && (Val & 1) == 0 && Res.
size() >= 2) {
233 int64_t ShiftedVal = Val >> TrailingZeros;
238 bool IsShiftedCompressible =
239 isInt<6>(ShiftedVal) && !STI.
hasFeature(RISCV::TuneLUIADDIFusion);
244 if ((TmpSeq.
size() + 1) < Res.
size() || IsShiftedCompressible) {
256 "Expected RV32 to only need 2 instructions");
263 if ((Val & 0xfff) != 0 && (Val & 0x1800) == 0x1000) {
264 int64_t Imm12 = -(0x800 - (Val & 0xfff));
265 int64_t AdjustedVal = Val - Imm12;
270 if ((TmpSeq.
size() + 1) < Res.
size()) {
278 if (Val > 0 && Res.
size() > 2) {
284 if (Val < 0 && Res.
size() > 3) {
300 int64_t LoVal = SignExtend64<32>(Val);
301 int64_t HiVal = SignExtend64<32>(Val >> 32);
302 if (LoVal == HiVal) {
305 if ((TmpSeq.
size() + 1) < Res.
size()) {
324 NewVal = Val | 0x80000000ll;
327 NewVal = Val & ~0x80000000ll;
329 if (isInt<32>(NewVal)) {
332 if ((TmpSeq.
size() + 1) < Res.
size()) {
371 if ((Val % 3) == 0 && isInt<32>(Val / 3)) {
374 }
else if ((Val % 5) == 0 && isInt<32>(Val / 5)) {
377 }
else if ((Val % 9) == 0 && isInt<32>(Val / 9)) {
384 if ((TmpSeq.
size() + 1) < Res.
size()) {
390 int64_t Hi52 = ((
uint64_t)Val + 0x800ull) & ~0xfffull;
391 int64_t Lo12 = SignExtend64<12>(Val);
393 if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) {
396 }
else if (isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) {
399 }
else if (isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) {
408 "unexpected instruction sequence for immediate materialisation");
411 if ((TmpSeq.
size() + 2) < Res.
size()) {
423 STI.
hasFeature(RISCV::FeatureVendorXTHeadBb))) {
426 uint64_t NegImm12 = llvm::rotl<uint64_t>(Val, Rotate);
427 assert(isInt<12>(NegImm12));
440 unsigned &ShiftAmt,
unsigned &AddOpc) {
441 int64_t LoVal = SignExtend64<32>(Val);
455 assert(TzLo < 32 && TzHi >= 32);
456 ShiftAmt = TzHi - TzLo;
459 if (Tmp == ((
uint64_t)LoVal << ShiftAmt))
465 AddOpc = RISCV::ADD_UW;
473 bool CompressionCost) {
474 bool IsRV64 = STI.
hasFeature(RISCV::Feature64Bit);
477 int PlatRegSize = IsRV64 ? 64 : 32;
482 for (
unsigned ShiftVal = 0; ShiftVal <
Size; ShiftVal += PlatRegSize) {
487 return std::max(1,
Cost);
This file implements a class to represent arbitrary precision integral constant values and operations...
static void generateInstSeqLeadingZeros(int64_t Val, const MCSubtargetInfo &STI, RISCVMatInt::InstSeq &Res)
static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI, RISCVMatInt::InstSeq &Res)
static unsigned extractRotateInfo(int64_t Val)
static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
int64_t getSExtValue() const
Get sign extended value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
OpndKind getOpndKind() const
reference emplace_back(ArgTypes &&... Args)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI)
int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI, bool CompressionCost)
SmallVector< Inst, 8 > InstSeq
InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI, unsigned &ShiftAmt, unsigned &AddOpc)
This is an optimization pass for GlobalISel generic memory operations.
int popcount(T Value) noexcept
Count the number of set bits in a value.
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
int countl_zero(T Val)
Count number of 0's from the most significant bit to the least stopping at the first 1.
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
int countl_one(T Value)
Count the number of ones from the most significant bit to the first zero bit.
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.