20 for (
auto Instr : Res) {
22 bool Compressed =
false;
31 Compressed = isInt<6>(Instr.Imm);
51 bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
61 int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
62 int64_t Lo12 = SignExtend64<12>(Val);
67 if (Lo12 || Hi20 == 0) {
68 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
74 assert(IsRV64 &&
"Can't emit >32-bit imm for non-RV64 target");
77 if (ActiveFeatures[RISCV::FeatureStdExtZbs] &&
isPowerOf2_64(Val)) {
105 int64_t Lo12 = SignExtend64<12>(Val);
118 if (ShiftAmount > 12 && !isInt<12>(Val)) {
124 ActiveFeatures[RISCV::FeatureStdExtZba]) {
128 Val = ((
uint64_t)Val << 12) | (0xffffffffull << 32);
135 ActiveFeatures[RISCV::FeatureStdExtZba]) {
138 Val = ((
uint64_t)Val) | (0xffffffffull << 32);
161 if (TrailingOnes > 0 && TrailingOnes < 64 &&
162 (LeadingOnes + TrailingOnes) > (64 - 12))
163 return 64 - TrailingOnes;
168 if (UpperTrailingOnes < 32 &&
169 (UpperTrailingOnes + LowerLeadingOnes) > (64 - 12))
170 return 32 - UpperTrailingOnes;
176 namespace RISCVMatInt {
183 if ((Val & 1) == 0 && Res.size() > 2) {
185 int64_t ShiftedVal = Val >> TrailingZeros;
191 if (TmpSeq.size() < Res.size()) {
201 if (Val > 0 && Res.size() > 2) {
202 assert(ActiveFeatures[RISCV::Feature64Bit] &&
203 "Expected RV32 to only need 2 instructions");
209 ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros);
216 if (TmpSeq.size() < Res.size()) {
224 ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
230 if (TmpSeq.size() < Res.size()) {
239 if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
241 uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
247 if (TmpSeq.size() < Res.size()) {
257 if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbs]) {
258 assert(ActiveFeatures[RISCV::Feature64Bit] &&
259 "Expected RV32 to only need 2 instructions");
271 NewVal = Val | 0x80000000
ll;
274 NewVal = Val & ~0x80000000
ll;
280 if (TmpSeq.size() < Res.size())
295 }
else if (Lo < 0 && TmpSeq.size() +
countPopulation(~Hi) < Res.size()) {
306 if (TmpSeq.size() < Res.size())
312 if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
313 assert(ActiveFeatures[RISCV::Feature64Bit] &&
314 "Expected RV32 to only need 2 instructions");
319 if ((Val % 3) == 0 &&
isInt<32>(Val / 3)) {
322 }
else if ((Val % 5) == 0 &&
isInt<32>(Val / 5)) {
325 }
else if ((Val % 9) == 0 &&
isInt<32>(Val / 9)) {
333 if (TmpSeq.size() < Res.size())
337 int64_t Hi52 = ((
uint64_t)Val + 0x800ull) & ~0xfffull;
338 int64_t Lo12 = SignExtend64<12>(Val);
340 if (
isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) {
343 }
else if (
isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) {
346 }
else if (
isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) {
355 "unexpected instruction sequence for immediate materialisation");
356 assert(TmpSeq.empty() &&
"Expected empty TmpSeq");
360 if (TmpSeq.size() < Res.size())
367 if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbb]) {
372 assert(isInt<12>(NegImm12));
383 bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
384 bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC];
385 int PlatRegSize = IsRV64 ? 64 : 32;
390 for (
unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) {