20 for (
auto Instr : Res) {
22 bool Compressed =
false;
23 switch (Instr.getOpcode()) {
31 Compressed = isInt<6>(Instr.getImm());
51 bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
54 if (ActiveFeatures[RISCV::FeatureStdExtZbs] &&
isPowerOf2_64(Val) &&
55 (!isInt<32>(Val) || Val == 0x800)) {
68 int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
69 int64_t Lo12 = SignExtend64<12>(Val);
74 if (Lo12 || Hi20 == 0) {
75 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
81 assert(IsRV64 &&
"Can't emit >32-bit imm for non-RV64 target");
106 int64_t Lo12 = SignExtend64<12>(Val);
113 if (!isInt<32>(Val)) {
119 if (ShiftAmount > 12 && !isInt<12>(Val)) {
120 if (isInt<32>((
uint64_t)Val << 12)) {
124 }
else if (isUInt<32>((
uint64_t)Val << 12) &&
125 ActiveFeatures[RISCV::FeatureStdExtZba]) {
129 Val = ((
uint64_t)Val << 12) | (0xffffffffull << 32);
136 ActiveFeatures[RISCV::FeatureStdExtZba]) {
139 Val = ((
uint64_t)Val) | (0xffffffffull << 32);
148 unsigned Opc =
Unsigned ? RISCV::SLLI_UW : RISCV::SLLI;
160 if (TrailingOnes > 0 && TrailingOnes < 64 &&
161 (LeadingOnes + TrailingOnes) > (64 - 12))
162 return 64 - TrailingOnes;
167 if (UpperTrailingOnes < 32 &&
168 (UpperTrailingOnes + LowerLeadingOnes) > (64 - 12))
169 return 32 - UpperTrailingOnes;
182 if ((Val & 0xfff) != 0 && (Val & 1) == 0 && Res.
size() >= 2) {
184 int64_t ShiftedVal = Val >> TrailingZeros;
189 bool IsShiftedCompressible =
190 isInt<6>(ShiftedVal) && !ActiveFeatures[RISCV::TuneLUIADDIFusion];
196 if (TmpSeq.
size() < Res.
size() || IsShiftedCompressible)
202 if (Val > 0 && Res.
size() > 2) {
203 assert(ActiveFeatures[RISCV::Feature64Bit] &&
204 "Expected RV32 to only need 2 instructions");
210 ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros);
221 ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
232 if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
234 uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
246 if (Res.
size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbs]) {
247 assert(ActiveFeatures[RISCV::Feature64Bit] &&
248 "Expected RV32 to only need 2 instructions");
260 NewVal = Val | 0x80000000ll;
263 NewVal = Val & ~0x80000000ll;
265 if (isInt<32>(NewVal)) {
301 if (Res.
size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
302 assert(ActiveFeatures[RISCV::Feature64Bit] &&
303 "Expected RV32 to only need 2 instructions");
308 if ((Val % 3) == 0 && isInt<32>(Val / 3)) {
311 }
else if ((Val % 5) == 0 && isInt<32>(Val / 5)) {
314 }
else if ((Val % 9) == 0 && isInt<32>(Val / 9)) {
326 int64_t Hi52 = ((
uint64_t)Val + 0x800ull) & ~0xfffull;
327 int64_t Lo12 = SignExtend64<12>(Val);
329 if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) {
332 }
else if (isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) {
335 }
else if (isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) {
344 "unexpected instruction sequence for immediate materialisation");
357 if (Res.
size() > 2 && (ActiveFeatures[RISCV::FeatureStdExtZbb] ||
358 ActiveFeatures[RISCV::FeatureVendorXTHeadBb])) {
361 uint64_t NegImm12 = llvm::rotl<uint64_t>(Val, Rotate);
362 assert(isInt<12>(NegImm12));
364 TmpSeq.
emplace_back(ActiveFeatures[RISCV::FeatureStdExtZbb]
376 bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
377 bool HasRVC = CompressionCost && (ActiveFeatures[RISCV::FeatureStdExtC] ||
378 ActiveFeatures[RISCV::FeatureStdExtZca]);
379 int PlatRegSize = IsRV64 ? 64 : 32;
384 for (
unsigned ShiftVal = 0; ShiftVal <
Size; ShiftVal += PlatRegSize) {
389 return std::max(1,
Cost);
This file implements a class to represent arbitrary precision integral constant values and operations...
static void generateInstSeqImpl(int64_t Val, const FeatureBitset &ActiveFeatures, RISCVMatInt::InstSeq &Res)
static unsigned extractRotateInfo(int64_t Val)
static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
int64_t getSExtValue() const
Get sign extended value.
Container class for subtarget features.
OpndKind getOpndKind() const
reference emplace_back(ArgTypes &&... Args)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getIntMatCost(const APInt &Val, unsigned Size, const FeatureBitset &ActiveFeatures, bool CompressionCost)
InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures)
This is an optimization pass for GlobalISel generic memory operations.
int popcount(T Value) noexcept
Count the number of set bits in a value.
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
int countl_zero(T Val)
Count number of 0's from the most significant bit to the least stopping at the first 1.
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
int countl_one(T Value)
Count the number of ones from the most significant bit to the first zero bit.
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.