LLVM 19.0.0git
Namespaces | Enumerations | Functions | Variables
RISCVTargetParser.h File Reference
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"

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Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::RISCV
 
namespace  llvm::RISCVII
 
namespace  llvm::RISCVVType
 

Enumerations

enum  llvm::RISCVII::VLMUL : uint8_t {
  llvm::RISCVII::LMUL_1 = 0 , llvm::RISCVII::LMUL_2 , llvm::RISCVII::LMUL_4 , llvm::RISCVII::LMUL_8 ,
  llvm::RISCVII::LMUL_RESERVED , llvm::RISCVII::LMUL_F8 , llvm::RISCVII::LMUL_F4 , llvm::RISCVII::LMUL_F2
}
 
enum  { llvm::RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED = 0 , llvm::RISCVII::TAIL_AGNOSTIC = 1 , llvm::RISCVII::MASK_AGNOSTIC = 2 }
 

Functions

void llvm::RISCV::getFeaturesForCPU (StringRef CPU, SmallVectorImpl< std::string > &EnabledFeatures, bool NeedPlus=false)
 
bool llvm::RISCV::parseCPU (StringRef CPU, bool IsRV64)
 
bool llvm::RISCV::parseTuneCPU (StringRef CPU, bool IsRV64)
 
StringRef llvm::RISCV::getMArchFromMcpu (StringRef CPU)
 
void llvm::RISCV::fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
 
void llvm::RISCV::fillValidTuneCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
 
bool llvm::RISCV::hasFastScalarUnalignedAccess (StringRef CPU)
 
bool llvm::RISCV::hasFastVectorUnalignedAccess (StringRef CPU)
 
static bool llvm::RISCVVType::isValidSEW (unsigned SEW)
 
static bool llvm::RISCVVType::isValidLMUL (unsigned LMUL, bool Fractional)
 
unsigned llvm::RISCVVType::encodeVTYPE (RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
 
static RISCVII::VLMUL llvm::RISCVVType::getVLMUL (unsigned VType)
 
std::pair< unsigned, boolllvm::RISCVVType::decodeVLMUL (RISCVII::VLMUL VLMUL)
 
static RISCVII::VLMUL llvm::RISCVVType::encodeLMUL (unsigned LMUL, bool Fractional)
 
static unsigned llvm::RISCVVType::decodeVSEW (unsigned VSEW)
 
static unsigned llvm::RISCVVType::encodeSEW (unsigned SEW)
 
static unsigned llvm::RISCVVType::getSEW (unsigned VType)
 
static bool llvm::RISCVVType::isTailAgnostic (unsigned VType)
 
static bool llvm::RISCVVType::isMaskAgnostic (unsigned VType)
 
void llvm::RISCVVType::printVType (unsigned VType, raw_ostream &OS)
 
unsigned llvm::RISCVVType::getSEWLMULRatio (unsigned SEW, RISCVII::VLMUL VLMul)
 
std::optional< RISCVII::VLMUL > llvm::RISCVVType::getSameRatioLMUL (unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW)
 

Variables

static constexpr unsigned llvm::RISCV::RVVBitsPerBlock = 64