LLVM 18.0.0git
RISCVTargetParser.h
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1//===-- RISCVTargetParser - Parser for target features ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise hardware features
10// for RISC-V CPUs.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGETPARSER_RISCVTARGETPARSER_H
15#define LLVM_TARGETPARSER_RISCVTARGETPARSER_H
16
17#include "llvm/ADT/StringRef.h"
18#include <vector>
19
20namespace llvm {
21
22class Triple;
23
24namespace RISCV {
25
26// We use 64 bits as the known part in the scalable vector types.
27static constexpr unsigned RVVBitsPerBlock = 64;
28
29bool parseCPU(StringRef CPU, bool IsRV64);
30bool parseTuneCPU(StringRef CPU, bool IsRV64);
32void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
34
35} // namespace RISCV
36} // namespace llvm
37
38#endif
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
void fillValidTuneCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
StringRef getMArchFromMcpu(StringRef CPU)
bool parseCPU(StringRef CPU, bool IsRV64)
static constexpr unsigned RVVBitsPerBlock
bool parseTuneCPU(StringRef CPU, bool IsRV64)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18