20#define DEBUG_TYPE "llvm-mca"
28 const unsigned MaxRetirePerCycle = RCU.getMaxRetirePerCycle();
29 unsigned NumRetired = 0;
30 while (!RCU.isEmpty()) {
31 if (MaxRetirePerCycle != 0 && NumRetired == MaxRetirePerCycle)
37 RCU.consumeCurrentToken();
52 PRF.onInstructionExecuted(&IS);
55 RCU.onInstructionExecuted(TokenID);
67 LSU.onInstructionRetired(
IR);
70 PRF.removeRegisterWrite(WS, FreedRegs);
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file defines the main interface for hardware event listeners.
Legalize the Machine IR a function s Machine IR
This file defines the retire stage of a default instruction pipeline.
Subclass of Error for the sole purpose of identifying the success path in the type system.
Lightweight error class with error context and mandatory checking.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An InstRef contains both a SourceMgr index and Instruction pair.
SmallVectorImpl< WriteState > & getDefs()
An instruction propagated through the simulated instruction pipeline.
unsigned getRCUTokenID() const
Error cycleEnd() override
Called once at the end of each cycle.
void notifyInstructionRetired(const InstRef &IR) const
Error cycleStart() override
Called once at the start of each cycle.
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
void notifyEvent(const EventT &Event) const
Notify listeners of a particular hardware event.
Tracks uses of a register definition (e.g.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static const unsigned UnhandledTokenID