LLVM 17.0.0git
VECustomDAG.h
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1//===------------ VECustomDAG.h - VE Custom DAG Nodes -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the helper functions that VE uses to lower LLVM code into a
10// selection DAG. For example, hiding SDLoc, and easy to use SDNodeFlags.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_VE_VECUSTOMDAG_H
15#define LLVM_LIB_TARGET_VE_VECUSTOMDAG_H
16
17#include "VE.h"
18#include "VEISelLowering.h"
21
22namespace llvm {
23
24std::optional<unsigned> getVVPOpcode(unsigned Opcode);
25
26bool isVVPUnaryOp(unsigned Opcode);
27bool isVVPBinaryOp(unsigned Opcode);
28bool isVVPReductionOp(unsigned Opcode);
29
30MVT splitVectorType(MVT VT);
31
32bool isPackedVectorType(EVT SomeVT);
33
34bool isMaskType(EVT SomeVT);
35
36bool isMaskArithmetic(SDValue Op);
37
38bool isVVPOrVEC(unsigned);
39
40bool supportsPackedMode(unsigned Opcode, EVT IdiomVT);
41
42bool isPackingSupportOpcode(unsigned Opc);
43
44bool maySafelyIgnoreMask(SDValue Op);
45
46/// The VE backend uses a two-staged process to lower and legalize vector
47/// instructions:
48//
49/// 1. VP and standard vector SDNodes are lowered to SDNodes of the VVP_* layer.
50//
51// All VVP nodes have a mask and an Active Vector Length (AVL) parameter.
52// The AVL parameters refers to the element position in the vector the VVP
53// node operates on.
54//
55//
56// 2. The VVP SDNodes are legalized. The AVL in a legal VVP node refers to
57// chunks of 64bit. We track this by wrapping the AVL in a LEGALAVL node.
58//
59// The AVL mechanism in the VE architecture always refers to chunks of
60// 64bit, regardless of the actual element type vector instructions are
61// operating on. For vector types v256.32 or v256.64 nothing needs to be
62// legalized since each element occupies a 64bit chunk - there is no
63// difference between counting 64bit chunks or element positions. However,
64// all vector types with > 256 elements store more than one logical element
65// per 64bit chunk and need to be transformed.
66// However legalization is performed, the resulting legal VVP SDNodes will
67// have a LEGALAVL node as their AVL operand. The LEGALAVL nodes wraps
68// around an AVL that refers to 64 bit chunks just as the architecture
69// demands - that is, the wrapped AVL is the correct setting for the VL
70// register for this VVP operation to get the desired behavior.
71//
72/// AVL Functions {
73// The AVL operand position of this node.
74std::optional<int> getAVLPos(unsigned);
75
76// Whether this is a LEGALAVL node.
77bool isLegalAVL(SDValue AVL);
78
79// The AVL operand of this node.
80SDValue getNodeAVL(SDValue);
81
82// Mask position of this node.
83std::optional<int> getMaskPos(unsigned);
84
85SDValue getNodeMask(SDValue);
86
87// Return the AVL operand of this node. If it is a LEGALAVL node, unwrap it.
88// Return with the boolean whether unwrapping happened.
89std::pair<SDValue, bool> getAnnotatedNodeAVL(SDValue);
90
91/// } AVL Functions
92
93/// Node Properties {
94
95std::optional<EVT> getIdiomaticVectorType(SDNode *Op);
96
97SDValue getLoadStoreStride(SDValue Op, VECustomDAG &CDAG);
98
99SDValue getMemoryPtr(SDValue Op);
100
101SDValue getNodeChain(SDValue Op);
102
103SDValue getStoredValue(SDValue Op);
104
105SDValue getNodePassthru(SDValue Op);
106
107SDValue getGatherScatterIndex(SDValue Op);
108
109SDValue getGatherScatterScale(SDValue Op);
110
111unsigned getScalarReductionOpcode(unsigned VVPOC, bool IsMask);
112
113// Whether this VP_REDUCE_*/ VECREDUCE_*/VVP_REDUCE_* SDNode has a start
114// parameter.
115bool hasReductionStartParam(unsigned VVPOC);
116
117/// } Node Properties
118
119enum class Packing {
120 Normal = 0, // 256 element standard mode.
121 Dense = 1 // 512 element packed mode.
122};
123
124// Get the vector or mask register type for this packing and element type.
125MVT getLegalVectorType(Packing P, MVT ElemVT);
126
127// Whether this type belongs to a packed mask or vector register.
129
130enum class PackElem : int8_t {
131 Lo = 0, // Integer (63, 32]
132 Hi = 1 // Float (32, 0]
133};
134
139 : Mask(Mask), AVL(AVL) {}
140};
141
143 SelectionDAG &DAG;
144 SDLoc DL;
145
146public:
147 SelectionDAG *getDAG() const { return &DAG; }
148
149 VECustomDAG(SelectionDAG &DAG, SDLoc DL) : DAG(DAG), DL(DL) {}
150
151 VECustomDAG(SelectionDAG &DAG, SDValue WhereOp) : DAG(DAG), DL(WhereOp) {}
152
153 VECustomDAG(SelectionDAG &DAG, const SDNode *WhereN) : DAG(DAG), DL(WhereN) {}
154
155 /// getNode {
157 std::optional<SDNodeFlags> Flags = std::nullopt) const {
158 auto N = DAG.getNode(OC, DL, VTL, OpV);
159 if (Flags)
160 N->setFlags(*Flags);
161 return N;
162 }
163
165 std::optional<SDNodeFlags> Flags = std::nullopt) const {
166 auto N = DAG.getNode(OC, DL, ResVT, OpV);
167 if (Flags)
168 N->setFlags(*Flags);
169 return N;
170 }
171
172 SDValue getNode(unsigned OC, EVT ResVT, ArrayRef<SDValue> OpV,
173 std::optional<SDNodeFlags> Flags = std::nullopt) const {
174 auto N = DAG.getNode(OC, DL, ResVT, OpV);
175 if (Flags)
176 N->setFlags(*Flags);
177 return N;
178 }
179
180 SDValue getUNDEF(EVT VT) const { return DAG.getUNDEF(VT); }
181 /// } getNode
182
183 /// Legalizing getNode {
184 SDValue getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, SDValue StartV,
185 SDValue VectorV, SDValue Mask, SDValue AVL,
186 SDNodeFlags Flags) const;
187 /// } Legalizing getNode
188
189 /// Packing {
190 SDValue getUnpack(EVT DestVT, SDValue Vec, PackElem Part, SDValue AVL) const;
191 SDValue getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, SDValue AVL) const;
192 /// } Packing
193
195 return DAG.getMergeValues(Values, DL);
196 }
197
198 SDValue getConstant(uint64_t Val, EVT VT, bool IsTarget = false,
199 bool IsOpaque = false) const;
200
201 SDValue getConstantMask(Packing Packing, bool AllTrue) const;
202 SDValue getMaskBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const;
203 SDValue getBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const;
204
205 // Wrap AVL in a LEGALAVL node (unless it is one already).
208 PackElem Part) const;
209
210 // Splitting support
212 PackElem Part) const;
213 SDValue getSplitPtrStride(SDValue PackStride) const;
215 SDValue Mask, SDValue AVL) const;
216 EVT getVectorVT(EVT ElemVT, unsigned NumElems) const {
217 return EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElems);
218 }
219};
220
221} // namespace llvm
222
223#endif // LLVM_LIB_TARGET_VE_VECUSTOMDAG_H
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define P(N)
This file describes how to lower LLVM code to machine code.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
LLVMContext * getContext() const
Definition: SelectionDAG.h:481
SDValue getSplitPtrOffset(SDValue Ptr, SDValue ByteStride, PackElem Part) const
SDValue getNode(unsigned OC, ArrayRef< EVT > ResVT, ArrayRef< SDValue > OpV, std::optional< SDNodeFlags > Flags=std::nullopt) const
Definition: VECustomDAG.h:164
VECustomDAG(SelectionDAG &DAG, SDValue WhereOp)
Definition: VECustomDAG.h:151
SDValue getMergeValues(ArrayRef< SDValue > Values) const
} Packing
Definition: VECustomDAG.h:194
SDValue getBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const
SDValue getConstantMask(Packing Packing, bool AllTrue) const
VECustomDAG(SelectionDAG &DAG, SDLoc DL)
Definition: VECustomDAG.h:149
SDValue getGatherScatterAddress(SDValue BasePtr, SDValue Scale, SDValue Index, SDValue Mask, SDValue AVL) const
SDValue getMaskBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const
SDValue getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, SDValue StartV, SDValue VectorV, SDValue Mask, SDValue AVL, SDNodeFlags Flags) const
} getNode
SDValue getNode(unsigned OC, SDVTList VTL, ArrayRef< SDValue > OpV, std::optional< SDNodeFlags > Flags=std::nullopt) const
getNode {
Definition: VECustomDAG.h:156
VECustomDAG(SelectionDAG &DAG, const SDNode *WhereN)
Definition: VECustomDAG.h:153
SDValue annotateLegalAVL(SDValue AVL) const
SDValue getUnpack(EVT DestVT, SDValue Vec, PackElem Part, SDValue AVL) const
} Legalizing getNode
SDValue getUNDEF(EVT VT) const
Definition: VECustomDAG.h:180
SelectionDAG * getDAG() const
Definition: VECustomDAG.h:147
SDValue getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, SDValue AVL) const
EVT getVectorVT(EVT ElemVT, unsigned NumElems) const
Definition: VECustomDAG.h:216
SDValue getConstant(uint64_t Val, EVT VT, bool IsTarget=false, bool IsOpaque=false) const
SDValue getSplitPtrStride(SDValue PackStride) const
VETargetMasks getTargetSplitMask(SDValue RawMask, SDValue RawAVL, PackElem Part) const
SDValue getNode(unsigned OC, EVT ResVT, ArrayRef< SDValue > OpV, std::optional< SDNodeFlags > Flags=std::nullopt) const
Definition: VECustomDAG.h:172
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool isVVPReductionOp(unsigned Opcode)
bool isPackedVectorType(EVT SomeVT)
Definition: VECustomDAG.cpp:22
bool supportsPackedMode(unsigned Opcode, EVT IdiomVT)
std::optional< int > getAVLPos(unsigned Opc)
The VE backend uses a two-staged process to lower and legalize vector instructions:
SDValue getGatherScatterScale(SDValue Op)
SDValue getStoredValue(SDValue Op)
bool isVVPBinaryOp(unsigned VVPOpcode)
std::optional< EVT > getIdiomaticVectorType(SDNode *Op)
} AVL Functions
SDValue getNodeChain(SDValue Op)
Node Properties {.
Packing
} Node Properties
Definition: VECustomDAG.h:119
bool isMaskArithmetic(SDValue Op)
Definition: VECustomDAG.cpp:50
SDValue getNodeAVL(SDValue Op)
} Node Properties
bool isMaskType(EVT SomeVT)
Definition: VECustomDAG.cpp:44
bool isLegalAVL(SDValue AVL)
MVT splitVectorType(MVT VT)
Definition: VECustomDAG.cpp:28
SDValue getNodePassthru(SDValue Op)
bool maySafelyIgnoreMask(SDValue Op)
Definition: VECustomDAG.cpp:85
bool isVVPOrVEC(unsigned Opcode)
MVT getLegalVectorType(Packing P, MVT ElemVT)
Definition: VECustomDAG.cpp:34
SDValue getMemoryPtr(SDValue Op)
std::optional< int > getMaskPos(unsigned Opc)
bool isPackingSupportOpcode(unsigned Opc)
std::pair< SDValue, bool > getAnnotatedNodeAVL(SDValue Op)
bool hasReductionStartParam(unsigned OPC)
SDValue getGatherScatterIndex(SDValue Op)
Packing getTypePacking(EVT VT)
Definition: VECustomDAG.cpp:39
unsigned getScalarReductionOpcode(unsigned VVPOC, bool IsMask)
std::optional< unsigned > getVVPOpcode(unsigned Opcode)
Definition: VECustomDAG.cpp:62
bool isVVPUnaryOp(unsigned VVPOpcode)
SDValue getNodeMask(SDValue Op)
SDValue getLoadStoreStride(SDValue Op, VECustomDAG &CDAG)
#define N
Extended Value Type.
Definition: ValueTypes.h:34
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:73
These are IR-level optimization flags that may be propagated to SDNodes.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
VETargetMasks(SDValue Mask=SDValue(), SDValue AVL=SDValue())
Definition: VECustomDAG.h:138