99void SelectionDAG::DAGNodeDeletedListener::anchor() {}
100void SelectionDAG::DAGNodeInsertedListener::anchor() {}
102#define DEBUG_TYPE "selectiondag"
106 cl::desc(
"Gang up loads and stores generated by inlining of memcpy"));
109 cl::desc(
"Number limit for gluing ld/st of memcpy."),
125 return getValueAPF().bitwiseIsEqual(V);
148 N->getValueType(0).getVectorElementType().getSizeInBits();
149 if (
auto *Op0 = dyn_cast<ConstantSDNode>(
N->getOperand(0))) {
150 SplatVal = Op0->getAPIntValue().
trunc(EltSize);
153 if (
auto *Op0 = dyn_cast<ConstantFPSDNode>(
N->getOperand(0))) {
154 SplatVal = Op0->getValueAPF().bitcastToAPInt().
trunc(EltSize);
159 auto *BV = dyn_cast<BuildVectorSDNode>(
N);
164 unsigned SplatBitSize;
166 unsigned EltSize =
N->getValueType(0).getVectorElementType().getSizeInBits();
171 const bool IsBigEndian =
false;
172 return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs,
173 EltSize, IsBigEndian) &&
174 EltSize == SplatBitSize;
183 N =
N->getOperand(0).getNode();
192 unsigned i = 0, e =
N->getNumOperands();
195 while (i != e &&
N->getOperand(i).isUndef())
199 if (i == e)
return false;
210 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
212 if (CN->getAPIntValue().countr_one() < EltSize)
215 if (CFPN->getValueAPF().bitcastToAPInt().countr_one() < EltSize)
223 for (++i; i != e; ++i)
224 if (
N->getOperand(i) != NotZero && !
N->getOperand(i).isUndef())
232 N =
N->getOperand(0).getNode();
241 bool IsAllUndef =
true;
254 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
256 if (CN->getAPIntValue().countr_zero() < EltSize)
259 if (CFPN->getValueAPF().bitcastToAPInt().countr_zero() < EltSize)
286 if (!isa<ConstantSDNode>(
Op))
299 if (!isa<ConstantFPSDNode>(
Op))
307 assert(
N->getValueType(0).isVector() &&
"Expected a vector!");
309 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
310 if (EltSize <= NewEltSize)
314 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
319 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
329 if (!isa<ConstantSDNode>(
Op))
332 APInt C =
Op->getAsAPIntVal().trunc(EltSize);
333 if (
Signed &&
C.trunc(NewEltSize).sext(EltSize) !=
C)
335 if (!
Signed &&
C.trunc(NewEltSize).zext(EltSize) !=
C)
346 if (
N->getNumOperands() == 0)
352 return N->getOpcode() ==
ISD::FREEZE &&
N->getOperand(0).isUndef();
355template <
typename ConstNodeType>
357 std::function<
bool(ConstNodeType *)>
Match,
360 if (
auto *
C = dyn_cast<ConstNodeType>(
Op))
368 EVT SVT =
Op.getValueType().getScalarType();
370 if (AllowUndefs &&
Op.getOperand(i).isUndef()) {
376 auto *Cst = dyn_cast<ConstNodeType>(
Op.getOperand(i));
377 if (!Cst || Cst->getValueType(0) != SVT || !
Match(Cst))
383template bool ISD::matchUnaryPredicateImpl<ConstantSDNode>(
385template bool ISD::matchUnaryPredicateImpl<ConstantFPSDNode>(
391 bool AllowUndefs,
bool AllowTypeMismatch) {
392 if (!AllowTypeMismatch &&
LHS.getValueType() !=
RHS.getValueType())
396 if (
auto *LHSCst = dyn_cast<ConstantSDNode>(
LHS))
397 if (
auto *RHSCst = dyn_cast<ConstantSDNode>(
RHS))
398 return Match(LHSCst, RHSCst);
401 if (
LHS.getOpcode() !=
RHS.getOpcode() ||
406 EVT SVT =
LHS.getValueType().getScalarType();
407 for (
unsigned i = 0, e =
LHS.getNumOperands(); i != e; ++i) {
410 bool LHSUndef = AllowUndefs && LHSOp.
isUndef();
411 bool RHSUndef = AllowUndefs && RHSOp.
isUndef();
412 auto *LHSCst = dyn_cast<ConstantSDNode>(LHSOp);
413 auto *RHSCst = dyn_cast<ConstantSDNode>(RHSOp);
414 if ((!LHSCst && !LHSUndef) || (!RHSCst && !RHSUndef))
416 if (!AllowTypeMismatch && (LHSOp.
getValueType() != SVT ||
419 if (!
Match(LHSCst, RHSCst))
426 switch (VecReduceOpcode) {
431 case ISD::VP_REDUCE_FADD:
432 case ISD::VP_REDUCE_SEQ_FADD:
436 case ISD::VP_REDUCE_FMUL:
437 case ISD::VP_REDUCE_SEQ_FMUL:
440 case ISD::VP_REDUCE_ADD:
443 case ISD::VP_REDUCE_MUL:
446 case ISD::VP_REDUCE_AND:
449 case ISD::VP_REDUCE_OR:
452 case ISD::VP_REDUCE_XOR:
455 case ISD::VP_REDUCE_SMAX:
458 case ISD::VP_REDUCE_SMIN:
461 case ISD::VP_REDUCE_UMAX:
464 case ISD::VP_REDUCE_UMIN:
467 case ISD::VP_REDUCE_FMAX:
470 case ISD::VP_REDUCE_FMIN:
483#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) \
486#include "llvm/IR/VPIntrinsics.def"
494#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
495#define VP_PROPERTY_BINARYOP return true;
496#define END_REGISTER_VP_SDNODE(VPSD) break;
497#include "llvm/IR/VPIntrinsics.def"
506#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
507#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
508#define END_REGISTER_VP_SDNODE(VPSD) break;
509#include "llvm/IR/VPIntrinsics.def"
519#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, ...) \
522#include "llvm/IR/VPIntrinsics.def"
531#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, EVLPOS) \
534#include "llvm/IR/VPIntrinsics.def"
544#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) case ISD::VPOPC:
545#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) return ISD::SDOPC;
546#define END_REGISTER_VP_SDNODE(VPOPC) break;
547#include "llvm/IR/VPIntrinsics.def"
556#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) break;
557#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) case ISD::SDOPC:
558#define END_REGISTER_VP_SDNODE(VPOPC) return ISD::VPOPC;
559#include "llvm/IR/VPIntrinsics.def"
606 bool isIntegerLike) {
631 bool IsInteger =
Type.isInteger();
636 unsigned Op = Op1 | Op2;
652 bool IsInteger =
Type.isInteger();
687 ID.AddPointer(VTList.
VTs);
693 for (
const auto &
Op : Ops) {
694 ID.AddPointer(
Op.getNode());
695 ID.AddInteger(
Op.getResNo());
702 for (
const auto &
Op : Ops) {
703 ID.AddPointer(
Op.getNode());
704 ID.AddInteger(
Op.getResNo());
717 switch (
N->getOpcode()) {
726 ID.AddPointer(
C->getConstantIntValue());
727 ID.AddBoolean(
C->isOpaque());
732 ID.AddPointer(cast<ConstantFPSDNode>(
N)->getConstantFPValue());
748 ID.AddInteger(cast<RegisterSDNode>(
N)->
getReg());
751 ID.AddPointer(cast<RegisterMaskSDNode>(
N)->getRegMask());
754 ID.AddPointer(cast<SrcValueSDNode>(
N)->getValue());
758 ID.AddInteger(cast<FrameIndexSDNode>(
N)->getIndex());
762 if (cast<LifetimeSDNode>(
N)->hasOffset()) {
763 ID.AddInteger(cast<LifetimeSDNode>(
N)->
getSize());
768 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getGuid());
769 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getIndex());
770 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getAttributes());
774 ID.AddInteger(cast<JumpTableSDNode>(
N)->getIndex());
775 ID.AddInteger(cast<JumpTableSDNode>(
N)->getTargetFlags());
780 ID.AddInteger(CP->getAlign().value());
781 ID.AddInteger(CP->getOffset());
782 if (CP->isMachineConstantPoolEntry())
783 CP->getMachineCPVal()->addSelectionDAGCSEId(
ID);
785 ID.AddPointer(CP->getConstVal());
786 ID.AddInteger(CP->getTargetFlags());
798 ID.AddInteger(LD->getMemoryVT().getRawBits());
799 ID.AddInteger(LD->getRawSubclassData());
800 ID.AddInteger(LD->getPointerInfo().getAddrSpace());
801 ID.AddInteger(LD->getMemOperand()->getFlags());
806 ID.AddInteger(ST->getMemoryVT().getRawBits());
807 ID.AddInteger(ST->getRawSubclassData());
808 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
809 ID.AddInteger(ST->getMemOperand()->getFlags());
820 case ISD::VP_STORE: {
828 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: {
835 case ISD::EXPERIMENTAL_VP_STRIDED_STORE: {
842 case ISD::VP_GATHER: {
850 case ISD::VP_SCATTER: {
939 if (
auto *MN = dyn_cast<MemIntrinsicSDNode>(
N)) {
940 ID.AddInteger(MN->getRawSubclassData());
941 ID.AddInteger(MN->getPointerInfo().getAddrSpace());
942 ID.AddInteger(MN->getMemOperand()->getFlags());
943 ID.AddInteger(MN->getMemoryVT().getRawBits());
966 if (
N->getValueType(0) == MVT::Glue)
969 switch (
N->getOpcode()) {
977 for (
unsigned i = 1, e =
N->getNumValues(); i != e; ++i)
978 if (
N->getValueType(i) == MVT::Glue)
995 if (Node.use_empty())
1010 while (!DeadNodes.
empty()) {
1019 DUL->NodeDeleted(
N,
nullptr);
1022 RemoveNodeFromCSEMaps(
N);
1053 RemoveNodeFromCSEMaps(
N);
1057 DeleteNodeNotInCSEMaps(
N);
1060void SelectionDAG::DeleteNodeNotInCSEMaps(
SDNode *
N) {
1061 assert(
N->getIterator() != AllNodes.begin() &&
1062 "Cannot delete the entry node!");
1063 assert(
N->use_empty() &&
"Cannot delete a node that is not dead!");
1072 assert(!(V->isVariadic() && isParameter));
1074 ByvalParmDbgValues.push_back(V);
1076 DbgValues.push_back(V);
1077 for (
const SDNode *Node : V->getSDNodes())
1079 DbgValMap[Node].push_back(V);
1084 if (
I == DbgValMap.end())
1086 for (
auto &Val:
I->second)
1087 Val->setIsInvalidated();
1091void SelectionDAG::DeallocateNode(
SDNode *
N) {
1115 switch (
N->getOpcode()) {
1119 EVT VT =
N->getValueType(0);
1120 assert(
N->getNumValues() == 1 &&
"Too many results!");
1122 "Wrong return type!");
1123 assert(
N->getNumOperands() == 2 &&
"Wrong number of operands!");
1124 assert(
N->getOperand(0).getValueType() ==
N->getOperand(1).getValueType() &&
1125 "Mismatched operand types!");
1127 "Wrong operand type!");
1129 "Wrong return type size");
1133 assert(
N->getNumValues() == 1 &&
"Too many results!");
1134 assert(
N->getValueType(0).isVector() &&
"Wrong return type!");
1135 assert(
N->getNumOperands() ==
N->getValueType(0).getVectorNumElements() &&
1136 "Wrong number of operands!");
1137 EVT EltVT =
N->getValueType(0).getVectorElementType();
1139 assert((
Op.getValueType() == EltVT ||
1140 (EltVT.
isInteger() &&
Op.getValueType().isInteger() &&
1141 EltVT.
bitsLE(
Op.getValueType()))) &&
1142 "Wrong operand type!");
1143 assert(
Op.getValueType() ==
N->getOperand(0).getValueType() &&
1144 "Operands must all have the same type");
1156void SelectionDAG::InsertNode(
SDNode *
N) {
1157 AllNodes.push_back(
N);
1159 N->PersistentId = NextPersistentId++;
1162 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1163 DUL->NodeInserted(
N);
1170bool SelectionDAG::RemoveNodeFromCSEMaps(
SDNode *
N) {
1171 bool Erased =
false;
1172 switch (
N->getOpcode()) {
1175 assert(CondCodeNodes[cast<CondCodeSDNode>(
N)->
get()] &&
1176 "Cond code doesn't exist!");
1177 Erased = CondCodeNodes[cast<CondCodeSDNode>(
N)->get()] !=
nullptr;
1178 CondCodeNodes[cast<CondCodeSDNode>(
N)->get()] =
nullptr;
1181 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(
N)->getSymbol());
1185 Erased = TargetExternalSymbols.erase(std::pair<std::string, unsigned>(
1190 auto *MCSN = cast<MCSymbolSDNode>(
N);
1191 Erased = MCSymbols.erase(MCSN->getMCSymbol());
1195 EVT VT = cast<VTSDNode>(
N)->getVT();
1197 Erased = ExtendedValueTypeNodes.erase(VT);
1208 Erased = CSEMap.RemoveNode(
N);
1215 if (!Erased &&
N->getValueType(
N->getNumValues()-1) != MVT::Glue &&
1230SelectionDAG::AddModifiedNodeToCSEMaps(
SDNode *
N) {
1234 SDNode *Existing = CSEMap.GetOrInsertNode(
N);
1235 if (Existing !=
N) {
1242 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1243 DUL->NodeDeleted(
N, Existing);
1244 DeleteNodeNotInCSEMaps(
N);
1250 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1251 DUL->NodeUpdated(
N);
1269 Node->intersectFlagsWith(
N->getFlags());
1289 Node->intersectFlagsWith(
N->getFlags());
1307 Node->intersectFlagsWith(
N->getFlags());
1320 : TM(tm), OptLevel(OL), EntryNode(ISD::EntryToken, 0,
DebugLoc(),
1323 InsertNode(&EntryNode);
1334 SDAGISelPass = PassPtr;
1338 LibInfo = LibraryInfo;
1343 FnVarLocs = VarLocs;
1347 assert(!UpdateListeners &&
"Dangling registered DAGUpdateListeners");
1349 OperandRecycler.clear(OperandAllocator);
1358void SelectionDAG::allnodes_clear() {
1359 assert(&*AllNodes.begin() == &EntryNode);
1360 AllNodes.remove(AllNodes.begin());
1361 while (!AllNodes.empty())
1362 DeallocateNode(&AllNodes.front());
1364 NextPersistentId = 0;
1370 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1372 switch (
N->getOpcode()) {
1377 "debug location. Use another overload.");
1384 const SDLoc &
DL,
void *&InsertPos) {
1385 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1387 switch (
N->getOpcode()) {
1393 if (
N->getDebugLoc() !=
DL.getDebugLoc())
1400 if (
DL.getIROrder() &&
DL.getIROrder() <
N->getIROrder())
1401 N->setDebugLoc(
DL.getDebugLoc());
1410 OperandRecycler.clear(OperandAllocator);
1411 OperandAllocator.
Reset();
1414 ExtendedValueTypeNodes.clear();
1415 ExternalSymbols.clear();
1416 TargetExternalSymbols.clear();
1419 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(),
1421 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
1422 static_cast<SDNode*
>(
nullptr));
1424 EntryNode.UseList =
nullptr;
1425 InsertNode(&EntryNode);
1431 return VT.
bitsGT(
Op.getValueType())
1437std::pair<SDValue, SDValue>
1441 "Strict no-op FP extend/round not allowed.");
1448 return std::pair<SDValue, SDValue>(Res,
SDValue(Res.
getNode(), 1));
1452 return VT.
bitsGT(
Op.getValueType()) ?
1458 return VT.
bitsGT(
Op.getValueType()) ?
1464 return VT.
bitsGT(
Op.getValueType()) ?
1472 auto Type =
Op.getValueType();
1476 auto Size =
Op.getValueSizeInBits();
1487 auto Type =
Op.getValueType();
1491 auto Size =
Op.getValueSizeInBits();
1502 auto Type =
Op.getValueType();
1506 auto Size =
Op.getValueSizeInBits();
1524 EVT OpVT =
Op.getValueType();
1526 "Cannot getZeroExtendInReg FP types");
1528 "getZeroExtendInReg type should be vector iff the operand "
1532 "Vector element counts must match in getZeroExtendInReg");
1570 return getNode(ISD::VP_XOR,
DL, VT, Val, TrueValue, Mask, EVL);
1581 return getNode(ISD::VP_ZERO_EXTEND,
DL, VT,
Op, Mask, EVL);
1583 return getNode(ISD::VP_TRUNCATE,
DL, VT,
Op, Mask, EVL);
1603 bool isT,
bool isO) {
1607 "getConstant with a uint64_t value that doesn't fit in the type!");
1612 bool isT,
bool isO) {
1613 return getConstant(*ConstantInt::get(*Context, Val),
DL, VT, isT, isO);
1617 EVT VT,
bool isT,
bool isO) {
1635 Elt = ConstantInt::get(*
getContext(), NewVal);
1654 "Can only handle an even split!");
1658 for (
unsigned i = 0; i != Parts; ++i)
1660 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1661 ViaEltVT, isT, isO));
1666 unsigned ViaVecNumElts = VT.
getSizeInBits() / ViaEltSizeInBits;
1677 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1678 ViaEltVT, isT, isO));
1683 std::reverse(EltParts.
begin(), EltParts.
end());
1702 "APInt size does not match type size!");
1710 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1715 N = newSDNode<ConstantSDNode>(isT, isO, Elt, EltVT);
1716 CSEMap.InsertNode(
N, IP);
1733 const SDLoc &
DL,
bool LegalTypes) {
1740 const SDLoc &
DL,
bool LegalTypes) {
1756 EVT VT,
bool isTarget) {
1770 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1775 N = newSDNode<ConstantFPSDNode>(isTarget, &V, EltVT);
1776 CSEMap.InsertNode(
N, IP);
1790 if (EltVT == MVT::f32)
1792 if (EltVT == MVT::f64)
1794 if (EltVT == MVT::f80 || EltVT == MVT::f128 || EltVT == MVT::ppcf128 ||
1795 EltVT == MVT::f16 || EltVT == MVT::bf16) {
1806 EVT VT, int64_t
Offset,
bool isTargetGA,
1807 unsigned TargetFlags) {
1808 assert((TargetFlags == 0 || isTargetGA) &&
1809 "Cannot set target flags on target-independent globals");
1826 ID.AddInteger(TargetFlags);
1831 auto *
N = newSDNode<GlobalAddressSDNode>(
1832 Opc,
DL.getIROrder(),
DL.getDebugLoc(), GV, VT,
Offset, TargetFlags);
1833 CSEMap.InsertNode(
N, IP);
1844 if (
SDNode *
E = FindNodeOrInsertPos(
ID, IP))
1847 auto *
N = newSDNode<FrameIndexSDNode>(FI, VT, isTarget);
1848 CSEMap.InsertNode(
N, IP);
1854 unsigned TargetFlags) {
1855 assert((TargetFlags == 0 || isTarget) &&
1856 "Cannot set target flags on target-independent jump tables");
1861 ID.AddInteger(TargetFlags);
1863 if (
SDNode *
E = FindNodeOrInsertPos(
ID, IP))
1866 auto *
N = newSDNode<JumpTableSDNode>(JTI, VT, isTarget, TargetFlags);
1867 CSEMap.InsertNode(
N, IP);
1881 bool isTarget,
unsigned TargetFlags) {
1882 assert((TargetFlags == 0 || isTarget) &&
1883 "Cannot set target flags on target-independent globals");
1891 ID.AddInteger(Alignment->value());
1894 ID.AddInteger(TargetFlags);
1896 if (
SDNode *
E = FindNodeOrInsertPos(
ID, IP))
1899 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VT,
Offset, *Alignment,
1901 CSEMap.InsertNode(
N, IP);
1910 bool isTarget,
unsigned TargetFlags) {
1911 assert((TargetFlags == 0 || isTarget) &&
1912 "Cannot set target flags on target-independent globals");
1918 ID.AddInteger(Alignment->value());
1920 C->addSelectionDAGCSEId(
ID);
1921 ID.AddInteger(TargetFlags);
1923 if (
SDNode *
E = FindNodeOrInsertPos(
ID, IP))
1926 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VT,
Offset, *Alignment,
1928 CSEMap.InsertNode(
N, IP);
1938 if (
SDNode *
E = FindNodeOrInsertPos(
ID, IP))
1941 auto *
N = newSDNode<BasicBlockSDNode>(
MBB);
1942 CSEMap.InsertNode(
N, IP);
1949 ValueTypeNodes.size())
1956 N = newSDNode<VTSDNode>(VT);
1964 N = newSDNode<ExternalSymbolSDNode>(
false,
Sym, 0, VT);
1973 N = newSDNode<MCSymbolSDNode>(
Sym, VT);
1979 unsigned TargetFlags) {
1981 TargetExternalSymbols[std::pair<std::string, unsigned>(
Sym, TargetFlags)];
1983 N = newSDNode<ExternalSymbolSDNode>(
true,
Sym, TargetFlags, VT);
1989 if ((
unsigned)
Cond >= CondCodeNodes.size())
1990 CondCodeNodes.resize(
Cond+1);
1992 if (!CondCodeNodes[
Cond]) {
1993 auto *
N = newSDNode<CondCodeSDNode>(
Cond);
1994 CondCodeNodes[
Cond] =
N;
2004 "APInt size does not match type size!");
2022 if (EC.isScalable())
2058 "Must have the same number of vector elements as mask elements!");
2060 "Invalid VECTOR_SHUFFLE");
2068 int NElts = Mask.size();
2070 [&](
int M) {
return M < (NElts * 2) && M >= -1; }) &&
2071 "Index out of range");
2079 for (
int i = 0; i != NElts; ++i)
2080 if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
2096 for (
int i = 0; i < NElts; ++i) {
2097 if (MaskVec[i] <
Offset || MaskVec[i] >= (
Offset + NElts))
2101 if (UndefElements[MaskVec[i] -
Offset]) {
2107 if (!UndefElements[i])
2111 if (
auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
2112 BlendSplat(N1BV, 0);
2113 if (
auto *N2BV = dyn_cast<BuildVectorSDNode>(N2))
2114 BlendSplat(N2BV, NElts);
2119 bool AllLHS =
true, AllRHS =
true;
2121 for (
int i = 0; i != NElts; ++i) {
2122 if (MaskVec[i] >= NElts) {
2127 }
else if (MaskVec[i] >= 0) {
2131 if (AllLHS && AllRHS)
2133 if (AllLHS && !N2Undef)
2146 bool Identity =
true, AllSame =
true;
2147 for (
int i = 0; i != NElts; ++i) {
2148 if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity =
false;
2149 if (MaskVec[i] != MaskVec[0]) AllSame =
false;
2151 if (Identity && NElts)
2161 V = V->getOperand(0);
2164 if (
auto *BV = dyn_cast<BuildVectorSDNode>(V)) {
2184 if (AllSame && SameNumElts) {
2185 EVT BuildVT = BV->getValueType(0);
2201 for (
int i = 0; i != NElts; ++i)
2202 ID.AddInteger(MaskVec[i]);
2205 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP))
2211 int *MaskAlloc = OperandAllocator.
Allocate<
int>(NElts);
2214 auto *
N = newSDNode<ShuffleVectorSDNode>(VT, dl.
getIROrder(),
2216 createOperands(
N, Ops);
2218 CSEMap.InsertNode(
N, IP);
2238 ID.AddInteger(RegNo);
2240 if (
SDNode *
E = FindNodeOrInsertPos(
ID, IP))
2243 auto *
N = newSDNode<RegisterSDNode>(RegNo, VT);
2245 CSEMap.InsertNode(
N, IP);
2253 ID.AddPointer(RegMask);
2255 if (
SDNode *
E = FindNodeOrInsertPos(
ID, IP))
2258 auto *
N = newSDNode<RegisterMaskSDNode>(RegMask);
2259 CSEMap.InsertNode(
N, IP);
2274 ID.AddPointer(Label);
2276 if (
SDNode *
E = FindNodeOrInsertPos(
ID, IP))
2281 createOperands(
N, Ops);
2283 CSEMap.InsertNode(
N, IP);
2289 int64_t
Offset,
bool isTarget,
2290 unsigned TargetFlags) {
2297 ID.AddInteger(TargetFlags);
2299 if (
SDNode *
E = FindNodeOrInsertPos(
ID, IP))
2302 auto *
N = newSDNode<BlockAddressSDNode>(Opc, VT, BA,
Offset, TargetFlags);
2303 CSEMap.InsertNode(
N, IP);
2314 if (
SDNode *
E = FindNodeOrInsertPos(
ID, IP))
2317 auto *
N = newSDNode<SrcValueSDNode>(V);
2318 CSEMap.InsertNode(
N, IP);
2329 if (
SDNode *
E = FindNodeOrInsertPos(
ID, IP))
2332 auto *
N = newSDNode<MDNodeSDNode>(MD);
2333 CSEMap.InsertNode(
N, IP);
2339 if (VT == V.getValueType())
2346 unsigned SrcAS,
unsigned DestAS) {
2350 ID.AddInteger(SrcAS);
2351 ID.AddInteger(DestAS);
2354 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP))
2359 createOperands(
N, Ops);
2361 CSEMap.InsertNode(
N, IP);
2373 EVT OpTy =
Op.getValueType();
2375 if (OpTy == ShTy || OpTy.
isVector())
return Op;
2383 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2384 EVT VT = Node->getValueType(0);
2385 SDValue Tmp1 = Node->getOperand(0);
2386 SDValue Tmp2 = Node->getOperand(1);
2387 const MaybeAlign MA(Node->getConstantOperandVal(3));
2419 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2420 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2431 Align RedAlign = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2441 if (RedAlign > StackAlign) {
2444 unsigned NumIntermediates;
2446 NumIntermediates, RegisterVT);
2448 Align RedAlign2 = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2449 if (RedAlign2 < RedAlign)
2450 RedAlign = RedAlign2;
2465 false,
nullptr, StackID);
2480 "Don't know how to choose the maximum size when creating a stack "
2489 Align Align = std::max(
DL.getPrefTypeAlign(Ty1),
DL.getPrefTypeAlign(Ty2));
2497 auto GetUndefBooleanConstant = [&]() {
2536 return GetUndefBooleanConstant();
2541 return GetUndefBooleanConstant();
2550 const APInt &C2 = N2C->getAPIntValue();
2552 const APInt &C1 = N1C->getAPIntValue();
2559 auto *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2560 auto *N2CFP = dyn_cast<ConstantFPSDNode>(N2);
2562 if (N1CFP && N2CFP) {
2567 return GetUndefBooleanConstant();
2572 return GetUndefBooleanConstant();
2578 return GetUndefBooleanConstant();
2583 return GetUndefBooleanConstant();
2588 return GetUndefBooleanConstant();
2594 return GetUndefBooleanConstant();
2623 return getSetCC(dl, VT, N2, N1, SwappedCond);
2624 }
else if ((N2CFP && N2CFP->getValueAPF().isNaN()) ||
2639 return GetUndefBooleanConstant();
2650 unsigned BitWidth =
Op.getScalarValueSizeInBits();
2658 unsigned Depth)
const {
2666 const APInt &DemandedElts,
2667 unsigned Depth)
const {
2674 unsigned Depth )
const {
2680 unsigned Depth)
const {
2685 const APInt &DemandedElts,
2686 unsigned Depth)
const {
2687 EVT VT =
Op.getValueType();
2694 for (
unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx) {
2695 if (!DemandedElts[EltIdx])
2699 KnownZeroElements.
setBit(EltIdx);
2701 return KnownZeroElements;
2711 unsigned Opcode = V.getOpcode();
2712 EVT VT = V.getValueType();
2715 "scalable demanded bits are ignored");
2727 UndefElts = V.getOperand(0).isUndef()
2736 APInt UndefLHS, UndefRHS;
2741 UndefElts = UndefLHS | UndefRHS;
2771 for (
unsigned i = 0; i != NumElts; ++i) {
2777 if (!DemandedElts[i])
2779 if (Scl && Scl !=
Op)
2789 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(V)->getMask();
2790 for (
int i = 0; i != (int)NumElts; ++i) {
2796 if (!DemandedElts[i])
2798 if (M < (
int)NumElts)
2801 DemandedRHS.
setBit(M - NumElts);
2813 auto CheckSplatSrc = [&](
SDValue Src,
const APInt &SrcElts) {
2815 return (SrcElts.popcount() == 1) ||
2817 (SrcElts & SrcUndefs).
isZero());
2819 if (!DemandedLHS.
isZero())
2820 return CheckSplatSrc(V.getOperand(0), DemandedLHS);
2821 return CheckSplatSrc(V.getOperand(1), DemandedRHS);
2825 SDValue Src = V.getOperand(0);
2827 if (Src.getValueType().isScalableVector())
2830 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2843 SDValue Src = V.getOperand(0);
2845 if (Src.getValueType().isScalableVector())
2847 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2849 APInt DemandedSrcElts = DemandedElts.
zext(NumSrcElts);
2851 UndefElts = UndefSrcElts.
trunc(NumElts);
2857 SDValue Src = V.getOperand(0);
2858 EVT SrcVT = Src.getValueType();
2868 if ((
BitWidth % SrcBitWidth) == 0) {
2870 unsigned Scale =
BitWidth / SrcBitWidth;
2872 APInt ScaledDemandedElts =
2874 for (
unsigned I = 0;
I != Scale; ++
I) {
2878 SubDemandedElts &= ScaledDemandedElts;
2882 if (!SubUndefElts.
isZero())
2896 EVT VT = V.getValueType();
2906 (AllowUndefs || !UndefElts);
2912 EVT VT = V.getValueType();
2913 unsigned Opcode = V.getOpcode();
2934 SplatIdx = (UndefElts & DemandedElts).
countr_one();
2948 auto *SVN = cast<ShuffleVectorSDNode>(V);
2949 if (!SVN->isSplat())
2951 int Idx = SVN->getSplatIndex();
2952 int NumElts = V.getValueType().getVectorNumElements();
2953 SplatIdx =
Idx % NumElts;
2954 return V.getOperand(
Idx / NumElts);
2970 if (LegalSVT.
bitsLT(SVT))
2981 const APInt &DemandedElts)
const {
2984 "Unknown shift node");
2985 unsigned BitWidth = V.getScalarValueSizeInBits();
2988 const APInt &ShAmt = SA->getAPIntValue();
2999 "Unknown shift node");
3002 unsigned BitWidth = V.getScalarValueSizeInBits();
3003 auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
3006 const APInt *MinShAmt =
nullptr;
3007 for (
unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3008 if (!DemandedElts[i])
3010 auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
3014 const APInt &ShAmt = SA->getAPIntValue();
3017 if (MinShAmt && MinShAmt->
ule(ShAmt))
3028 "Unknown shift node");
3031 unsigned BitWidth = V.getScalarValueSizeInBits();
3032 auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
3035 const APInt *MaxShAmt =
nullptr;
3036 for (
unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3037 if (!DemandedElts[i])
3039 auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
3043 const APInt &ShAmt = SA->getAPIntValue();
3046 if (MaxShAmt && MaxShAmt->
uge(ShAmt))
3057 EVT VT =
Op.getValueType();
3072 unsigned Depth)
const {
3073 unsigned BitWidth =
Op.getScalarValueSizeInBits();
3077 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
3081 if (
auto *
C = dyn_cast<ConstantFPSDNode>(
Op)) {
3091 assert((!
Op.getValueType().isFixedLengthVector() ||
3092 NumElts ==
Op.getValueType().getVectorNumElements()) &&
3093 "Unexpected vector size");
3098 unsigned Opcode =
Op.getOpcode();
3106 "Expected SPLAT_VECTOR implicit truncation");
3113 unsigned ScalarSize =
Op.getOperand(0).getScalarValueSizeInBits();
3115 "Expected SPLAT_VECTOR_PARTS scalars to cover element width");
3122 const APInt &Step =
Op.getConstantOperandAPInt(0);
3131 const APInt MinNumElts =
3137 .
umul_ov(MinNumElts, Overflow);
3141 const APInt MaxValue = (MaxNumElts - 1).
umul_ov(Step, Overflow);
3149 assert(!
Op.getValueType().isScalableVector());
3153 if (!DemandedElts[i])
3162 "Expected BUILD_VECTOR implicit truncation");
3175 assert(!
Op.getValueType().isScalableVector());
3178 APInt DemandedLHS, DemandedRHS;
3182 DemandedLHS, DemandedRHS))
3187 if (!!DemandedLHS) {
3195 if (!!DemandedRHS) {
3204 const APInt &Multiplier =
Op.getConstantOperandAPInt(0);
3209 if (
Op.getValueType().isScalableVector())
3213 EVT SubVectorVT =
Op.getOperand(0).getValueType();
3216 for (
unsigned i = 0; i != NumSubVectors; ++i) {
3218 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
3219 if (!!DemandedSub) {
3231 if (
Op.getValueType().isScalableVector())
3240 APInt DemandedSrcElts = DemandedElts;
3245 if (!!DemandedSubElts) {
3250 if (!!DemandedSrcElts) {
3260 if (
Op.getValueType().isScalableVector() || Src.getValueType().isScalableVector())
3263 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
3269 if (
Op.getValueType().isScalableVector())
3273 if (DemandedElts != 1)
3284 if (
Op.getValueType().isScalableVector())
3304 if ((
BitWidth % SubBitWidth) == 0) {
3311 unsigned SubScale =
BitWidth / SubBitWidth;
3312 APInt SubDemandedElts(NumElts * SubScale, 0);
3313 for (
unsigned i = 0; i != NumElts; ++i)
3314 if (DemandedElts[i])
3315 SubDemandedElts.
setBit(i * SubScale);
3317 for (
unsigned i = 0; i != SubScale; ++i) {
3320 unsigned Shifts = IsLE ? i : SubScale - 1 - i;
3321 Known.
insertBits(Known2, SubBitWidth * Shifts);
3326 if ((SubBitWidth %
BitWidth) == 0) {
3327 assert(
Op.getValueType().isVector() &&
"Expected bitcast to vector");
3332 unsigned SubScale = SubBitWidth /
BitWidth;
3333 APInt SubDemandedElts =
3338 for (
unsigned i = 0; i != NumElts; ++i)
3339 if (DemandedElts[i]) {
3340 unsigned Shifts = IsLE ? i : NumElts - 1 - i;
3371 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3375 Op.getOperand(0), DemandedElts,
false,
Depth + 1);
3381 if (
Op->getFlags().hasNoSignedWrap() &&
3382 Op.getOperand(0) ==
Op.getOperand(1) &&
3400 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3403 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3404 if (
Op.getResNo() == 0)
3411 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3414 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3415 if (
Op.getResNo() == 0)
3454 if (
Op.getResNo() != 1)
3469 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
3483 if (
const APInt *ShMinAmt =
3491 Op->getFlags().hasExact());
3494 if (
const APInt *ShMinAmt =
3502 Op->getFlags().hasExact());
3507 unsigned Amt =
C->getAPIntValue().urem(
BitWidth);
3513 DemandedElts,
Depth + 1);
3538 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3541 unsigned LoBits =
Op.getOperand(0).getScalarValueSizeInBits();
3542 unsigned HiBits =
Op.getOperand(1).getScalarValueSizeInBits();
3545 Known = Known2.
concat(Known);
3559 if (
Op.getResNo() == 0)
3567 EVT EVT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
3608 !
Op.getValueType().isScalableVector()) {
3622 for (
unsigned i = 0; i != NumElts; ++i) {
3623 if (!DemandedElts[i])
3626 if (
auto *CInt = dyn_cast<ConstantInt>(Elt)) {
3632 if (
auto *CFP = dyn_cast<ConstantFP>(Elt)) {
3633 APInt Value = CFP->getValueAPF().bitcastToAPInt();
3644 if (
auto *CInt = dyn_cast<ConstantInt>(Cst)) {
3646 }
else if (
auto *CFP = dyn_cast<ConstantFP>(Cst)) {
3652 }
else if (
Op.getResNo() == 0) {
3653 KnownBits Known0(!LD->getMemoryVT().isScalableVT()
3654 ? LD->getMemoryVT().getFixedSizeInBits()
3656 EVT VT =
Op.getValueType();
3663 if (
const MDNode *MD = LD->getRanges()) {
3674 if (LD->getMemoryVT().isVector())
3675 Known0 = Known0.
trunc(LD->getMemoryVT().getScalarSizeInBits());
3692 if (
Op.getValueType().isScalableVector())
3694 EVT InVT =
Op.getOperand(0).getValueType();
3706 if (
Op.getValueType().isScalableVector())
3708 EVT InVT =
Op.getOperand(0).getValueType();
3724 if (
Op.getValueType().isScalableVector())
3726 EVT InVT =
Op.getOperand(0).getValueType();
3743 EVT VT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
3746 Known.
Zero |= (~InMask);
3747 Known.
One &= (~Known.Zero);
3751 unsigned LogOfAlign =
Log2(cast<AssertAlignSDNode>(
Op)->
getAlign());
3771 Op.getOpcode() ==
ISD::ADD, Flags.hasNoSignedWrap(),
3772 Flags.hasNoUnsignedWrap(), Known, Known2);
3779 if (
Op.getResNo() == 1) {
3790 "We only compute knownbits for the difference here.");
3797 Borrow = Borrow.
trunc(1);
3811 if (
Op.getResNo() == 1) {
3822 assert(
Op.getResNo() == 0 &&
"We only compute knownbits for the sum here.");
3832 Carry = Carry.
trunc(1);
3868 const unsigned Index =
Op.getConstantOperandVal(1);
3869 const unsigned EltBitWidth =
Op.getValueSizeInBits();
3876 Known = Known.
trunc(EltBitWidth);
3892 Known = Known.
trunc(EltBitWidth);
3897 auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
3898 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
3908 if (
Op.getValueType().isScalableVector())
3917 bool DemandedVal =
true;
3918 APInt DemandedVecElts = DemandedElts;
3919 auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
3920 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
3921 unsigned EltIdx = CEltNo->getZExtValue();
3922 DemandedVal = !!DemandedElts[EltIdx];
3931 if (!!DemandedVecElts) {
3949 Known = Known2.
abs();
3980 if (CstLow && CstHigh) {
3985 const APInt &ValueHigh = CstHigh->getAPIntValue();
3986 if (ValueLow.
sle(ValueHigh)) {
3989 unsigned MinSignBits = std::min(LowSignBits, HighSignBits);
4012 if (IsMax && CstLow) {
4036 EVT VT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
4041 if (
Op.getResNo() == 1) {
4068 cast<AtomicSDNode>(
Op)->getMemoryVT().getScalarSizeInBits();
4070 if (
Op.getResNo() == 0) {
4091 if (
Op.getValueType().isScalableVector())
4238 return C->getAPIntValue().zextOrTrunc(
BitWidth).isPowerOf2();
4246 if (
C &&
C->getAPIntValue() == 1)
4256 if (
C &&
C->getAPIntValue().isSignMask())
4268 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(E))
4269 return C->getAPIntValue().zextOrTrunc(BitWidth).isPowerOf2();
4277 if (
C->getAPIntValue().zextOrTrunc(
BitWidth).isPowerOf2())
4314 EVT VT =
Op.getValueType();
4326 unsigned Depth)
const {
4327 EVT VT =
Op.getValueType();
4332 unsigned FirstAnswer = 1;
4334 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
4335 const APInt &Val =
C->getAPIntValue();
4345 unsigned Opcode =
Op.getOpcode();
4349 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getSizeInBits();
4350 return VTBits-Tmp+1;
4352 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getSizeInBits();
4359 unsigned NumSrcBits =
Op.getOperand(0).getValueSizeInBits();
4361 if (NumSrcSignBits > (NumSrcBits - VTBits))
4362 return NumSrcSignBits - (NumSrcBits - VTBits);
4369 if (!DemandedElts[i])
4376 APInt T =
C->getAPIntValue().trunc(VTBits);
4377 Tmp2 =
T.getNumSignBits();
4381 if (
SrcOp.getValueSizeInBits() != VTBits) {
4383 "Expected BUILD_VECTOR implicit truncation");
4384 unsigned ExtraBits =
SrcOp.getValueSizeInBits() - VTBits;
4385 Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1);
4388 Tmp = std::min(Tmp, Tmp2);
4395 APInt DemandedLHS, DemandedRHS;
4399 DemandedLHS, DemandedRHS))
4402 Tmp = std::numeric_limits<unsigned>::max();
4405 if (!!DemandedRHS) {
4407 Tmp = std::min(Tmp, Tmp2);
4412 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4428 if (VTBits == SrcBits)
4434 if ((SrcBits % VTBits) == 0) {
4437 unsigned Scale = SrcBits / VTBits;
4438 APInt SrcDemandedElts =
4448 for (
unsigned i = 0; i != NumElts; ++i)
4449 if (DemandedElts[i]) {
4450 unsigned SubOffset = i % Scale;
4451 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset);
4452 SubOffset = SubOffset * VTBits;
4453 if (Tmp <= SubOffset)
4455 Tmp2 = std::min(Tmp2, Tmp - SubOffset);
4464 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getScalarSizeInBits();
4465 return VTBits - Tmp + 1;
4467 Tmp = VTBits -
Op.getOperand(0).getScalarValueSizeInBits();
4471 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getScalarSizeInBits();
4474 return std::max(Tmp, Tmp2);
4479 EVT SrcVT = Src.getValueType();
4487 if (
const APInt *ShAmt =
4489 Tmp = std::min<uint64_t>(Tmp + ShAmt->getZExtValue(), VTBits);
4492 if (
const APInt *ShAmt =
4496 if (ShAmt->ult(Tmp))
4497 return Tmp - ShAmt->getZExtValue();
4507 FirstAnswer = std::min(Tmp, Tmp2);
4517 if (Tmp == 1)
return 1;
4519 return std::min(Tmp, Tmp2);
4522 if (Tmp == 1)
return 1;
4524 return std::min(Tmp, Tmp2);
4536 if (CstLow && CstHigh) {
4541 Tmp2 = CstHigh->getAPIntValue().getNumSignBits();
4542 return std::min(Tmp, Tmp2);
4551 return std::min(Tmp, Tmp2);
4559 return std::min(Tmp, Tmp2);
4570 if (
Op.getResNo() != 1)
4584 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
4601 unsigned RotAmt =
C->getAPIntValue().urem(VTBits);
4605 RotAmt = (VTBits - RotAmt) % VTBits;
4609 if (Tmp > (RotAmt + 1))
return (Tmp - RotAmt);
4617 if (Tmp == 1)
return 1;
4622 if (CRHS->isAllOnes()) {
4628 if ((Known.
Zero | 1).isAllOnes())
4638 if (Tmp2 == 1)
return 1;
4639 return std::min(Tmp, Tmp2) - 1;
4642 if (Tmp2 == 1)
return 1;
4647 if (CLHS->isZero()) {
4652 if ((Known.
Zero | 1).isAllOnes())
4666 if (Tmp == 1)
return 1;
4667 return std::min(Tmp, Tmp2) - 1;
4671 if (SignBitsOp0 == 1)
4674 if (SignBitsOp1 == 1)
4676 unsigned OutValidBits =
4677 (VTBits - SignBitsOp0 + 1) + (VTBits - SignBitsOp1 + 1);
4678 return OutValidBits > VTBits ? 1 : VTBits - OutValidBits + 1;
4688 unsigned NumSrcBits =
Op.getOperand(0).getScalarValueSizeInBits();
4690 if (NumSrcSignBits > (NumSrcBits - VTBits))
4691 return NumSrcSignBits - (NumSrcBits - VTBits);
4698 const int BitWidth =
Op.getValueSizeInBits();
4699 const int Items =
Op.getOperand(0).getValueSizeInBits() /
BitWidth;
4703 const int rIndex = Items - 1 -
Op.getConstantOperandVal(1);
4718 bool DemandedVal =
true;
4719 APInt DemandedVecElts = DemandedElts;
4720 auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
4721 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
4722 unsigned EltIdx = CEltNo->getZExtValue();
4723 DemandedVal = !!DemandedElts[EltIdx];
4726 Tmp = std::numeric_limits<unsigned>::max();
4732 Tmp = std::min(Tmp, Tmp2);
4734 if (!!DemandedVecElts) {
4736 Tmp = std::min(Tmp, Tmp2);
4738 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4749 const unsigned BitWidth =
Op.getValueSizeInBits();
4750 const unsigned EltBitWidth =
Op.getOperand(0).getScalarValueSizeInBits();
4762 auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
4763 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
4773 if (Src.getValueType().isScalableVector())
4776 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
4785 Tmp = std::numeric_limits<unsigned>::max();
4786 EVT SubVectorVT =
Op.getOperand(0).getValueType();
4789 for (
unsigned i = 0; (i < NumSubVectors) && (Tmp > 1); ++i) {
4791 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
4795 Tmp = std::min(Tmp, Tmp2);
4797 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4810 APInt DemandedSrcElts = DemandedElts;
4813 Tmp = std::numeric_limits<unsigned>::max();
4814 if (!!DemandedSubElts) {
4819 if (!!DemandedSrcElts) {
4821 Tmp = std::min(Tmp, Tmp2);
4823 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4828 if (
const MDNode *Ranges = LD->getRanges()) {
4829 if (DemandedElts != 1)
4834 switch (LD->getExtensionType()) {
4869 Tmp = cast<AtomicSDNode>(
Op)->getMemoryVT().getScalarSizeInBits();
4871 if (
Op.getResNo() == 0) {
4875 return VTBits - Tmp + 1;
4877 return VTBits - Tmp;
4884 if (
Op.getResNo() == 0) {
4887 unsigned ExtType = LD->getExtensionType();
4891 Tmp = LD->getMemoryVT().getScalarSizeInBits();
4892 return VTBits - Tmp + 1;
4894 Tmp = LD->getMemoryVT().getScalarSizeInBits();
4895 return VTBits - Tmp;
4900 Type *CstTy = Cst->getType();
4905 for (
unsigned i = 0; i != NumElts; ++i) {
4906 if (!DemandedElts[i])
4909 if (
auto *CInt = dyn_cast<ConstantInt>(Elt)) {
4911 Tmp = std::min(Tmp,
Value.getNumSignBits());
4914 if (
auto *CFP = dyn_cast<ConstantFP>(Elt)) {
4915 APInt Value = CFP->getValueAPF().bitcastToAPInt();
4916 Tmp = std::min(Tmp,
Value.getNumSignBits());
4942 FirstAnswer = std::max(FirstAnswer, NumBits);
4953 unsigned Depth)
const {
4955 return Op.getScalarValueSizeInBits() - SignBits + 1;
4959 const APInt &DemandedElts,
4960 unsigned Depth)
const {
4962 return Op.getScalarValueSizeInBits() - SignBits + 1;
4966 unsigned Depth)
const {
4972 EVT VT =
Op.getValueType();
4983 const APInt &DemandedElts,
4985 unsigned Depth)
const {
4986 unsigned Opcode =
Op.getOpcode();
5012 if (!DemandedElts[i])
5040 return isGuaranteedNotToBeUndefOrPoison(V, PoisonOnly, Depth + 1);
5046 unsigned Depth)
const {
5048 EVT VT =
Op.getValueType();
5061 unsigned Depth)
const {
5063 EVT VT =
Op.getValueType();
5067 unsigned Opcode =
Op.getOpcode();
5094 if (
Op.getOperand(0).getValueType().isInteger())
5102 if (((
unsigned)CCCode & 0x10U))
5108 (
Op->getFlags().hasNoNaNs() ||
Op->getFlags().hasNoInfs()));
5113 return ConsiderFlags &&
Op->getFlags().hasNonNeg();
5119 return ConsiderFlags && (
Op->getFlags().hasNoSignedWrap() ||
5120 Op->getFlags().hasNoUnsignedWrap());
5128 return ConsiderFlags && (
Op->getFlags().hasNoSignedWrap() ||
5129 Op->getFlags().hasNoUnsignedWrap());
5133 return ConsiderFlags &&
Op->getFlags().hasDisjoint();
5137 EVT VecVT =
Op.getOperand(0).getValueType();
5156 unsigned Opcode =
Op.getOpcode();
5158 return Op->getFlags().hasDisjoint() ||
5167 !isa<ConstantSDNode>(
Op.getOperand(1)))
5187 return !
C->getValueAPF().isNaN() ||
5188 (SNaN && !
C->getValueAPF().isSignaling());
5191 unsigned Opcode =
Op.getOpcode();
5299 assert(
Op.getValueType().isFloatingPoint() &&
5300 "Floating point type expected");
5311 assert(!
Op.getValueType().isFloatingPoint() &&
5312 "Floating point types unsupported - use isKnownNeverZeroFloat");
5321 switch (
Op.getOpcode()) {
5335 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
5339 if (ValKnown.
One[0])
5371 if (
Op->getFlags().hasExact())
5387 if (
Op->getFlags().hasExact())
5392 if (
Op->getFlags().hasNoUnsignedWrap())
5403 std::optional<bool> ne =
5410 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
5426 if (
A ==
B)
return true;
5431 if (CA->isZero() && CB->isZero())
return true;
5440 return V.getOperand(0);
5447 SDValue ExtArg = V.getOperand(0);
5466 NotOperand = NotOperand->getOperand(0);
5468 if (
Other == NotOperand)
5471 return NotOperand ==
Other->getOperand(0) ||
5472 NotOperand ==
Other->getOperand(1);
5478 A =
A->getOperand(0);
5481 B =
B->getOperand(0);
5484 return MatchNoCommonBitsPattern(
A->getOperand(0),
A->getOperand(1),
B) ||
5485 MatchNoCommonBitsPattern(
A->getOperand(1),
A->getOperand(0),
B);
5491 assert(
A.getValueType() ==
B.getValueType() &&
5492 "Values must have the same type");
5502 if (cast<ConstantSDNode>(Step)->
isZero())
5511 int NumOps = Ops.
size();
5512 assert(NumOps != 0 &&
"Can't build an empty vector!");
5514 "BUILD_VECTOR cannot be used with scalable types");
5516 "Incorrect element count in BUILD_VECTOR!");
5524 bool IsIdentity =
true;
5525 for (
int i = 0; i != NumOps; ++i) {
5527 Ops[i].getOperand(0).getValueType() != VT ||
5528 (IdentitySrc && Ops[i].getOperand(0) != IdentitySrc) ||
5529 !isa<ConstantSDNode>(Ops[i].getOperand(1)) ||
5530 Ops[i].getConstantOperandAPInt(1) != i) {
5534 IdentitySrc = Ops[i].getOperand(0);
5547 assert(!Ops.
empty() &&
"Can't concatenate an empty list of vectors!");
5550 return Ops[0].getValueType() ==
Op.getValueType();
5552 "Concatenation of vectors with inconsistent value types!");
5553 assert((Ops[0].getValueType().getVectorElementCount() * Ops.
size()) ==
5555 "Incorrect element count in vector concatenation!");
5557 if (Ops.
size() == 1)
5568 bool IsIdentity =
true;
5569 for (
unsigned i = 0, e = Ops.
size(); i != e; ++i) {
5571 unsigned IdentityIndex = i *
Op.getValueType().getVectorMinNumElements();
5573 Op.getOperand(0).getValueType() != VT ||
5574 (IdentitySrc &&
Op.getOperand(0) != IdentitySrc) ||
5575 Op.getConstantOperandVal(1) != IdentityIndex) {
5579 assert((!IdentitySrc || IdentitySrc ==
Op.getOperand(0)) &&
5580 "Unexpected identity source vector for concat of extracts");
5581 IdentitySrc =
Op.getOperand(0);
5584 assert(IdentitySrc &&
"Failed to set source vector of extracts");
5599 EVT OpVT =
Op.getValueType();
5611 SVT = (SVT.
bitsLT(
Op.getValueType()) ?
Op.getValueType() : SVT);
5637 auto *
N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(),
5639 CSEMap.InsertNode(
N, IP);
5652 return getNode(Opcode,
DL, VT, N1, Flags);
5703 "STEP_VECTOR can only be used with scalable types");
5706 "Unexpected step operand");
5728 "Invalid FP cast!");
5732 "Vector element count mismatch!");
5750 "Invalid SIGN_EXTEND!");
5752 "SIGN_EXTEND result type type should be vector iff the operand "
5757 "Vector element count mismatch!");
5771 "Invalid ZERO_EXTEND!");
5773 "ZERO_EXTEND result type type should be vector iff the operand "
5778 "Vector element count mismatch!");
5809 "Invalid ANY_EXTEND!");
5811 "ANY_EXTEND result type type should be vector iff the operand "
5816 "Vector element count mismatch!");
5841 "Invalid TRUNCATE!");
5843 "TRUNCATE result type type should be vector iff the operand "
5848 "Vector element count mismatch!");
5871 assert(VT.
isVector() &&
"This DAG node is restricted to vector types.");
5873 "The input must be the same size or smaller than the result.");
5876 "The destination vector type must have fewer lanes than the input.");
5886 "BSWAP types must be a multiple of 16 bits!");
5900 "Cannot BITCAST between types of different sizes!");
5913 "Illegal SCALAR_TO_VECTOR node!");
5966 if (VT != MVT::Glue) {
5970 if (
SDNode *
E = FindNodeOrInsertPos(
ID,
DL, IP)) {
5971 E->intersectFlagsWith(Flags);
5975 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
5977 createOperands(
N, Ops);
5978 CSEMap.InsertNode(
N, IP);
5980 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
5981 createOperands(
N, Ops);
6015 if (!C2.getBoolValue())
6019 if (!C2.getBoolValue())
6023 if (!C2.getBoolValue())
6027 if (!C2.getBoolValue())
6055 return std::nullopt;
6061 bool IsUndef1,
const APInt &C2,
6063 if (!(IsUndef1 || IsUndef2))
6071 return std::nullopt;
6081 auto *C2 = dyn_cast<ConstantSDNode>(N2);
6084 int64_t
Offset = C2->getSExtValue();
6102 assert(Ops.
size() == 2 &&
"Div/rem should have 2 operands");
6109 [](
SDValue V) { return V.isUndef() ||
6110 isNullConstant(V); });
6130 unsigned NumOps = Ops.
size();
6146 if (
auto *
C = dyn_cast<ConstantSDNode>(N1)) {
6147 const APInt &Val =
C->getAPIntValue();
6151 C->isTargetOpcode(),
C->isOpaque());
6158 C->isTargetOpcode(),
C->isOpaque());
6163 C->isTargetOpcode(),
C->isOpaque());
6165 C->isTargetOpcode(),
C->isOpaque());
6212 if (VT == MVT::f16 &&
C->getValueType(0) == MVT::i16)
6214 if (VT == MVT::f32 &&
C->getValueType(0) == MVT::i32)
6216 if (VT == MVT::f64 &&
C->getValueType(0) == MVT::i64)
6218 if (VT == MVT::f128 &&
C->getValueType(0) == MVT::i128)
6225 if (
auto *
C = dyn_cast<ConstantFPSDNode>(N1)) {
6279 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
6282 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::f16)
6285 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::bf16)
6288 if (VT == MVT::i32 &&
C->getValueType(0) == MVT::f32)
6291 if (VT == MVT::i64 &&
C->getValueType(0) == MVT::f64)
6292 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
6307 if (
auto *C1 = dyn_cast<ConstantSDNode>(Ops[0])) {
6308 if (
auto *C2 = dyn_cast<ConstantSDNode>(Ops[1])) {
6309 if (C1->isOpaque() || C2->isOpaque())
6312 std::optional<APInt> FoldAttempt =
6313 FoldValue(Opcode, C1->getAPIntValue(), C2->getAPIntValue());
6319 "Can't fold vectors ops with scalar operands");
6340 Ops[0].getValueType() == VT && Ops[1].getValueType() == VT &&
6345 auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
6346 auto *BV2 = dyn_cast<BuildVectorSDNode>(N2);
6353 if (BV1->getConstantRawBits(IsLE, EltBits, RawBits1, UndefElts1) &&
6354 BV2->getConstantRawBits(IsLE, EltBits, RawBits2, UndefElts2)) {
6358 Opcode, RawBits1[
I], UndefElts1[
I], RawBits2[
I], UndefElts2[
I]);
6369 DstBits, RawBits, DstUndefs,
6371 EVT BVEltVT = BV1->getOperand(0).getValueType();
6374 for (
unsigned I = 0,
E = DstBits.
size();
I !=
E; ++
I) {
6392 ? Ops[0].getConstantOperandAPInt(0) * RHSVal
6393 : Ops[0].getConstantOperandAPInt(0) << RHSVal;
6398 auto IsScalarOrSameVectorSize = [NumElts](
const SDValue &
Op) {
6399 return !
Op.getValueType().isVector() ||
6400 Op.getValueType().getVectorElementCount() == NumElts;
6403 auto IsBuildVectorSplatVectorOrUndef = [](
const SDValue &
Op) {
6412 if (!
llvm::all_of(Ops, IsBuildVectorSplatVectorOrUndef) ||
6441 for (
unsigned I = 0;
I != NumVectorElts;
I++) {
6444 EVT InSVT =
Op.getValueType().getScalarType();
6466 !isa<ConstantSDNode>(ScalarOp) &&
6480 if (LegalSVT != SVT)
6481 ScalarResult =
getNode(ExtendCode,
DL, LegalSVT, ScalarResult);
6499 if (Ops.
size() != 2)
6510 if (N1CFP && N2CFP) {
6557 if (N1C && N1C->getValueAPF().isNegZero() && N2.
isUndef())
6585 ID.AddInteger(
A.value());
6591 auto *
N = newSDNode<AssertAlignSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
6593 createOperands(
N, {Val});
6595 CSEMap.InsertNode(
N, IP);
6608 return getNode(Opcode,
DL, VT, N1, N2, Flags);
6622 if ((N1C && !N2C) || (N1CFP && !N2CFP))
6636 "Operand is DELETED_NODE!");
6640 auto *N1C = dyn_cast<ConstantSDNode>(N1);
6641 auto *N2C = dyn_cast<ConstantSDNode>(N2);
6652 N2.
getValueType() == MVT::Other &&
"Invalid token factor!");
6656 if (N1 == N2)
return N1;
6672 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6674 N1.
getValueType() == VT &&
"Binary operator types must match!");
6677 if (N2CV && N2CV->
isZero())
6686 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6688 N1.
getValueType() == VT &&
"Binary operator types must match!");
6691 if (N2CV && N2CV->
isZero())
6698 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6700 N1.
getValueType() == VT &&
"Binary operator types must match!");
6705 const APInt &N2CImm = N2C->getAPIntValue();
6719 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6721 N1.
getValueType() == VT &&
"Binary operator types must match!");
6733 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6735 N1.
getValueType() == VT &&
"Binary operator types must match!");
6739 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6741 N1.
getValueType() == VT &&
"Binary operator types must match!");
6747 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6749 N1.
getValueType() == VT &&
"Binary operator types must match!");
6760 N1.
getValueType() == VT &&
"Binary operator types must match!");
6768 "Invalid FCOPYSIGN!");
6773 const APInt &ShiftImm = N2C->getAPIntValue();
6785 "Shift operators return type must be the same as their first arg");
6787 "Shifts only work on integers");
6789 "Vector shift amounts must be in the same as their first arg");
6796 "Invalid use of small shift amount with oversized value!");
6803 if (N2CV && N2CV->
isZero())
6810 N2C && (N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
6811 "Invalid FP_ROUND!");
6816 EVT EVT = cast<VTSDNode>(N2)->getVT();
6819 "Cannot *_EXTEND_INREG FP types");
6821 "AssertSExt/AssertZExt type should be the vector element type "
6822 "rather than the vector type!");
6828 EVT EVT = cast<VTSDNode>(N2)->getVT();
6831 "Cannot *_EXTEND_INREG FP types");
6833 "SIGN_EXTEND_INREG type should be vector iff the operand "
6837 "Vector element counts must match in SIGN_EXTEND_INREG");
6839 if (
EVT == VT)
return N1;
6849 const APInt &Val = N1C->getAPIntValue();
6850 return SignExtendInReg(Val, VT);
6863 APInt Val =
C->getAPIntValue();
6864 Ops.
push_back(SignExtendInReg(Val, OpVT));
6882 "FP_TO_*INT_SAT type should be vector iff the operand type is "
6886 "Vector element counts must match in FP_TO_*INT_SAT");
6887 assert(!cast<VTSDNode>(N2)->getVT().isVector() &&
6888 "Type to saturate to must be a scalar.");
6895 "The result of EXTRACT_VECTOR_ELT must be at least as wide as the \
6896 element type of the vector.");
6928 "BUILD_VECTOR used for scalable vectors");
6951 if (N1Op2C && N2C) {
6981 assert(N2C && (
unsigned)N2C->getZExtValue() < 2 &&
"Bad EXTRACT_ELEMENT!");
6985 "Wrong types for EXTRACT_ELEMENT!");
6996 unsigned Shift = ElementSize * N2C->getZExtValue();
6997 const APInt &Val = N1C->getAPIntValue();
7004 "Extract subvector VTs must be vectors!");
7006 "Extract subvector VTs must have the same element type!");
7008 "Cannot extract a scalable vector from a fixed length vector!");
7011 "Extract subvector must be from larger vector to smaller vector!");
7012 assert(N2C &&
"Extract subvector index must be a constant");
7016 "Extract subvector overflow!");
7017 assert(N2C->getAPIntValue().getBitWidth() ==
7019 "Constant index for EXTRACT_SUBVECTOR has an invalid size");
7034 return N1.
getOperand(N2C->getZExtValue() / Factor);
7102 if (VT != MVT::Glue) {
7106 if (
SDNode *
E = FindNodeOrInsertPos(
ID,
DL, IP)) {
7107 E->intersectFlagsWith(Flags);
7111 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7113 createOperands(
N, Ops);
7114 CSEMap.InsertNode(
N, IP);
7116 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7117 createOperands(
N, Ops);
7131 return getNode(Opcode,
DL, VT, N1, N2, N3, Flags);
7140 "Operand is DELETED_NODE!");
7151 if (N1CFP && N2CFP && N3CFP) {
7180 "SETCC operands must have the same type!");
7182 "SETCC type should be vector iff the operand type is vector!");
7185 "SETCC vector element counts must match!");
7205 if (cast<ConstantSDNode>(N3)->
isZero())
7235 "Dest and insert subvector source types must match!");
7237 "Insert subvector VTs must be vectors!");
7239 "Insert subvector VTs must have the same element type!");
7241 "Cannot insert a scalable vector into a fixed length vector!");
7244 "Insert subvector must be from smaller vector to larger vector!");
7245 assert(isa<ConstantSDNode>(N3) &&
7246 "Insert subvector index must be constant");
7250 "Insert subvector overflow!");
7253 "Constant index for INSERT_SUBVECTOR has an invalid size");
7271 case ISD::VP_TRUNCATE:
7272 case ISD::VP_SIGN_EXTEND:
7273 case ISD::VP_ZERO_EXTEND:
7284 if (VT != MVT::Glue) {
7288 if (
SDNode *
E = FindNodeOrInsertPos(
ID,
DL, IP)) {
7289 E->intersectFlagsWith(Flags);
7293 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7295 createOperands(
N, Ops);
7296 CSEMap.InsertNode(
N, IP);
7298 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7299 createOperands(
N, Ops);
7310 SDValue Ops[] = { N1, N2, N3, N4 };
7317 SDValue Ops[] = { N1, N2, N3, N4, N5 };
7335 if (FI->getIndex() < 0)
7350 assert(
C->getAPIntValue().getBitWidth() == 8);
7355 return DAG.
getConstant(Val, dl, VT,
false, IsOpaque);
7361 assert(
Value.getValueType() == MVT::i8 &&
"memset with non-byte fill value?");
7377 if (VT !=
Value.getValueType())
7390 if (Slice.
Array ==
nullptr) {
7393 if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
7408 unsigned NumVTBytes = NumVTBits / 8;
7409 unsigned NumBytes = std::min(NumVTBytes,
unsigned(Slice.
Length));
7411 APInt Val(NumVTBits, 0);
7413 for (
unsigned i = 0; i != NumBytes; ++i)
7416 for (
unsigned i = 0; i != NumBytes; ++i)
7417 Val |= (
uint64_t)(
unsigned char)Slice[i] << (NumVTBytes-i-1)*8;
7436 APInt(
Base.getValueSizeInBits().getFixedValue(),
7437 Offset.getKnownMinValue()));
7448 EVT BasePtrVT =
Ptr.getValueType();
7457 G = cast<GlobalAddressSDNode>(Src);
7458 else if (Src.getOpcode() ==
ISD::ADD &&
7461 G = cast<GlobalAddressSDNode>(Src.getOperand(0));
7462 SrcDelta = Src.getConstantOperandVal(1);
7468 SrcDelta +
G->getOffset());
7484 assert(OutLoadChains.
size() &&
"Missing loads in memcpy inlining");
7485 assert(OutStoreChains.
size() &&
"Missing stores in memcpy inlining");
7487 for (
unsigned i =
From; i < To; ++i) {
7489 GluedLoadChains.
push_back(OutLoadChains[i]);
7496 for (
unsigned i =
From; i < To; ++i) {
7497 StoreSDNode *ST = dyn_cast<StoreSDNode>(OutStoreChains[i]);
7499 ST->getBasePtr(), ST->getMemoryVT(),
7500 ST->getMemOperand());
7508 bool isVol,
bool AlwaysInline,
7524 std::vector<EVT> MemOps;
7525 bool DstAlignCanChange =
false;
7531 DstAlignCanChange =
true;
7533 if (!SrcAlign || Alignment > *SrcAlign)
7534 SrcAlign = Alignment;
7535 assert(SrcAlign &&
"SrcAlign must be set");
7539 bool isZeroConstant = CopyFromConstant && Slice.
Array ==
nullptr;
7541 const MemOp Op = isZeroConstant
7545 *SrcAlign, isVol, CopyFromConstant);
7551 if (DstAlignCanChange) {
7552 Type *Ty = MemOps[0].getTypeForEVT(
C);
7553 Align NewAlign =
DL.getABITypeAlign(Ty);
7559 if (!
TRI->hasStackRealignment(MF))
7560 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7563 if (NewAlign > Alignment) {
7567 Alignment = NewAlign;
7575 const Value *SrcVal = dyn_cast_if_present<const Value *>(SrcPtrInfo.
V);
7585 unsigned NumMemOps = MemOps.
size();
7587 for (
unsigned i = 0; i != NumMemOps; ++i) {
7592 if (VTSize >
Size) {
7595 assert(i == NumMemOps-1 && i != 0);
7596 SrcOff -= VTSize -
Size;
7597 DstOff -= VTSize -
Size;
7600 if (CopyFromConstant &&
7608 if (SrcOff < Slice.
Length) {
7610 SubSlice.
move(SrcOff);
7613 SubSlice.
Array =
nullptr;
7615 SubSlice.
Length = VTSize;
7618 if (
Value.getNode()) {
7622 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
7627 if (!Store.getNode()) {
7636 bool isDereferenceable =
7639 if (isDereferenceable)
7654 DstPtrInfo.
getWithOffset(DstOff), VT, Alignment, MMOFlags, NewAAInfo);
7664 unsigned NumLdStInMemcpy = OutStoreChains.
size();
7666 if (NumLdStInMemcpy) {
7672 for (
unsigned i = 0; i < NumLdStInMemcpy; ++i) {
7678 if (NumLdStInMemcpy <= GluedLdStLimit) {
7680 NumLdStInMemcpy, OutLoadChains,
7683 unsigned NumberLdChain = NumLdStInMemcpy / GluedLdStLimit;
7684 unsigned RemainingLdStInMemcpy = NumLdStInMemcpy % GluedLdStLimit;
7685 unsigned GlueIter = 0;
7687 for (
unsigned cnt = 0; cnt < NumberLdChain; ++cnt) {
7688 unsigned IndexFrom = NumLdStInMemcpy - GlueIter - GluedLdStLimit;
7689 unsigned IndexTo = NumLdStInMemcpy - GlueIter;
7692 OutLoadChains, OutStoreChains);
7693 GlueIter += GluedLdStLimit;
7697 if (RemainingLdStInMemcpy) {
7699 RemainingLdStInMemcpy, OutLoadChains,
7711 bool isVol,
bool AlwaysInline,
7725 std::vector<EVT> MemOps;
7726 bool DstAlignCanChange =
false;
7732 DstAlignCanChange =
true;
7734 if (!SrcAlign || Alignment > *SrcAlign)
7735 SrcAlign = Alignment;
7736 assert(SrcAlign &&
"SrcAlign must be set");
7746 if (DstAlignCanChange) {
7747 Type *Ty = MemOps[0].getTypeForEVT(
C);
7748 Align NewAlign =
DL.getABITypeAlign(Ty);
7754 if (!
TRI->hasStackRealignment(MF))
7755 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7758 if (NewAlign > Alignment) {
7762 Alignment = NewAlign;
7776 unsigned NumMemOps = MemOps.
size();
7777 for (
unsigned i = 0; i < NumMemOps; i++) {
7782 bool isDereferenceable =
7785 if (isDereferenceable)
7791 SrcPtrInfo.
getWithOffset(SrcOff), *SrcAlign, SrcMMOFlags, NewAAInfo);
7798 for (
unsigned i = 0; i < NumMemOps; i++) {
7804 Chain, dl, LoadValues[i],
7806 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
7846 std::vector<EVT> MemOps;
7847 bool DstAlignCanChange =
false;
7853 DstAlignCanChange =
true;
7859 MemOp::Set(
Size, DstAlignCanChange, Alignment, IsZeroVal, isVol),
7863 if (DstAlignCanChange) {
7866 Align NewAlign =
DL.getABITypeAlign(Ty);
7872 if (!
TRI->hasStackRealignment(MF))
7873 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7876 if (NewAlign > Alignment) {
7880 Alignment = NewAlign;
7886 unsigned NumMemOps = MemOps.size();
7889 EVT LargestVT = MemOps[0];
7890 for (
unsigned i = 1; i < NumMemOps; i++)
7891 if (MemOps[i].bitsGT(LargestVT))
7892 LargestVT = MemOps[i];
7899 for (
unsigned i = 0; i < NumMemOps; i++) {
7902 if (VTSize >
Size) {
7905 assert(i == NumMemOps-1 && i != 0);
7906 DstOff -= VTSize -
Size;
7913 if (VT.
bitsLT(LargestVT)) {
7934 assert(
Value.getValueType() == VT &&
"Value with wrong type.");
7961 bool isVol,
bool AlwaysInline,
bool isTailCall,
7970 if (ConstantSize->
isZero())
7974 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
7975 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
7976 if (Result.getNode())
7984 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline,
7985 DstPtrInfo, SrcPtrInfo);
7986 if (Result.getNode())
7993 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
7995 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
7996 isVol,
true, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
8012 Entry.Node = Dst; Args.push_back(Entry);
8013 Entry.Node = Src; Args.push_back(Entry);
8016 Entry.Node =
Size; Args.push_back(Entry);
8022 Dst.getValueType().getTypeForEVT(*
getContext()),
8029 std::pair<SDValue,SDValue> CallResult = TLI->
LowerCallTo(CLI);
8030 return CallResult.second;
8035 Type *SizeTy,
unsigned ElemSz,
8044 Args.push_back(Entry);
8047 Args.push_back(Entry);
8051 Args.push_back(Entry);
8055 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8069 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8070 return CallResult.second;
8075 bool isVol,
bool isTailCall,
8084 if (ConstantSize->
isZero())
8088 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8089 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo);
8090 if (Result.getNode())
8099 Alignment, isVol, DstPtrInfo, SrcPtrInfo);
8100 if (Result.getNode())
8114 Entry.Node = Dst; Args.push_back(Entry);
8115 Entry.Node = Src; Args.push_back(Entry);
8118 Entry.Node =
Size; Args.push_back(Entry);
8124 Dst.getValueType().getTypeForEVT(*
getContext()),
8131 std::pair<SDValue,SDValue> CallResult = TLI->
LowerCallTo(CLI);
8132 return CallResult.second;
8137 Type *SizeTy,
unsigned ElemSz,
8146 Args.push_back(Entry);
8149 Args.push_back(Entry);
8153 Args.push_back(Entry);
8157 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8171 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8172 return CallResult.second;
8177 bool isVol,
bool AlwaysInline,
bool isTailCall,
8185 if (ConstantSize->
isZero())
8190 isVol,
false, DstPtrInfo, AAInfo);
8192 if (Result.getNode())
8200 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline, DstPtrInfo);
8201 if (Result.getNode())
8208 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
8211 isVol,
true, DstPtrInfo, AAInfo);
8213 "getMemsetStores must return a valid sequence when AlwaysInline");
8230 const auto CreateEntry = [](
SDValue Node,
Type *Ty) {
8241 Args.push_back(CreateEntry(
Size,
DL.getIntPtrType(Ctx)));
8248 Args.push_back(CreateEntry(Src, Src.getValueType().getTypeForEVT(Ctx)));
8249 Args.push_back(CreateEntry(
Size,
DL.getIntPtrType(Ctx)));
8251 Dst.getValueType().getTypeForEVT(Ctx),
8259 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8260 return CallResult.second;
8265 Type *SizeTy,
unsigned ElemSz,
8273 Args.push_back(Entry);
8277 Args.push_back(Entry);
8281 Args.push_back(Entry);
8285 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8299 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8300 return CallResult.second;
8312 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
8313 cast<AtomicSDNode>(
E)->refineAlignment(MMO);
8318 VTList, MemVT, MMO);
8319 createOperands(
N, Ops);
8321 CSEMap.InsertNode(
N, IP);
8335 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8360 "Invalid Atomic Op");
8367 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8377 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8382 if (Ops.
size() == 1)
8415 (Opcode <= (
unsigned)std::numeric_limits<int>::max() &&
8417 "Opcode is not a memory-accessing opcode!");
8421 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
8424 ID.AddInteger(getSyntheticNodeSubclassData<MemIntrinsicSDNode>(
8425 Opcode, dl.
getIROrder(), VTList, MemVT, MMO));
8430 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
8431 cast<MemIntrinsicSDNode>(
E)->refineAlignment(MMO);
8436 VTList, MemVT, MMO);
8437 createOperands(
N, Ops);
8439 CSEMap.InsertNode(
N, IP);
8442 VTList, MemVT, MMO);
8443 createOperands(
N, Ops);
8452 SDValue Chain,
int FrameIndex,
8464 ID.AddInteger(FrameIndex);
8468 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP))
8473 createOperands(
N, Ops);
8474 CSEMap.InsertNode(
N, IP);
8489 ID.AddInteger(Guid);
8492 if (
SDNode *
E = FindNodeOrInsertPos(
ID, Dl, IP))
8495 auto *
N = newSDNode<PseudoProbeSDNode>(
8497 createOperands(
N, Ops);
8498 CSEMap.InsertNode(
N, IP);
8519 !isa<ConstantSDNode>(
Ptr.getOperand(1)) ||
8520 !isa<FrameIndexSDNode>(
Ptr.getOperand(0)))
8523 int FI = cast<FrameIndexSDNode>(
Ptr.getOperand(0))->getIndex();
8526 Offset + cast<ConstantSDNode>(
Ptr.getOperand(1))->getSExtValue());
8537 if (
ConstantSDNode *OffsetNode = dyn_cast<ConstantSDNode>(OffsetOp))
8552 "Invalid chain type");
8564 Alignment, AAInfo, Ranges);
8575 assert(VT == MemVT &&
"Non-extending load from different memory type!");
8579 "Should only be an extending load, not truncating!");
8581 "Cannot convert from FP to Int or Int -> FP!");
8583 "Cannot use an ext load to convert to or from a vector!");
8586 "Cannot use an ext load to change the number of vector elements!");
8598 ID.AddInteger(getSyntheticNodeSubclassData<LoadSDNode>(
8599 dl.
getIROrder(), VTs, AM, ExtType, MemVT, MMO));
8603 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
8604 cast<LoadSDNode>(
E)->refineAlignment(MMO);
8608 ExtType, MemVT, MMO);
8609 createOperands(
N, Ops);
8611 CSEMap.InsertNode(
N, IP);
8625 PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges);
8643 MemVT, Alignment, MMOFlags, AAInfo);
8658 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
8661 LD->getMemOperand()->getFlags() &
8664 LD->getChain(),
Base,
Offset, LD->getPointerInfo(),
8665 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo());
8692 "Invalid chain type");
8700 ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
8705 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
8706 cast<StoreSDNode>(
E)->refineAlignment(MMO);
8711 createOperands(
N, Ops);
8713 CSEMap.InsertNode(
N, IP);
8726 "Invalid chain type");
8747 "Invalid chain type");
8752 "Should only be a truncating store, not extending!");
8754 "Can't do FP-INT conversion!");
8756 "Cannot use trunc store to convert to or from a vector!");
8759 "Cannot use trunc store to change the number of vector elements!");
8767 ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
8772 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
8773 cast<StoreSDNode>(
E)->refineAlignment(MMO);
8778 createOperands(
N, Ops);
8780 CSEMap.InsertNode(
N, IP);
8791 assert(ST->getOffset().isUndef() &&
"Store is already a indexed store!");
8796 ID.AddInteger(ST->getMemoryVT().getRawBits());
8797 ID.AddInteger(ST->getRawSubclassData());
8798 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
8799 ID.AddInteger(ST->getMemOperand()->getFlags());
8801 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP))
8805 ST->isTruncatingStore(), ST->getMemoryVT(),
8806 ST->getMemOperand());
8807 createOperands(
N, Ops);
8809 CSEMap.InsertNode(
N, IP);
8821 const MDNode *Ranges,
bool IsExpanding) {
8834 Alignment, AAInfo, Ranges);
8835 return getLoadVP(AM, ExtType, VT, dl, Chain,
Ptr,
Offset, Mask, EVL, MemVT,
8854 ID.AddInteger(getSyntheticNodeSubclassData<VPLoadSDNode>(
8855 dl.
getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
8859 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
8860 cast<VPLoadSDNode>(
E)->refineAlignment(MMO);
8864 ExtType, IsExpanding, MemVT, MMO);
8865 createOperands(
N, Ops);
8867 CSEMap.InsertNode(
N, IP);
8883 Mask, EVL, PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges,
8892 Mask, EVL, VT, MMO, IsExpanding);
8901 const AAMDNodes &AAInfo,
bool IsExpanding) {
8904 EVL, PtrInfo, MemVT, Alignment, MMOFlags, AAInfo,
nullptr,
8914 EVL, MemVT, MMO, IsExpanding);
8920 auto *LD = cast<VPLoadSDNode>(OrigLoad);
8921 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
8924 LD->getMemOperand()->getFlags() &
8928 LD->getVectorLength(), LD->getPointerInfo(),
8929 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo(),
8930 nullptr, LD->isExpandingLoad());
8937 bool IsCompressing) {
8947 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
8948 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
8952 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
8953 cast<VPStoreSDNode>(
E)->refineAlignment(MMO);
8957 IsTruncating, IsCompressing, MemVT, MMO);
8958 createOperands(
N, Ops);
8960 CSEMap.InsertNode(
N, IP);
8973 bool IsCompressing) {
8994 bool IsCompressing) {
9001 false, IsCompressing);
9004 "Should only be a truncating store, not extending!");
9007 "Cannot use trunc store to convert to or from a vector!");
9010 "Cannot use trunc store to change the number of vector elements!");
9014 SDValue Ops[] = {Chain, Val,
Ptr, Undef, Mask, EVL};
9018 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
9023 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
9024 cast<VPStoreSDNode>(
E)->refineAlignment(MMO);
9030 createOperands(
N, Ops);
9032 CSEMap.InsertNode(
N, IP);
9042 auto *ST = cast<VPStoreSDNode>(OrigStore);
9043 assert(ST->getOffset().isUndef() &&
"Store is already an indexed store!");
9045 SDValue Ops[] = {ST->getChain(), ST->getValue(),
Base,
9046 Offset, ST->getMask(), ST->getVectorLength()};
9049 ID.AddInteger(ST->getMemoryVT().getRawBits());
9050 ID.AddInteger(ST->getRawSubclassData());
9051 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
9052 ID.AddInteger(ST->getMemOperand()->getFlags());
9054 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP))
9057 auto *
N = newSDNode<VPStoreSDNode>(
9059 ST->isCompressingStore(), ST->getMemoryVT(), ST->getMemOperand());
9060 createOperands(
N, Ops);
9062 CSEMap.InsertNode(
N, IP);
9082 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedLoadSDNode>(
9083 DL.getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
9087 if (
SDNode *
E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9088 cast<VPStridedLoadSDNode>(
E)->refineAlignment(MMO);
9093 newSDNode<VPStridedLoadSDNode>(
DL.getIROrder(),
DL.getDebugLoc(), VTs, AM,
9094 ExtType, IsExpanding, MemVT, MMO);
9095 createOperands(
N, Ops);
9096 CSEMap.InsertNode(
N, IP);
9110 Undef, Stride, Mask, EVL, VT, MMO, IsExpanding);
9119 Stride, Mask, EVL, MemVT, MMO, IsExpanding);
9128 bool IsTruncating,
bool IsCompressing) {
9138 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
9139 DL.getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9142 if (
SDNode *
E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9143 cast<VPStridedStoreSDNode>(
E)->refineAlignment(MMO);
9146 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
9147 VTs, AM, IsTruncating,
9148 IsCompressing, MemVT, MMO);
9149 createOperands(
N, Ops);
9151 CSEMap.InsertNode(
N, IP);
9163 bool IsCompressing) {
9170 false, IsCompressing);
9173 "Should only be a truncating store, not extending!");
9176 "Cannot use trunc store to convert to or from a vector!");
9179 "Cannot use trunc store to change the number of vector elements!");
9183 SDValue Ops[] = {Chain, Val,
Ptr, Undef, Stride, Mask, EVL};
9187 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
9191 if (
SDNode *
E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9192 cast<VPStridedStoreSDNode>(
E)->refineAlignment(MMO);
9195 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
9197 IsCompressing, SVT, MMO);
9198 createOperands(
N, Ops);
9200 CSEMap.InsertNode(
N, IP);
9210 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9215 ID.AddInteger(getSyntheticNodeSubclassData<VPGatherSDNode>(
9220 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
9221 cast<VPGatherSDNode>(
E)->refineAlignment(MMO);
9226 VT, MMO, IndexType);
9227 createOperands(
N, Ops);
9229 assert(
N->getMask().getValueType().getVectorElementCount() ==
9230 N->getValueType(0).getVectorElementCount() &&
9231 "Vector width mismatch between mask and data");
9232 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9233 N->getValueType(0).getVectorElementCount().isScalable() &&
9234 "Scalable flags of index and data do not match");
9236 N->getIndex().getValueType().getVectorElementCount(),
9237 N->getValueType(0).getVectorElementCount()) &&
9238 "Vector width mismatch between index and data");
9239 assert(isa<ConstantSDNode>(
N->getScale()) &&
9240 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9241 "Scale should be a constant power of 2");
9243 CSEMap.InsertNode(
N, IP);
9254 assert(Ops.
size() == 7 &&
"Incompatible number of operands");
9259 ID.AddInteger(getSyntheticNodeSubclassData<VPScatterSDNode>(
9264 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
9265 cast<VPScatterSDNode>(
E)->refineAlignment(MMO);
9269 VT, MMO, IndexType);
9270 createOperands(
N, Ops);
9272 assert(
N->getMask().getValueType().getVectorElementCount() ==
9273 N->getValue().getValueType().getVectorElementCount() &&
9274 "Vector width mismatch between mask and data");
9276 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9277 N->getValue().getValueType().getVectorElementCount().isScalable() &&
9278 "Scalable flags of index and data do not match");
9280 N->getIndex().getValueType().getVectorElementCount(),
9281 N->getValue().getValueType().getVectorElementCount()) &&
9282 "Vector width mismatch between index and data");
9283 assert(isa<ConstantSDNode>(
N->getScale()) &&
9284 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9285 "Scale should be a constant power of 2");
9287 CSEMap.InsertNode(
N, IP);
9302 "Unindexed masked load with an offset!");
9309 ID.AddInteger(getSyntheticNodeSubclassData<MaskedLoadSDNode>(
9310 dl.
getIROrder(), VTs, AM, ExtTy, isExpanding, MemVT, MMO));
9314 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
9315 cast<MaskedLoadSDNode>(
E)->refineAlignment(MMO);
9319 AM, ExtTy, isExpanding, MemVT, MMO);
9320 createOperands(
N, Ops);
9322 CSEMap.InsertNode(
N, IP);
9333 assert(LD->getOffset().isUndef() &&
"Masked load is already a indexed load!");
9335 Offset, LD->getMask(), LD->getPassThru(),
9336 LD->getMemoryVT(), LD->getMemOperand(), AM,
9337 LD->getExtensionType(), LD->isExpandingLoad());
9345 bool IsCompressing) {
9347 "Invalid chain type");
9350 "Unindexed masked store with an offset!");
9357 ID.AddInteger(getSyntheticNodeSubclassData<MaskedStoreSDNode>(
9358 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9362 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
9363 cast<MaskedStoreSDNode>(
E)->refineAlignment(MMO);
9368 IsTruncating, IsCompressing, MemVT, MMO);
9369 createOperands(
N, Ops);
9371 CSEMap.InsertNode(
N, IP);
9382 assert(ST->getOffset().isUndef() &&
9383 "Masked store is already a indexed store!");
9385 ST->getMask(), ST->getMemoryVT(), ST->getMemOperand(),
9386 AM, ST->isTruncatingStore(), ST->isCompressingStore());
9394 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9399 ID.AddInteger(getSyntheticNodeSubclassData<MaskedGatherSDNode>(
9400 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, ExtTy));
9404 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
9405 cast<MaskedGatherSDNode>(
E)->refineAlignment(MMO);
9410 VTs, MemVT, MMO, IndexType, ExtTy);
9411 createOperands(
N, Ops);
9413 assert(
N->getPassThru().getValueType() ==
N->getValueType(0) &&
9414 "Incompatible type of the PassThru value in MaskedGatherSDNode");
9415 assert(
N->getMask().getValueType().getVectorElementCount() ==
9416 N->getValueType(0).getVectorElementCount() &&
9417 "Vector width mismatch between mask and data");
9418 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9419 N->getValueType(0).getVectorElementCount().isScalable() &&
9420 "Scalable flags of index and data do not match");
9422 N->getIndex().getValueType().getVectorElementCount(),
9423 N->getValueType(0).getVectorElementCount()) &&
9424 "Vector width mismatch between index and data");
9425 assert(isa<ConstantSDNode>(
N->getScale()) &&
9426 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9427 "Scale should be a constant power of 2");
9429 CSEMap.InsertNode(
N, IP);
9441 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9446 ID.AddInteger(getSyntheticNodeSubclassData<MaskedScatterSDNode>(
9447 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, IsTrunc));
9451 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP)) {
9452 cast<MaskedScatterSDNode>(
E)->refineAlignment(MMO);
9457 VTs, MemVT, MMO, IndexType, IsTrunc);
9458 createOperands(
N, Ops);
9460 assert(
N->getMask().getValueType().getVectorElementCount() ==
9461 N->getValue().getValueType().getVectorElementCount() &&
9462 "Vector width mismatch between mask and data");
9464 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9465 N->getValue().getValueType().getVectorElementCount().isScalable() &&
9466 "Scalable flags of index and data do not match");
9468 N->getIndex().getValueType().getVectorElementCount(),
9469 N->getValue().getValueType().getVectorElementCount()) &&
9470 "Vector width mismatch between index and data");
9471 assert(isa<ConstantSDNode>(
N->getScale()) &&
9472 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9473 "Scale should be a constant power of 2");
9475 CSEMap.InsertNode(
N, IP);
9490 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
9495 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP))
9500 createOperands(
N, Ops);
9502 CSEMap.InsertNode(
N, IP);
9517 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
9522 if (
SDNode *
E = FindNodeOrInsertPos(
ID, dl, IP))
9527 createOperands(
N, Ops);
9529 CSEMap.InsertNode(
N, IP);
9549 if (
auto *CondC = dyn_cast<ConstantSDNode>(
Cond))
9550 return CondC->isZero() ?
F :
T;
9556 if (CondC->isZero())
9582 return !Val || Val->getAPIntValue().uge(
X.getScalarValueSizeInBits());
9597 bool HasNan = (XC && XC->getValueAPF().isNaN()) ||
9599 bool HasInf = (XC && XC->getValueAPF().isInfinity()) ||
9602 if (Flags.hasNoNaNs() && (HasNan ||
X.isUndef() ||
Y.isUndef()))
9605 if (Flags.hasNoInfs() && (HasInf ||
X.isUndef() ||
Y.isUndef()))
9628 if (Opcode ==
ISD::FMUL && Flags.hasNoNaNs() && Flags.hasNoSignedZeros())
9643 switch (Ops.
size()) {
9645 case 1:
return getNode(Opcode,
DL, VT,
static_cast<const SDValue>(Ops[0]));
9646 case 2:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1]);
9647 case 3:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Ops[2]);
9662 return getNode(Opcode,
DL, VT, Ops, Flags);
9667 unsigned NumOps = Ops.
size();
9670 case 1:
return getNode(Opcode,
DL, VT, Ops[0], Flags);
9671 case 2:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Flags);
9672 case 3:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Ops[2], Flags);
9677 for (
const auto &
Op : Ops)
9679 "Operand is DELETED_NODE!");
9694 assert(NumOps == 5 &&
"SELECT_CC takes 5 operands!");
9696 "LHS and RHS of condition must have same type!");
9698 "True and False arms of SelectCC must have same type!");
9700 "select_cc node must be of same type as true and false value!");
9704 "Expected select_cc with vector result to have the same sized "
9705 "comparison type!");
9708 assert(NumOps == 5 &&
"BR_CC takes 5 operands!");
9710 "LHS/RHS of comparison should match types!");
9716 Opcode = ISD::VP_XOR;
9721 Opcode = ISD::VP_AND;
9723 case ISD::VP_REDUCE_MUL:
9726 Opcode = ISD::VP_REDUCE_AND;
9728 case ISD::VP_REDUCE_ADD:
9731 Opcode = ISD::VP_REDUCE_XOR;
9733 case ISD::VP_REDUCE_SMAX:
9734 case ISD::VP_REDUCE_UMIN:
9738 Opcode = ISD::VP_REDUCE_AND;
9740 case ISD::VP_REDUCE_SMIN:
9741 case ISD::VP_REDUCE_UMAX:
9745 Opcode = ISD::VP_REDUCE_OR;
9753 if (VT != MVT::Glue) {
9761 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
9762 createOperands(
N, Ops);
9764 CSEMap.InsertNode(
N, IP);
9766 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
9767 createOperands(
N, Ops);
9787 return getNode(Opcode,
DL, VTList, Ops, Flags);
9796 for (
const auto &
Op : Ops)
9798 "Operand is DELETED_NODE!");
9807 "Invalid add/sub overflow op!");
9809 Ops[0].getValueType() == Ops[1].getValueType() &&
9810 Ops[0].getValueType() == VTList.
VTs[0] &&
9811 "Binary operator types must match!");
9812 SDValue N1 = Ops[0], N2 = Ops[1];
9818 if (N2CV && N2CV->
isZero()) {
9849 VTList.
VTs[0] == Ops[0].getValueType() &&
9850 VTList.
VTs[0] == Ops[1].getValueType() &&
9851 "Binary operator types must match!");
9857 unsigned OutWidth = Width * 2;
9861 Val = Val.
sext(OutWidth);
9862 Mul =
Mul.sext(OutWidth);
9864 Val = Val.
zext(OutWidth);
9865 Mul =
Mul.zext(OutWidth);
9879 VTList.
VTs[0] == Ops[0].getValueType() &&
"frexp type mismatch");
9895 "Invalid STRICT_FP_EXTEND!");
9897 Ops[1].getValueType().isFloatingPoint() &&
"Invalid FP cast!");
9899 "STRICT_FP_EXTEND result type should be vector iff the operand "
9903 Ops[1].getValueType().getVectorElementCount()) &&
9904 "Vector element count mismatch!");
9906 "Invalid fpext node, dst <= src!");
9909 assert(VTList.
NumVTs == 2 && Ops.
size() == 3 &&
"Invalid STRICT_FP_ROUND!");
9911 "STRICT_FP_ROUND result type should be vector iff the operand "
9915 Ops[1].getValueType().getVectorElementCount()) &&
9916 "Vector element count mismatch!");
9918 Ops[1].getValueType().isFloatingPoint() &&
9919 VTList.
VTs[0].
bitsLT(Ops[1].getValueType()) &&
9920 isa<ConstantSDNode>(Ops[2]) &&
9921 (Ops[2]->getAsZExtVal() == 0 || Ops[2]->getAsZExtVal() == 1) &&
9922 "Invalid STRICT_FP_ROUND!");
9932 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
9933 return getNode(Opcode,
DL, VT, N1, N2, N3.getOperand(0));
9934 else if (N3.getOpcode() ==
ISD::AND)
9935 if (
ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
9939 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
9940 return getNode(Opcode,
DL, VT, N1, N2, N3.getOperand(0));
9948 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
9955 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
9956 createOperands(
N, Ops);
9957 CSEMap.InsertNode(
N, IP);
9959 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
9960 createOperands(
N, Ops);
9972 return getNode(Opcode,
DL, VTList, std::nullopt);
9978 return getNode(Opcode,
DL, VTList, Ops);
9984 return getNode(Opcode,
DL, VTList, Ops);
9989 SDValue Ops[] = { N1, N2, N3 };
9990 return getNode(Opcode,
DL, VTList, Ops);
9995 SDValue Ops[] = { N1, N2, N3, N4 };
9996 return getNode(Opcode,
DL, VTList, Ops);
10002 SDValue Ops[] = { N1, N2, N3, N4, N5 };
10003 return getNode(Opcode,
DL, VTList, Ops);
10007 return makeVTList(SDNode::getValueTypeList(VT), 1);
10016 void *IP =
nullptr;
10022 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 2);
10023 VTListMap.InsertNode(Result, IP);
10025 return Result->getSDVTList();
10035 void *IP =
nullptr;
10042 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 3);
10043 VTListMap.InsertNode(Result, IP);
10045 return Result->getSDVTList();
10056 void *IP =
nullptr;
10064 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 4);
10065 VTListMap.InsertNode(Result, IP);
10067 return Result->getSDVTList();
10071 unsigned NumVTs = VTs.
size();
10073 ID.AddInteger(NumVTs);
10074 for (
unsigned index = 0; index < NumVTs; index++) {
10075 ID.AddInteger(VTs[index].getRawBits());
10078 void *IP =
nullptr;
10083 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, NumVTs);
10084 VTListMap.InsertNode(Result, IP);
10086 return Result->getSDVTList();
10097 assert(
N->getNumOperands() == 1 &&
"Update with wrong number of operands");
10100 if (
Op ==
N->getOperand(0))
return N;
10103 void *InsertPos =
nullptr;
10104 if (
SDNode *Existing = FindModifiedNodeSlot(
N,
Op, InsertPos))
10109 if (!RemoveNodeFromCSEMaps(
N))
10110 InsertPos =
nullptr;
10113 N->OperandList[0].set(
Op);
10117 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10122 assert(
N->getNumOperands() == 2 &&
"Update with wrong number of operands");
10125 if (Op1 ==
N->getOperand(0) && Op2 ==
N->getOperand(1))
10129 void *InsertPos =
nullptr;
10130 if (
SDNode *Existing = FindModifiedNodeSlot(
N, Op1, Op2, InsertPos))
10135 if (!RemoveNodeFromCSEMaps(
N))
10136 InsertPos =
nullptr;
10139 if (
N->OperandList[0] != Op1)
10140 N->OperandList[0].set(Op1);
10141 if (
N->OperandList[1] != Op2)
10142 N->OperandList[1].set(Op2);
10146 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10152 SDValue Ops[] = { Op1, Op2, Op3 };
10159 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
10166 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
10172 unsigned NumOps = Ops.
size();
10173 assert(
N->getNumOperands() == NumOps &&
10174 "Update with wrong number of operands");
10177 if (std::equal(Ops.
begin(), Ops.
end(),
N->op_begin()))
10181 void *InsertPos =
nullptr;
10182 if (
SDNode *Existing = FindModifiedNodeSlot(
N, Ops, InsertPos))
10187 if (!RemoveNodeFromCSEMaps(
N))
10188 InsertPos =
nullptr;
10191 for (
unsigned i = 0; i != NumOps; ++i)
10192 if (
N->OperandList[i] != Ops[i])
10193 N->OperandList[i].set(Ops[i]);
10197 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10214 if (NewMemRefs.
empty()) {
10220 if (NewMemRefs.
size() == 1) {
10221 N->MemRefs = NewMemRefs[0];
10227 Allocator.template Allocate<MachineMemOperand *>(NewMemRefs.
size());
10229 N->MemRefs = MemRefsBuffer;
10230 N->NumMemRefs =
static_cast<int>(NewMemRefs.
size());
10253 SDValue Ops[] = { Op1, Op2 };
10261 SDValue Ops[] = { Op1, Op2, Op3 };
10294 SDValue Ops[] = { Op1, Op2 };
10302 New->setNodeId(-1);
10322 unsigned Order = std::min(
N->getIROrder(), OLoc.
getIROrder());
10323 N->setIROrder(Order);
10346 void *IP =
nullptr;
10347 if (VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue) {
10351 return UpdateSDLocOnMergeSDNode(ON,
SDLoc(
N));
10354 if (!RemoveNodeFromCSEMaps(
N))
10359 N->ValueList = VTs.
VTs;
10369 if (Used->use_empty())
10370 DeadNodeSet.
insert(Used);
10375 MN->clearMemRefs();
10379 createOperands(
N, Ops);
10383 if (!DeadNodeSet.
empty()) {
10385 for (
SDNode *
N : DeadNodeSet)
10386 if (
N->use_empty())
10392 CSEMap.InsertNode(
N, IP);
10397 unsigned OrigOpc = Node->getOpcode();
10402#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
10403 case ISD::STRICT_##DAGN: NewOpc = ISD::DAGN; break;
10404#define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
10405 case ISD::STRICT_##DAGN: NewOpc = ISD::SETCC; break;
10406#include "llvm/IR/ConstrainedOps.def"
10409 assert(Node->getNumValues() == 2 &&
"Unexpected number of results!");
10412 SDValue InputChain = Node->getOperand(0);
10417 for (
unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
10460 SDValue Ops[] = { Op1, Op2 };
10468 SDValue Ops[] = { Op1, Op2, Op3 };
10482 SDValue Ops[] = { Op1, Op2 };
10490 SDValue Ops[] = { Op1, Op2, Op3 };
10505 SDValue Ops[] = { Op1, Op2 };
10514 SDValue Ops[] = { Op1, Op2, Op3 };
10535 bool DoCSE = VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue;
10537 void *IP =
nullptr;
10543 if (
SDNode *
E = FindNodeOrInsertPos(
ID,
DL, IP)) {
10544 return cast<MachineSDNode>(UpdateSDLocOnMergeSDNode(
E,
DL));
10549 N = newSDNode<MachineSDNode>(~Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
10550 createOperands(
N, Ops);
10553 CSEMap.InsertNode(
N, IP);
10566 VT, Operand, SRIdxVal);
10576 VT, Operand, Subreg, SRIdxVal);
10593 if (VTList.
VTs[VTList.
NumVTs - 1] != MVT::Glue) {
10596 void *IP =
nullptr;
10598 E->intersectFlagsWith(Flags);
10608 if (VTList.
VTs[VTList.
NumVTs - 1] != MVT::Glue) {
10611 void *IP =
nullptr;
10612 if (FindNodeOrInsertPos(
ID,
SDLoc(), IP))
10622 SDNode *
N,
unsigned R,
bool IsIndirect,
10624 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10625 "Expected inlined-at fields to agree");
10628 {}, IsIndirect,
DL, O,
10637 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10638 "Expected inlined-at fields to agree");
10651 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10652 "Expected inlined-at fields to agree");
10663 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10664 "Expected inlined-at fields to agree");
10667 Dependencies, IsIndirect,
DL, O,
10673 unsigned VReg,
bool IsIndirect,
10675 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10676 "Expected inlined-at fields to agree");
10679 {}, IsIndirect,
DL, O,
10687 unsigned O,
bool IsVariadic) {
10688 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10689 "Expected inlined-at fields to agree");
10692 DL, O, IsVariadic);
10696 unsigned OffsetInBits,
unsigned SizeInBits,
10697 bool InvalidateDbg) {
10700 assert(FromNode && ToNode &&
"Can't modify dbg values");
10705 if (
From == To || FromNode == ToNode)
10717 if (Dbg->isInvalidated())
10724 bool Changed =
false;
10725 auto NewLocOps = Dbg->copyLocationOps();
10727 NewLocOps.begin(), NewLocOps.end(),
10729 bool Match = Op == FromLocOp;
10739 auto *Expr = Dbg->getExpression();
10745 if (
auto FI = Expr->getFragmentInfo())
10746 if (OffsetInBits + SizeInBits > FI->SizeInBits)
10755 auto AdditionalDependencies = Dbg->getAdditionalDependencies();
10758 Var, Expr, NewLocOps, AdditionalDependencies, Dbg->isIndirect(),
10759 Dbg->getDebugLoc(), std::max(ToNode->
getIROrder(), Dbg->getOrder()),
10760 Dbg->isVariadic());
10763 if (InvalidateDbg) {
10765 Dbg->setIsInvalidated();
10766 Dbg->setIsEmitted();
10772 "Transferred DbgValues should depend on the new SDNode");
10778 if (!
N.getHasDebugValue())
10783 if (DV->isInvalidated())
10785 switch (
N.getOpcode()) {
10791 if (!isa<ConstantSDNode>(N0)) {
10792 bool RHSConstant = isa<ConstantSDNode>(N1);
10795 Offset =
N.getConstantOperandVal(1);
10798 if (!RHSConstant && DV->isIndirect())
10805 auto *DIExpr = DV->getExpression();
10806 auto NewLocOps = DV->copyLocationOps();
10807 bool Changed =
false;
10808 size_t OrigLocOpsSize = NewLocOps.size();
10809 for (
size_t i = 0; i < OrigLocOpsSize; ++i) {
10814 NewLocOps[i].getSDNode() != &
N)
10825 const auto *TmpDIExpr =
10833 NewLocOps.push_back(
RHS);
10839 assert(Changed &&
"Salvage target doesn't use N");
10842 DV->isVariadic() || OrigLocOpsSize != NewLocOps.size();
10844 auto AdditionalDependencies = DV->getAdditionalDependencies();
10846 DV->getVariable(), DIExpr, NewLocOps, AdditionalDependencies,
10847 DV->isIndirect(), DV->getDebugLoc(), DV->getOrder(), IsVariadic);
10849 DV->setIsInvalidated();
10850 DV->setIsEmitted();
10852 N0.
getNode()->dumprFull(
this);
10853 dbgs() <<
" into " << *DIExpr <<
'\n');
10860 TypeSize ToSize =
N.getValueSizeInBits(0);
10864 auto NewLocOps = DV->copyLocationOps();
10865 bool Changed =
false;
10866 for (
size_t i = 0; i < NewLocOps.size(); ++i) {
10868 NewLocOps[i].getSDNode() != &
N)
10875 assert(Changed &&
"Salvage target doesn't use N");
10880 DV->getAdditionalDependencies(), DV->isIndirect(),
10881 DV->getDebugLoc(), DV->getOrder(), DV->isVariadic());
10884 DV->setIsInvalidated();
10885 DV->setIsEmitted();
10887 dbgs() <<
" into " << *DbgExpression <<
'\n');
10894 assert(!Dbg->getSDNodes().empty() &&
10895 "Salvaged DbgValue should depend on a new SDNode");
10903 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) &&
10904 "Expected inlined-at fields to agree");
10920 while (UI != UE &&
N == *UI)
10928 :
SelectionDAG::DAGUpdateListener(d), UI(ui), UE(ue) {}
10941 "Cannot replace with this method!");
10957 RAUWUpdateListener Listener(*
this, UI, UE);
10962 RemoveNodeFromCSEMaps(
User);
10974 }
while (UI != UE && *UI ==
User);
10977 AddModifiedNodeToCSEMaps(
User);
10993 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i)
10996 "Cannot use this version of ReplaceAllUsesWith!");
11004 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i)
11005 if (
From->hasAnyUseOfValue(i)) {
11006 assert((i < To->getNumValues()) &&
"Invalid To location");
11015 RAUWUpdateListener Listener(*
this, UI, UE);
11020 RemoveNodeFromCSEMaps(
User);
11032 }
while (UI != UE && *UI ==
User);
11036 AddModifiedNodeToCSEMaps(
User);
11050 if (
From->getNumValues() == 1)
11053 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i) {
11063 RAUWUpdateListener Listener(*
this, UI, UE);
11068 RemoveNodeFromCSEMaps(
User);
11074 bool To_IsDivergent =
false;
11081 }
while (UI != UE && *UI ==
User);
11083 if (To_IsDivergent !=
From->isDivergent())
11088 AddModifiedNodeToCSEMaps(
User);
11101 if (
From == To)
return;
11104 if (
From.getNode()->getNumValues() == 1) {
11116 UE =
From.getNode()->use_end();
11117 RAUWUpdateListener Listener(*
this, UI, UE);
11120 bool UserRemovedFromCSEMaps =
false;
11130 if (
Use.getResNo() !=
From.getResNo()) {
11137 if (!UserRemovedFromCSEMaps) {
11138 RemoveNodeFromCSEMaps(
User);
11139 UserRemovedFromCSEMaps =
true;
11146 }
while (UI != UE && *UI ==
User);
11149 if (!UserRemovedFromCSEMaps)
11154 AddModifiedNodeToCSEMaps(
User);
11173bool operator<(
const UseMemo &L,
const UseMemo &R) {
11174 return (intptr_t)L.User < (intptr_t)R.User;
11184 for (UseMemo &Memo :
Uses)
11185 if (Memo.User ==
N)
11186 Memo.User =
nullptr;
11199 "Conflicting divergence information!");
11204 for (
const auto &
Op :
N->ops()) {
11205 if (
Op.Val.getValueType() != MVT::Other &&
Op.getNode()->isDivergent())
11216 if (
N->SDNodeBits.IsDivergent != IsDivergent) {
11217 N->SDNodeBits.IsDivergent = IsDivergent;
11220 }
while (!Worklist.
empty());
11223void SelectionDAG::CreateTopologicalOrder(std::vector<SDNode *> &Order) {
11225 Order.
reserve(AllNodes.size());
11227 unsigned NOps =
N.getNumOperands();
11230 Order.push_back(&
N);
11232 for (
size_t I = 0;
I != Order.size(); ++
I) {
11234 for (
auto *U :
N->uses()) {
11235 unsigned &UnsortedOps = Degree[U];
11236 if (0 == --UnsortedOps)
11237 Order.push_back(U);
11244 std::vector<SDNode *> TopoOrder;
11245 CreateTopologicalOrder(TopoOrder);
11246 for (
auto *
N : TopoOrder) {
11248 "Divergence bit inconsistency detected");
11271 for (
unsigned i = 0; i != Num; ++i) {
11272 unsigned FromResNo =
From[i].getResNo();
11275 E = FromNode->
use_end(); UI !=
E; ++UI) {
11277 if (
Use.getResNo() == FromResNo) {
11278 UseMemo Memo = { *UI, i, &
Use };
11279 Uses.push_back(Memo);
11286 RAUOVWUpdateListener Listener(*
this,
Uses);
11288 for (
unsigned UseIndex = 0, UseIndexEnd =
Uses.size();
11289 UseIndex != UseIndexEnd; ) {
11295 if (
User ==
nullptr) {
11301 RemoveNodeFromCSEMaps(
User);
11308 unsigned i =
Uses[UseIndex].Index;
11313 }
while (UseIndex != UseIndexEnd &&
Uses[UseIndex].
User ==
User);
11317 AddModifiedNodeToCSEMaps(
User);
11325 unsigned DAGSize = 0;
11341 unsigned Degree =
N.getNumOperands();
11344 N.setNodeId(DAGSize++);
11346 if (Q != SortedPos)
11347 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q));
11348 assert(SortedPos != AllNodes.end() &&
"Overran node list");
11352 N.setNodeId(Degree);
11364 unsigned Degree =
P->getNodeId();
11365 assert(Degree != 0 &&
"Invalid node degree");
11369 P->setNodeId(DAGSize++);
11370 if (
P->getIterator() != SortedPos)
11371 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(
P));
11372 assert(SortedPos != AllNodes.end() &&
"Overran node list");
11376 P->setNodeId(Degree);
11379 if (Node.getIterator() == SortedPos) {
11383 dbgs() <<
"Overran sorted position:\n";
11385 dbgs() <<
"Checking if this is due to cycles\n";
11392 assert(SortedPos == AllNodes.end() &&
11393 "Topological sort incomplete!");
11395 "First node in topological sort is not the entry token!");
11396 assert(AllNodes.front().getNodeId() == 0 &&
11397 "First node in topological sort has non-zero id!");
11398 assert(AllNodes.front().getNumOperands() == 0 &&
11399 "First node in topological sort has operands!");
11400 assert(AllNodes.back().getNodeId() == (
int)DAGSize-1 &&
11401 "Last node in topologic sort has unexpected id!");
11402 assert(AllNodes.back().use_empty() &&
11403 "Last node in topologic sort has users!");
11411 for (
SDNode *SD : DB->getSDNodes()) {
11415 SD->setHasDebugValue(
true);
11417 DbgInfo->
add(DB, isParameter);
11424 assert(isa<MemSDNode>(NewMemOpChain) &&
"Expected a memop node");
11430 if (OldChain == NewMemOpChain || OldChain.
use_empty())
11431 return NewMemOpChain;
11434 OldChain, NewMemOpChain);
11437 return TokenFactor;
11442 assert(isa<MemSDNode>(NewMemOp.
getNode()) &&
"Expected a memop node");
11450 assert(isa<ExternalSymbolSDNode>(
Op) &&
"Node should be an ExternalSymbol");
11452 auto *Symbol = cast<ExternalSymbolSDNode>(
Op)->getSymbol();
11456 if (OutFunction !=
nullptr)
11464 std::string ErrorStr;
11466 ErrorFormatter <<
"Undefined external symbol ";
11467 ErrorFormatter <<
'"' << Symbol <<
'"';
11477 return Const !=
nullptr && Const->isZero();
11482 return Const !=
nullptr && Const->isZero() && !Const->isNegative();
11487 return Const !=
nullptr && Const->isAllOnes();
11492 return Const !=
nullptr && Const->isOne();
11497 return Const !=
nullptr && Const->isMinSignedValue();
11501 unsigned OperandNo) {
11510 return Const->isZero();
11512 return Const->isOne();
11515 return Const->isAllOnes();
11517 return Const->isMinSignedValue();
11519 return Const->isMaxSignedValue();
11524 return OperandNo == 1 && Const->isZero();
11527 return OperandNo == 1 && Const->isOne();
11532 return ConstFP->isZero() &&
11533 (Flags.hasNoSignedZeros() || ConstFP->isNegative());
11535 return OperandNo == 1 && ConstFP->isZero() &&
11536 (Flags.hasNoSignedZeros() || !ConstFP->isNegative());
11538 return ConstFP->isExactlyValue(1.0);
11540 return OperandNo == 1 && ConstFP->isExactlyValue(1.0);
11544 EVT VT = V.getValueType();
11546 APFloat NeutralAF = !Flags.hasNoNaNs()
11548 : !Flags.hasNoInfs()
11554 return ConstFP->isExactlyValue(NeutralAF);
11563 V = V.getOperand(0);
11568 while (V.getOpcode() ==
ISD::BITCAST && V.getOperand(0).hasOneUse())
11569 V = V.getOperand(0);
11575 V = V.getOperand(0);
11581 V = V.getOperand(0);
11589 unsigned NumBits = V.getScalarValueSizeInBits();
11592 return C && (
C->getAPIntValue().countr_one() >= NumBits);
11596 bool AllowTruncation) {
11597 EVT VT =
N.getValueType();
11606 bool AllowTruncation) {
11613 EVT VecEltVT =
N->getValueType(0).getVectorElementType();
11614 if (
auto *CN = dyn_cast<ConstantSDNode>(
N->getOperand(0))) {
11615 EVT CVT = CN->getValueType(0);
11616 assert(CVT.
bitsGE(VecEltVT) &&
"Illegal splat_vector element extension");
11617 if (AllowTruncation || CVT == VecEltVT)
11624 ConstantSDNode *CN = BV->getConstantSplatNode(DemandedElts, &UndefElements);
11629 if (CN && (UndefElements.
none() || AllowUndefs)) {
11631 EVT NSVT =
N.getValueType().getScalarType();
11632 assert(CVT.
bitsGE(NSVT) &&
"Illegal build vector element extension");
11633 if (AllowTruncation || (CVT == NSVT))
11642 EVT VT =
N.getValueType();
11650 const APInt &DemandedElts,
11651 bool AllowUndefs) {
11658 BV->getConstantFPSplatNode(DemandedElts, &UndefElements);
11660 if (CN && (UndefElements.
none() || AllowUndefs))
11675 return C &&
C->isZero();
11681 return C &&
C->isOne();
11686 unsigned BitWidth =
N.getScalarValueSizeInBits();
11688 return C &&
C->isAllOnes() &&
C->getValueSizeInBits(0) ==
BitWidth;
11695GlobalAddressSDNode::GlobalAddressSDNode(
unsigned Opc,
unsigned Order,
11698 int64_t o,
unsigned TF)
11699 :
SDNode(Opc, Order,
DL, getSDVTList(VT)),
Offset(o), TargetFlags(TF) {
11704 EVT VT,
unsigned SrcAS,
11706 :
SDNode(ISD::ADDRSPACECAST, Order, dl, getSDVTList(VT)),
11707 SrcAddrSpace(SrcAS), DestAddrSpace(DestAS) {}
11711 :
SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MMO(mmo) {
11734 std::vector<EVT> VTs;
11747const EVT *SDNode::getValueTypeList(
EVT VT) {
11748 static std::set<EVT, EVT::compareRawBits> EVTs;
11749 static EVTArray SimpleVTArray;
11754 return &(*EVTs.insert(VT).first);
11768 if (UI.getUse().getResNo() ==
Value) {
11785 if (UI.getUse().getResNo() ==
Value)
11823 return any_of(
N->op_values(),
11824 [
this](
SDValue Op) { return this == Op.getNode(); });
11838 unsigned Depth)
const {
11839 if (*
this == Dest)
return true;
11843 if (
Depth == 0)
return false;
11863 return Op.reachesChainWithoutSideEffects(Dest, Depth - 1);
11868 if (
LoadSDNode *Ld = dyn_cast<LoadSDNode>(*
this)) {
11869 if (Ld->isUnordered())
11870 return Ld->getChain().reachesChainWithoutSideEffects(Dest,
Depth-1);
11889 bool AllowPartials) {
11898 return Op.getOpcode() ==
unsigned(BinOp);
11904 unsigned CandidateBinOp =
Op.getOpcode();
11905 if (
Op.getValueType().isFloatingPoint()) {
11907 switch (CandidateBinOp) {
11909 if (!Flags.hasNoSignedZeros() || !Flags.hasAllowReassociation())
11919 auto PartialReduction = [&](
SDValue Op,
unsigned NumSubElts) {
11920 if (!AllowPartials || !
Op)
11922 EVT OpVT =
Op.getValueType();
11945 unsigned Stages =
Log2_32(
Op.getValueType().getVectorNumElements());
11947 for (
unsigned i = 0; i < Stages; ++i) {
11948 unsigned MaskEnd = (1 << i);
11950 if (
Op.getOpcode() != CandidateBinOp)
11951 return PartialReduction(PrevOp, MaskEnd);
11960 Shuffle = dyn_cast<ShuffleVectorSDNode>(Op1);
11967 return PartialReduction(PrevOp, MaskEnd);
11972 return PartialReduction(PrevOp, MaskEnd);
11979 while (
Op.getOpcode() == CandidateBinOp) {
11980 unsigned NumElts =
Op.getValueType().getVectorNumElements();
11988 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
11989 if (NumSrcElts != (2 * NumElts))
12004 EVT VT =
N->getValueType(0);
12013 else if (NE > ResNE)
12016 if (
N->getNumValues() == 2) {
12019 EVT VT1 =
N->getValueType(1);
12023 for (i = 0; i != NE; ++i) {
12024 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
12025 SDValue Operand =
N->getOperand(j);
12044 assert(
N->getNumValues() == 1 &&
12045 "Can't unroll a vector with multiple results!");
12051 for (i= 0; i != NE; ++i) {
12052 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
12053 SDValue Operand =
N->getOperand(j);
12066 switch (
N->getOpcode()) {
12093 for (; i < ResNE; ++i)
12102 unsigned Opcode =
N->getOpcode();
12106 "Expected an overflow opcode");
12108 EVT ResVT =
N->getValueType(0);
12109 EVT OvVT =
N->getValueType(1);
12118 else if (NE > ResNE)
12130 for (
unsigned i = 0; i < NE; ++i) {
12131 SDValue Res =
getNode(Opcode, dl, VTs, LHSScalars[i], RHSScalars[i]);
12154 if (LD->isVolatile() ||
Base->isVolatile())
12157 if (!LD->isSimple())
12159 if (LD->isIndexed() ||
Base->isIndexed())
12161 if (LD->getChain() !=
Base->getChain())
12163 EVT VT = LD->getMemoryVT();
12171 if (BaseLocDecomp.equalBaseIndex(LocDecomp, *
this,
Offset))
12172 return (Dist * (int64_t)Bytes ==
Offset);
12181 int64_t GVOffset = 0;
12193 int FrameIdx = INT_MIN;
12194 int64_t FrameOffset = 0;
12196 FrameIdx = FI->getIndex();
12198 isa<FrameIndexSDNode>(
Ptr.getOperand(0))) {
12200 FrameIdx = cast<FrameIndexSDNode>(
Ptr.getOperand(0))->getIndex();
12201 FrameOffset =
Ptr.getConstantOperandVal(1);
12204 if (FrameIdx != INT_MIN) {
12209 return std::nullopt;
12219 "Split node must be a scalar type");
12224 return std::make_pair(
Lo,
Hi);
12237 return std::make_pair(LoVT, HiVT);
12245 bool *HiIsEmpty)
const {
12255 "Mixing fixed width and scalable vectors when enveloping a type");
12260 *HiIsEmpty =
false;
12268 return std::make_pair(LoVT, HiVT);
12273std::pair<SDValue, SDValue>
12278 "Splitting vector with an invalid mixture of fixed and scalable "
12281 N.getValueType().getVectorMinNumElements() &&
12282 "More vector elements requested than available!");
12292 return std::make_pair(
Lo,
Hi);
12299 EVT VT =
N.getValueType();
12301 "Expecting the mask to be an evenly-sized vector");
12309 return std::make_pair(
Lo,
Hi);
12314 EVT VT =
N.getValueType();
12323 unsigned Start,
unsigned Count,
12325 EVT VT =
Op.getValueType();
12328 if (EltVT ==
EVT())
12331 for (
unsigned i = Start, e = Start + Count; i != e; ++i) {
12344 return Val.MachineCPVal->getType();
12345 return Val.ConstVal->getType();
12349 unsigned &SplatBitSize,
12350 bool &HasAnyUndefs,
12351 unsigned MinSplatBits,
12352 bool IsBigEndian)
const {
12356 if (MinSplatBits > VecWidth)
12361 SplatValue =
APInt(VecWidth, 0);
12362 SplatUndef =
APInt(VecWidth, 0);
12369 assert(NumOps > 0 &&
"isConstantSplat has 0-size build vector");
12372 for (
unsigned j = 0; j < NumOps; ++j) {
12373 unsigned i = IsBigEndian ? NumOps - 1 - j : j;
12375 unsigned BitPos = j * EltWidth;
12378 SplatUndef.
setBits(BitPos, BitPos + EltWidth);
12379 else if (
auto *CN = dyn_cast<ConstantSDNode>(OpVal))
12380 SplatValue.
insertBits(CN->getAPIntValue().zextOrTrunc(EltWidth), BitPos);
12381 else if (
auto *CN = dyn_cast<ConstantFPSDNode>(OpVal))
12382 SplatValue.
insertBits(CN->getValueAPF().bitcastToAPInt(), BitPos);
12389 HasAnyUndefs = (SplatUndef != 0);
12392 while (VecWidth > 8) {
12397 unsigned HalfSize = VecWidth / 2;
12404 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) ||
12405 MinSplatBits > HalfSize)
12408 SplatValue = HighValue | LowValue;
12409 SplatUndef = HighUndef & LowUndef;
12411 VecWidth = HalfSize;
12420 SplatBitSize = VecWidth;
12427 if (UndefElements) {
12428 UndefElements->
clear();
12429 UndefElements->
resize(NumOps);
12435 for (
unsigned i = 0; i != NumOps; ++i) {
12436 if (!DemandedElts[i])
12439 if (
Op.isUndef()) {
12441 (*UndefElements)[i] =
true;
12442 }
else if (!Splatted) {
12444 }
else if (Splatted !=
Op) {
12450 unsigned FirstDemandedIdx = DemandedElts.
countr_zero();
12452 "Can only have a splat without a constant for all undefs.");
12469 if (UndefElements) {
12470 UndefElements->
clear();
12471 UndefElements->
resize(NumOps);
12479 for (
unsigned I = 0;
I != NumOps; ++
I)
12481 (*UndefElements)[
I] =
true;
12484 for (
unsigned SeqLen = 1; SeqLen < NumOps; SeqLen *= 2) {
12485 Sequence.append(SeqLen,
SDValue());
12486 for (
unsigned I = 0;
I != NumOps; ++
I) {
12487 if (!DemandedElts[
I])
12489 SDValue &SeqOp = Sequence[
I % SeqLen];
12491 if (
Op.isUndef()) {
12496 if (SeqOp && !SeqOp.
isUndef() && SeqOp !=
Op) {
12502 if (!Sequence.empty())
12506 assert(Sequence.empty() &&
"Failed to empty non-repeating sequence pattern");
12519 return dyn_cast_or_null<ConstantSDNode>(
12525 return dyn_cast_or_null<ConstantSDNode>(
getSplatValue(UndefElements));
12531 return dyn_cast_or_null<ConstantFPSDNode>(
12537 return dyn_cast_or_null<ConstantFPSDNode>(
getSplatValue(UndefElements));
12544 dyn_cast_or_null<ConstantFPSDNode>(
getSplatValue(UndefElements))) {
12547 const APFloat &APF = CN->getValueAPF();
12553 return IntVal.exactLogBase2();
12559 bool IsLittleEndian,
unsigned DstEltSizeInBits,
12567 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
12568 "Invalid bitcast scale");
12573 BitVector SrcUndeElements(NumSrcOps,
false);
12575 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
12577 if (
Op.isUndef()) {
12578 SrcUndeElements.
set(
I);
12581 auto *CInt = dyn_cast<ConstantSDNode>(
Op);
12582 auto *CFP = dyn_cast<ConstantFPSDNode>(
Op);
12583 assert((CInt || CFP) &&
"Unknown constant");
12584 SrcBitElements[
I] = CInt ? CInt->getAPIntValue().trunc(SrcEltSizeInBits)
12585 : CFP->getValueAPF().bitcastToAPInt();
12589 recastRawBits(IsLittleEndian, DstEltSizeInBits, RawBitElements,
12590 SrcBitElements, UndefElements, SrcUndeElements);
12595 unsigned DstEltSizeInBits,
12600 unsigned NumSrcOps = SrcBitElements.
size();
12601 unsigned SrcEltSizeInBits = SrcBitElements[0].getBitWidth();
12602 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
12603 "Invalid bitcast scale");
12604 assert(NumSrcOps == SrcUndefElements.
size() &&
12605 "Vector size mismatch");
12607 unsigned NumDstOps = (NumSrcOps * SrcEltSizeInBits) / DstEltSizeInBits;
12608 DstUndefElements.
clear();
12609 DstUndefElements.
resize(NumDstOps,
false);
12613 if (SrcEltSizeInBits <= DstEltSizeInBits) {
12614 unsigned Scale = DstEltSizeInBits / SrcEltSizeInBits;
12615 for (
unsigned I = 0;
I != NumDstOps; ++
I) {
12616 DstUndefElements.
set(
I);
12617 APInt &DstBits = DstBitElements[
I];
12618 for (
unsigned J = 0; J != Scale; ++J) {
12619 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
12620 if (SrcUndefElements[
Idx])
12622 DstUndefElements.
reset(
I);
12623 const APInt &SrcBits = SrcBitElements[
Idx];
12625 "Illegal constant bitwidths");
12626 DstBits.
insertBits(SrcBits, J * SrcEltSizeInBits);
12633 unsigned Scale = SrcEltSizeInBits / DstEltSizeInBits;
12634 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
12635 if (SrcUndefElements[
I]) {
12636 DstUndefElements.
set(
I * Scale, (
I + 1) * Scale);
12639 const APInt &SrcBits = SrcBitElements[
I];
12640 for (
unsigned J = 0; J != Scale; ++J) {
12641 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
12642 APInt &DstBits = DstBitElements[
Idx];
12643 DstBits = SrcBits.
extractBits(DstEltSizeInBits, J * DstEltSizeInBits);
12650 unsigned Opc =
Op.getOpcode();
12657std::optional<std::pair<APInt, APInt>>
12661 return std::nullopt;
12665 return std::nullopt;
12672 return std::nullopt;
12674 for (
unsigned i = 2; i < NumOps; ++i) {
12676 return std::nullopt;
12679 if (Val != (Start + (Stride * i)))
12680 return std::nullopt;
12683 return std::make_pair(Start, Stride);
12699 for (
int Idx = Mask[i]; i != e; ++i)
12700 if (Mask[i] >= 0 && Mask[i] !=
Idx)
12708 if (isa<ConstantSDNode>(
N))
12709 return N.getNode();
12711 return N.getNode();
12719 isa<ConstantSDNode>(
N.getOperand(0)))
12720 return N.getNode();
12727 if (isa<ConstantFPSDNode>(
N))
12728 return N.getNode();
12731 return N.getNode();
12734 isa<ConstantFPSDNode>(
N.getOperand(0)))
12735 return N.getNode();
12741 assert(!Node->OperandList &&
"Node already has operands");
12743 "too many operands to fit into SDNode");
12744 SDUse *Ops = OperandRecycler.allocate(
12747 bool IsDivergent =
false;
12748 for (
unsigned I = 0;
I != Vals.
size(); ++
I) {
12749 Ops[
I].setUser(Node);
12750 Ops[
I].setInitial(Vals[
I]);
12751 if (Ops[
I].Val.getValueType() != MVT::Other)
12755 Node->OperandList = Ops;
12758 Node->SDNodeBits.IsDivergent = IsDivergent;
12766 while (Vals.
size() > Limit) {
12767 unsigned SliceIdx = Vals.
size() - Limit;
12841 const SDLoc &DLoc) {
12846 Entry.Ty =
Ptr.getValueType().getTypeForEVT(*
getContext());
12847 Args.push_back(Entry);
12859 assert(
From && To &&
"Invalid SDNode; empty source SDValue?");
12860 auto I = SDEI.find(
From);
12861 if (
I == SDEI.end())
12866 NodeExtraInfo NEI =
I->second;
12875 SDEI[To] = std::move(NEI);
12894 Leafs.emplace_back(
N);
12897 if (!FromReach.
insert(
N).second)
12905 auto DeepCopyTo = [&](
auto &&Self,
const SDNode *
N) {
12908 if (!Visited.
insert(
N).second)
12913 if (!Self(Self,
Op.getNode()))
12933 for (
const SDNode *
N : StartFrom)
12934 VisitFrom(VisitFrom,
N,
MaxDepth - PrevDepth);
12946 errs() <<
"warning: incomplete propagation of SelectionDAG::NodeExtraInfo\n";
12947 assert(
false &&
"From subgraph too complex - increase max. MaxDepth?");
12949 SDEI[To] = std::move(NEI);
12963 if (!Visited.
insert(
N).second) {
12964 errs() <<
"Detected cycle in SelectionDAG\n";
12965 dbgs() <<
"Offending node:\n";
12966 N->dumprFull(DAG);
dbgs() <<
"\n";
12982 bool check = force;
12983#ifdef EXPENSIVE_CHECKS
12987 assert(
N &&
"Checking nonexistent SDNode");
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static bool isConstant(const MachineInstr &MI)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
This file implements the BitVector class.
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
static std::optional< bool > isBigEndian(const SmallDenseMap< int64_t, int64_t, 8 > &MemOffset2Idx, int64_t LowestIdx)
Given a map from byte offsets in memory to indices in a load/store, determine if that map corresponds...
#define __asan_unpoison_memory_region(p, size)
#define LLVM_LIKELY(EXPR)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Looks at all the uses of the given value Returns the Liveness deduced from the uses of this value Adds all uses that cause the result to be MaybeLive to MaybeLiveRetUses If the result is MaybeLiveUses might be modified but its content should be ignored(since it might not be complete). DeadArgumentEliminationPass
Given that RA is a live propagate it s liveness to any other values it uses(according to Uses). void DeadArgumentEliminationPass
Given that RA is a live value
This file defines the DenseSet and SmallDenseSet classes.
This file contains constants used for implementing Dwarf debug support.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file defines a hash set that can be used to remove duplication of nodes in a graph.
Rewrite Partial Register Uses
static const unsigned MaxDepth
static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB)
static bool shouldLowerMemFuncForSize(const MachineFunction &MF)
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
static Align getPrefTypeAlign(EVT VT, SelectionDAG &DAG)
mir Rename Register Operands
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PowerPC Reduce CR logical Operation
const SmallVectorImpl< MachineOperand > & Cond
Contains matchers for matching SelectionDAG nodes and values.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static uint64_t umul_ov(uint64_t i, uint64_t j, bool &Overflow)
static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo)
Lower the call to 'memset' intrinsic function into a series of store operations.
static std::optional< APInt > FoldValueWithUndef(unsigned Opcode, const APInt &C1, bool IsUndef1, const APInt &C2, bool IsUndef2)
static SDValue FoldSTEP_VECTOR(const SDLoc &DL, EVT VT, SDValue Step, SelectionDAG &DAG)
static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned OpC, SDVTList VTList, ArrayRef< SDValue > OpList)
static SDValue getMemsetStringVal(EVT VT, const SDLoc &dl, SelectionDAG &DAG, const TargetLowering &TLI, const ConstantDataArraySlice &Slice)
getMemsetStringVal - Similar to getMemsetValue.
static cl::opt< bool > EnableMemCpyDAGOpt("enable-memcpy-dag-opt", cl::Hidden, cl::init(true), cl::desc("Gang up loads and stores generated by inlining of memcpy"))
static bool haveNoCommonBitsSetCommutative(SDValue A, SDValue B)
static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList)
AddNodeIDValueTypes - Value type lists are intern'd so we can represent them solely with their pointe...
static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef< int > M)
Swaps the values of N1 and N2.
static bool isMemSrcFromConstant(SDValue Src, ConstantDataArraySlice &Slice)
Returns true if memcpy source is constant data.
static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo)
static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo, AAResults *AA)
static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC)
AddNodeIDOpcode - Add the node opcode to the NodeID data.
static ISD::CondCode getSetCCInverseImpl(ISD::CondCode Op, bool isIntegerLike)
static bool doNotCSE(SDNode *N)
doNotCSE - Return true if CSE should not be performed for this node.
static cl::opt< int > MaxLdStGlue("ldstmemcpy-glue-max", cl::desc("Number limit for gluing ld/st of memcpy."), cl::Hidden, cl::init(0))
static void AddNodeIDOperands(FoldingSetNodeID &ID, ArrayRef< SDValue > Ops)
AddNodeIDOperands - Various routines for adding operands to the NodeID data.
static void VerifySDNode(SDNode *N)
VerifySDNode - Check the given SDNode. Aborts if it is invalid.
static SDValue foldCONCAT_VECTORS(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
Try to simplify vector concatenation to an input value, undef, or build vector.
static MachinePointerInfo InferPointerInfo(const MachinePointerInfo &Info, SelectionDAG &DAG, SDValue Ptr, int64_t Offset=0)
InferPointerInfo - If the specified ptr/offset is a frame index, infer a MachinePointerInfo record fr...
static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N)
If this is an SDNode with special info, add this info to the NodeID data.
static void NewSDValueDbgMsg(SDValue V, StringRef Msg, SelectionDAG *G)
static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs)
makeVTList - Return an instance of the SDVTList struct initialized with the specified members.
static void checkForCyclesHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallPtrSetImpl< const SDNode * > &Checked, const llvm::SelectionDAG *DAG)
static void chainLoadsAndStoresForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SmallVector< SDValue, 32 > &OutChains, unsigned From, unsigned To, SmallVector< SDValue, 16 > &OutLoadChains, SmallVector< SDValue, 16 > &OutStoreChains)
static int isSignedOp(ISD::CondCode Opcode)
For an integer comparison, return 1 if the comparison is a signed operation and 2 if the result is an...
static std::optional< APInt > FoldValue(unsigned Opcode, const APInt &C1, const APInt &C2)
static SDValue FoldBUILD_VECTOR(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
static void checkAddrSpaceIsValidForLibcall(const TargetLowering *TLI, unsigned AS)
static Constant * ConstantFold(Instruction *I, const DataLayout &DL, const SmallDenseMap< Value *, Constant * > &ConstantPool)
Try to fold instruction I into a constant.
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file describes how to lower LLVM code to machine code.
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
static OverflowResult mapOverflowResult(ConstantRange::OverflowResult OR)
Convert ConstantRange OverflowResult into ValueTracking OverflowResult.
static unsigned getSize(unsigned Kind)
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
static APFloat getQNaN(const fltSemantics &Sem, bool Negative=false, const APInt *payload=nullptr)
Factory for QNaN values.
opStatus divide(const APFloat &RHS, roundingMode RM)
void copySign(const APFloat &RHS)
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
opStatus subtract(const APFloat &RHS, roundingMode RM)
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
opStatus add(const APFloat &RHS, roundingMode RM)
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
opStatus multiply(const APFloat &RHS, roundingMode RM)
opStatus fusedMultiplyAdd(const APFloat &Multiplicand, const APFloat &Addend, roundingMode RM)
static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)
Returns the largest finite number in the given semantics.
opStatus convertToInteger(MutableArrayRef< integerPart > Input, unsigned int Width, bool IsSigned, roundingMode RM, bool *IsExact) const
static APFloat getInf(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Infinity.
opStatus mod(const APFloat &RHS)
static APFloat getNaN(const fltSemantics &Sem, bool Negative=false, uint64_t payload=0)
Factory for NaN values.
Class for arbitrary precision integers.
APInt umul_ov(const APInt &RHS, bool &Overflow) const
APInt usub_sat(const APInt &RHS) const
APInt udiv(const APInt &RHS) const
Unsigned division operation.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
void clearBit(unsigned BitPosition)
Set a given bit to 0.
APInt zext(unsigned width) const
Zero extend to a new width.
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
uint64_t getZExtValue() const
Get zero extended value.
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
unsigned popcount() const
Count the number of bits set.
void setBitsFrom(unsigned loBit)
Set the top bits starting from loBit.
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
unsigned getActiveBits() const
Compute the number of active bits in the value.
APInt trunc(unsigned width) const
Truncate to new width.
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
APInt abs() const
Get the absolute value.
APInt sadd_sat(const APInt &RHS) const
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
bool isZero() const
Determine if this value is zero, i.e. all bits are clear.
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool ult(const APInt &RHS) const
Unsigned less than comparison.
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
bool isNegative() const
Determine sign of this APInt.
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
void clearAllBits()
Set every bit to 0.
APInt rotr(unsigned rotateAmt) const
Rotate right by rotateAmt.
APInt reverseBits() const
void ashrInPlace(unsigned ShiftAmt)
Arithmetic right-shift this APInt by ShiftAmt in place.
bool sle(const APInt &RHS) const
Signed less or equal comparison.
unsigned countr_zero() const
Count the number of trailing zero bits.
unsigned getNumSignBits() const
Computes the number of leading bits of this APInt that are equal to its sign bit.
unsigned countl_zero() const
The APInt version of std::countl_zero.
static APInt getSplat(unsigned NewLen, const APInt &V)
Return a value containing V broadcasted over NewLen bits.
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
APInt sshl_sat(const APInt &RHS) const
APInt ushl_sat(const APInt &RHS) const
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
void insertBits(const APInt &SubBits, unsigned bitPosition)
Insert the bits from a smaller APInt starting at bitPosition.
void clearLowBits(unsigned loBits)
Set bottom loBits bits to 0.
unsigned logBase2() const
APInt uadd_sat(const APInt &RHS) const
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
void setAllBits()
Set every bit to 1.
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
bool ule(const APInt &RHS) const
Unsigned less or equal comparison.
APInt sext(unsigned width) const
Sign extend to a new width.
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
APInt shl(unsigned shiftAmt) const
Left-shift function.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
void setLowBits(unsigned loBits)
Set the bottom loBits bits.
APInt extractBits(unsigned numBits, unsigned bitPosition) const
Return an APInt with the extracted bits [bitPosition,bitPosition+numBits).
bool sge(const APInt &RHS) const
Signed greater or equal comparison.
static APInt getBitsSetFrom(unsigned numBits, unsigned loBit)
Constructs an APInt value that has a contiguous range of bits set.
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
void lshrInPlace(unsigned ShiftAmt)
Logical right-shift this APInt by ShiftAmt in place.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
APInt ssub_sat(const APInt &RHS) const
An arbitrary precision integer that knows its signedness.
AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT, unsigned SrcAS, unsigned DestAS)
Recycle small arrays allocated from a BumpPtrAllocator.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
This is an SDNode representing atomic operations.
static BaseIndexOffset match(const SDNode *N, const SelectionDAG &DAG)
Parses tree in N for base, index, offset addresses.
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void clear()
clear - Removes all bits from the bitvector.
bool none() const
none - Returns true if none of the bits are set.
size_type size() const
size - Returns the number of bits in this bitvector.
int64_t getOffset() const
unsigned getTargetFlags() const
const BlockAddress * getBlockAddress() const
The address of a basic block.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
A "pseudo-class" with methods for operating on BUILD_VECTORs.
bool getConstantRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &RawBitElements, BitVector &UndefElements) const
Extract the raw bit data from a build vector of Undef, Constant or ConstantFP node elements.
static void recastRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &DstBitElements, ArrayRef< APInt > SrcBitElements, BitVector &DstUndefElements, const BitVector &SrcUndefElements)
Recast bit data SrcBitElements to DstEltSizeInBits wide elements.
bool getRepeatedSequence(const APInt &DemandedElts, SmallVectorImpl< SDValue > &Sequence, BitVector *UndefElements=nullptr) const
Find the shortest repeating sequence of values in the build vector.
ConstantFPSDNode * getConstantFPSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant FP or null if this is not a constant FP splat.
std::optional< std::pair< APInt, APInt > > isConstantSequence() const
If this BuildVector is constant and represents the numerical series "<a, a+n, a+2n,...
SDValue getSplatValue(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted value or a null value if this is not a splat.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
ConstantSDNode * getConstantSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant or null if this is not a constant splat.
int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements, uint32_t BitWidth) const
If this is a constant FP splat and the splatted constant FP is an exact power or 2,...
LLVM_ATTRIBUTE_RETURNS_NONNULL void * Allocate(size_t Size, Align Alignment)
Allocate space at the specified alignment.
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it,...
static bool isValueValidForType(EVT VT, const APFloat &Val)
const APFloat & getValueAPF() const
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
const APInt & getValue() const
Return the constant as an APInt value reference.
bool isMachineConstantPoolEntry() const
This class represents a range of values.
ConstantRange multiply(const ConstantRange &Other) const
Return a new range representing the possible values resulting from a multiplication of a value in thi...
const APInt * getSingleElement() const
If this set contains a single element, return it, otherwise return null.
static ConstantRange fromKnownBits(const KnownBits &Known, bool IsSigned)
Initialize a range based on a known bits constraint.
OverflowResult unsignedSubMayOverflow(const ConstantRange &Other) const
Return whether unsigned sub of the two ranges always/never overflows.
OverflowResult unsignedAddMayOverflow(const ConstantRange &Other) const
Return whether unsigned add of the two ranges always/never overflows.
KnownBits toKnownBits() const
Return known bits for values in this range.
ConstantRange zeroExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
APInt getSignedMin() const
Return the smallest signed value contained in the ConstantRange.
OverflowResult unsignedMulMayOverflow(const ConstantRange &Other) const
Return whether unsigned mul of the two ranges always/never overflows.
ConstantRange signExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
APInt getUnsignedMax() const
Return the largest unsigned value contained in the ConstantRange.
APInt getSignedMax() const
Return the largest signed value contained in the ConstantRange.
OverflowResult
Represents whether an operation on the given constant range is known to always or never overflow.
@ NeverOverflows
Never overflows.
@ AlwaysOverflowsHigh
Always overflows in the direction of signed/unsigned max value.
@ AlwaysOverflowsLow
Always overflows in the direction of signed/unsigned min value.
@ MayOverflow
May or may not overflow.
uint32_t getBitWidth() const
Get the bit width of this ConstantRange.
OverflowResult signedSubMayOverflow(const ConstantRange &Other) const
Return whether signed sub of the two ranges always/never overflows.
uint64_t getZExtValue() const
const APInt & getAPIntValue() const
This is an important base class in LLVM.
Constant * getSplatValue(bool AllowUndefs=false) const
If all elements of the vector constant have the same value, return that value.
Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
static ExtOps getExtOps(unsigned FromSize, unsigned ToSize, bool Signed)
Returns the ops for a zero- or sign-extension in a DIExpression.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static const DIExpression * convertToVariadicExpression(const DIExpression *Expr)
If Expr is a non-variadic expression (i.e.
static std::optional< DIExpression * > createFragmentExpression(const DIExpression *Expr, unsigned OffsetInBits, unsigned SizeInBits)
Create a DIExpression to describe one part of an aggregate variable that is fragmented across multipl...
Base class for variables.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
bool isLittleEndian() const
Layout endianness...
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
unsigned getPointerTypeSizeInBits(Type *) const
Layout pointer size, in bits, based on the type.
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
void reserve(size_type NumEntries)
Grow the densemap so that it can contain at least NumEntries items before resizing again.
Implements a dense probed hash-table based set.
const char * getSymbol() const
unsigned getTargetFlags() const
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
MachineBasicBlock * MBB
MBB - The current block.
Data structure describing the variable locations in a function.
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
AttributeList getAttributes() const
Return the attribute list for this Function.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
int64_t getOffset() const
unsigned getAddressSpace() const
unsigned getTargetFlags() const
const GlobalValue * getGlobal() const
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
unsigned getAddressSpace() const
Module * getParent()
Get the module that this global value is contained inside of...
PointerType * getType() const
Global values are always pointers.
This class is used to form a handle around another node that is persistent and is updated across invo...
static bool compare(const APInt &LHS, const APInt &RHS, ICmpInst::Predicate Pred)
Return result of LHS Pred RHS comparison.
This is an important class for using LLVM in a threaded context.
This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate the offet and size that ar...
This class is used to represent ISD::LOAD nodes.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MVT getIntegerVT(unsigned BitWidth)
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Abstract base class for all machine specific constantpool value subclasses.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
A description of a memory reference used in the backend.
bool isNonTemporal() const
uint64_t getSize() const
Return the size in bytes of the memory reference.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
const MachinePointerInfo & getPointerInfo() const
Flags getFlags() const
Return the raw flags of the source value,.
bool isDereferenceable() const
An SDNode that represents everything that will be needed to construct a MachineInstr.
This class is used to represent an MGATHER node.
This class is used to represent an MLOAD node.
This class is used to represent an MSCATTER node.
This class is used to represent an MSTORE node.
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT memvt, MachineMemOperand *MMO)
MachineMemOperand * MMO
Memory reference information.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
unsigned getRawSubclassData() const
Return the SubclassData value, without HasDebugValue.
EVT getMemoryVT() const
Return the type of the in-memory value.
Representation for a specific memory location.
static uint64_t getSizeOrUnknown(const TypeSize &T)
A Module instance is used to store all the information related to an LLVM module.
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Pass interface - Implemented by all 'passes'.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Analysis providing profile information.
void Deallocate(SubClass *E)
Deallocate - Release storage for the pointed-to object.
Keeps track of dbg_value information through SDISel.
BumpPtrAllocator & getAlloc()
void add(SDDbgValue *V, bool isParameter)
void erase(const SDNode *Node)
Invalidate all DbgValues attached to the node and remove it from the Node-to-DbgValues map.
ArrayRef< SDDbgValue * > getSDDbgValues(const SDNode *Node) const
Holds the information from a dbg_label node through SDISel.
Holds the information for a single machine location through SDISel; either an SDNode,...
static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo)
static SDDbgOperand fromFrameIdx(unsigned FrameIdx)
static SDDbgOperand fromVReg(unsigned VReg)
static SDDbgOperand fromConst(const Value *Const)
@ SDNODE
Value is the result of an expression.
Holds the information from a dbg_value node through SDISel.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
const DebugLoc & getDebugLoc() const
unsigned getIROrder() const
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
ArrayRef< SDUse > ops() const
const APInt & getAsAPIntVal() const
Helper method returns the APInt value of a ConstantSDNode.
void dumprFull(const SelectionDAG *G=nullptr) const
printrFull to dbgs().
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isOnlyUserOf(const SDNode *N) const
Return true if this node is the only use of N.
iterator_range< value_op_iterator > op_values() const
unsigned getIROrder() const
Return the node ordering.
static constexpr size_t getMaxNumOperands()
Return the maximum number of operands that a SDNode can hold.
MemSDNodeBitfields MemSDNodeBits
void Profile(FoldingSetNodeID &ID) const
Gather unique data for the node.
bool getHasDebugValue() const
SDNodeFlags getFlags() const
void setNodeId(int Id)
Set unique node id.
void intersectFlagsWith(const SDNodeFlags Flags)
Clear any flags in this node that aren't also set in Flags.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallVectorImpl< const SDNode * > &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
bool use_empty() const
Return true if there are no uses of this node.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
unsigned getNumOperands() const
Return the number of values used by this operation.
const SDValue & getOperand(unsigned Num) const
static bool areOnlyUsersOf(ArrayRef< const SDNode * > Nodes, const SDNode *N)
Return true if all the users of N are contained in Nodes.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
bool isOperandOf(const SDNode *N) const
Return true if this node is an operand of N.
const APInt & getConstantOperandAPInt(unsigned Num) const
Helper method returns the APInt of a ConstantSDNode operand.
bool hasPredecessor(const SDNode *N) const
Return true if N is a predecessor of this node.
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isUndef() const
Return true if the type of the node type undefined.
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
Return true if there are exactly NUSES uses of the indicated value.
op_iterator op_end() const
op_iterator op_begin() const
static use_iterator use_end()
void DropOperands()
Release the operands and set this node to have zero operands.
Represents a use of a SDNode.
SDNode * getNode() const
Convenience function for get().getNode().
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool isOperandOf(const SDNode *N) const
Return true if this node is an operand of N.
bool reachesChainWithoutSideEffects(SDValue Dest, unsigned Depth=2) const
Return true if this operand (which must be a chain) reaches the specified operand without crossing an...
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
bool use_empty() const
Return true if there are no nodes using value ResNo of Node.
const APInt & getConstantOperandAPInt(unsigned i) const
uint64_t getScalarValueSizeInBits() const
unsigned getResNo() const
get the index which selects a specific result in the SDNode
uint64_t getConstantOperandVal(unsigned i) const
unsigned getOpcode() const
virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo) const
Emit target-specific code that performs a memset.
virtual SDValue EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memmove.
virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memcpy.
SDNodeFlags getFlags() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Align getReducedAlign(EVT VT, bool UseABI)
In most cases this function returns the ABI alignment for a given type, except for illegal vector typ...
SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op)
Return the specified value casted to the target's desired shift amount type.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getExtLoadVP(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsExpanding=false)
SDValue getSplatSourceVector(SDValue V, int &SplatIndex)
If V is a splatted value, return the source vector and its splat index.
SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
OverflowKind computeOverflowForUnsignedSub(SDValue N0, SDValue N1) const
Determine if the result of the unsigned sub of 2 nodes can overflow.
unsigned ComputeMaxSignificantBits(SDValue Op, unsigned Depth=0) const
Get the upper bound on bit size for this Value Op as a signed integer.
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy)
bool isKnownNeverSNaN(SDValue Op, unsigned Depth=0) const
SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
Return an AddrSpaceCastSDNode.
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
SDValue getStackArgumentTokenFactor(SDValue Chain)
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
const TargetSubtargetInfo & getSubtarget() const
const APInt * getValidMaximumShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has constant shift amounts that are all less than the element bit-width of th...
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
void updateDivergence(SDNode *N)
SDValue getSplatValue(SDValue V, bool LegalTypes=false)
If V is a splat vector, return its scalar source operand by extracting that element from the source v...
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl)
Constant fold a setcc to true or false.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
SDValue getNeutralElement(unsigned Opcode, const SDLoc &DL, EVT VT, SDNodeFlags Flags)
Get the (commutative) neutral element for the given opcode, if it exists.
SDValue getAtomicMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo)
SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold=true)
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr)
Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing,...
SDValue getFreeze(SDValue V)
Return a freeze using the SDLoc of the value operand.
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type,...
SelectionDAG(const TargetMachine &TM, CodeGenOptLevel)
SDValue getBitcastedSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getStridedLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDNode * isConstantIntBuildVectorOrConstantInt(SDValue N) const
Test whether the given value is a constant int or similar node.
SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
Gets a node for an atomic cmpxchg op.
SDValue makeEquivalentMemoryOrdering(SDValue OldChain, SDValue NewMemOpChain)
If an existing load has uses of its chain, create a token factor node with that chain and the new mem...
SDDbgValue * getVRegDbgValue(DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a VReg SDDbgValue node.
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
SDValue getJumpTableDebugInfo(int JTI, SDValue Chain, const SDLoc &DL)
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getSymbolFunctionGlobalAddress(SDValue Op, Function **TargetFunction=nullptr)
Return a GlobalAddress of the function from the current module with name matching the given ExternalS...
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
OverflowKind
Used to represent the possible overflow behavior of an operation.
bool isADDLike(SDValue Op) const
Return true if the specified operand is an ISD::OR or ISD::XOR node that can be treated as an ISD::AD...
bool haveNoCommonBitsSet(SDValue A, SDValue B) const
Return true if A and B have no common bits set.
bool calculateDivergence(SDNode *N)
SDValue getElementCount(const SDLoc &DL, EVT VT, ElementCount EC, bool ConstantFold=true)
SDValue getGetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getAssertAlign(const SDLoc &DL, SDValue V, Align A)
Return an AssertAlignSDNode.
SDNode * mutateStrictFPToFP(SDNode *Node)
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain a...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getBitcastedZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Align getEVTAlign(EVT MemoryVT) const
Compute the default alignment value for the given type.
void VerifyDAGDivergence()
bool shouldOptForSize() const
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
SDValue getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT,...
const TargetLowering & getTargetLoweringInfo() const
bool isEqualTo(SDValue A, SDValue B) const
Test whether two SDValues are known to compare equal.
static constexpr unsigned MaxRecursionDepth
SDValue getStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
SDValue expandVACopy(SDNode *Node)
Expand the specified ISD::VACOPY node as the Legalize pass would.
SDValue getIndexedMaskedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
APInt computeVectorKnownZeroElements(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
For each demanded element of a vector, see if it is known to be zero.
void AddDbgValue(SDDbgValue *DB, bool isParameter)
Add a dbg_value SDNode.
bool NewNodesMustHaveLegalTypes
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG n...
std::pair< EVT, EVT > GetSplitDestVTs(const EVT &VT) const
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not neces...
void salvageDebugInfo(SDNode &N)
To be invoked on an SDNode that is slated to be erased.
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
std::pair< SDValue, SDValue > UnrollVectorOverflowOp(SDNode *N, unsigned ResNE=0)
Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.
allnodes_const_iterator allnodes_begin() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const
Test whether V has a splatted value for all the demanded elements.
void DeleteNode(SDNode *N)
Remove the specified node from the system.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
SDDbgValue * getDbgValueList(DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic)
Creates a SDDbgValue node from a list of locations.
SDValue getNegative(SDValue Val, const SDLoc &DL, EVT VT)
Create negative operation as (SUB 0, Val).
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
SDValue simplifySelect(SDValue Cond, SDValue TVal, SDValue FVal)
Try to simplify a select/vselect into 1 of its operands or a constant.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
const DataLayout & getDataLayout() const
SDNode * isConstantFPBuildVectorOrConstantFP(SDValue N) const
Test whether the given value is a constant FP or similar node.
SDValue expandVAArg(SDNode *Node)
Expand the specified ISD::VAARG node as the Legalize pass would.
SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
Creates a new TokenFactor containing Vals.
bool doesNodeExist(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops)
Check if a node exists without modifying its flags.
bool areNonVolatileConsecutiveLoads(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const
Return true if loads are next to each other and can be merged.
SDDbgLabel * getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O)
Creates a SDDbgLabel node.
SDValue getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
OverflowKind computeOverflowForUnsignedMul(SDValue N0, SDValue N1) const
Determine if the result of the unsigned mul of 2 nodes can overflow.
void copyExtraInfo(SDNode *From, SDNode *To)
Copy extra info associated with one node to another.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
void clear()
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV)
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swa...
std::pair< SDValue, SDValue > SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part.
const APInt * getValidShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has a constant or splat constant shift amount that is less than the element b...
SDValue makeStateFunctionCall(unsigned LibFunc, SDValue Ptr, SDValue InChain, const SDLoc &DLoc)
Helper used to make a call to a library function that has one argument of pointer type.
bool isGuaranteedNotToBeUndefOrPoison(SDValue Op, bool PoisonOnly=false, unsigned Depth=0) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getIndexedLoadVP(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getSrcValue(const Value *v)
Construct a node to track a Value* through the backend.
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op)
SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
OverflowKind computeOverflowForSignedMul(SDValue N0, SDValue N1) const
Determine if the result of the signed mul of 2 nodes can overflow.
MaybeAlign InferPtrAlign(SDValue Ptr) const
Infer alignment of a load / store address.
bool MaskedValueIsAllOnes(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if '(Op & Mask) == Mask'.
bool SignBitIsZero(SDValue Op, unsigned Depth=0) const
Return true if the sign bit of Op is known to be zero.
SDValue getRegister(unsigned Reg, EVT VT)
void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, FunctionVarLocs const *FnVarLocs)
Prepare this SelectionDAG to process code in the given MachineFunction.
void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
void AddDbgLabel(SDDbgLabel *DB)
Add a dbg_label SDNode.
bool isConstantValueOfAnyType(SDValue N) const
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getBasicBlock(MachineBasicBlock *MBB)
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
bool isKnownToBeAPowerOfTwo(SDValue Val, unsigned Depth=0) const
Test if the given value is known to have exactly one bit set.
SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label)
SDValue getIndexedStoreVP(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
bool isKnownNeverZero(SDValue Op, unsigned Depth=0) const
Test whether the given SDValue is known to contain non-zero value(s).
SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getSetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate ...
SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
std::pair< SDValue, SDValue > getStrictFPExtendOrRound(SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT)
Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending...
std::pair< SDValue, SDValue > SplitEVL(SDValue N, EVT VecVT, const SDLoc &DL)
Split the explicit vector length parameter of a VP operation.
SDValue getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or perform...
SDValue getStepVector(const SDLoc &DL, EVT ResVT, APInt StepVal)
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step,...
SDValue getVPLogicalNOT(const SDLoc &DL, SDValue Val, SDValue Mask, SDValue EVL, EVT VT)
Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask,...
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
iterator_range< allnodes_iterator > allnodes()
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
SDValue WidenVector(const SDValue &N, const SDLoc &DL)
Widen the vector up to the next power of two using INSERT_SUBVECTOR.
bool isKnownNeverZeroFloat(SDValue Op) const
Test whether the given floating point SDValue is known to never be positive or negative zero.
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, uint64_t Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDDbgValue * getConstantDbgValue(DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
Creates a constant SDDbgValue node.
SDValue getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getValueType(EVT)
ArrayRef< SDDbgValue * > GetDbgValues(const SDNode *SD) const
Get the debug values which reference the given SDNode.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
OverflowKind computeOverflowForSignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the signed addition of 2 nodes can overflow.
SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by tr...
unsigned AssignTopologicalOrder()
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on th...
ilist< SDNode >::size_type allnodes_size() const
SDValue getAtomicMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
bool isKnownNeverNaN(SDValue Op, bool SNaN=false, unsigned Depth=0) const
Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.
SDValue getIndexedMaskedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getTruncStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsCompressing=false)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
bool MaskedVectorIsZero(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
Return true if 'Op' is known to be zero in DemandedElts.
SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT)
Create a true or false constant of type VT using the target's BooleanContent for type OpVT.
SDDbgValue * getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a FrameIndex SDDbgValue node.
SDValue getExtStridedLoadVP(ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDValue getJumpTable(int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0)
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
SDValue getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT,...
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy ...
bool canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
OverflowKind computeOverflowForUnsignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the unsigned addition of 2 nodes can overflow.
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getTruncStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false)
void canonicalizeCommutativeBinop(unsigned Opcode, SDValue &N1, SDValue &N2) const
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite o...
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue getCondCode(ISD::CondCode Cond)
SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset=-1)
Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the por...
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
OverflowKind computeOverflowForSignedSub(SDValue N0, SDValue N1) const
Determine if the result of the signed sub of 2 nodes can overflow.
LLVMContext * getContext() const
SDValue simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y, SDNodeFlags Flags)
Try to simplify a floating-point binary operation into 1 of its operands or a constant.
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
const APInt * getValidMinimumShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has constant shift amounts that are all less than the element bit-width of th...
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL, bool LegalTypes=true)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
bool isUndef(unsigned Opcode, ArrayRef< SDValue > Ops)
Return true if the result of this operation is always undefined.
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
std::pair< EVT, EVT > GetDependentSplitDestVTs(const EVT &VT, const EVT &EnvVT, bool *HiIsEmpty) const
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been sp...
SDValue foldConstantFPMath(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
Fold floating-point operations when all operands are constants and/or undefined.
SDNode * getNodeIfExists(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
Get the specified node if it's already available, or else return NULL.
SDValue FoldSymbolOffset(unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2)
SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDDbgValue * getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a SDDbgValue node.
SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false)
SDValue getSplat(EVT VT, const SDLoc &DL, SDValue Op)
Returns a node representing a splat of one value into all lanes of the provided vector type.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
SDValue matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp, ArrayRef< ISD::NodeType > CandidateBinOps, bool AllowPartials=false)
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector ...
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
SDValue simplifyShift(SDValue X, SDValue Y)
Try to simplify a shift into 1 of its operands or a constant.
void transferDbgValues(SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true)
Transfer debug values from one node to another, while optionally generating fragment expressions for ...
SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a logical NOT operation as (XOR Val, BooleanOne).
SDValue getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false)
ilist< SDNode >::iterator allnodes_iterator
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
static bool isSplatMask(const int *Mask, EVT VT)
int getMaskElt(unsigned Idx) const
ArrayRef< int > getMask() const
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void assign(size_type NumElts, ValueParamT Elt)
reference emplace_back(ArgTypes &&... Args)
void reserve(size_type N)
iterator erase(const_iterator CI)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
Information about stack frame layout on the target.
virtual TargetStackID::Value getStackIDForScalableVectors() const
Returns the StackID that scalable vectors should be associated with.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Completely target-dependent object reference.
int64_t getOffset() const
unsigned getTargetFlags() const
Provides information about what library functions are available for the current target.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself.
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
const TargetMachine & getTargetMachine() const
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
virtual bool shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const
Return true if the target shall perform extract vector element and store given that the vector is kno...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it's free to truncate a value of type FromTy to type ToTy.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
BooleanContent
Enum that describes how the target represents true/false values.
@ ZeroOrOneBooleanContent
@ UndefinedBooleanContent
@ ZeroOrNegativeOneBooleanContent
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
virtual unsigned getMaxGluedStoresPerMemcpy() const
Get maximum # of store operations to be glued together.
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
std::vector< ArgListEntry > ArgListTy
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
virtual bool isLegalStoreImmediate(int64_t Value) const
Return true if the specified immediate is legal for the value input of a store instruction.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
static ISD::NodeType getExtendForContent(BooleanContent Content)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual void computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) const
Determine which of the bits of FrameIndex FIOp are known to be 0.
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
virtual bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const
Determines the optimal series of memory ops to replace the memset / memcpy.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const
If SNaN is false,.
virtual void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
virtual bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const
virtual bool isSDNodeAlwaysUniform(const SDNode *N) const
virtual bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) const
Return true if vector Op has the same value across all DemandedElts, indicating any elements which ma...
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
virtual const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const
This method returns the constant pool value that will be loaded by LD.
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
virtual bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
virtual bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
Primary interface to the complete machine description for the target machine.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetLowering * getTargetLowering() const
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
static Type * getVoidTy(LLVMContext &C)
static IntegerType * getInt8Ty(LLVMContext &C)
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
A Use represents the edge between a Value definition and its users.
This class is used to represent an VP_GATHER node.
This class is used to represent a VP_LOAD node.
This class is used to represent an VP_SCATTER node.
This class is used to represent a VP_STORE node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_LOAD node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_STORE node.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
std::pair< iterator, bool > insert(const ValueT &V)
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
constexpr ScalarTy getFixedValue() const
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr bool isKnownEven() const
A return value of true indicates we know at compile time that the number of elements (vscale * Min) i...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
static constexpr bool isKnownGE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
SmartMutex - A mutex with a compile time constant parameter that indicates whether this mutex should ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const APInt abdu(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be unsigned.
APInt avgCeilU(const APInt &C1, const APInt &C2)
Compute the ceil of the unsigned average of C1 and C2.
APInt avgFloorU(const APInt &C1, const APInt &C2)
Compute the floor of the unsigned average of C1 and C2.
const APInt abds(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be signed.
APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth, bool MatchAllBits=false)
Splat/Merge neighboring bits to widen/narrow the bitmask represented by.
APInt avgFloorS(const APInt &C1, const APInt &C2)
Compute the floor of the signed average of C1 and C2.
APInt avgCeilS(const APInt &C1, const APInt &C2)
Compute the ceil of the signed average of C1 and C2.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X...
bool isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are ~0 ...
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ JUMP_TABLE_DEBUG_INFO
JUMP_TABLE_DEBUG_INFO - Jumptable debug info.
@ BSWAP
Byte Swap and Counting operators.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ FADD
Simple binary floating point operators.
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SRCVALUE
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ SIGN_EXTEND
Conversion operators.
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ SSUBO
Same for subtraction.
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ UNDEF
UNDEF - An undefined node.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
@ BasicBlock
Various leaf nodes.
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ SMULO
Same for multiplication.
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ LIFETIME_START
This corresponds to the llvm.lifetime.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
@ BF16_TO_FP
BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions and truncation for bfloat16.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ GET_FPENV_MEM
Gets the current floating-point environment.
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ SET_FPENV_MEM
Sets the current floating point environment.
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
unsigned getVPForBaseOpcode(unsigned Opcode)
Translate this non-VP Opcode to its corresponding VP Opcode.
bool isBuildVectorOfConstantSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantSDNode or undef.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
bool matchUnaryPredicate(SDValue Op, std::function< bool(ConstantSDNode *)> Match, bool AllowUndefs=false)
Hook for matching ConstantSDNode predicate.
bool isZEXTLoad(const SDNode *N)
Returns true if the specified node is a ZEXTLOAD.
bool matchUnaryFpPredicate(SDValue Op, std::function< bool(ConstantFPSDNode *)> Match, bool AllowUndefs=false)
Hook for matching ConstantFPSDNode predicate.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
bool isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are 0 o...
bool isVectorShrinkable(const SDNode *N, unsigned NewEltSize, bool Signed)
Returns true if the specified node is a vector where all elements can be truncated to the specified e...
bool matchUnaryPredicateImpl(SDValue Op, std::function< bool(ConstNodeType *)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant BUI...
bool isVPBinaryOp(unsigned Opcode)
Whether this is a vector-predicated binary operation opcode.
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
std::optional< unsigned > getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept)
Translate this VP Opcode to its corresponding non-VP Opcode.
bool isTrueWhenEqual(CondCode Cond)
Return true if the specified condition returns true if the two operands to the condition are equal.
std::optional< unsigned > getVPMaskIdx(unsigned Opcode)
The operand position of the vector mask.
unsigned getUnorderedFlavor(CondCode Cond)
This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition i...
std::optional< unsigned > getVPExplicitVectorLengthIdx(unsigned Opcode)
The operand position of the explicit vector length parameter.
bool isEXTLoad(const SDNode *N)
Returns true if the specified node is a EXTLOAD.
bool allOperandsUndef(const SDNode *N)
Return true if the node has at least one operand and all operands of the specified node are ISD::UNDE...
bool isFreezeUndef(const SDNode *N)
Return true if the specified node is FREEZE(UNDEF).
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
bool isBuildVectorAllZeros(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.
bool isConstantSplatVector(const SDNode *N, APInt &SplatValue)
Node predicates.
bool matchBinaryPredicate(SDValue LHS, SDValue RHS, std::function< bool(ConstantSDNode *, ConstantSDNode *)> Match, bool AllowUndefs=false, bool AllowTypeMismatch=false)
Attempt to match a binary predicate against a pair of scalar/splat constants or every element of a pa...
bool isVPReduction(unsigned Opcode)
Whether this is a vector-predicated reduction opcode.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
bool isBuildVectorOfConstantFPSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantFPSDNode or undef.
bool isSEXTLoad(const SDNode *N)
Returns true if the specified node is a SEXTLOAD.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
bool isBuildVectorAllOnes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef.
NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode)
Get underlying scalar opcode for VECREDUCE opcode.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X ...
BinaryOp_match< LHS, RHS, Instruction::And > m_And(const LHS &L, const RHS &R)
deferredval_ty< Value > m_Deferred(Value *const &V)
Like m_Specific(), but works if the specific value to match is determined as part of the same match()...
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
is_zero m_Zero()
Match any null constant or a vector with all elements equal to 0.
BinaryOp_match< LHS, RHS, Instruction::Sub > m_Sub(const LHS &L, const RHS &R)
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
bool sd_match(SDNode *N, const SelectionDAG *DAG, Pattern &&P)
initializer< Ty > init(const Ty &Val)
@ DW_OP_LLVM_arg
Only used in LLVM metadata.
std::lock_guard< SmartMutex< mt_only > > SmartScopedLock
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
bool operator<(int64_t V1, const APSInt &V2)
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
SDValue peekThroughExtractSubvectors(SDValue V)
Return the non-extracted vector source operand of V if it exists.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
SDValue getBitwiseNotOperand(SDValue V, SDValue Mask, bool AllowUndefs)
If V is a bitwise not, returns the inverted operand.
SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
bool isIntOrFPConstant(SDValue V)
Return true if V is either a integer or FP constant.
bool getAlign(const Function &F, unsigned index, unsigned &align)
bool getConstantDataArrayInfo(const Value *V, ConstantDataArraySlice &Slice, unsigned ElementSize, uint64_t Offset=0)
Returns true if the value V is a pointer into a ConstantDataArray.
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 maximum semantics.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
bool isMinSignedConstant(SDValue V)
Returns true if V is a constant min signed integer value.
ConstantFPSDNode * isConstOrConstSplatFP(SDValue N, bool AllowUndefs=false)
Returns the SDNode if it is a constant splat BuildVector or constant float.
ConstantRange getConstantRangeFromMetadata(const MDNode &RangeMD)
Parse out a conservative ConstantRange from !range metadata.
APFloat frexp(const APFloat &X, int &Exp, APFloat::roundingMode RM)
Equivalent of C standard library function.
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
bool getShuffleDemandedElts(int SrcWidth, ArrayRef< int > Mask, const APInt &DemandedElts, APInt &DemandedLHS, APInt &DemandedRHS, bool AllowUndefElts=false)
Transform a shuffle mask's output demanded element mask into demanded element masks for the 2 operand...
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 maximumNumber semantics.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
bool isBitwiseNot(SDValue V, bool AllowUndefs=false)
Returns true if V is a bitwise not operation.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void checkForCycles(const SelectionDAG *DAG, bool force=false)
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
SDValue peekThroughTruncates(SDValue V)
Return the non-truncated source operand of V if it exists.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
SDValue peekThroughOneUseBitcasts(SDValue V)
Return the non-bitcasted and one-use source operand of V if it exists.
CodeGenOptLevel
Code generation optimization level.
bool isOneOrOneSplat(SDValue V, bool AllowUndefs=false)
Return true if the value is a constant 1 integer or a splatted vector of a constant 1 integer (with n...
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 minimumNumber semantics.
@ Mul
Product of integers.
void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
DWARFExpression::Operation Op
ConstantSDNode * isConstOrConstSplat(SDValue N, bool AllowUndefs=false, bool AllowTruncation=false)
Returns the SDNode if it is a constant splat BuildVector or constant int.
OutputIt copy(R &&Range, OutputIt Out)
constexpr unsigned BitWidth
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
bool isNullFPConstant(SDValue V)
Returns true if V is an FP constant with a value of positive zero.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
unsigned Log2(Align A)
Returns the log2 of the alignment.
void computeKnownBitsFromRangeMetadata(const MDNode &Ranges, KnownBits &Known)
Compute known bits from the range metadata.
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 minimum semantics.
bool isNeutralConstant(unsigned Opc, SDNodeFlags Flags, SDValue V, unsigned OperandNo)
Returns true if V is a neutral element of Opc with Flags.
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
constexpr uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * TBAAStruct
The tag for type-based alias analysis (tbaa struct).
MDNode * TBAA
The tag for type-based alias analysis.
static const fltSemantics & IEEEsingle() LLVM_READNONE
cmpResult
IEEE-754R 5.11: Floating Point Comparison Relations.
static constexpr roundingMode rmTowardNegative
static constexpr roundingMode rmNearestTiesToEven
static constexpr roundingMode rmTowardZero
static const fltSemantics & IEEEquad() LLVM_READNONE
static const fltSemantics & IEEEdouble() LLVM_READNONE
static const fltSemantics & IEEEhalf() LLVM_READNONE
static constexpr roundingMode rmTowardPositive
static const fltSemantics & BFloat() LLVM_READNONE
opStatus
IEEE-754R 7: Default exception handling.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Represents offset+length into a ConstantDataArray.
uint64_t Length
Length of the slice.
uint64_t Offset
Slice starts at this Offset.
void move(uint64_t Delta)
Moves the Offset and adjusts Length accordingly.
const ConstantDataArray * Array
ConstantDataArray pointer.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
intptr_t getRawBits() const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
ElementCount getVectorElementCount() const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
bool isFixedLengthVector() const
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
bool bitsEq(EVT VT) const
Return true if this has the same number of bits as VT.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isExtended() const
Test if the given EVT is extended (as opposed to being simple).
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
bool isInteger() const
Return true if this is an integer or a vector integer type.
static KnownBits makeConstant(const APInt &C)
Create known bits from a known constant.
KnownBits sextInReg(unsigned SrcBitWidth) const
Return known bits for a in-register sign extension of the value we're tracking.
static KnownBits mulhu(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from zero-extended multiply-hi.
unsigned countMinSignBits() const
Returns the number of times the sign bit is replicated into the other bits.
static KnownBits smax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smax(LHS, RHS).
bool isNonNegative() const
Returns true if this value is known to be non-negative.
bool isZero() const
Returns true if value is all zero.
void makeNonNegative()
Make this value non-negative.
static KnownBits usub_sat(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from llvm.usub.sat(LHS, RHS)
unsigned countMinTrailingZeros() const
Returns the minimum number of trailing zero bits.
static KnownBits ashr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for ashr(LHS, RHS).
static KnownBits urem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for urem(LHS, RHS).
bool isUnknown() const
Returns true if we don't know any bits.
unsigned countMaxTrailingZeros() const
Returns the maximum number of trailing zero bits possible.
static std::optional< bool > ne(const KnownBits &LHS, const KnownBits &RHS)
Determine if these known bits always give the same ICMP_NE result.
void makeNegative()
Make this value negative.
KnownBits trunc(unsigned BitWidth) const
Return known bits for a truncation of the value we're tracking.
KnownBits byteSwap() const
bool hasConflict() const
Returns true if there is conflicting information.
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
void setAllZero()
Make all bits known to be zero and discard any previous information.
KnownBits reverseBits() const
KnownBits concat(const KnownBits &Lo) const
Concatenate the bits from Lo onto the bottom of *this.
unsigned getBitWidth() const
Get the bit width of this value.
static KnownBits umax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umax(LHS, RHS).
KnownBits zext(unsigned BitWidth) const
Return known bits for a zero extension of the value we're tracking.
void resetAll()
Resets the known state of all bits.
KnownBits unionWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for either this or RHS or both.
static KnownBits lshr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for lshr(LHS, RHS).
bool isNonZero() const
Returns true if this value is known to be non-zero.
KnownBits extractBits(unsigned NumBits, unsigned BitPosition) const
Return a subset of the known bits from [bitPosition,bitPosition+numBits).
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
KnownBits sext(unsigned BitWidth) const
Return known bits for a sign extension of the value we're tracking.
static KnownBits computeForSubBorrow(const KnownBits &LHS, KnownBits RHS, const KnownBits &Borrow)
Compute known bits results from subtracting RHS from LHS with 1-bit Borrow.
KnownBits zextOrTrunc(unsigned BitWidth) const
Return known bits for a zero extension or truncation of the value we're tracking.
APInt getMaxValue() const
Return the maximal unsigned value possible given these KnownBits.
static KnownBits smin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smin(LHS, RHS).
static KnownBits mulhs(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from sign-extended multiply-hi.
static KnownBits srem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for srem(LHS, RHS).
static KnownBits udiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for udiv(LHS, RHS).
static KnownBits computeForAddSub(bool Add, bool NSW, bool NUW, const KnownBits &LHS, const KnownBits &RHS)
Compute known bits resulting from adding LHS and RHS.
static KnownBits sdiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for sdiv(LHS, RHS).
static bool haveNoCommonBitsSet(const KnownBits &LHS, const KnownBits &RHS)
Return true if LHS and RHS have no common bits set.
bool isNegative() const
Returns true if this value is known to be negative.
static KnownBits computeForAddCarry(const KnownBits &LHS, const KnownBits &RHS, const KnownBits &Carry)
Compute known bits resulting from adding LHS, RHS and a 1-bit Carry.
unsigned countMaxLeadingZeros() const
Returns the maximum number of leading zero bits possible.
void insertBits(const KnownBits &SubBits, unsigned BitPosition)
Insert the bits from a smaller known bits starting at bitPosition.
static KnownBits mul(const KnownBits &LHS, const KnownBits &RHS, bool NoUndefSelfMultiply=false)
Compute known bits resulting from multiplying LHS and RHS.
KnownBits anyext(unsigned BitWidth) const
Return known bits for an "any" extension of the value we're tracking, where we don't know anything ab...
KnownBits abs(bool IntMinIsPoison=false) const
Compute known bits for the absolute value.
static KnownBits shl(const KnownBits &LHS, const KnownBits &RHS, bool NUW=false, bool NSW=false, bool ShAmtNonZero=false)
Compute known bits for shl(LHS, RHS).
static KnownBits umin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umin(LHS, RHS).
This class contains a discriminated union of information about pointers in memory operands,...
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
MachinePointerInfo getWithOffset(int64_t O) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign, bool IsZeroMemset, bool IsVolatile)
static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign, Align SrcAlign, bool IsVolatile, bool MemcpyStrSrc=false)
These are IR-level optimization flags that may be propagated to SDNodes.
void intersectWith(const SDNodeFlags Flags)
Clear any flags in this flag set that aren't also set in Flags.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Clients of various APIs that cause global effects on the DAG can optionally implement this interface.
DAGUpdateListener *const Next
virtual void NodeDeleted(SDNode *N, SDNode *E)
The node N that was deleted and, if E is not null, an equivalent node E that replaced it.
virtual void NodeInserted(SDNode *N)
The node N that was inserted.
virtual void NodeUpdated(SDNode *N)
The node N that was updated.
This structure contains all information that is necessary for lowering calls.
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setTailCall(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)