LLVM 20.0.0git
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Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation. More...
#include "llvm/CodeGen/SelectionDAGNodes.h"
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struct | DenseMapInfo< SDValue > |
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Many nodes return multiple values, from loads (which define a token and a return value) to ADDC (which returns a result and a carry value), to calls (which may return an arbitrary number of values).
As such, each use of a SelectionDAG computation must indicate the node that computes it as well as which return value to use from that node. This pair of information is represented with the SDValue value type.
Definition at line 145 of file SelectionDAGNodes.h.
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Referenced by getValue().
Definition at line 1186 of file SelectionDAGNodes.h.
References assert().
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Definition at line 1252 of file SelectionDAGNodes.h.
References Node::dump().
Referenced by lowerStatepointMetaArgs(), PerformSHLSimplify(), llvm::AArch64TargetLowering::ReconstructShuffle(), and llvm::SelectionDAGBuilder::resolveDanglingDebugInfo().
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Definition at line 1256 of file SelectionDAGNodes.h.
References Node::dump(), and G.
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Definition at line 1260 of file SelectionDAGNodes.h.
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Definition at line 1264 of file SelectionDAGNodes.h.
References G.
Definition at line 1216 of file SelectionDAGNodes.h.
Referenced by combineAndShuffleNot(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineOr(), combineShiftLeft(), foldXorTruncShiftIntoCmp(), getFauxShuffleMask(), llvm::SelectionDAG::getNode(), LowerBuildVectorv4x32(), lowerShuffleOfExtractsAsVperm(), llvm::SelectionDAG::matchBinOpReduction(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformMinMaxToSatCombine(), llvm::RISCVDAGToDAGISel::selectShiftMask(), and llvm::TargetLowering::SimplifySetCC().
Definition at line 1212 of file SelectionDAGNodes.h.
Referenced by canonicalizeLaneShuffleWithRepeatedOps(), checkBoolTestSetCCCombine(), combine_CC(), combineAnd(), combineAndOrForCcmpCtest(), combineCarryThroughADD(), combineCMP(), combineCompareEqual(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineSubABS(), combineSubSetcc(), combineTargetShuffle(), combineVectorShiftImm(), combineX86ShuffleChainWithExtract(), constructDup(), findMoreOptimalIndexType(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), getBaseWithOffsetUsingSplitOR(), getFauxShuffleMask(), llvm::SelectionDAG::getNode(), getPowerOf2Factor(), getVectorCompareInfo(), getVPermMask(), isAbsolute(), isAddSubOrSubAdd(), IsCMPZCSINC(), isDeinterleaveShuffle(), llvm::AArch64TargetLowering::isDesirableToCommuteWithShift(), isHopBuildVector(), isHorizontalBinOpPart(), isI128MovedFromParts(), isStoreConditional(), LowerBUILD_VECTORToVIDUP(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv4x32(), mergeEltWithShuffle(), PeepholePPC64ZExtGather(), performANDORCSELCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSETCCCombine(), performSetCCPunpkCombine(), performSRACombine(), performUADDVAddCombine(), performUzpCombine(), PerformVMOVRRDCombine(), PerformVSetCCToVCTPCombine(), ReconstructTruncateFromBuildVector(), reduceBuildVecToShuffleWithZero(), ReorganizeVector(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), tryWhileWRFromOR(), and vectorizeExtractedCast().
Definition at line 1248 of file SelectionDAGNodes.h.
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Definition at line 1232 of file SelectionDAGNodes.h.
Referenced by isEligibleToFoldADDIForFasterLocalAccesses(), isF128MovedFromParts(), PeepholePPC64ZExtGather(), llvm::SITargetLowering::PostISelFolding(), and usesAllOnesMask().
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get the SDNode which holds the desired result
Definition at line 159 of file SelectionDAGNodes.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineTo64bitUMAAL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), AddGlue(), llvm::AMDGPUTargetLowering::addTokenForArgument(), adjustBitcastSrcVectorSSE1(), buildCallOperands(), BuildExactSDIV(), BuildExactUDIV(), buildFromShuffleMostly(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), calculatePreExtendType(), canonicalizeShuffleMaskWithHorizOp(), llvm::checkForCycles(), CheckForMaskedLoad(), combineAdd(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAnd(), combineAndnp(), combineBitcast(), combineBoolVectorAndTruncateStore(), combineCarryDiamond(), combineCarryThroughADD(), combineCCMask(), combineCMov(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineFaddCFmul(), combineHorizOpWithShuffle(), combineINSERT_SUBVECTOR(), combineOrXorWithSETCC(), combinePTESTCC(), combineSelectAndUse(), combineSelectAndUseCommutative(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineSextInRegCmov(), combineShiftLeft(), combineShiftRightLogical(), combineShuffleOfScalars(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendCMOV(), combineUADDO_CARRYDiamond(), combineVectorMulToSraBitcast(), combineVectorPack(), combineVectorShiftImm(), combineVectorShiftVar(), CombineVLDDUP(), combineX86SubCmpForFlags(), combineXor(), combineZext(), computeZeroableShuffleElements(), llvm::SelectionDAG::copyExtraInfo(), distributeOpThroughSelect(), EltsFromConsecutiveLoads(), emitCmp(), emitConjunctionRec(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandMUL_LOHI(), ExpandPowI(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), findConsecutiveLoad(), findEltLoadSrc(), findMemSDNode(), foldADDIForFasterLocalAccesses(), foldBoolSelectToLogic(), llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), foldVectorXorShiftIntoCmp(), GenerateTBL(), llvm::PPC::get_VSPLTI_elt(), getBuildPairElt(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::TargetLowering::getCheaperOrNeutralNegatedExpression(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::ScheduleDAGSDNodes::getCustomGraphFeatures(), getFauxShuffleMask(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), llvm::SDNode::getGluedNode(), llvm::DenseMapInfo< SDValue >::getHashValue(), getMaskSetter(), llvm::SDUse::getNode(), llvm::SelectionDAG::getNode(), llvm::MipsTargetLowering::getOpndList(), getPointerConstIncrement(), getPowerOf2Factor(), llvm::PPCTargetLowering::getPreIndexedAddressParts(), llvm::simplify_type< const SDValue >::getSimplifiedValue(), llvm::simplify_type< SDValue >::getSimplifiedValue(), llvm::SelectionDAG::getStrictFPExtendOrRound(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorShuffle(), insert1BitVector(), insertDAGNode(), isBitfieldExtractOpFromAnd(), isBitfieldPositioningOpFromAnd(), isBLACompatibleAddress(), isBSwapHWordElement(), isCalleeLoad(), isConsecutiveLSLoc(), isEligibleToFoldADDIForFasterLocalAccesses(), isExtendedFrom16Bits(), isF128MovedFromParts(), isFNEG(), isFusableLoadOpStorePattern(), llvm::TargetLowering::isGAPlusOffset(), isI128MovedFromParts(), isMemOPCandidate(), llvm::AArch64TargetLowering::isReassocProfitable(), isSeveralBitsPositioningOpFromShl(), IsSVECntIntrinsic(), llvm::SelectionDAG::isUndef(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), isWorthFoldingIntoOrrWithShift(), llvm::SelectionDAG::Legalize(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), LowerAVXCONCAT_VECTORS(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallFromStatepointLoweringInfo(), llvm::TargetLowering::LowerCallTo(), LowerCONCAT_VECTORSvXi1(), lowerDSPIntr(), LowerF128Load(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), lowerLaneOp(), llvm::HexagonTargetLowering::LowerLoad(), lowerLoadF128(), lowerLoadI1(), LowerMLOAD(), lowerMSABinaryBitImmIntr(), LowerMUL(), llvm::TargetLowering::LowerOperationWrapper(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerRotate(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsPermuteAndUnpack(), LowerStore(), LowerVSETCC(), llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::VPMatchContext::match(), llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(), matchShuffleAsBlend(), moveBelowOrigChain(), narrowExtractedVectorSelect(), narrowIndex(), narrowVectorSelect(), parseTexFail(), llvm::SITargetLowering::passSpecialInputs(), PeepholePPC64ZExtGather(), PerformADDCombineWithOperands(), performAddDotCombine(), PerformADDVecReduce(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performConcatVectorsCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::MipsSETargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), performExtendCombine(), PerformExtractEltToVMOVRRD(), PerformFADDCombineWithOperands(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFPExtendCombine(), PerformHWLoopCombine(), performINSERT_VECTOR_ELTCombine(), PerformInsertEltCombine(), performIntToFpCombine(), PerformLongShiftCombine(), PerformMinMaxCombine(), performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), performMulVectorCmpZeroCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), PerformMVEVLDCombine(), performNEONPostLDSTCombine(), performORCombine(), PerformORCombine(), performPostLD1Combine(), performSETCCCombine(), performSignExtendSetCCCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToWideningLoad(), PerformSTORECombine(), PerformSUBCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformUMLALCombine(), performUnpackCombine(), PerformVECREDUCE_ADDCombine(), PerformVMOVDRRCombine(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), performVSelectCombine(), performXORCombine(), llvm::SITargetLowering::PostISelFolding(), prepareIndirectCall(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), removeRedundantInsertVectorElt(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), ReplaceINTRINSIC_W_CHAIN(), llvm::ARMTargetLowering::ReplaceNodeResults(), reservePreviousStackSlotForValue(), llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), llvm::SelectionDAG::salvageDebugInfo(), scalarizeExtractedBinop(), llvm::RISCVDAGToDAGISel::Select(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HvxSelector::selectRor(), llvm::HvxSelector::selectShuffle(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::AMDGPUTargetLowering::shouldFoldFNegIntoSrc(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), spillIncomingStatepointValue(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), llvm::SelectionDAG::transferDbgValues(), tryBitfieldInsertOpFromOr(), TryCombineBaseUpdate(), tryCombineMULLWithUZP1(), tryCombineToBSL(), llvm::HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(), tryLowerToSLI(), tryMemPairCombine(), tryOrrWithShift(), tryToFoldExtendOfConstant(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), tryToFoldExtOfMaskedLoad(), and useSinCos().
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Definition at line 1204 of file SelectionDAGNodes.h.
Referenced by combineBitcast(), combineShuffleOfConcatUndef(), ExtendToType(), fnegFoldsIntoOp(), foldShuffleOfConcatUndefs(), isCalleeLoad(), IsElementEquivalent(), isFusableLoadOpStorePattern(), isLoadOrMultipleLoads(), LowerVECTOR_SHUFFLE(), matchPMADDWD_2(), moveBelowOrigChain(), partitionShuffleOfConcats(), PerformADDVecReduce(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformExtractEltCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), PerformSplittingMVETruncToNarrowingStores(), PerformVECTOR_SHUFFLECombine(), and llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 1196 of file SelectionDAGNodes.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitUMAAL(), AddCombineVUZPToVPADDL(), adjustBitcastSrcVectorSSE1(), areLoadedOffsetButOtherwiseSame(), BuildExactSDIV(), BuildExactUDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), calculatePreExtendType(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canonicalizeBitSelect(), llvm::SelectionDAG::canonicalizeCommutativeBinop(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleWithOp(), checkBoolTestAndOrSetCCCombine(), checkBoolTestSetCCCombine(), collectConcatOps(), combine_CC(), combineAdd(), combineAddOfBooleanXor(), combineAddOfPMADDWD(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndMaskToShift(), combineAndnp(), combineAndOrForCcmpCtest(), combineAndShuffleNot(), combineArithReduction(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineBitcast(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBITREVERSE(), combineBoolVectorAndTruncateStore(), combineBVOfConsecutiveLoads(), combineBVOfVecSExt(), combineBVZEXTLOAD(), combineCarryDiamond(), combineCarryThroughADD(), combineCMov(), combineCMP(), combineCompareEqual(), combineConcatVectorOps(), combineDeMorganOfBoolean(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFaddCFmul(), combineFAndFNotToFAndn(), combineFneg(), combineFP_ROUND(), combineINSERT_SUBVECTOR(), combineMOVMSK(), combineMulToPMADDWD(), combineOr(), combineOrOfCZERO(), combineOrXorWithSETCC(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectAndUse(), combineSelectToBinOp(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToAVG(), combineShiftToMULH(), combineShiftToPMULH(), combineShuffleOfBitcast(), combineShuffleOfConcatUndef(), combineShuffleToFMAddSub(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubABS(), combineSubOfBoolean(), combineSubSetcc(), combineSubShiftToOrcB(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineToVWMACC(), combineTruncationShuffle(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineUADDO_CARRYDiamond(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVectorShiftImm(), combineVPDPBUSDPattern(), combineVWADDSUBWSelect(), combineX86CloadCstore(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86SubCmpForFlags(), combineXor(), combineXorSubCTLZ(), combineZext(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SelectionDAG::computeOverflowForUnsignedAdd(), constructDup(), convertIntLogicToFPLogic(), detectExtMul(), detectPMADDUBSW(), detectZextAbsDiff(), EmitAVX512Test(), EmitCmp(), EmitTest(), ExtendToType(), extractShiftForRotate(), extractSubVector(), findEltLoadSrc(), fnegFoldsIntoOp(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldBinOpIntoSelectIfProfitable(), foldBitOrderCrossLogicOp(), llvm::SelectionDAG::FoldConstantArithmetic(), foldCSELOfCSEL(), foldExtendedSignBitTest(), foldFPToIntToFP(), llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), FoldIntToFPToInt(), foldLogicOfShifts(), foldLogicTreeOfShifts(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldSelectOfCTTZOrCTLZ(), foldSelectWithIdentityConstant(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldShuffleOfConcatUndefs(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), getBaseWithOffsetUsingSplitOR(), llvm::getBitwiseNotOperand(), getBT(), getBuildPairElt(), getCmp(), getFauxShuffleMask(), getIndexFromUnindexedLoad(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getNode(), getOutputChainFromCallSeq(), getPowerOf2Factor(), getSToVPermuted(), getTargetVShiftNode(), getVPermMask(), isAbsolute(), isADDADDMUL(), isAddCarryChain(), isAddSubOrSubAdd(), isBitfieldPositioningOpFromAnd(), isBSwapHWordElement(), isCalleeLoad(), llvm::SITargetLowering::isCanonicalized(), IsCMPZCSINC(), isConsecutiveLSLoc(), IsCopyFromSGPR(), isDeinterleaveShuffle(), llvm::AArch64TargetLowering::isDesirableToCommuteWithShift(), llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(), IsElementEquivalent(), isExtendedFrom16Bits(), isFMAddSubOrFMSubAdd(), isFusableLoadOpStorePattern(), isHopBuildVector(), isHorizontalBinOpPart(), isI128MovedFromParts(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::SelectionDAG::isKnownToBeAPowerOfTwoFP(), isLoadOrMultipleLoads(), llvm::AArch64TargetLowering::isReassocProfitable(), isSaturatingMinMax(), isSubBorrowChain(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), lookThroughSignExtension(), lower1BitShuffle(), LowerAndToBT(), LowerAndToBTST(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORToVIDUP(), lowerBuildVectorAsBroadcast(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv4x32(), llvm::NVPTXTargetLowering::LowerCall(), LowerFABSorFNEG(), lowerFP_TO_SINT_STORE(), lowerFPToIntToFP(), LowerMLOAD(), LowerSaturatingConditional(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), LowerSMELdrStr(), lowerV4F64Shuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), LowerVSETCC(), llvm::SelectionDAG::matchBinOpReduction(), matchBSwapHWordOrAndAnd(), MatchingStackOffset(), matchLogicBlend(), matchPMADDWD(), matchPMADDWD_2(), matchRotateSub(), matchSplatAsGather(), matchUnaryShuffle(), mayUseP9Setb(), mergeEltWithShuffle(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowExtractedVectorSelect(), narrowIndex(), narrowInsertExtractVectorBinOp(), peekFNeg(), peekFPSignOps(), PerformADDCombineWithOperands(), performAddDotCombine(), performAddSubIntoVectorOp(), performAddUADDVCombine(), performANDCombine(), PerformANDCombine(), performANDORCSELCombine(), performANDSETCCCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), performBuildShuffleExtendCombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformExtendCombine(), PerformExtractEltCombine(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), PerformFADDCombineWithOperands(), PerformFAddVSelectCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performINSERT_VECTOR_ELTCombine(), performMADD_MSUBCombine(), PerformMinMaxFpToSatCombine(), PerformMinMaxToSatCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), performNegCSelCombine(), performORCombine(), PerformORCombine(), PerformORCombineToBFI(), performScalarToVectorCombine(), performSELECTCombine(), performSelectCombine(), performSETCCCombine(), performSetCCPunpkCombine(), performSHLCombine(), PerformShuffleVMOVNCombine(), PerformSplittingToWideningLoad(), performSRACombine(), performSRLCombine(), performSubAddMULCombine(), performSUBCombine(), performSVEAndCombine(), performSVEMulAddSubCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTruncateCombine(), performTRUNCATECombine(), performUADDVAddCombine(), performUADDVZextCombine(), PerformUMinFpToSatCombine(), performUzpCombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), performVecReduceAddCombineWithUADDLP(), PerformVECTOR_SHUFFLECombine(), performVectorExtendCombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), PerformVMULCombine(), PerformVQDMULHCombine(), performVSelectCombine(), performVSELECTCombine(), PerformVSetCCToVCTPCombine(), performXORCombine(), PromoteMaskArithmetic(), pushAddIntoCmovOfConsts(), reachesChainWithoutSideEffects(), ReconstructShuffleWithRuntimeMask(), ReconstructTruncateFromBuildVector(), reduceBuildVecToShuffleWithZero(), removeRedundantInsertVectorElt(), replaceShuffleOfInsert(), replaceSplatVectorStore(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), scalarizeExtEltFP(), scalarizeExtractedBinop(), llvm::RISCVDAGToDAGISel::Select(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), SelectSAddrFI(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex(), llvm::AArch64TargetLowering::shouldRemoveRedundantExtend(), llvm::RISCVTargetLowering::shouldScalarizeBinop(), llvm::X86TargetLowering::shouldScalarizeBinop(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::AMDGPUTargetLowering::stripBitcast(), tryCombineCRC32(), tryCombineExtendRShTrunc(), tryCombineFixedPointConvert(), tryCombineMULLWithUZP1(), tryCombineToBSL(), tryConvertSVEWideCompare(), tryDemorganOfBooleanCondition(), TryDistrubutionADDVecReduce(), tryLowerToSLI(), llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), trySwapVSelectOperands(), tryWhileWRFromOR(), vectorizeExtractedCast(), visitORCommutative(), widenAbs(), and widenCtPop().
Definition at line 1208 of file SelectionDAGNodes.h.
Referenced by AddCombineVUZPToVPADDL(), adjustBitcastSrcVectorSSE1(), areBitwiseNotOfEachother(), areLoadedOffsetButOtherwiseSame(), calculatePreExtendType(), canonicalizeBitSelect(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleWithOp(), checkBoolTestSetCCCombine(), collectConcatOps(), combine_CC(), combineAdd(), combineAddOfBooleanXor(), combineAddOfPMADDWD(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndMaskToShift(), combineAndnp(), combineAndOrForCcmpCtest(), combineAndShuffleNot(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineBitcast(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBITREVERSE(), combineBVOfConsecutiveLoads(), combineBVOfVecSExt(), combineCarryDiamond(), combineCarryThroughADD(), combineCMov(), combineCMP(), combineCompareEqual(), combineConcatVectorOps(), combineDeMorganOfBoolean(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFaddCFmul(), combineFAndFNotToFAndn(), combineFneg(), combineFP_ROUND(), combineGatherScatter(), combineINSERT_SUBVECTOR(), combineMOVMSK(), combineMulToPMADDWD(), combineOr(), combineOrOfCZERO(), combineOrXorWithSETCC(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectAndUse(), combineSelectToBinOp(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToAVG(), combineShiftToMULH(), combineShiftToPMULH(), combineShuffleOfBitcast(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineShuffleToFMAddSub(), combineSignExtendInReg(), combineStore(), combineSub(), combineSubABS(), combineSubOfBoolean(), combineSubSetcc(), combineSubShiftToOrcB(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineToVWMACC(), combineTruncationShuffle(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineUADDO_CARRYDiamond(), combineVectorCompareAndMaskUnaryOp(), combineVectorMulToSraBitcast(), combineVectorPack(), combineVectorShiftImm(), combineX86CloadCstore(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86SubCmpForFlags(), combineXor(), combineXorSubCTLZ(), combineZext(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), constructDup(), convertIntLogicToFPLogic(), createPSADBW(), detectPMADDUBSW(), detectZextAbsDiff(), distributeOpThroughSelect(), EmitAVX512Test(), EmitCmp(), ExtendToType(), extractShiftForRotate(), extractSubVector(), findEltLoadSrc(), findMoreOptimalIndexType(), fnegFoldsIntoOp(), foldADDIForFasterLocalAccesses(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldBinOpIntoSelectIfProfitable(), foldBitOrderCrossLogicOp(), foldCSELOfCSEL(), foldExtendedSignBitTest(), foldFPToIntToFP(), foldIndexIntoBase(), FoldIntToFPToInt(), foldLogicOfShifts(), foldLogicTreeOfShifts(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldOverflowCheck(), foldSelectOfCTTZOrCTLZ(), foldSelectWithIdentityConstant(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldShuffleOfConcatUndefs(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), getBaseWithConstantOffset(), getBaseWithOffsetUsingSplitOR(), llvm::getBitwiseNotOperand(), getBT(), getBuildPairElt(), getFauxShuffleMask(), getIndexFromUnindexedLoad(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getNode(), getPowerOf2Factor(), getReductionSDNode(), getSToVPermuted(), getTargetVShiftNode(), getVPermMask(), isAbsolute(), isADDADDMUL(), isAddCarryChain(), isAddSubOrSubAdd(), isBitfieldExtractOpFromAnd(), isBitfieldPositioningOpFromAnd(), isBSwapHWordElement(), isCalleeLoad(), llvm::SITargetLowering::isCanonicalized(), IsCMPZCSINC(), IsCopyFromSGPR(), isDeinterleaveShuffle(), llvm::AArch64TargetLowering::isDesirableToCommuteWithShift(), IsElementEquivalent(), isEligibleToFoldADDIForFasterLocalAccesses(), isExtendedFrom16Bits(), isFMAddSubOrFMSubAdd(), isFusableLoadOpStorePattern(), isHopBuildVector(), isHorizontalBinOpPart(), isI128MovedFromParts(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::SelectionDAG::isKnownToBeAPowerOfTwoFP(), isLoadOrMultipleLoads(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::ARMTargetLowering::isMulAddWithConstProfitable(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), isSaturatingMinMax(), isSeveralBitsPositioningOpFromShl(), isSubBorrowChain(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), llvm::X86TargetLowering::isVectorLoadExtDesirable(), isWorthFoldingIntoOrrWithShift(), LookThroughSetCC(), lookThroughSignExtension(), lower1BitShuffle(), LowerAndToBT(), LowerAndToBTST(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORToVIDUP(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv4x32(), llvm::NVPTXTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), LowerFABSorFNEG(), lowerFP_TO_SINT_STORE(), lowerFPToIntToFP(), LowerSaturatingConditional(), LowerShift(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), LowerSMELdrStr(), LowerTruncateToBTST(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVSETCC(), llvm::VPMatchContext::match(), llvm::SelectionDAG::matchBinOpReduction(), matchBSwapHWordOrAndAnd(), MatchingStackOffset(), matchLogicBlend(), matchPMADDWD_2(), matchRotateSub(), matchSetCC(), matchSplatAsGather(), mayUseP9Setb(), mergeEltWithShuffle(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowExtractedVectorSelect(), narrowIndex(), narrowInsertExtractVectorBinOp(), partitionShuffleOfConcats(), peekFNeg(), peekFPSignOps(), PeepholePPC64ZExtGather(), PerformADDCombineWithOperands(), performAddDotCombine(), performAddSubIntoVectorOp(), performAddUADDVCombine(), PerformADDVecReduce(), performANDCombine(), PerformANDCombine(), performANDORCSELCombine(), performANDSETCCCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), performBuildShuffleExtendCombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformExtendCombine(), PerformExtractEltCombine(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), PerformFADDCombineWithOperands(), PerformFAddVSelectCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performINSERT_VECTOR_ELTCombine(), PerformMinMaxFpToSatCombine(), PerformMinMaxToSatCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), performMulVectorCmpZeroCombine(), performNegCSelCombine(), performORCombine(), PerformORCombineToBFI(), performScalarToVectorCombine(), performSELECTCombine(), performSelectCombine(), performSETCCCombine(), performSetCCPunpkCombine(), performSHLCombine(), PerformShuffleVMOVNCombine(), performSignExtendSetCCCombine(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), performSRACombine(), performSRLCombine(), PerformSTORECombine(), performSUBCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTruncateCombine(), performTRUNCATECombine(), performUADDVAddCombine(), performUADDVZextCombine(), PerformUMinFpToSatCombine(), performUzpCombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), PerformVECTOR_SHUFFLECombine(), performVectorExtendCombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), PerformVQDMULHCombine(), performVSelectCombine(), performVSELECTCombine(), PerformVSetCCToVCTPCombine(), performXORCombine(), PromoteMaskArithmetic(), pushAddIntoCmovOfConsts(), ReconstructShuffleWithRuntimeMask(), ReconstructTruncateFromBuildVector(), reduceBuildVecToShuffleWithZero(), reduceVSXSwap(), refineUniformBase(), removeRedundantInsertVectorElt(), replaceShuffleOfInsert(), replaceSplatVectorStore(), replaceZeroVectorStore(), scalarizeExtEltFP(), scalarizeExtractedBinop(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), SelectSAddrFI(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), selectUmullSmull(), llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex(), llvm::AArch64TargetLowering::shouldRemoveRedundantExtend(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::AMDGPUTargetLowering::stripBitcast(), tryCombineCRC32(), tryCombineExtendRShTrunc(), tryCombineFixedPointConvert(), tryCombineMULLWithUZP1(), tryCombineToBSL(), tryConvertSVEWideCompare(), tryDemorganOfBooleanCondition(), TryDistrubutionADDVecReduce(), tryLowerToSLI(), tryOrrWithShift(), llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), trySwapVSelectOperands(), tryToFoldExtendOfConstant(), tryWhileWRFromOR(), vectorizeExtractedCast(), visitORCommutative(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), widenAbs(), and widenCtPop().
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get the index which selects a specific result in the SDNode
Definition at line 156 of file SelectionDAGNodes.h.
Referenced by carryFlagToValue(), combineAddOrSubToADCOrSBB(), combineCarryThroughADD(), combineExtractVectorElt(), combineUADDO_CARRYDiamond(), CombineVLDDUP(), llvm::SelectionDAG::computeOverflowForUnsignedAdd(), ExtendUsesToFormExtLoad(), getBuildPairElt(), getCmp(), llvm::RegsForValue::getCopyToRegs(), llvm::DenseMapInfo< SDValue >::getHashValue(), llvm::SDUse::getResNo(), isFusableLoadOpStorePattern(), overflowFlagToValue(), PerformADDVecReduce(), PerformExtractEltToVMOVRRD(), PerformVMOVDRRCombine(), llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::SelectionDAG::salvageDebugInfo(), and llvm::SelectionDAG::transferDbgValues().
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Definition at line 203 of file SelectionDAGNodes.h.
References llvm::EVT::getFixedSizeInBits(), llvm::EVT::getScalarType(), and getValueType().
Referenced by calculateByteProvider(), combineConcatVectorOps(), combineExtractWithShuffle(), combineMulToPMADDWD(), combineTargetShuffle(), combineTruncationShuffle(), combineVectorPack(), combineVectorShiftImm(), combineVectorSizedSetCCEquality(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineZext(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SelectionDAG::computeOverflowForSignedMul(), constructDup(), findEltLoadSrc(), foldSetCCWithFunnelShift(), foldVectorXorShiftIntoCmp(), llvm::getBitwiseNotOperand(), getFauxShuffleMask(), llvm::SelectionDAG::getNode(), isFNEG(), isSaturatingMinMax(), LowerEXTRACT_VECTOR_ELT(), lowerShuffleAsBroadcast(), matchBinaryShuffle(), matchRotateSub(), matchShuffleWithPACK(), matchUnaryShuffle(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), truncateVecElts(), and widenSubVector().
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Return the simple ValueType of the referenced return value.
Definition at line 190 of file SelectionDAGNodes.h.
References llvm::EVT::getSimpleVT(), and getValueType().
Referenced by canonicalizeShuffleMaskWithHorizOp(), combineAdd(), combineAddOfPMADDWD(), combineBinOpToReduce(), combineBitcast(), combineBitOpWithPACK(), combineConcatVectorOps(), combineINSERT_SUBVECTOR(), combinePTESTCC(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineTruncToVnclip(), combineVectorPack(), combineVEXTRACT_STORE(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), constructDup(), convertShiftLeftToScale(), EmitAVX512Test(), ExpandHorizontalBinOp(), ExtendToType(), ExtractBitFromMaskVector(), foldMaskedShiftToScaledMask(), getCopyFromPartsVector(), getReductionSDNode(), getScalarValueForVectorElement(), getShuffleHalfVectors(), getTargetVShiftNode(), getUnderlyingExtractedFromVec(), getWideningInterleave(), insert1BitVector(), InsertBitToMaskVector(), isAddSubOrSubAdd(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORSvXi1(), lowerCttzElts(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerFCOPYSIGN(), LowerFGETSIGN(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), lowerFPToIntToFP(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerINTRINSIC_W_CHAIN(), LowerMSTORE(), lowerReductionSeq(), lowerScalarInsert(), lowerShuffleAsInsertPS(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPERMV(), LowerStore(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vec(), LowerUnalignedLoadRetParam(), lowerV16F32Shuffle(), lowerV16I16Shuffle(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2I64Shuffle(), lowerV32I16Shuffle(), lowerV32I8Shuffle(), lowerV4F32Shuffle(), lowerV4F64Shuffle(), lowerV4I32Shuffle(), lowerV4I64Shuffle(), lowerV64I8Shuffle(), lowerV8F16Shuffle(), lowerV8F32Shuffle(), lowerV8F64Shuffle(), lowerV8I16Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), lowerVectorIntrinsicScalars(), LowerVSETCC(), matchShuffleAsInsertPS(), narrowExtractedVectorSelect(), llvm::PPCTargetLowering::PerformDAGCombine(), performUzpCombine(), promoteVCIXScalar(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), splitAndLowerShuffle(), vectorizeExtractedCast(), widenMaskVector(), and widenSubVector().
Definition at line 179 of file SelectionDAGNodes.h.
References SDValue().
Referenced by AddCombineTo64bitMLAL(), llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), AVRDAGToDAGISel::select< AVRISD::CALL >(), AVRDAGToDAGISel::select< ISD::LOAD >(), combineAddOrSubToADCOrSBB(), combineBitcast(), combineCarryDiamond(), combineCVTP2I_CVTTP2I(), combineCVTPH2PS(), combineFP_EXTEND(), combineFP_ROUND(), combineINSERT_SUBVECTOR(), combineLoad(), combineMaskedLoadConstantMask(), combineMOVDQ2Q(), combineSetCCAtomicArith(), combineSIntToFP(), combineTargetShuffle(), combineUADDO_CARRYDiamond(), combineVectorCompareAndMaskUnaryOp(), combineVectorSizedSetCCEquality(), combineX86INT_TO_FP(), ConvertBooleanCarryToCarryFlag(), EmitCmp(), emitComparison(), emitRepmovs(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemcmp(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), EmitTest(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFP_TO_UINT(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandREM(), llvm::TargetLowering::expandUnalignedLoad(), llvm::SelectionDAG::expandVAArg(), llvm::SelectionDAG::expandVACopy(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), GeneratePerfectShuffle(), getAArch64XALUOOp(), getAVX2GatherNode(), getBROADCAST_LOAD(), llvm::RegsForValue::getCopyToRegs(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getFPBinOp(), getFPTernOp(), getGatherNode(), getMemCmpLoad(), llvm::MipsTargetLowering::getOpndList(), getOutputChainFromCallSeq(), getReadTimeStampCounter(), GetTLSADDR(), getv64i1Argument(), getVCIXISDNodeWCHAIN(), llvm::TargetLowering::LegalizeSetCCCondCode(), llvm::SITargetLowering::legalizeTargetIndependentNode(), LowerABD(), LowerADDSUBO_CARRY(), lowerADDSUBO_CARRY(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), LowerATOMIC_STORE(), lowerAtomicArith(), lowerBuildVectorAsBroadcast(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::SITargetLowering::LowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), LowerCallResult(), LowerCMP_SWAP(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), LowerFP16_TO_FP(), LowerFP_TO_FP16(), llvm::SITargetLowering::lowerGET_FPENV(), llvm::SITargetLowering::lowerGET_ROUNDING(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerI64IntToFP16(), LowerI64IntToFP_AVX512DQ(), lowerINT_TO_FP_vXi64(), LowerINTRINSIC_W_CHAIN(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), llvm::RISCVTargetLowering::LowerOperation(), llvm::TargetLowering::LowerOperationWrapper(), llvm::SystemZTargetLowering::LowerOperationWrapper(), lowerOverflowArithmetic(), LowerPARITY(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerSETCCCARRY(), llvm::SITargetLowering::LowerSTACKSAVE(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerUAddSubOCarry(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerUnalignedLoadRetParam(), LowerUnalignedStoreParam(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), LowerVECTOR_SHUFFLE(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), LowerVSETCC(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(), llvm::ARMTargetLowering::PerformCMOVCombine(), performConcatVectorsCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDivRemCombine(), performExtractVectorEltCombine(), performFPExtendCombine(), performGatherLoadCombine(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformLOADCombine(), performScatterStoreCombine(), PerformSETCCCombine(), performSignExtendInRegCombine(), PerformSTORECombine(), performUnpackCombine(), PerformVDUPCombine(), PerformVECREDUCE_ADDCombine(), PerformVMOVhrCombine(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), llvm::SITargetLowering::PostISelFolding(), prepareDescriptorIndirectCall(), prepareIndirectCall(), PrepareTailCall(), ReplaceCopyFromReg_128(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), ReplaceLongIntrinsic(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), replaceVecCondBranchResults(), replaceVPICKVE2GRResults(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::RISCVDAGToDAGISel::Select(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), SkipExtensionForVMULL(), splitStores(), splitStoreSplat(), SplitStrictFPVectorOp(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), tryMemPairCombine(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), llvm::SelectionDAG::UnrollVectorOp(), llvm::SelectionDAG::UnrollVectorOverflowOp(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), and widenVectorOpsToi8().
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Returns the size of the value in bits.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 199 of file SelectionDAGNodes.h.
References llvm::EVT::getSizeInBits(), and getValueType().
Referenced by calculateByteProvider(), CalculateTailCallArgDest(), checkDot4MulSignedness(), combineArithReduction(), combineBT(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractFromVectorLoad(), combineExtractWithShuffle(), combineINSERT_SUBVECTOR(), combineMulToPMADDWD(), combineSetCCMOVMSK(), combineShiftLeft(), combineStore(), combineTargetShuffle(), combineVectorCompareAndMaskUnaryOp(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesRecursively(), combineXorSubCTLZ(), combineZext(), llvm::SelectionDAG::computeKnownBits(), computeZeroableShuffleElements(), constructDup(), createVariablePermute(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandMULO(), fnegFoldsIntoOp(), foldSelectOfCTTZOrCTLZ(), getBT(), getFauxShuffleMask(), getHopForBuildVector(), llvm::SelectionDAG::getNode(), isHorizontalBinOp(), isTruncWithZeroHighBitsInput(), lookThroughSignExtension(), LowerAndToBT(), LowerAndToBTST(), lowerBuildVectorAsBroadcast(), lowerFP_TO_SINT_STORE(), llvm::NVPTXTargetLowering::LowerReturn(), matchBinaryShuffle(), MatchingStackOffset(), matchPERM(), matchPMADDWD_2(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMulCombine(), performSUBCombine(), reduceBuildVecToShuffleWithZero(), llvm::SelectionDAG::salvageDebugInfo(), llvm::SelectionDAGISel::SelectCodeCommon(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), tryCombineFixedPointConvert(), tryFormConcatFromShuffle(), and widenSubVector().
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Return the ValueType of the referenced return value.
Definition at line 1200 of file SelectionDAGNodes.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), adjustBitcastSrcVectorSSE1(), llvm::VECustomDAG::annotateLegalAVL(), areLoadedOffsetButOtherwiseSame(), buildFromShuffleMostly(), BuildIntrinsicOp(), calculatePreExtendType(), calculateSrcByte(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canEmitConjunction(), canLowerSRLToRoundingShiftForVT(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleWithOp(), checkZExtBool(), collectConcatOps(), combineAdd(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndMaskToShift(), combineAndnp(), combineAndShuffleNot(), combineArithReduction(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineBitcast(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBitOpWithShift(), combineBoolVectorAndTruncateStore(), combineBVOfVecSExt(), combineCarryDiamond(), combineCarryThroughADD(), combineCMov(), combineCMP(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFneg(), combineFP_EXTEND(), combineFP_ROUND(), combineHorizOpWithShuffle(), combineMaskedStore(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToMULH(), combineShuffleOfBitcast(), combineShuffleOfScalars(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubOfBoolean(), combineSVEReductionFP(), combineSVEReductionOrderedFP(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineTruncate(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineUIntToFP(), combineVectorPack(), combineVectorShiftImm(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineXor(), combineZext(), CompactSwizzlableVector(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), concatSubVectors(), constructDup(), ConvertBooleanCarryToCarryFlag(), convertFixedMaskToScalableVector(), convertIntLogicToFPLogic(), createCMovFP(), createPSADBW(), createVariablePermute(), detectPMADDUBSW(), detectZextAbsDiff(), distributeOpThroughSelect(), EltsFromConsecutiveLoads(), EmitCmp(), llvm::AArch64SelectionDAGInfo::EmitMOPS(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandMULO(), ExpandPowI(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandUnalignedStore(), llvm::SelectionDAG::expandVAArg(), llvm::TargetLowering::expandVecReduceSeq(), llvm::TargetLowering::expandVECTOR_COMPRESS(), ExtendToType(), ExtendUsesToFormExtLoad(), extract128BitVector(), extract256BitVector(), ExtractBitFromMaskVector(), extractShiftForRotate(), extractSubVector(), FixupMMXIntrinsicTypes(), fnegFoldsIntoOp(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldAndOrOfSETCC(), llvm::SelectionDAG::FoldConstantArithmetic(), foldExtendedSignBitTest(), foldExtractSubvectorFromShuffleVector(), foldFPToIntToFP(), FoldIntToFPToInt(), foldSelectOfCTTZOrCTLZ(), llvm::SelectionDAG::FoldSetCC(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldTruncStoreOfExt(), foldVectorXorShiftIntoCmp(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandWideMUL(), GeneratePerfectShuffle(), llvm::SelectionDAG::getAssertAlign(), llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getAtomicCmpSwap(), llvm::SelectionDAG::getBitcastedAnyExtOrTrunc(), llvm::SelectionDAG::getBitcastedSExtOrTrunc(), llvm::SelectionDAG::getBitcastedZExtOrTrunc(), getBitTestCondition(), llvm::getBitwiseNotOperand(), getBT(), getBuildDwordsVector(), getConstantLaneNumOfExtractHalfOperand(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getEstimate(), getFauxShuffleMask(), llvm::SelectionDAG::getGetFPEnv(), llvm::SelectionDAG::getIndexedLoad(), llvm::SelectionDAG::getIndexedLoadVP(), llvm::SelectionDAG::getIndexedMaskedLoad(), getKnownUndefForVectorBinop(), llvm::VECustomDAG::getLegalReductionOpVVP(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getLoadVP(), llvm::SelectionDAG::getMaskedStore(), llvm::SelectionDAG::getNode(), getOutputChainFromCallSeq(), llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), getPTest(), llvm::AMDGPUTargetLowering::getRecipEstimate(), getReductionSDNode(), getScalarValueSizeInBits(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getSetFPEnv(), getShuffleHalfVectors(), getShuffleScalarElt(), getSimpleValueType(), llvm::NVPTXTargetLowering::getSqrtEstimate(), llvm::AMDGPUTargetLowering::getSqrtEstimate(), llvm::TargetLowering::getSqrtResultForDenormInput(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getStoreVP(), getSToVPermuted(), llvm::SelectionDAG::getStridedStoreVP(), getTargetShuffleAndZeroables(), getTargetVShiftNode(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), getValueSizeInBits(), llvm::SDUse::getValueType(), getVectorBitwiseReduce(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLowering::getVectorSubVecPointer(), getVPermMask(), insert128BitVector(), insertSubVector(), InvertCarryFlag(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOpFromAnd(), llvm::SITargetLowering::isCanonicalized(), llvm::X86TargetLowering::isDesirableToCombineLogicOpOfSETCC(), llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(), isExtendedFrom16Bits(), isHorizontalBinOpPart(), isI128MovedFromParts(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::ARMTargetLowering::isMulAddWithConstProfitable(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), isSaturatingMinMax(), isTargetShuffleEquivalent(), llvm::TargetLoweringBase::isTruncateFree(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), llvm::X86TargetLowering::isVectorLoadExtDesirable(), llvm::TargetLoweringBase::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), llvm::SITargetLowering::legalizeTargetIndependentNode(), lower1BitShuffle(), lower1BitShuffleAsKSHIFTR(), LowerADDSUBO_CARRY(), lowerBuildVectorAsBroadcast(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), LowerCONCAT_VECTORS_i1(), LowerConvertLow(), lowerDSPIntr(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), LowerF128Load(), LowerF128Store(), LowerF64Op(), lowerFCMPIntrinsic(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), LowerFSINCOS(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), LowerLabelRef(), lowerLaneOp(), lowerLoadF128(), lowerMasksToReg(), LowerMUL(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::NVPTXTargetLowering::LowerReturn(), lowerScalarInsert(), llvm::SITargetLowering::lowerSET_ROUNDING(), lowerShuffleAsElementInsertion(), lowerShuffleToEXPAND(), lowerShuffleWithPACK(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), lowerStatepointMetaArgs(), LowerStore(), lowerStoreF128(), LowerSVEIntrinsicIndex(), LowerUINT_TO_FP_i32(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), LowerVecReduce(), LowerVecReduceMinMax(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), lowerVectorIntrinsicScalars(), LowerVSETCC(), LowerWRITE_REGISTER(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::TargetLowering::makeLibCall(), llvm::SelectionDAG::makeStateFunctionCall(), llvm::ISD::matchBinaryPredicate(), matchBinaryShuffle(), MatchingStackOffset(), matchPERM(), matchPMADDWD_2(), matchSetCC(), matchSplatAsGather(), MatchVectorAllEqualTest(), matchZExtFromI32(), mergeEltWithShuffle(), narrowExtractedVectorBinOp(), narrowIndex(), narrowInsertExtractVectorBinOp(), NarrowVector(), partitionShuffleOfConcats(), Passv64i1ArgInRegs(), PerformADDCombine(), PerformADDCombineWithOperands(), performAddSubIntoVectorOp(), performAddUADDVCombine(), PerformANDCombine(), performANDSETCCCombine(), PerformARMBUILD_VECTORCombine(), performBuildShuffleExtendCombine(), performBuildVectorCombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performDupLane128Combine(), performExtBinopLoadFold(), PerformExtendCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), PerformExtractFpToIntStores(), PerformFADDCombine(), PerformFADDCombineWithOperands(), performFirstTrueTestVectorCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFPExtendCombine(), performINSERT_VECTOR_ELTCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), performLastTrueTestVectorCombine(), PerformMinMaxFpToSatCombine(), PerformMULCombineWithOperands(), performNegCSelCombine(), performReinterpretCastCombine(), performScalarToVectorCombine(), performSELECTCombine(), performSelectCombine(), performSetccAddFolding(), performSETCCCombine(), PerformShuffleVMOVNCombine(), performSignExtendInRegCombine(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSTORECombine(), performSVEMulAddSubCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTruncateCombine(), performTRUNCATECombine(), PerformTruncatingStoreCombine(), performUADDVAddCombine(), performUADDVZextCombine(), PerformUMinFpToSatCombine(), performUzpCombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), performVecReduceBitwiseCombine(), PerformVECTOR_SHUFFLECombine(), performVECTOR_SHUFFLECombine(), performVectorExtCombine(), performVectorExtendCombine(), PerformVMOVRRDCombine(), PerformVQDMULHCombine(), performVSelectCombine(), PerformVSELECTCombine(), performXORCombine(), llvm::SITargetLowering::PostISelFolding(), prepareTS1AM(), PromoteMaskArithmetic(), ReconstructShuffleWithRuntimeMask(), ReconstructTruncateFromBuildVector(), reduceBuildVecToShuffleWithZero(), refineUniformBase(), removeRedundantInsertVectorElt(), ReorganizeVector(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), replaceSplatVectorStore(), replaceVPICKVE2GRResults(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), scalarizeExtEltFP(), scalarizeVectorStore(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::SelectAddrRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::HvxSelector::selectShuffle(), selectUmullSmull(), llvm::SITargetLowering::shouldExpandVectorDynExt(), llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex(), llvm::AArch64TargetLowering::shouldRemoveRedundantExtend(), llvm::RISCVTargetLowering::shouldScalarizeBinop(), llvm::X86TargetLowering::shouldScalarizeBinop(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), llvm::TargetLowering::softenSetCCOperands(), splatPartsI64WithVL(), llvm::SITargetLowering::splitBinaryVectorOp(), splitStores(), splitStoreSplat(), llvm::SITargetLowering::splitTernaryVectorOp(), llvm::PPCTargetLowering::splitValueIntoRegisterParts(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::SystemZTargetLowering::splitValueIntoRegisterParts(), llvm::AMDGPUTargetLowering::SplitVectorStore(), splitVectorStore(), stripModuloOnShift(), tryBitfieldInsertOpFromOr(), tryCombineFixedPointConvert(), tryCombineMULLWithUZP1(), tryDemorganOfBooleanCondition(), tryFoldSelectIntoOp(), tryFormConcatFromShuffle(), tryGetOriginalBoolVectorType(), llvm::RISCVDAGToDAGISel::tryIndexedLoad(), trySwapVSelectOperands(), tryToFoldExtendOfConstant(), tryToFoldExtOfLoad(), tryWhileWRFromOR(), llvm::SelectionDAG::UnrollVectorOp(), vectorToScalarBitmask(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::X86TargetLowering::visitMaskedLoad(), llvm::X86TargetLowering::visitMaskedStore(), visitORCommutative(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), llvm::VPMatchContext::VPMatchContext(), widenAbs(), widenCtPop(), widenSubVector(), widenVec(), WidenVector(), and widenVectorToPartType().
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Return true if there is exactly one node using value ResNo of Node.
Definition at line 1244 of file SelectionDAGNodes.h.
Referenced by areLoadedOffsetButOtherwiseSame(), canEmitConjunction(), canonicalizeBitSelect(), CheckForMaskedLoad(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndMaskToShift(), combineAndShuffleNot(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineBitcast(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBITREVERSE(), combineBlendOfPermutes(), combineCMP(), combineDeMorganOfBoolean(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineINSERT_SUBVECTOR(), combineOr(), combineOrOfCZERO(), combineOrXorWithSETCC(), combineSelectAndUse(), combineSetCCAtomicArith(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToMULH(), combineShiftToPMULH(), combineShuffleToFMAddSub(), combineSIntToFP(), combineStore(), combineSubABS(), combineSubOfBoolean(), combineSubSetcc(), combineSubShiftToOrcB(), combineTargetShuffle(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineVWADDSUBWSelect(), combineX86ShuffleChain(), combineXor(), combineXorSubCTLZ(), combineZext(), convertIntLogicToFPLogic(), EmitAVX512Test(), EmitCmp(), foldBinOpIntoSelectIfProfitable(), foldBitOrderCrossLogicOp(), foldExtendedSignBitTest(), llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), foldLogicOfShifts(), foldLogicTreeOfShifts(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldSelectWithIdentityConstant(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), isADDADDMUL(), isBitfieldPositioningOpFromAnd(), isCalleeLoad(), isLoadOrMultipleLoads(), llvm::TargetLowering::isReassocProfitable(), llvm::AArch64TargetLowering::isReassocProfitable(), llvm::SITargetLowering::isReassocProfitable(), isWorthFoldingIntoOrrWithShift(), LowerAVXCONCAT_VECTORS(), lowerShuffleOfExtractsAsVperm(), LowerStore(), lowerV2X128Shuffle(), LowerVSETCC(), mayUseP9Setb(), narrowExtractedVectorBinOp(), narrowVectorSelect(), performANDCombine(), PerformBFICombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFPExtendCombine(), performINSERT_VECTOR_ELTCombine(), performIntToFpCombine(), PerformORCombine(), performSETCCCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToWideningLoad(), performSRACombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), performSUBCombine(), performSVEMulAddSubCombine(), performTruncateCombine(), performTRUNCATECombine(), PerformVMOVrhCombine(), performXORCombine(), pushAddIntoCmovOfConsts(), reachesChainWithoutSideEffects(), reduceBuildVecToShuffleWithZero(), replaceZeroVectorStore(), scalarizeExtEltFP(), scalarizeExtractedBinop(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::AMDGPUTargetLowering::shouldFoldFNegIntoSrc(), llvm::AArch64TargetLowering::shouldRemoveRedundantExtend(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), tryBitfieldInsertOpFromOr(), tryDemorganOfBooleanCondition(), tryOrrWithShift(), llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), trySwapVSelectOperands(), tryToFoldExtendSelectLoad(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), tryToFoldExtOfMaskedLoad(), usePartialVectorLoads(), widenAbs(), and widenCtPop().
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Definition at line 1228 of file SelectionDAGNodes.h.
Referenced by isEligibleToFoldADDIForFasterLocalAccesses(), isF128MovedFromParts(), PeepholePPC64ZExtGather(), and llvm::SITargetLowering::PostISelFolding().
Return true if this node is an operand of N.
isOperand - Return true if this node is an operand of N.
Definition at line 12247 of file SelectionDAG.cpp.
References llvm::is_contained(), and N.
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Definition at line 1224 of file SelectionDAGNodes.h.
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Definition at line 1220 of file SelectionDAGNodes.h.
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Definition at line 1236 of file SelectionDAGNodes.h.
Referenced by buildMergeScalars(), canonicalizeLaneShuffleWithRepeatedOps(), combineAndnp(), combineAndShuffleNot(), combineConcatVectorOfExtracts(), combineConcatVectorOfShuffleAndItsOperands(), combineINSERT_SUBVECTOR(), combineSetCCMOVMSK(), combineShuffleOfBitcast(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineShuffleOfSplatVal(), combineTargetShuffle(), combineToVWMACC(), combineVectorHADDSUB(), combineVectorInsert(), combineVectorPack(), combineVectorShiftImm(), combineVWADDSUBWSelect(), combineXor(), combineZext(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandVECTOR_COMPRESS(), ExtendToType(), extractSubVector(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::foldConstantFPMath(), llvm::SelectionDAG::FoldSetCC(), foldShuffleOfConcatUndefs(), formSplatFromShuffles(), GenerateTBL(), getFauxShuffleMask(), getHopForBuildVector(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getNode(), llvm::BuildVectorSDNode::getRepeatedSequence(), getScalarMaskingNode(), getTargetShuffleAndZeroables(), getVectorMaskingNode(), llvm::SelectionDAG::getVectorShuffle(), getVectorShuffle(), getVSlidedown(), getVSlideup(), getWideningInterleave(), InferPointerInfo(), insert1BitVector(), insertSubVector(), isAddSubOrSubAdd(), llvm::BuildVectorSDNode::isConstantSplat(), isFNEG(), isHopBuildVector(), isHorizontalBinOpPart(), isSplatBV(), llvm::SelectionDAG::isUndef(), joinDwords(), LowerAVXCONCAT_VECTORS(), lowerBitreverseShuffle(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerF128Load(), LowerF128Store(), lowerLoadF128(), lowerLoadI1(), LowerMGATHER(), LowerMLOAD(), llvm::RISCVTargetLowering::LowerOperation(), lowerScalarSplat(), llvm::VETargetLowering::lowerSTORE(), lowerStoreF128(), lowerStoreI1(), LowerToHorizontalOp(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVectorIntrinsicScalars(), llvm::ISD::matchBinaryPredicate(), matchShuffleAsBlend(), matchShuffleWithPACK(), partitionShuffleOfConcats(), PerformARMBUILD_VECTORCombine(), performBuildShuffleExtendCombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), PerformSplittingToNarrowingStores(), PerformVECTOR_SHUFFLECombine(), PerformVSetCCToVCTPCombine(), llvm::HvxSelector::selectShuffle(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), simplifyShuffleOfShuffle(), and llvm::X86TargetLowering::visitMaskedLoad().
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Definition at line 175 of file SelectionDAGNodes.h.
Definition at line 169 of file SelectionDAGNodes.h.
References operator==().
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Definition at line 164 of file SelectionDAGNodes.h.
Definition at line 172 of file SelectionDAGNodes.h.
Definition at line 166 of file SelectionDAGNodes.h.
Referenced by operator!=().
Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions.
reachesChainWithoutSideEffects - Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions on any chain path.
In practice, this looks through token factors and non-volatile loads. In order to remain efficient, this only looks a couple of nodes in, it does not do an exhaustive search.
In practice, this looks through token factors and non-volatile loads. In order to remain efficient, this only looks a couple of nodes in, it does not do an exhaustive search.
Note that we only need to examine chains when we're searching for side-effects; SelectionDAG requires that all side-effects are represented by chains, even if another operand would force a specific ordering. This constraint is necessary to allow transformations like splitting loads.
Definition at line 12266 of file SelectionDAG.cpp.
References llvm::all_of(), llvm::Depth, getOpcode(), hasOneUse(), llvm::is_contained(), and llvm::ISD::TokenFactor.
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set the SDNode
Definition at line 162 of file SelectionDAGNodes.h.
References N.
Referenced by tryCombineMULLWithUZP1().
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Return true if there are no nodes using value ResNo of Node.
Definition at line 1240 of file SelectionDAGNodes.h.
Referenced by llvm::TargetLowering::getNegatedExpression(), and llvm::SelectionDAG::makeEquivalentMemoryOrdering().
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Definition at line 130 of file SelectionDAGNodes.h.