LLVM
15.0.0git
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Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation. More...
#include "llvm/CodeGen/SelectionDAGNodes.h"
Public Member Functions | |
SDValue ()=default | |
SDValue (SDNode *node, unsigned resno) | |
unsigned | getResNo () const |
get the index which selects a specific result in the SDNode More... | |
SDNode * | getNode () const |
get the SDNode which holds the desired result More... | |
void | setNode (SDNode *N) |
set the SDNode More... | |
SDNode * | operator-> () const |
bool | operator== (const SDValue &O) const |
bool | operator!= (const SDValue &O) const |
bool | operator< (const SDValue &O) const |
operator bool () const | |
SDValue | getValue (unsigned R) const |
bool | isOperandOf (const SDNode *N) const |
Return true if this node is an operand of N. More... | |
EVT | getValueType () const |
Return the ValueType of the referenced return value. More... | |
MVT | getSimpleValueType () const |
Return the simple ValueType of the referenced return value. More... | |
TypeSize | getValueSizeInBits () const |
Returns the size of the value in bits. More... | |
uint64_t | getScalarValueSizeInBits () const |
unsigned | getOpcode () const |
unsigned | getNumOperands () const |
const SDValue & | getOperand (unsigned i) const |
uint64_t | getConstantOperandVal (unsigned i) const |
const APInt & | getConstantOperandAPInt (unsigned i) const |
bool | isTargetMemoryOpcode () const |
bool | isTargetOpcode () const |
bool | isMachineOpcode () const |
bool | isUndef () const |
unsigned | getMachineOpcode () const |
const DebugLoc & | getDebugLoc () const |
void | dump () const |
void | dump (const SelectionDAG *G) const |
void | dumpr () const |
void | dumpr (const SelectionDAG *G) const |
bool | reachesChainWithoutSideEffects (SDValue Dest, unsigned Depth=2) const |
Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions. More... | |
bool | use_empty () const |
Return true if there are no nodes using value ResNo of Node. More... | |
bool | hasOneUse () const |
Return true if there is exactly one node using value ResNo of Node. More... | |
Friends | |
struct | DenseMapInfo< SDValue > |
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Many nodes return multiple values, from loads (which define a token and a return value) to ADDC (which returns a result and a carry value), to calls (which may return an arbitrary number of values).
As such, each use of a SelectionDAG computation must indicate the node that computes it as well as which return value to use from that node. This pair of information is represented with the SDValue value type.
Definition at line 137 of file SelectionDAGNodes.h.
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Referenced by getValue().
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Definition at line 1111 of file SelectionDAGNodes.h.
References assert().
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Definition at line 1177 of file SelectionDAGNodes.h.
References Node::dump().
Referenced by lowerStatepointMetaArgs(), PerformSHLSimplify(), and llvm::SelectionDAGBuilder::resolveDanglingDebugInfo().
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Definition at line 1181 of file SelectionDAGNodes.h.
References Node::dump(), and G.
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Definition at line 1185 of file SelectionDAGNodes.h.
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Definition at line 1189 of file SelectionDAGNodes.h.
References G.
Definition at line 1141 of file SelectionDAGNodes.h.
References i.
Referenced by combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineOr(), combineShiftAnd1ToBitTest(), combineShiftLeft(), getFauxShuffleMask(), llvm::SelectionDAG::getNode(), LowerBuildVectorv4x32(), lowerShuffleOfExtractsAsVperm(), llvm::SelectionDAG::matchBinOpReduction(), PerformBFICombine(), PerformMinMaxToSatCombine(), llvm::TargetLowering::SimplifySetCC(), and llvm::X86TargetLowering::targetShrinkDemandedConstant().
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Definition at line 1137 of file SelectionDAGNodes.h.
References i.
Referenced by canonicalizeLaneShuffleWithRepeatedOps(), checkBoolTestSetCCCombine(), combineAnd(), combineCarryThroughADD(), combineCommutableSHUFP(), combineCompareEqual(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineORToGORC(), combineSubABS(), combineTargetShuffle(), constructDup(), getBaseWithOffsetUsingSplitOR(), getFauxShuffleMask(), llvm::SelectionDAG::getNode(), getPowerOf2Factor(), getTargetShuffleAndZeroables(), getVPermMask(), llvm::SelectionDAG::InferPtrAlign(), isAddSubOrSubAdd(), IsCMPZCSINC(), isHopBuildVector(), isHorizontalBinOpPart(), llvm::SelectionDAG::isSplatValue(), LowerAsSplatVectorLoad(), LowerBUILD_VECTORToVIDUP(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv4x32(), lowerConvertToSVBool(), lowerShuffleAsBroadcast(), PeepholePPC64ZExtGather(), performANDORCSELCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSetCCPunpkCombine(), performUADDVCombine(), PerformVMOVRRDCombine(), PerformVSetCCToVCTPCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructTruncateFromBuildVector(), reduceBuildVecToShuffleWithZero(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), vectorizeExtractedCast(), and willShiftRightEliminate().
Definition at line 1173 of file SelectionDAGNodes.h.
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Definition at line 1157 of file SelectionDAGNodes.h.
Referenced by PeepholePPC64ZExtGather().
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get the SDNode which holds the desired result
Definition at line 151 of file SelectionDAGNodes.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineTo64bitUMAAL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), AddGlue(), llvm::AMDGPUTargetLowering::addTokenForArgument(), adjustBitcastSrcVectorSSE1(), buildCallOperands(), BuildExactSDIV(), buildFromShuffleMostly(), llvm::TargetLowering::BuildSDIV(), llvm::RISCVTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildUDIV(), calculatePreExtendType(), canonicalizeShuffleMaskWithHorizOp(), llvm::checkForCycles(), CheckForMaskedLoad(), checkHighLaneIndex(), checkV64LaneV128(), checkValueWidth(), combineADDCARRYDiamond(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAnd(), combineAndMaskToShift(), combineAndnp(), combineBinOpToReduce(), combineBitcast(), combineCarryDiamond(), combineCarryThroughADD(), combineCCMask(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractWithShuffle(), combineFaddCFmul(), combineHorizOpWithShuffle(), combineINSERT_SUBVECTOR(), combineMaskedLoadConstantMask(), combinePTESTCC(), combineRedundantDWordShuffle(), combineSelectAndUse(), combineSelectAndUseCommutative(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineSextInRegCmov(), combineShuffleOfScalars(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendCMOV(), combineVectorPack(), combineVectorShiftImm(), combineVectorShiftVar(), CombineVLDDUP(), combineXor(), combineZext(), computeZeroableShuffleElements(), createGPRPairNode(), detectSSatPattern(), detectUSatPattern(), distributeOpThroughSelect(), EltsFromConsecutiveLoads(), emitConjunctionRec(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandMUL_LOHI(), ExpandPowI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), FindBFIToCombineWith(), findConsecutiveLoad(), findEltLoadSrc(), foldFreeOpFromSelect(), foldVectorXorShiftIntoCmp(), GenerateTBL(), llvm::PPC::get_VSPLTI_elt(), getBuildPairElt(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::TargetLowering::getCheaperNegatedExpression(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::ScheduleDAGSDNodes::getCustomGraphFeatures(), llvm::SelectionDAG::GetDemandedBits(), getFauxShuffleMask(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), llvm::SDNode::getGluedNode(), llvm::DenseMapInfo< SDValue >::getHashValue(), llvm::SDUse::getNode(), llvm::SelectionDAG::getNode(), llvm::MipsTargetLowering::getOpndList(), getPointerConstIncrement(), getPostIndexedLoadStoreOp(), getPowerOf2Factor(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::PPCTargetLowering::getPreIndexedAddressParts(), llvm::simplify_type< SDValue >::getSimplifiedValue(), llvm::simplify_type< const SDValue >::getSimplifiedValue(), llvm::SelectionDAG::getStrictFPExtendOrRound(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorShuffle(), haveEfficientBuildVectorPattern(), incDecVectorConstant(), llvm::SelectionDAG::InferPtrAlign(), insert1BitVector(), insertDAGNode(), isAnyConstantBuildVector(), isBitfieldExtractOpFromAnd(), isBLACompatibleAddress(), isBSwapHWordElement(), isCalleeLoad(), isConsecutiveLSLoc(), isFNEG(), isFusableLoadOpStorePattern(), llvm::TargetLowering::isGAPlusOffset(), isMemOPCandidate(), IsNOT(), isNullFPScalarOrVectorConst(), isShuffleFoldableLoad(), llvm::SelectionDAG::isUndef(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), llvm::SelectionDAG::Legalize(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), LowerAVXCONCAT_VECTORS(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), llvm::VETargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallFromStatepointLoweringInfo(), LowerCONCAT_VECTORSvXi1(), lowerConvertToSVBool(), lowerDSPIntr(), LowerF128Load(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), llvm::HexagonTargetLowering::LowerLoad(), lowerLoadF128(), LowerMLOAD(), lowerMSABinaryBitImmIntr(), LowerMUL(), llvm::TargetLowering::LowerOperationWrapper(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), LowerRotate(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsPermuteAndUnpack(), lowerStatepointMetaArgs(), llvm::HexagonTargetLowering::LowerStore(), LowerStore(), lowerVECTOR_SHUFFLE(), LowerVSETCC(), llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(), matchShuffleAsBlend(), moveBelowOrigChain(), narrowExtractedVectorSelect(), narrowVectorSelect(), NewSDValueDbgMsg(), parseTexFail(), llvm::SITargetLowering::passSpecialInputs(), PeepholePPC64ZExtGather(), PerformADDCombineWithOperands(), performAddDotCombine(), PerformADDVecReduce(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::MipsSETargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performExtendCombine(), PerformExtractEltToVMOVRRD(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFPExtendCombine(), PerformHWLoopCombine(), PerformInsertEltCombine(), performIntToFpCombine(), PerformLongShiftCombine(), PerformMinMaxCombine(), performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), PerformMVEVLDCombine(), performNEONPostLDSTCombine(), performORCombine(), PerformORCombine(), performPostLD1Combine(), performSignExtendSetCCCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToWideningLoad(), PerformSTORECombine(), PerformSUBCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformUMLALCombine(), PerformVECREDUCE_ADDCombine(), PerformVMOVDRRCombine(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), performVSelectCombine(), performXORCombine(), prepareIndirectCall(), PromoteMaskArithmetic(), reduceVSXSwap(), removeRedundantInsertVectorElt(), llvm::SelectionDAG::ReplaceAllUsesWith(), ReplaceINTRINSIC_W_CHAIN(), llvm::ARMTargetLowering::ReplaceNodeResults(), reservePreviousStackSlotForValue(), llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), llvm::SelectionDAG::salvageDebugInfo(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HvxSelector::selectRor(), llvm::HvxSelector::selectShuffle(), shouldCombineToPostInc(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), spillIncomingStatepointValue(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), llvm::SelectionDAG::transferDbgValues(), tryBitfieldInsertOpFromOr(), TryCombineBaseUpdate(), tryCombineToBSL(), llvm::HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(), tryToFoldExtendOfConstant(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), and tryToFoldExtOfMaskedLoad().
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Definition at line 1129 of file SelectionDAGNodes.h.
Referenced by llvm::InstrEmitter::AddDbgValueLocationOps(), combineBitcast(), combineFMulcFCMulc(), combineShuffleOfConcatUndef(), computeZeroableShuffleElements(), ExtendToType(), foldShuffleOfConcatUndefs(), llvm::SelectionDAG::getNode(), getPermuteMask(), isCalleeLoad(), IsElementEquivalent(), isFusableLoadOpStorePattern(), LowerBUILD_VECTORAsVariablePermute(), LowerVECTOR_SHUFFLE(), matchPMADDWD_2(), moveBelowOrigChain(), partitionShuffleOfConcats(), PerformADDVecReduce(), PerformExtractEltCombine(), PerformSplittingMVETruncToNarrowingStores(), PerformVECTOR_SHUFFLECombine(), ReconstructTruncateFromBuildVector(), llvm::ARMTargetLowering::ReplaceNodeResults(), and llvm::X86TargetLowering::targetShrinkDemandedConstant().
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Definition at line 1121 of file SelectionDAGNodes.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitUMAAL(), AddCombineVUZPToVPADDL(), adjustBitcastSrcVectorSSE1(), BuildExactSDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), calculatePreExtendType(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canonicalizeBitSelect(), llvm::SelectionDAG::canonicalizeCommutativeBinop(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleWithBinOps(), checkBoolTestAndOrSetCCCombine(), checkBoolTestSetCCCombine(), checkHighLaneIndex(), collectConcatOps(), combineABSToABD(), combineAdd(), combineADDCARRYDiamond(), combineAddOfPMADDWD(), combineAddOrSubToADCOrSBB(), combineADDSUB_VLToVWADDSUB_VL(), combineAnd(), combineAndMaskToShift(), combineArithReduction(), combineBasicSADPattern(), combineBinOpToReduce(), combineBitcast(), combineBitcastToBoolVector(), combineBitOpWithMOVMSK(), combineBitOpWithShift(), combineBVOfConsecutiveLoads(), combineBVOfVecSExt(), combineBVZEXTLOAD(), combineCarryDiamond(), combineCarryThroughADD(), combineCompareEqual(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFaddCFmul(), combineFAndFNotToFAndn(), combineFMulcFCMulc(), combineINSERT_SUBVECTOR(), combineMUL_VLToVWMUL_VL(), combineMulToPMADDWD(), combineOr(), combineORToGORC(), combineORToSHFL(), combinePTESTCC(), combineRedundantDWordShuffle(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectAndUse(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToAVG(), combineShiftToMULH(), combineShiftToPMULH(), combineShuffleOfBitcast(), combineShuffleOfConcatUndef(), combineShuffleToFMAddSub(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubABS(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineTruncationShuffle(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVectorShiftImm(), combineVPDPBUSDPattern(), combineVWADD_W_VL_VWSUB_W_VL(), combineX86ShuffleChain(), combineXor(), combineZext(), llvm::SelectionDAG::computeOverflowKind(), computeZeroableShuffleElements(), constructDup(), convertIntLogicToFPLogic(), detectAVGPattern(), detectExtMul(), detectPMADDUBSW(), detectSSatPattern(), detectUSatPattern(), detectZextAbsDiff(), EmitAVX512Test(), EmitCmp(), EmitTest(), EmitUnrolledSetTag(), ExtendToType(), extractBooleanFlip(), extractShiftForRotate(), extractSubVector(), FindBFIToCombineWith(), findEltLoadSrc(), foldAddSubBoolOfMaskedVal(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldAndToUsubsat(), foldBitcastedFPLogic(), llvm::SelectionDAG::FoldConstantArithmetic(), foldExtendedSignBitTest(), foldFPToIntToFP(), foldFreeOpFromSelect(), FoldIntToFPToInt(), foldLogicOfShifts(), foldSelectWithIdentityConstant(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldShuffleOfConcatUndefs(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), getARMIndexedAddressParts(), getAsCarry(), getBaseWithOffsetUsingSplitOR(), llvm::getBitwiseNotOperand(), getBT(), getBuildPairElt(), getCmp(), llvm::SelectionDAG::GetDemandedBits(), getFauxShuffleMask(), getGatherScatterIndexIsExtended(), getIndexFromUnindexedLoad(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getNode(), getOutputChainFromCallSeq(), getPermuteMask(), getPowerOf2Factor(), getScalarValueForVectorElement(), llvm::SelectionDAG::getSplatSourceVector(), getSToVPermuted(), getSubVectorSrc(), getTargetConstantFromBasePtr(), getTargetShuffleAndZeroables(), getTargetVShiftNode(), llvm::SelectionDAG::getValidMaximumShiftAmountConstant(), llvm::SelectionDAG::getValidMinimumShiftAmountConstant(), llvm::SelectionDAG::getValidShiftAmountConstant(), llvm::SelectionDAG::getVectorShuffle(), getVPermMask(), haveEfficientBuildVectorPattern(), InferPointerInfo(), isAbsolute(), isADDADDMUL(), isAddCarryChain(), isADDLike(), isAddSubOrSubAdd(), isAnyConstantBuildVector(), llvm::isBitwiseNot(), isBoolSGPR(), isBSwapHWordElement(), isCalleeLoad(), llvm::SITargetLowering::isCanonicalized(), IsCMPZCSINC(), isConditionalZeroOrAllOnes(), isConsecutiveLSLoc(), IsCopyFromSGPR(), llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(), IsElementEquivalent(), isFMAddSubOrFMSubAdd(), isFusableLoadOpStorePattern(), isHopBuildVector(), isHorizontalBinOpPart(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), IsNOT(), isSaturatingMinMax(), llvm::SelectionDAG::isSplatValue(), isSubBorrowChain(), isTargetConstant(), isTruncWithZeroHighBitsInput(), isWorthFoldingSHL(), llvm::XCoreTargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), lookThroughSignExtension(), lower1BitShuffle(), LowerAndToBT(), LowerAndToBTST(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORToVIDUP(), lowerBuildVectorAsBroadcast(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv4x32(), lowerConvertToSVBool(), LowerFABSorFNEG(), lowerFP_TO_SINT_STORE(), lowerFPToIntToFP(), LowerMLOAD(), LowerSaturatingConditional(), lowerShuffleAsBroadcast(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), lowerV4F64Shuffle(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVSETCC(), llvm::SelectionDAG::matchBinOpReduction(), matchBSwapHWordOrAndAnd(), MatchingStackOffset(), matchLogicBlend(), matchPMADDWD(), matchPMADDWD_2(), matchRotateSub(), matchSplatAsGather(), matchUnaryShuffle(), mayUseP9Setb(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowExtractedVectorSelect(), narrowInsertExtractVectorBinOp(), llvm::peekThroughBitcasts(), llvm::peekThroughExtractSubvectors(), llvm::peekThroughOneUseBitcasts(), PerformADDCombineWithOperands(), performAddDotCombine(), performAddUADDVCombine(), performANDCombine(), PerformANDCombine(), performANDORCSELCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), performBuildShuffleExtendCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformExtendCombine(), PerformExtractEltCombine(), performExtractSubvectorCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), PerformFAddVSelectCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performLastTrueTestVectorCombine(), performMADD_MSUBCombine(), PerformMinMaxFpToSatCombine(), PerformMinMaxToSatCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), performNegCSelCombine(), performORCombine(), PerformORCombine(), PerformORCombineToBFI(), performSELECTCombine(), performSelectCombine(), performSetCCPunpkCombine(), performSHLCombine(), PerformSHLSimplify(), PerformShuffleVMOVNCombine(), PerformSplittingToWideningLoad(), performSVEAndCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performUADDVCombine(), PerformUMinFpToSatCombine(), performUzpCombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), performVecReduceAddCombineWithUADDLP(), PerformVECTOR_SHUFFLECombine(), performVectorExtendCombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), PerformVMULCombine(), PerformVQDMULHCombine(), performVSELECTCombine(), performVSelectCombine(), PerformVSetCCToVCTPCombine(), performXORCombine(), PromoteMaskArithmetic(), pushAddIntoCmovOfConsts(), reachesChainWithoutSideEffects(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructTruncateFromBuildVector(), removeRedundantInsertVectorElt(), replaceShuffleOfInsert(), replaceSplatVectorStore(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), scalarizeExtEltFP(), scalarizeExtractedBinop(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), SelectSAddrFI(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::X86TargetLowering::shouldScalarizeBinop(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::AMDGPUTargetLowering::stripBitcast(), tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineToBSL(), tryConvertSVEWideCompare(), TryDistrubutionADDVecReduce(), tryLowerToSLI(), trySwapVSelectOperands(), vectorizeExtractedCast(), visitORCommutative(), widenCtPop(), and willShiftRightEliminate().
Definition at line 1133 of file SelectionDAGNodes.h.
References i.
Referenced by AddCombineVUZPToVPADDL(), adjustBitcastSrcVectorSSE1(), adjustForLTGFR(), calculatePreExtendType(), canonicalizeBitSelect(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleWithBinOps(), checkBoolTestSetCCCombine(), checkHighLaneIndex(), collectConcatOps(), combineABSToABD(), combineAdd(), combineADDCARRYDiamond(), combineAddOfPMADDWD(), combineAddOrSubToADCOrSBB(), combineADDSUB_VLToVWADDSUB_VL(), combineAnd(), combineAndMaskToShift(), combineBasicSADPattern(), combineBinOpToReduce(), combineBitcast(), combineBitcastToBoolVector(), combineBitOpWithMOVMSK(), combineBitOpWithShift(), combineBVOfConsecutiveLoads(), combineBVOfVecSExt(), combineCarryDiamond(), combineCarryThroughADD(), combineCommutableSHUFP(), combineCompareEqual(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFaddCFmul(), combineFAndFNotToFAndn(), combineFMA(), combineFMulcFCMulc(), combineINSERT_SUBVECTOR(), combineMUL_VLToVWMUL_VL(), combineMulToPMADDWD(), combineOr(), combineORToGORC(), combineORToSHFL(), combinePTESTCC(), combineRedundantDWordShuffle(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectAndUse(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToAVG(), combineShiftToMULH(), combineShiftToPMULH(), combineShuffleOfBitcast(), combineShuffleOfConcatUndef(), combineShuffleToFMAddSub(), combineSignExtendInReg(), combineStore(), combineSub(), combineSubABS(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineTruncationShuffle(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVectorShiftImm(), combineVWADD_W_VL_VWSUB_W_VL(), combineX86ShuffleChain(), combineXor(), combineZext(), computeZeroableShuffleElements(), constructDup(), convertIntLogicToFPLogic(), createPSADBW(), detectAVGPattern(), detectPMADDUBSW(), detectSSatPattern(), detectUSatPattern(), detectZextAbsDiff(), distributeOpThroughSelect(), EmitAVX512Test(), EmitCmp(), ExtendToType(), extractBooleanFlip(), extractShiftForRotate(), findEltLoadSrc(), foldAddSubBoolOfMaskedVal(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldAndToUsubsat(), foldBitcastedFPLogic(), foldExtendedSignBitTest(), foldFPToIntToFP(), FoldIntToFPToInt(), foldLogicOfShifts(), foldOverflowCheck(), foldSelectWithIdentityConstant(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldShuffleOfConcatUndefs(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), getAsCarry(), getBaseWithConstantOffset(), getBaseWithOffsetUsingSplitOR(), llvm::getBitwiseNotOperand(), getBT(), getBuildPairElt(), llvm::SelectionDAG::GetDemandedBits(), getFauxShuffleMask(), getGatherScatterIndexIsExtended(), getIndexFromUnindexedLoad(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getNode(), getPermuteMask(), getPowerOf2Factor(), getReductionSDNode(), getScalarValueForVectorElement(), llvm::SelectionDAG::getSplatSourceVector(), getSToVPermuted(), getSubVectorSrc(), getTargetConstantFromBasePtr(), getTargetShuffleAndZeroables(), getTargetVShiftNode(), llvm::SelectionDAG::getValidMaximumShiftAmountConstant(), llvm::SelectionDAG::getValidMinimumShiftAmountConstant(), llvm::SelectionDAG::getValidShiftAmountConstant(), getVectorCompareInfo(), getVectorShuffle(), getVPermMask(), haveEfficientBuildVectorPattern(), InferPointerInfo(), llvm::SelectionDAG::InferPtrAlign(), isAbsolute(), isADDADDMUL(), isAddCarryChain(), isADDLike(), isAddSubOrSubAdd(), isBitfieldExtractOpFromAnd(), llvm::isBitwiseNot(), isBoolSGPR(), isBSwapHWordElement(), isCalleeLoad(), llvm::SITargetLowering::isCanonicalized(), IsCMPZCSINC(), IsCopyFromSGPR(), IsElementEquivalent(), isFMAddSubOrFMSubAdd(), isFusableLoadOpStorePattern(), isHopBuildVector(), isHorizontalBinOpPart(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::ARMTargetLowering::isMulAddWithConstProfitable(), IsNOT(), isSaturatingMinMax(), llvm::SelectionDAG::isSplatValue(), isSubBorrowChain(), isTruncWithZeroHighBitsInput(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), llvm::X86TargetLowering::isVectorLoadExtDesirable(), isWorthFoldingSHL(), LookThroughSetCC(), lookThroughSignExtension(), lower1BitShuffle(), LowerAndToBT(), LowerAndToBTST(), LowerAsSplatVectorLoad(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORToVIDUP(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv4x32(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), LowerFABSorFNEG(), lowerFP_TO_SINT_STORE(), lowerFPToIntToFP(), LowerSaturatingConditional(), LowerShift(), lowerShuffleAsBroadcast(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), LowerTruncateToBTST(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVSETCC(), llvm::SelectionDAG::matchBinOpReduction(), matchBSwapHWordOrAndAnd(), MatchingStackOffset(), matchLogicBlend(), matchPMADDWD_2(), matchRotateSub(), matchSplatAsGather(), mayUseP9Setb(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowExtractedVectorSelect(), narrowInsertExtractVectorBinOp(), partitionShuffleOfConcats(), llvm::peekThroughBitcasts(), llvm::peekThroughExtractSubvectors(), llvm::peekThroughOneUseBitcasts(), PeepholePPC64ZExtGather(), PerformADDCombineWithOperands(), performAddDotCombine(), performAddUADDVCombine(), PerformADDVecReduce(), performANDCombine(), performANDORCSELCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), performBuildShuffleExtendCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformExtendCombine(), PerformExtractEltCombine(), performExtractSubvectorCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), PerformFAddVSelectCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performLastTrueTestVectorCombine(), PerformMinMaxFpToSatCombine(), PerformMinMaxToSatCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), performNegCSelCombine(), performORCombine(), PerformORCombineToBFI(), performSELECTCombine(), performSelectCombine(), performSetCCPunpkCombine(), performSHLCombine(), PerformShuffleVMOVNCombine(), performSignExtendSetCCCombine(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performUADDVCombine(), PerformUMinFpToSatCombine(), performUzpCombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), PerformVECTOR_SHUFFLECombine(), performVectorExtendCombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), PerformVQDMULHCombine(), performVSELECTCombine(), performVSelectCombine(), PerformVSetCCToVCTPCombine(), performXORCombine(), PromoteMaskArithmetic(), pushAddIntoCmovOfConsts(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructTruncateFromBuildVector(), reduceBuildVecToShuffleWithZero(), reduceVSXSwap(), removeRedundantInsertVectorElt(), replaceShuffleOfInsert(), replaceSplatVectorStore(), replaceZeroVectorStore(), scalarizeExtEltFP(), scalarizeExtractedBinop(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), SelectSAddrFI(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::AMDGPUTargetLowering::stripBitcast(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineToBSL(), tryConvertSVEWideCompare(), TryDistrubutionADDVecReduce(), trySwapVSelectOperands(), tryToFoldExtendOfConstant(), vectorizeExtractedCast(), visitORCommutative(), widenCtPop(), and willShiftRightEliminate().
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get the index which selects a specific result in the SDNode
Definition at line 148 of file SelectionDAGNodes.h.
Referenced by combineADDCARRYDiamond(), combineAddOrSubToADCOrSBB(), combineCarryThroughADD(), combineExtractVectorElt(), CombineVLDDUP(), llvm::SelectionDAG::computeOverflowKind(), ExtendUsesToFormExtLoad(), getAsCarry(), getBuildPairElt(), getCmp(), llvm::RegsForValue::getCopyToRegs(), llvm::DenseMapInfo< SDValue >::getHashValue(), llvm::SDUse::getResNo(), isFusableLoadOpStorePattern(), PerformADDVecReduce(), PerformExtractEltToVMOVRRD(), PerformVMOVDRRCombine(), llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::SelectionDAG::salvageDebugInfo(), and llvm::SelectionDAG::transferDbgValues().
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Definition at line 195 of file SelectionDAGNodes.h.
References llvm::EVT::getFixedSizeInBits(), llvm::EVT::getScalarType(), and getValueType().
Referenced by calculateByteProvider(), combineExtractWithShuffle(), combineMulToPMADDWD(), combineShiftOfShiftedLogic(), combineTargetShuffle(), combineTruncationShuffle(), combineVectorPack(), combineVectorSizedSetCCEquality(), combineX86ShuffleChain(), combineZext(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), constructDup(), findEltLoadSrc(), foldSetCCWithFunnelShift(), llvm::getBitwiseNotOperand(), getFauxShuffleMask(), llvm::SelectionDAG::getValidMaximumShiftAmountConstant(), llvm::SelectionDAG::getValidMinimumShiftAmountConstant(), llvm::SelectionDAG::getValidShiftAmountConstant(), llvm::isBitwiseNot(), LowerEXTRACT_VECTOR_ELT(), lowerShuffleAsBroadcast(), matchBinaryShuffle(), matchShuffleWithPACK(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), truncateVecElts(), and widenSubVector().
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Return the simple ValueType of the referenced return value.
Definition at line 182 of file SelectionDAGNodes.h.
References llvm::EVT::getSimpleVT(), and getValueType().
Referenced by canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), combineAddOfPMADDWD(), combineBinOpToReduce(), combineBitcast(), combineConcatVectorOps(), combineINSERT_SUBVECTOR(), combineLoad(), combineRedundantDWordShuffle(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVEXTRACT_STORE(), combineVWADD_W_VL_VWSUB_W_VL(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), constructDup(), convertShiftLeftToScale(), EmitAVX512Test(), ExpandHorizontalBinOp(), ExtendToType(), ExtractBitFromMaskVector(), getCopyFromPartsVector(), getNullFPConstForNullVal(), getPMOVMSKB(), getReductionSDNode(), getScalarValueForVectorElement(), getShuffleHalfVectors(), getTargetVShiftNode(), getUnderlyingExtractedFromVec(), incDecVectorConstant(), insert1BitVector(), InsertBitToMaskVector(), isAddSubOrSubAdd(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORSvXi1(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerFCOPYSIGN(), LowerFGETSIGN(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), lowerFPToIntToFP(), LowerHorizontalByteSum(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerMSTORE(), lowerShuffleAsBroadcast(), lowerShuffleAsInsertPS(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPERMV(), LowerStore(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vec(), lowerUINT_TO_FP_vXi32(), lowerV16F32Shuffle(), lowerV16I16Shuffle(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2I64Shuffle(), lowerV32I16Shuffle(), lowerV32I8Shuffle(), lowerV4F32Shuffle(), lowerV4F64Shuffle(), lowerV4I32Shuffle(), lowerV4I64Shuffle(), lowerV64I8Shuffle(), lowerV8F16Shuffle(), lowerV8F32Shuffle(), lowerV8F64Shuffle(), lowerV8I16Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), lowerVECTOR_SHUFFLE(), lowerVectorIntrinsicScalars(), LowerVSETCC(), matchShuffleAsInsertPS(), narrowExtractedVectorSelect(), llvm::PPCTargetLowering::PerformDAGCombine(), performVECTOR_SHUFFLECombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), splitAndLowerShuffle(), vectorizeExtractedCast(), and widenSubVector().
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Definition at line 171 of file SelectionDAGNodes.h.
References llvm::RISCVFenceField::R, and SDValue().
Referenced by AddCombineTo64bitMLAL(), adjustSubwordCmp(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), combineADDCARRYDiamond(), combineAddOrSubToADCOrSBB(), combineBitcast(), combineCarryDiamond(), combineCVTP2I_CVTTP2I(), combineCVTPH2PS(), combineFP_EXTEND(), combineINSERT_SUBVECTOR(), combineLoad(), combineMaskedLoadConstantMask(), combineMOVDQ2Q(), combineSetCCAtomicArith(), combineSIntToFP(), combineTargetShuffle(), combineVectorCompareAndMaskUnaryOp(), combineVectorSizedSetCCEquality(), combineX86INT_TO_FP(), ConvertBooleanCarryToCarryFlag(), EmitCmp(), emitComparison(), emitRepmovs(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemcmp(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), EmitTest(), llvm::TargetLowering::expandFixedPointDiv(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), GeneratePerfectShuffle(), getAArch64XALUOOp(), getAVX2GatherNode(), getBROADCAST_LOAD(), llvm::RegsForValue::getCopyToRegs(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getFPBinOp(), getFPTernOp(), getGatherNode(), getMemCmpLoad(), llvm::MipsTargetLowering::getOpndList(), getOutputChainFromCallSeq(), GetTLSADDR(), getv64i1Argument(), llvm::TargetLowering::LegalizeSetCCCondCode(), llvm::HexagonTargetLowering::LowerAddSubCarry(), lowerADDSUBCARRY(), LowerADDSUBCARRY(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), lowerAtomicArith(), lowerBuildVectorAsBroadcast(), llvm::VETargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), lowerCallResult(), LowerCallResult(), LowerCMP_SWAP(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), LowerFP16_TO_FP(), LowerFP_TO_FP16(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerI64IntToFP16(), LowerI64IntToFP_AVX512DQ(), lowerINT_TO_FP_vXi64(), LowerINTRINSIC_W_CHAIN(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::TargetLowering::LowerOperationWrapper(), LowerPARITY(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerSETCCCARRY(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSLocalDynamicModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerVECTOR_SHUFFLE(), LowerVSETCC(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(), llvm::ARMTargetLowering::PerformCMOVCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performDivRemCombine(), performExtractVectorEltCombine(), performFPExtendCombine(), performGatherLoadCombine(), performLDNT1Combine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performScatterStoreCombine(), PerformSETCCCombine(), performSignExtendInRegCombine(), PerformSTORECombine(), PerformVDUPCombine(), PerformVECREDUCE_ADDCombine(), PerformVMOVhrCombine(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), prepareDescriptorIndirectCall(), prepareIndirectCall(), PrepareTailCall(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), ReplaceLongIntrinsic(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), SkipExtensionForVMULL(), splitStores(), splitStoreSplat(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), tryToElideArgumentCopy(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), llvm::SelectionDAG::UnrollVectorOverflowOp(), and llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad().
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Returns the size of the value in bits.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 191 of file SelectionDAGNodes.h.
References llvm::EVT::getSizeInBits(), and getValueType().
Referenced by CheckForMaskedLoad(), combineArithReduction(), combineBT(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractWithShuffle(), combineINSERT_SUBVECTOR(), combineMUL_VLToVWMUL_VL(), combineMulToPMADDWD(), combineSetCCMOVMSK(), combineShiftLeft(), combineStore(), combineTargetShuffle(), combineVectorCompareAndMaskUnaryOp(), combineVWADD_W_VL_VWSUB_W_VL(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), combineZext(), llvm::SelectionDAG::computeKnownBits(), computeZeroableShuffleElements(), constructDup(), createVariablePermute(), EltsFromConsecutiveLoads(), getBT(), getFauxShuffleMask(), getHopForBuildVector(), llvm::SelectionDAG::getNode(), getPermuteMask(), isHorizontalBinOp(), isTruncWithZeroHighBitsInput(), lookThroughSignExtension(), LowerAndToBT(), LowerAndToBTST(), lowerBuildVectorAsBroadcast(), lowerFP_TO_SINT_STORE(), llvm::NVPTXTargetLowering::LowerReturn(), lowerShuffleAsBroadcast(), lowerV8I16GeneralSingleInputShuffle(), matchPMADDWD_2(), reduceBuildVecToShuffleWithZero(), llvm::SelectionDAGISel::SelectCodeCommon(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifySetCC(), spillIncomingStatepointValue(), tryCombineFixedPointConvert(), tryFormConcatFromShuffle(), and widenSubVector().
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Return the ValueType of the referenced return value.
Definition at line 1125 of file SelectionDAGNodes.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineVUZPToVPADDL(), adjustBitcastSrcVectorSSE1(), llvm::VECustomDAG::annotateLegalAVL(), buildFromShuffleMostly(), BuildIntrinsicOp(), calculatePreExtendType(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canEmitConjunction(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleWithBinOps(), CheckForMaskedLoad(), clampDynamicVectorIndex(), collectConcatOps(), combineABSToABD(), combineAdd(), combineADDCARRYDiamond(), combineAddOrSubToADCOrSBB(), combineADDSUB_VLToVWADDSUB_VL(), combineAnd(), combineAndMaskToShift(), combineArithReduction(), combineBasicSADPattern(), combineBinOpToReduce(), combineBitcast(), combineBitOpWithMOVMSK(), combineBitOpWithShift(), combineCarryDiamond(), combineCarryThroughADD(), combineCMov(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFP_EXTEND(), combineHorizOpWithShuffle(), combineMaskedStore(), combineMUL_VLToVWMUL_VL(), combinePTESTCC(), combineRedundantDWordShuffle(), combineScalarAndWithMaskSetcc(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineShiftLeft(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToMULH(), combineShuffleOfBitcast(), combineShuffleOfScalars(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSVEReductionFP(), combineSVEReductionOrderedFP(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineTruncate(), combineUIntToFP(), combineVectorPack(), combineVectorShiftImm(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), combineVWADD_W_VL_VWSUB_W_VL(), combineX86GatherScatter(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineXor(), combineZext(), CompactSwizzlableVector(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), concatSubVectors(), constructDup(), ConvertBooleanCarryToCarryFlag(), convertFixedMaskToScalableVector(), convertFromScalableVector(), convertIntLogicToFPLogic(), convertToScalableVector(), createCMovFP(), createLoadLR(), createPSADBW(), createStoreLR(), createVariablePermute(), detectAVGPattern(), detectPMADDUBSW(), detectZextAbsDiff(), distributeOpThroughSelect(), EltsFromConsecutiveLoads(), EmitCmp(), llvm::AArch64SelectionDAGInfo::EmitMOPS(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), EmitTruncSStore(), expandf64Toi32(), ExpandPowI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), ExtendToType(), ExtendUsesToFormExtLoad(), extract128BitVector(), extract256BitVector(), extractBooleanFlip(), extractShiftForRotate(), extractSubReg(), extractSubVector(), FlattenVectorShuffle(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldAndToUsubsat(), foldBitcastedFPLogic(), llvm::SelectionDAG::FoldConstantArithmetic(), foldExtendedSignBitTest(), foldExtractSubvectorFromShuffleVector(), foldFPToIntToFP(), FoldIntToFPToInt(), llvm::SelectionDAG::FoldSetCC(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldTruncStoreOfExt(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), GeneratePerfectShuffle(), getAsCarry(), llvm::SelectionDAG::getAssertAlign(), llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getAtomicCmpSwap(), llvm::SelectionDAG::getBitcast(), getBitTestCondition(), llvm::getBitwiseNotOperand(), getBT(), getBuildDwordsVector(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), llvm::SelectionDAG::GetDemandedBits(), getEstimate(), getExtFactor(), llvm::SelectionDAG::getExtLoad(), llvm::SelectionDAG::getExtLoadVP(), llvm::SelectionDAG::getExtStridedLoadVP(), getFauxShuffleMask(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getIndexedLoad(), llvm::SelectionDAG::getIndexedLoadVP(), llvm::SelectionDAG::getIndexedMaskedLoad(), llvm::SelectionDAG::getIndexedStridedLoadVP(), getKnownUndefForVectorBinop(), llvm::VECustomDAG::getLegalReductionOpVVP(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getLoadVP(), llvm::SelectionDAG::getMaskedStore(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getNode(), getNullFPConstForNullVal(), getOutputChainFromCallSeq(), llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), llvm::AMDGPUTargetLowering::getRecipEstimate(), getReductionSDNode(), getScalarValueSizeInBits(), llvm::SelectionDAG::getSelectCC(), getShuffleHalfVectors(), getShuffleScalarElt(), getSimpleValueType(), llvm::SelectionDAG::getSplatSourceVector(), llvm::AMDGPUTargetLowering::getSqrtEstimate(), llvm::NVPTXTargetLowering::getSqrtEstimate(), llvm::TargetLowering::getSqrtResultForDenormInput(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getStoreVP(), getSToVPermuted(), llvm::SelectionDAG::getStridedLoadVP(), llvm::SelectionDAG::getStridedStoreVP(), getSubVectorSrc(), getTargetShuffleAndZeroables(), getTargetVShiftNode(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), getValueSizeInBits(), llvm::SDUse::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLowering::getVectorSubVecPointer(), getVPermMask(), llvm::AArch64TargetLowering::hasAndNotCompare(), insert128BitVector(), insertSubReg(), insertSubVector(), InvertCarryFlag(), isBitfieldExtractOpFromShr(), isBoolSGPR(), llvm::SITargetLowering::isCanonicalized(), isConditionalZeroOrAllOnes(), llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(), isHorizontalBinOpPart(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::ARMTargetLowering::isMulAddWithConstProfitable(), IsNOT(), llvm::SelectionDAG::isSplatValue(), isTruncateOf(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), llvm::X86TargetLowering::isVectorLoadExtDesirable(), llvm::XCoreTargetLowering::isZExtFree(), llvm::MSP430TargetLowering::isZExtFree(), llvm::AMDGPUTargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::TargetLoweringBase::isZExtFree(), lower1BitShuffle(), LowerADDSUBCARRY(), LowerAsSplatVectorLoad(), llvm::VETargetLowering::lowerATOMIC_SWAP(), lowerBuildVectorAsBroadcast(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), LowerCONCAT_VECTORS_i1(), LowerConvertLow(), lowerConvertToSVBool(), lowerDSPIntr(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT(), LowerF128Load(), LowerF128Store(), LowerF64Op(), lowerFCMPIntrinsic(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), LowerFunnelShift(), lowerIncomingStatepointValue(), LowerINTRINSIC_W_CHAIN(), LowerLabelRef(), lowerLoadF128(), lowerMasksToReg(), LowerMUL(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), lowerShuffleAsBroadcast(), lowerShuffleAsElementInsertion(), lowerShuffleToEXPAND(), lowerShuffleWithPACK(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), lowerStatepointMetaArgs(), LowerStore(), lowerStoreF128(), LowerSVEIntrinsicIndex(), LowerUINT_TO_FP_i32(), LowerVecReduce(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVectorAllZero(), lowerVectorIntrinsicScalars(), LowerVSETCC(), LowerWRITE_REGISTER(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::ISD::matchBinaryPredicate(), matchBinaryShuffle(), matchPMADDWD_2(), matchSplatAsGather(), MatchVectorAllZeroTest(), matchZExtFromI32(), narrowExtractedVectorBinOp(), narrowInsertExtractVectorBinOp(), NarrowVector(), needCarryOrOverflowFlag(), onlyZeroFlagUsed(), partitionShuffleOfConcats(), PerformADDCombineWithOperands(), performAddUADDVCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), performBuildShuffleExtendCombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformExtendCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), PerformExtractFpToIntStores(), performFirstTrueTestVectorCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFPExtendCombine(), performInsertSubvectorCombine(), PerformInsertSubvectorCombine(), performLastTrueTestVectorCombine(), PerformMinMaxFpToSatCombine(), performNegCSelCombine(), performSELECTCombine(), performSelectCombine(), performSetccAddFolding(), PerformShuffleVMOVNCombine(), performSignExtendInRegCombine(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), performUADDVCombine(), PerformUMinFpToSatCombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), PerformVECTOR_SHUFFLECombine(), performVectorExtendCombine(), PerformVMOVRRDCombine(), PerformVQDMULHCombine(), performVSelectCombine(), prepareTS1AM(), PromoteMaskArithmetic(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructTruncateFromBuildVector(), reduceBuildVecToShuffleWithZero(), refineUniformBase(), removeRedundantInsertVectorElt(), ReorganizeVector(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), replaceSplatVectorStore(), replaceZeroVectorStore(), SaturateWidenedDIVFIX(), scalarizeBinOpOfSplats(), scalarizeExtEltFP(), scalarizeVectorStore(), llvm::SelectionDAGISel::SelectCodeCommon(), shouldExpandVectorDynExt(), llvm::X86TargetLowering::shouldScalarizeBinop(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), llvm::TargetLowering::softenSetCCOperands(), spillIncomingStatepointValue(), llvm::SITargetLowering::splitBinaryVectorOp(), splitStores(), splitStoreSplat(), llvm::SITargetLowering::splitTernaryVectorOp(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::SystemZTargetLowering::splitValueIntoRegisterParts(), llvm::PPCTargetLowering::splitValueIntoRegisterParts(), llvm::AMDGPUTargetLowering::SplitVectorStore(), splitVectorStore(), stripModuloOnShift(), tryBitfieldInsertOpFromOr(), tryCombineFixedPointConvert(), tryFormConcatFromShuffle(), trySwapVSelectOperands(), tryToFoldExtendOfConstant(), tryToFoldExtOfLoad(), llvm::SelectionDAG::UnrollVectorOp(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), visitORCommutative(), llvm::SelectionDAGBuilder::visitSwitchCase(), widenCtPop(), widenSubVector(), widenVec(), WidenVector(), widenVectorToPartType(), and willLowerDirectly().
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Return true if there is exactly one node using value ResNo of Node.
Definition at line 1169 of file SelectionDAGNodes.h.
Referenced by canEmitConjunction(), canonicalizeBitSelect(), CheckForMaskedLoad(), combineAddOrSubToADCOrSBB(), combineADDSUB_VLToVWADDSUB_VL(), combineAndMaskToShift(), combineBinOpToReduce(), combineBitcast(), combineBitOpWithMOVMSK(), combineBitOpWithShift(), combineCMP(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineFMulcFCMulc(), combineINSERT_SUBVECTOR(), combineMUL_VLToVWMUL_VL(), combineRedundantDWordShuffle(), combineSelectAndUse(), combineSetCCAtomicArith(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToPMULH(), combineShuffleToFMAddSub(), combineSIntToFP(), combineStore(), combineSubABS(), combineTargetShuffle(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineVWADD_W_VL_VWSUB_W_VL(), combineX86ShuffleChain(), combineXor(), combineZext(), convertIntLogicToFPLogic(), EmitAVX512Test(), EmitCmp(), foldAddSubOfSignBit(), foldAndToUsubsat(), foldExtendedSignBitTest(), foldFreeOpFromSelect(), foldLogicOfShifts(), foldSelectWithIdentityConstant(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), isADDADDMUL(), isCalleeLoad(), IsNOT(), llvm::SITargetLowering::isReassocProfitable(), llvm::TargetLowering::isReassocProfitable(), lowerShuffleAsBroadcast(), lowerShuffleOfExtractsAsVperm(), LowerStore(), lowerV2X128Shuffle(), LowerVSETCC(), mayUseP9Setb(), narrowExtractedVectorBinOp(), narrowVectorSelect(), llvm::peekThroughOneUseBitcasts(), performANDCombine(), PerformBFICombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFPExtendCombine(), performIntToFpCombine(), PerformORCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformVMOVrhCombine(), pushAddIntoCmovOfConsts(), reachesChainWithoutSideEffects(), reduceVSXSwap(), replaceZeroVectorStore(), scalarizeExtEltFP(), scalarizeExtractedBinop(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), tryBitfieldInsertOpFromOr(), trySwapVSelectOperands(), tryToFoldExtendSelectLoad(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), tryToFoldExtOfMaskedLoad(), usePartialVectorLoads(), and widenCtPop().
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Definition at line 1153 of file SelectionDAGNodes.h.
Referenced by PeepholePPC64ZExtGather().
Return true if this node is an operand of N.
isOperand - Return true if this node is an operand of N.
Definition at line 10750 of file SelectionDAG.cpp.
References llvm::is_contained(), and N.
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Definition at line 1149 of file SelectionDAGNodes.h.
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Definition at line 1145 of file SelectionDAGNodes.h.
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Definition at line 1161 of file SelectionDAGNodes.h.
Referenced by buildMergeScalars(), canonicalizeLaneShuffleWithRepeatedOps(), combineAndnp(), combineConcatVectorOfExtracts(), combineINSERT_SUBVECTOR(), combineMaskedLoadConstantMask(), combineMUL_VLToVWMUL_VL(), combineSetCCMOVMSK(), combineShuffleOfBitcast(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineShuffleOfSplatVal(), combineTargetShuffle(), combineVectorHADDSUB(), combineVectorPack(), combineVectorShiftImm(), combineVWADD_W_VL_VWSUB_W_VL(), combineXor(), combineZext(), createMMXBuildVector(), EltsFromConsecutiveLoads(), ExtendToType(), FlattenVectorShuffle(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::foldConstantFPMath(), llvm::SelectionDAG::FoldSetCC(), foldShuffleOfConcatUndefs(), formSplatFromShuffles(), GenerateTBL(), getFauxShuffleMask(), getHopForBuildVector(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getNode(), llvm::BuildVectorSDNode::getRepeatedSequence(), getScalarMaskingNode(), getTargetShuffleAndZeroables(), getVectorMaskingNode(), llvm::SelectionDAG::getVectorShuffle(), getVectorShuffle(), haveEfficientBuildVectorPattern(), InferPointerInfo(), insert1BitVector(), insertSubVector(), isAddSubOrSubAdd(), llvm::BuildVectorSDNode::isConstantSplat(), isFNEG(), isHopBuildVector(), isHorizontalBinOpPart(), isSplatBV(), llvm::SelectionDAG::isSplatValue(), llvm::SelectionDAG::isUndef(), joinDwords(), LowerAVXCONCAT_VECTORS(), lowerBUILD_VECTOR(), LowerBUILD_VECTOR_i1(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerF128Load(), LowerF128Store(), lowerIncomingStatepointValue(), lowerLoadF128(), LowerMGATHER(), LowerMLOAD(), llvm::RISCVTargetLowering::LowerOperation(), lowerScalarSplat(), llvm::VETargetLowering::lowerSTORE(), lowerStoreF128(), LowerToHorizontalOp(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVectorIntrinsicScalars(), llvm::ISD::matchBinaryPredicate(), matchShuffleAsBlend(), matchShuffleWithPACK(), partitionShuffleOfConcats(), PerformARMBUILD_VECTORCombine(), performBuildShuffleExtendCombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), performInsertSubvectorCombine(), PerformInsertSubvectorCombine(), PerformSplittingToNarrowingStores(), PerformVECTOR_SHUFFLECombine(), PerformVSetCCToVCTPCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), simplifyShuffleOfShuffle(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), and willLowerDirectly().
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Definition at line 167 of file SelectionDAGNodes.h.
Definition at line 161 of file SelectionDAGNodes.h.
References llvm::RISCVFenceField::O, and operator==().
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Definition at line 156 of file SelectionDAGNodes.h.
Definition at line 164 of file SelectionDAGNodes.h.
References llvm::RISCVFenceField::O.
Definition at line 158 of file SelectionDAGNodes.h.
References llvm::RISCVFenceField::O.
Referenced by operator!=().
bool SDValue::reachesChainWithoutSideEffects | ( | SDValue | Dest, |
unsigned | Depth = 2 |
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Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions.
reachesChainWithoutSideEffects - Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions on any chain path.
In practice, this looks through token factors and non-volatile loads. In order to remain efficient, this only looks a couple of nodes in, it does not do an exhaustive search.
In practice, this looks through token factors and non-volatile loads. In order to remain efficient, this only looks a couple of nodes in, it does not do an exhaustive search.
Note that we only need to examine chains when we're searching for side-effects; SelectionDAG requires that all side-effects are represented by chains, even if another operand would force a specific ordering. This constraint is necessary to allow transformations like splitting loads.
Definition at line 10769 of file SelectionDAG.cpp.
References llvm::all_of(), llvm::Depth, getOpcode(), hasOneUse(), llvm::is_contained(), and llvm::ISD::TokenFactor.
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Return true if there are no nodes using value ResNo of Node.
Definition at line 1165 of file SelectionDAGNodes.h.
Referenced by llvm::TargetLowering::getNegatedExpression(), and llvm::SelectionDAG::makeEquivalentMemoryOrdering().
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Definition at line 138 of file SelectionDAGNodes.h.