LLVM  15.0.0git
X86Operand.h
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1 //===- X86Operand.h - Parsed X86 machine instruction ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
10 #define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
11 
14 #include "X86AsmParserCommon.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/Support/Casting.h"
23 #include "llvm/Support/SMLoc.h"
24 #include <cassert>
25 #include <memory>
26 
27 namespace llvm {
28 
29 /// X86Operand - Instances of this class represent a parsed X86 machine
30 /// instruction.
31 struct X86Operand final : public MCParsedAsmOperand {
33 
37  void *OpDecl;
38  bool AddressOf;
39 
40  /// This used for inline asm which may specify base reg and index reg for
41  /// MemOp. e.g. ARR[eax + ecx*4], so no extra reg can be used for MemOp.
42  bool UseUpRegs = false;
43 
44  struct TokOp {
45  const char *Data;
46  unsigned Length;
47  };
48 
49  struct RegOp {
50  unsigned RegNo;
51  };
52 
53  struct PrefOp {
54  unsigned Prefixes;
55  };
56 
57  struct ImmOp {
58  const MCExpr *Val;
59  bool LocalRef;
60  };
61 
62  struct MemOp {
63  unsigned SegReg;
64  const MCExpr *Disp;
65  unsigned BaseReg;
66  unsigned DefaultBaseReg;
67  unsigned IndexReg;
68  unsigned Scale;
69  unsigned Size;
70  unsigned ModeSize;
71 
72  /// If the memory operand is unsized and there are multiple instruction
73  /// matches, prefer the one with this size.
74  unsigned FrontendSize;
75 
76  /// If false, then this operand must be a memory operand for an indirect
77  /// branch instruction. Otherwise, this operand may belong to either a
78  /// direct or indirect branch instruction.
80  };
81 
82  union {
83  struct TokOp Tok;
84  struct RegOp Reg;
85  struct ImmOp Imm;
86  struct MemOp Mem;
87  struct PrefOp Pref;
88  };
89 
90  X86Operand(KindTy K, SMLoc Start, SMLoc End)
91  : Kind(K), StartLoc(Start), EndLoc(End), OpDecl(nullptr),
92  AddressOf(false) {}
93 
94  StringRef getSymName() override { return SymName; }
95  void *getOpDecl() override { return OpDecl; }
96 
97  /// getStartLoc - Get the location of the first token of this operand.
98  SMLoc getStartLoc() const override { return StartLoc; }
99 
100  /// getEndLoc - Get the location of the last token of this operand.
101  SMLoc getEndLoc() const override { return EndLoc; }
102 
103  /// getLocRange - Get the range between the first and last token of this
104  /// operand.
105  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
106 
107  /// getOffsetOfLoc - Get the location of the offset operator.
108  SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
109 
110  void print(raw_ostream &OS) const override {
111 
112  auto PrintImmValue = [&](const MCExpr *Val, const char *VName) {
113  if (Val->getKind() == MCExpr::Constant) {
114  if (auto Imm = cast<MCConstantExpr>(Val)->getValue())
115  OS << VName << Imm;
116  } else if (Val->getKind() == MCExpr::SymbolRef) {
117  if (auto *SRE = dyn_cast<MCSymbolRefExpr>(Val)) {
118  const MCSymbol &Sym = SRE->getSymbol();
119  if (const char *SymNameStr = Sym.getName().data())
120  OS << VName << SymNameStr;
121  }
122  }
123  };
124 
125  switch (Kind) {
126  case Token:
127  OS << Tok.Data;
128  break;
129  case Register:
131  break;
132  case DXRegister:
133  OS << "DXReg";
134  break;
135  case Immediate:
136  PrintImmValue(Imm.Val, "Imm:");
137  break;
138  case Prefix:
139  OS << "Prefix:" << Pref.Prefixes;
140  break;
141  case Memory:
142  OS << "Memory: ModeSize=" << Mem.ModeSize;
143  if (Mem.Size)
144  OS << ",Size=" << Mem.Size;
145  if (Mem.BaseReg)
146  OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg);
147  if (Mem.IndexReg)
148  OS << ",IndexReg="
150  if (Mem.Scale)
151  OS << ",Scale=" << Mem.Scale;
152  if (Mem.Disp)
153  PrintImmValue(Mem.Disp, ",Disp=");
154  if (Mem.SegReg)
155  OS << ",SegReg=" << X86IntelInstPrinter::getRegisterName(Mem.SegReg);
156  break;
157  }
158  }
159 
160  StringRef getToken() const {
161  assert(Kind == Token && "Invalid access!");
162  return StringRef(Tok.Data, Tok.Length);
163  }
165  assert(Kind == Token && "Invalid access!");
166  Tok.Data = Value.data();
167  Tok.Length = Value.size();
168  }
169 
170  unsigned getReg() const override {
171  assert(Kind == Register && "Invalid access!");
172  return Reg.RegNo;
173  }
174 
175  unsigned getPrefix() const {
176  assert(Kind == Prefix && "Invalid access!");
177  return Pref.Prefixes;
178  }
179 
180  const MCExpr *getImm() const {
181  assert(Kind == Immediate && "Invalid access!");
182  return Imm.Val;
183  }
184 
185  const MCExpr *getMemDisp() const {
186  assert(Kind == Memory && "Invalid access!");
187  return Mem.Disp;
188  }
189  unsigned getMemSegReg() const {
190  assert(Kind == Memory && "Invalid access!");
191  return Mem.SegReg;
192  }
193  unsigned getMemBaseReg() const {
194  assert(Kind == Memory && "Invalid access!");
195  return Mem.BaseReg;
196  }
197  unsigned getMemDefaultBaseReg() const {
198  assert(Kind == Memory && "Invalid access!");
199  return Mem.DefaultBaseReg;
200  }
201  unsigned getMemIndexReg() const {
202  assert(Kind == Memory && "Invalid access!");
203  return Mem.IndexReg;
204  }
205  unsigned getMemScale() const {
206  assert(Kind == Memory && "Invalid access!");
207  return Mem.Scale;
208  }
209  unsigned getMemModeSize() const {
210  assert(Kind == Memory && "Invalid access!");
211  return Mem.ModeSize;
212  }
213  unsigned getMemFrontendSize() const {
214  assert(Kind == Memory && "Invalid access!");
215  return Mem.FrontendSize;
216  }
217  bool isMaybeDirectBranchDest() const {
218  assert(Kind == Memory && "Invalid access!");
219  return Mem.MaybeDirectBranchDest;
220  }
221 
222  bool isToken() const override {return Kind == Token; }
223 
224  bool isImm() const override { return Kind == Immediate; }
225 
226  bool isImmSExti16i8() const {
227  if (!isImm())
228  return false;
229 
230  // If this isn't a constant expr, just assume it fits and let relaxation
231  // handle it.
232  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
233  if (!CE)
234  return true;
235 
236  // Otherwise, check the value is in a range that makes sense for this
237  // extension.
238  return isImmSExti16i8Value(CE->getValue());
239  }
240  bool isImmSExti32i8() const {
241  if (!isImm())
242  return false;
243 
244  // If this isn't a constant expr, just assume it fits and let relaxation
245  // handle it.
246  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
247  if (!CE)
248  return true;
249 
250  // Otherwise, check the value is in a range that makes sense for this
251  // extension.
252  return isImmSExti32i8Value(CE->getValue());
253  }
254  bool isImmSExti64i8() const {
255  if (!isImm())
256  return false;
257 
258  // If this isn't a constant expr, just assume it fits and let relaxation
259  // handle it.
260  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
261  if (!CE)
262  return true;
263 
264  // Otherwise, check the value is in a range that makes sense for this
265  // extension.
266  return isImmSExti64i8Value(CE->getValue());
267  }
268  bool isImmSExti64i32() const {
269  if (!isImm())
270  return false;
271 
272  // If this isn't a constant expr, just assume it fits and let relaxation
273  // handle it.
274  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
275  if (!CE)
276  return true;
277 
278  // Otherwise, check the value is in a range that makes sense for this
279  // extension.
280  return isImmSExti64i32Value(CE->getValue());
281  }
282 
283  bool isImmUnsignedi4() const {
284  if (!isImm()) return false;
285  // If this isn't a constant expr, reject it. The immediate byte is shared
286  // with a register encoding. We can't have it affected by a relocation.
287  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
288  if (!CE) return false;
289  return isImmUnsignedi4Value(CE->getValue());
290  }
291 
292  bool isImmUnsignedi8() const {
293  if (!isImm()) return false;
294  // If this isn't a constant expr, just assume it fits and let relaxation
295  // handle it.
296  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
297  if (!CE) return true;
298  return isImmUnsignedi8Value(CE->getValue());
299  }
300 
301  bool isOffsetOfLocal() const override { return isImm() && Imm.LocalRef; }
302 
303  bool needAddressOf() const override { return AddressOf; }
304 
305  bool isMem() const override { return Kind == Memory; }
306  bool isMemUnsized() const {
307  return Kind == Memory && Mem.Size == 0;
308  }
309  bool isMem8() const {
310  return Kind == Memory && (!Mem.Size || Mem.Size == 8);
311  }
312  bool isMem16() const {
313  return Kind == Memory && (!Mem.Size || Mem.Size == 16);
314  }
315  bool isMem32() const {
316  return Kind == Memory && (!Mem.Size || Mem.Size == 32);
317  }
318  bool isMem64() const {
319  return Kind == Memory && (!Mem.Size || Mem.Size == 64);
320  }
321  bool isMem80() const {
322  return Kind == Memory && (!Mem.Size || Mem.Size == 80);
323  }
324  bool isMem128() const {
325  return Kind == Memory && (!Mem.Size || Mem.Size == 128);
326  }
327  bool isMem256() const {
328  return Kind == Memory && (!Mem.Size || Mem.Size == 256);
329  }
330  bool isMem512() const {
331  return Kind == Memory && (!Mem.Size || Mem.Size == 512);
332  }
333 
334  bool isSibMem() const {
335  return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP;
336  }
337 
338  bool isMemIndexReg(unsigned LowR, unsigned HighR) const {
339  assert(Kind == Memory && "Invalid access!");
340  return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR;
341  }
342 
343  bool isMem64_RC128() const {
344  return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM15);
345  }
346  bool isMem128_RC128() const {
347  return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM15);
348  }
349  bool isMem128_RC256() const {
350  return isMem128() && isMemIndexReg(X86::YMM0, X86::YMM15);
351  }
352  bool isMem256_RC128() const {
353  return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM15);
354  }
355  bool isMem256_RC256() const {
356  return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM15);
357  }
358 
359  bool isMem64_RC128X() const {
360  return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM31);
361  }
362  bool isMem128_RC128X() const {
363  return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM31);
364  }
365  bool isMem128_RC256X() const {
366  return isMem128() && isMemIndexReg(X86::YMM0, X86::YMM31);
367  }
368  bool isMem256_RC128X() const {
369  return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM31);
370  }
371  bool isMem256_RC256X() const {
372  return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM31);
373  }
374  bool isMem256_RC512() const {
375  return isMem256() && isMemIndexReg(X86::ZMM0, X86::ZMM31);
376  }
377  bool isMem512_RC256X() const {
378  return isMem512() && isMemIndexReg(X86::YMM0, X86::YMM31);
379  }
380  bool isMem512_RC512() const {
381  return isMem512() && isMemIndexReg(X86::ZMM0, X86::ZMM31);
382  }
383 
384  bool isAbsMem() const {
385  return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
387  }
388 
389  bool isAVX512RC() const{
390  return isImm();
391  }
392 
393  bool isAbsMem16() const {
394  return isAbsMem() && Mem.ModeSize == 16;
395  }
396 
397  bool isMemUseUpRegs() const override { return UseUpRegs; }
398 
399  bool isSrcIdx() const {
400  return !getMemIndexReg() && getMemScale() == 1 &&
401  (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
402  getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
403  cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
404  }
405  bool isSrcIdx8() const {
406  return isMem8() && isSrcIdx();
407  }
408  bool isSrcIdx16() const {
409  return isMem16() && isSrcIdx();
410  }
411  bool isSrcIdx32() const {
412  return isMem32() && isSrcIdx();
413  }
414  bool isSrcIdx64() const {
415  return isMem64() && isSrcIdx();
416  }
417 
418  bool isDstIdx() const {
419  return !getMemIndexReg() && getMemScale() == 1 &&
420  (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
421  (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
422  getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
423  cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
424  }
425  bool isDstIdx8() const {
426  return isMem8() && isDstIdx();
427  }
428  bool isDstIdx16() const {
429  return isMem16() && isDstIdx();
430  }
431  bool isDstIdx32() const {
432  return isMem32() && isDstIdx();
433  }
434  bool isDstIdx64() const {
435  return isMem64() && isDstIdx();
436  }
437 
438  bool isMemOffs() const {
439  return Kind == Memory && !getMemBaseReg() && !getMemIndexReg() &&
440  getMemScale() == 1;
441  }
442 
443  bool isMemOffs16_8() const {
444  return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 8);
445  }
446  bool isMemOffs16_16() const {
447  return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 16);
448  }
449  bool isMemOffs16_32() const {
450  return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 32);
451  }
452  bool isMemOffs32_8() const {
453  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 8);
454  }
455  bool isMemOffs32_16() const {
456  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 16);
457  }
458  bool isMemOffs32_32() const {
459  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 32);
460  }
461  bool isMemOffs32_64() const {
462  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 64);
463  }
464  bool isMemOffs64_8() const {
465  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 8);
466  }
467  bool isMemOffs64_16() const {
468  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 16);
469  }
470  bool isMemOffs64_32() const {
471  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 32);
472  }
473  bool isMemOffs64_64() const {
474  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 64);
475  }
476 
477  bool isPrefix() const { return Kind == Prefix; }
478  bool isReg() const override { return Kind == Register; }
479  bool isDXReg() const { return Kind == DXRegister; }
480 
481  bool isGR32orGR64() const {
482  return Kind == Register &&
483  (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
484  X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
485  }
486 
487  bool isGR16orGR32orGR64() const {
488  return Kind == Register &&
489  (X86MCRegisterClasses[X86::GR16RegClassID].contains(getReg()) ||
490  X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
491  X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
492  }
493 
494  bool isVectorReg() const {
495  return Kind == Register &&
496  (X86MCRegisterClasses[X86::VR64RegClassID].contains(getReg()) ||
497  X86MCRegisterClasses[X86::VR128XRegClassID].contains(getReg()) ||
498  X86MCRegisterClasses[X86::VR256XRegClassID].contains(getReg()) ||
499  X86MCRegisterClasses[X86::VR512RegClassID].contains(getReg()));
500  }
501 
502  bool isVK1Pair() const {
503  return Kind == Register &&
504  X86MCRegisterClasses[X86::VK1RegClassID].contains(getReg());
505  }
506 
507  bool isVK2Pair() const {
508  return Kind == Register &&
509  X86MCRegisterClasses[X86::VK2RegClassID].contains(getReg());
510  }
511 
512  bool isVK4Pair() const {
513  return Kind == Register &&
514  X86MCRegisterClasses[X86::VK4RegClassID].contains(getReg());
515  }
516 
517  bool isVK8Pair() const {
518  return Kind == Register &&
519  X86MCRegisterClasses[X86::VK8RegClassID].contains(getReg());
520  }
521 
522  bool isVK16Pair() const {
523  return Kind == Register &&
524  X86MCRegisterClasses[X86::VK16RegClassID].contains(getReg());
525  }
526 
527  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
528  // Add as immediates when possible.
529  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
530  Inst.addOperand(MCOperand::createImm(CE->getValue()));
531  else
532  Inst.addOperand(MCOperand::createExpr(Expr));
533  }
534 
535  void addRegOperands(MCInst &Inst, unsigned N) const {
536  assert(N == 1 && "Invalid number of operands!");
538  }
539 
540  void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
541  assert(N == 1 && "Invalid number of operands!");
542  MCRegister RegNo = getReg();
543  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
544  RegNo = getX86SubSuperRegister(RegNo, 32);
545  Inst.addOperand(MCOperand::createReg(RegNo));
546  }
547 
548  void addGR16orGR32orGR64Operands(MCInst &Inst, unsigned N) const {
549  assert(N == 1 && "Invalid number of operands!");
550  MCRegister RegNo = getReg();
551  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(RegNo) ||
552  X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
553  RegNo = getX86SubSuperRegister(RegNo, 16);
554  Inst.addOperand(MCOperand::createReg(RegNo));
555  }
556 
557  void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
558  assert(N == 1 && "Invalid number of operands!");
559  addExpr(Inst, getImm());
560  }
561 
562  void addImmOperands(MCInst &Inst, unsigned N) const {
563  assert(N == 1 && "Invalid number of operands!");
564  addExpr(Inst, getImm());
565  }
566 
567  void addMaskPairOperands(MCInst &Inst, unsigned N) const {
568  assert(N == 1 && "Invalid number of operands!");
569  unsigned Reg = getReg();
570  switch (Reg) {
571  case X86::K0:
572  case X86::K1:
573  Reg = X86::K0_K1;
574  break;
575  case X86::K2:
576  case X86::K3:
577  Reg = X86::K2_K3;
578  break;
579  case X86::K4:
580  case X86::K5:
581  Reg = X86::K4_K5;
582  break;
583  case X86::K6:
584  case X86::K7:
585  Reg = X86::K6_K7;
586  break;
587  }
589  }
590 
591  void addMemOperands(MCInst &Inst, unsigned N) const {
592  assert((N == 5) && "Invalid number of operands!");
593  if (getMemBaseReg())
595  else
599  addExpr(Inst, getMemDisp());
601  }
602 
603  void addAbsMemOperands(MCInst &Inst, unsigned N) const {
604  assert((N == 1) && "Invalid number of operands!");
605  // Add as immediates when possible.
606  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
607  Inst.addOperand(MCOperand::createImm(CE->getValue()));
608  else
610  }
611 
612  void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
613  assert((N == 2) && "Invalid number of operands!");
616  }
617 
618  void addDstIdxOperands(MCInst &Inst, unsigned N) const {
619  assert((N == 1) && "Invalid number of operands!");
621  }
622 
623  void addMemOffsOperands(MCInst &Inst, unsigned N) const {
624  assert((N == 2) && "Invalid number of operands!");
625  // Add as immediates when possible.
626  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
627  Inst.addOperand(MCOperand::createImm(CE->getValue()));
628  else
631  }
632 
633  static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
634  SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
635  auto Res = std::make_unique<X86Operand>(Token, Loc, EndLoc);
636  Res->Tok.Data = Str.data();
637  Res->Tok.Length = Str.size();
638  return Res;
639  }
640 
641  static std::unique_ptr<X86Operand>
642  CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
643  bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
644  StringRef SymName = StringRef(), void *OpDecl = nullptr) {
645  auto Res = std::make_unique<X86Operand>(Register, StartLoc, EndLoc);
646  Res->Reg.RegNo = RegNo;
647  Res->AddressOf = AddressOf;
648  Res->OffsetOfLoc = OffsetOfLoc;
649  Res->SymName = SymName;
650  Res->OpDecl = OpDecl;
651  return Res;
652  }
653 
654  static std::unique_ptr<X86Operand>
656  return std::make_unique<X86Operand>(DXRegister, StartLoc, EndLoc);
657  }
658 
659  static std::unique_ptr<X86Operand>
660  CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc) {
661  auto Res = std::make_unique<X86Operand>(Prefix, StartLoc, EndLoc);
662  Res->Pref.Prefixes = Prefixes;
663  return Res;
664  }
665 
666  static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
669  void *OpDecl = nullptr,
670  bool GlobalRef = true) {
671  auto Res = std::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
672  Res->Imm.Val = Val;
673  Res->Imm.LocalRef = !GlobalRef;
674  Res->SymName = SymName;
675  Res->OpDecl = OpDecl;
676  Res->AddressOf = true;
677  return Res;
678  }
679 
680  /// Create an absolute memory operand.
681  static std::unique_ptr<X86Operand>
682  CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
683  unsigned Size = 0, StringRef SymName = StringRef(),
684  void *OpDecl = nullptr, unsigned FrontendSize = 0,
685  bool UseUpRegs = false, bool MaybeDirectBranchDest = true) {
686  auto Res = std::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
687  Res->Mem.SegReg = 0;
688  Res->Mem.Disp = Disp;
689  Res->Mem.BaseReg = 0;
690  Res->Mem.DefaultBaseReg = 0;
691  Res->Mem.IndexReg = 0;
692  Res->Mem.Scale = 1;
693  Res->Mem.Size = Size;
694  Res->Mem.ModeSize = ModeSize;
695  Res->Mem.FrontendSize = FrontendSize;
696  Res->Mem.MaybeDirectBranchDest = MaybeDirectBranchDest;
697  Res->UseUpRegs = UseUpRegs;
698  Res->SymName = SymName;
699  Res->OpDecl = OpDecl;
700  Res->AddressOf = false;
701  return Res;
702  }
703 
704  /// Create a generalized memory operand.
705  static std::unique_ptr<X86Operand>
706  CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
707  unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
708  SMLoc EndLoc, unsigned Size = 0,
709  unsigned DefaultBaseReg = X86::NoRegister,
710  StringRef SymName = StringRef(), void *OpDecl = nullptr,
711  unsigned FrontendSize = 0, bool UseUpRegs = false,
712  bool MaybeDirectBranchDest = true) {
713  // We should never just have a displacement, that should be parsed as an
714  // absolute memory operand.
715  assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
716  "Invalid memory operand!");
717 
718  // The scale should always be one of {1,2,4,8}.
719  assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
720  "Invalid scale!");
721  auto Res = std::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
722  Res->Mem.SegReg = SegReg;
723  Res->Mem.Disp = Disp;
724  Res->Mem.BaseReg = BaseReg;
725  Res->Mem.DefaultBaseReg = DefaultBaseReg;
726  Res->Mem.IndexReg = IndexReg;
727  Res->Mem.Scale = Scale;
728  Res->Mem.Size = Size;
729  Res->Mem.ModeSize = ModeSize;
730  Res->Mem.FrontendSize = FrontendSize;
731  Res->Mem.MaybeDirectBranchDest = MaybeDirectBranchDest;
732  Res->UseUpRegs = UseUpRegs;
733  Res->SymName = SymName;
734  Res->OpDecl = OpDecl;
735  Res->AddressOf = false;
736  return Res;
737  }
738 };
739 
740 } // end namespace llvm
741 
742 #endif // LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
llvm::X86Operand::OffsetOfLoc
SMLoc OffsetOfLoc
Definition: X86Operand.h:35
llvm::Check::Size
@ Size
Definition: FileCheck.h:76
llvm::X86Operand::isDstIdx
bool isDstIdx() const
Definition: X86Operand.h:418
llvm::X86Operand::addAVX512RCOperands
void addAVX512RCOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:557
llvm::X86Operand::MemOp::IndexReg
unsigned IndexReg
Definition: X86Operand.h:67
llvm::X86Operand::isSrcIdx
bool isSrcIdx() const
Definition: X86Operand.h:399
llvm::X86Operand::getEndLoc
SMLoc getEndLoc() const override
getEndLoc - Get the location of the last token of this operand.
Definition: X86Operand.h:101
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::X86Operand::CreateMem
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0, bool UseUpRegs=false, bool MaybeDirectBranchDest=true)
Create an absolute memory operand.
Definition: X86Operand.h:682
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::X86Operand::isSrcIdx32
bool isSrcIdx32() const
Definition: X86Operand.h:411
llvm::X86Operand::Mem
struct MemOp Mem
Definition: X86Operand.h:86
llvm::X86Operand::getMemScale
unsigned getMemScale() const
Definition: X86Operand.h:205
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::MCParsedAsmOperand
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Definition: MCParsedAsmOperand.h:24
llvm::X86Operand::isMem128_RC256X
bool isMem128_RC256X() const
Definition: X86Operand.h:365
llvm::X86Operand::isMemIndexReg
bool isMemIndexReg(unsigned LowR, unsigned HighR) const
Definition: X86Operand.h:338
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
StringRef.h
llvm::X86Operand::addImmOperands
void addImmOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:562
llvm::X86Operand::isMem8
bool isMem8() const
Definition: X86Operand.h:309
llvm::X86Operand::isMem256_RC128X
bool isMem256_RC128X() const
Definition: X86Operand.h:368
llvm::isImmUnsignedi4Value
bool isImmUnsignedi4Value(uint64_t Value)
Definition: X86AsmParserCommon.h:38
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::X86Operand::isDXReg
bool isDXReg() const
Definition: X86Operand.h:479
llvm::X86Operand::isAVX512RC
bool isAVX512RC() const
Definition: X86Operand.h:389
MCParsedAsmOperand.h
llvm::X86Operand::isMem256_RC256X
bool isMem256_RC256X() const
Definition: X86Operand.h:371
llvm::isImmSExti32i8Value
bool isImmSExti32i8Value(uint64_t Value)
Definition: X86AsmParserCommon.h:21
llvm::X86Operand::isImmSExti32i8
bool isImmSExti32i8() const
Definition: X86Operand.h:240
llvm::X86Operand::Imm
struct ImmOp Imm
Definition: X86Operand.h:85
llvm::X86Operand::getMemIndexReg
unsigned getMemIndexReg() const
Definition: X86Operand.h:201
llvm::X86Operand::isMemUseUpRegs
bool isMemUseUpRegs() const override
isMemUseUpRegs - Is memory operand use up regs, for example, intel MS inline asm may use ARR[baseReg ...
Definition: X86Operand.h:397
llvm::X86Operand::StartLoc
SMLoc StartLoc
Definition: X86Operand.h:34
llvm::X86Operand::isMem
bool isMem() const override
isMem - Is this a memory operand?
Definition: X86Operand.h:305
llvm::X86Operand::getPrefix
unsigned getPrefix() const
Definition: X86Operand.h:175
llvm::X86Operand::isSrcIdx8
bool isSrcIdx8() const
Definition: X86Operand.h:405
llvm::X86Operand::isMem64
bool isMem64() const
Definition: X86Operand.h:318
STLExtras.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::X86Operand::isMemOffs32_8
bool isMemOffs32_8() const
Definition: X86Operand.h:452
llvm::X86Operand::isReg
bool isReg() const override
isReg - Is this a register operand?
Definition: X86Operand.h:478
llvm::X86Operand::isMem256_RC128
bool isMem256_RC128() const
Definition: X86Operand.h:352
llvm::X86Operand::isImmSExti64i32
bool isImmSExti64i32() const
Definition: X86Operand.h:268
llvm::X86Operand::isMem256_RC512
bool isMem256_RC512() const
Definition: X86Operand.h:374
llvm::X86Operand::CreatePrefix
static std::unique_ptr< X86Operand > CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:660
llvm::X86Operand::RegOp::RegNo
unsigned RegNo
Definition: X86Operand.h:50
llvm::X86Operand::isMem16
bool isMem16() const
Definition: X86Operand.h:312
llvm::X86Operand::isMem32
bool isMem32() const
Definition: X86Operand.h:315
llvm::X86Operand::isMemOffs64_16
bool isMemOffs64_16() const
Definition: X86Operand.h:467
llvm::X86Operand::addMaskPairOperands
void addMaskPairOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:567
llvm::X86Operand::addAbsMemOperands
void addAbsMemOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:603
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::X86Operand::addMemOffsOperands
void addMemOffsOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:623
llvm::X86Operand::isDstIdx16
bool isDstIdx16() const
Definition: X86Operand.h:428
llvm::X86Operand::MemOp::ModeSize
unsigned ModeSize
Definition: X86Operand.h:70
llvm::X86Operand::OpDecl
void * OpDecl
Definition: X86Operand.h:37
MCSymbol.h
llvm::X86Operand::isMem64_RC128X
bool isMem64_RC128X() const
Definition: X86Operand.h:359
llvm::X86Operand::addDstIdxOperands
void addDstIdxOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:618
MCInst.h
false
Definition: StackSlotColoring.cpp:141
llvm::X86Operand::Kind
enum llvm::X86Operand::KindTy Kind
SMLoc.h
llvm::X86Operand::TokOp::Data
const char * Data
Definition: X86Operand.h:45
llvm::isImmSExti64i8Value
bool isImmSExti64i8Value(uint64_t Value)
Definition: X86AsmParserCommon.h:26
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::X86Operand::isImm
bool isImm() const override
isImm - Is this an immediate operand?
Definition: X86Operand.h:224
llvm::X86Operand::SymName
StringRef SymName
Definition: X86Operand.h:36
llvm::X86Operand::UseUpRegs
bool UseUpRegs
This used for inline asm which may specify base reg and index reg for MemOp.
Definition: X86Operand.h:42
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:198
llvm::isImmUnsignedi8Value
bool isImmUnsignedi8Value(uint64_t Value)
Definition: X86AsmParserCommon.h:34
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:81
llvm::X86Operand::isVK1Pair
bool isVK1Pair() const
Definition: X86Operand.h:502
llvm::X86Operand::isDstIdx32
bool isDstIdx32() const
Definition: X86Operand.h:431
llvm::X86Operand::isImmSExti16i8
bool isImmSExti16i8() const
Definition: X86Operand.h:226
llvm::X86Operand::addGR16orGR32orGR64Operands
void addGR16orGR32orGR64Operands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:548
llvm::X86Operand::getLocRange
SMRange getLocRange() const
getLocRange - Get the range between the first and last token of this operand.
Definition: X86Operand.h:105
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::X86Operand::isSrcIdx64
bool isSrcIdx64() const
Definition: X86Operand.h:414
llvm::MCConstantExpr
Definition: MCExpr.h:144
llvm::X86Operand::isGR16orGR32orGR64
bool isGR16orGR32orGR64() const
Definition: X86Operand.h:487
llvm::X86Operand::ImmOp::LocalRef
bool LocalRef
Definition: X86Operand.h:59
llvm::X86Operand::Memory
@ Memory
Definition: X86Operand.h:32
llvm::X86Operand::isMemOffs64_32
bool isMemOffs64_32() const
Definition: X86Operand.h:470
llvm::X86Operand::MemOp::Disp
const MCExpr * Disp
Definition: X86Operand.h:64
llvm::X86Operand::isMem128_RC128
bool isMem128_RC128() const
Definition: X86Operand.h:346
llvm::X86Operand::isVK2Pair
bool isVK2Pair() const
Definition: X86Operand.h:507
llvm::X86Operand::isImmSExti64i8
bool isImmSExti64i8() const
Definition: X86Operand.h:254
llvm::isImmSExti16i8Value
bool isImmSExti16i8Value(uint64_t Value)
Definition: X86AsmParserCommon.h:16
llvm::X86Operand::getOpDecl
void * getOpDecl() override
Definition: X86Operand.h:95
llvm::X86Operand::ImmOp::Val
const MCExpr * Val
Definition: X86Operand.h:58
llvm::X86Operand::TokOp::Length
unsigned Length
Definition: X86Operand.h:46
llvm::X86Operand::getMemDefaultBaseReg
unsigned getMemDefaultBaseReg() const
Definition: X86Operand.h:197
X86MCTargetDesc.h
llvm::X86Operand::getMemDisp
const MCExpr * getMemDisp() const
Definition: X86Operand.h:185
llvm::X86Operand::Pref
struct PrefOp Pref
Definition: X86Operand.h:87
llvm::X86Operand::isMemOffs64_64
bool isMemOffs64_64() const
Definition: X86Operand.h:473
llvm::X86Operand::isAbsMem16
bool isAbsMem16() const
Definition: X86Operand.h:393
llvm::N86::EDI
@ EDI
Definition: X86MCTargetDesc.h:51
llvm::X86Operand::isVectorReg
bool isVectorReg() const
Definition: X86Operand.h:494
llvm::X86Operand
X86Operand - Instances of this class represent a parsed X86 machine instruction.
Definition: X86Operand.h:31
llvm::getX86SubSuperRegister
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:913
llvm::X86Operand::PrefOp::Prefixes
unsigned Prefixes
Definition: X86Operand.h:54
llvm::X86Operand::CreateImm
static std::unique_ptr< X86Operand > CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc, StringRef SymName=StringRef(), void *OpDecl=nullptr, bool GlobalRef=true)
Definition: X86Operand.h:666
llvm::X86Operand::KindTy
KindTy
Definition: X86Operand.h:32
llvm::X86Operand::isDstIdx64
bool isDstIdx64() const
Definition: X86Operand.h:434
MCRegisterInfo.h
llvm::X86Operand::isMemOffs16_16
bool isMemOffs16_16() const
Definition: X86Operand.h:446
llvm::X86Operand::TokOp
Definition: X86Operand.h:44
llvm::X86Operand::addSrcIdxOperands
void addSrcIdxOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:612
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::X86Operand::CreateDXReg
static std::unique_ptr< X86Operand > CreateDXReg(SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:655
llvm::X86Operand::isImmUnsignedi8
bool isImmUnsignedi8() const
Definition: X86Operand.h:292
llvm::X86Operand::isMem128_RC128X
bool isMem128_RC128X() const
Definition: X86Operand.h:362
llvm::X86Operand::isGR32orGR64
bool isGR32orGR64() const
Definition: X86Operand.h:481
llvm::X86Operand::Prefix
@ Prefix
Definition: X86Operand.h:32
llvm::X86Operand::MemOp::Size
unsigned Size
Definition: X86Operand.h:69
llvm::X86IntelInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo)
llvm::X86Operand::getImm
const MCExpr * getImm() const
Definition: X86Operand.h:180
llvm::X86Operand::Tok
struct TokOp Tok
Definition: X86Operand.h:83
llvm::X86Operand::addExpr
void addExpr(MCInst &Inst, const MCExpr *Expr) const
Definition: X86Operand.h:527
llvm::X86Operand::isMaybeDirectBranchDest
bool isMaybeDirectBranchDest() const
Definition: X86Operand.h:217
llvm::X86Operand::isMem512_RC512
bool isMem512_RC512() const
Definition: X86Operand.h:380
llvm::X86Operand::MemOp::Scale
unsigned Scale
Definition: X86Operand.h:68
llvm::N86::ESI
@ ESI
Definition: X86MCTargetDesc.h:51
llvm::sys::Memory
This class provides various memory handling functions that manipulate MemoryBlock instances.
Definition: Memory.h:52
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::X86Operand::addRegOperands
void addRegOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:535
llvm::X86Operand::isVK16Pair
bool isVK16Pair() const
Definition: X86Operand.h:522
X86IntelInstPrinter.h
llvm::X86Operand::isSibMem
bool isSibMem() const
Definition: X86Operand.h:334
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::X86Operand::isMem64_RC128
bool isMem64_RC128() const
Definition: X86Operand.h:343
llvm::X86Operand::getReg
unsigned getReg() const override
Definition: X86Operand.h:170
llvm::X86Operand::isMem256_RC256
bool isMem256_RC256() const
Definition: X86Operand.h:355
llvm::X86Operand::addMemOperands
void addMemOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:591
llvm::X86Operand::Register
@ Register
Definition: X86Operand.h:32
llvm::X86Operand::isMem80
bool isMem80() const
Definition: X86Operand.h:321
llvm::X86Operand::X86Operand
X86Operand(KindTy K, SMLoc Start, SMLoc End)
Definition: X86Operand.h:90
llvm::X86Operand::getStartLoc
SMLoc getStartLoc() const override
getStartLoc - Get the location of the first token of this operand.
Definition: X86Operand.h:98
llvm::X86Operand::CreateMem
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, unsigned DefaultBaseReg=X86::NoRegister, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0, bool UseUpRegs=false, bool MaybeDirectBranchDest=true)
Create a generalized memory operand.
Definition: X86Operand.h:706
llvm::SMLoc::getPointer
const char * getPointer() const
Definition: SMLoc.h:34
llvm::X86Operand::DXRegister
@ DXRegister
Definition: X86Operand.h:32
llvm::X86Operand::getMemModeSize
unsigned getMemModeSize() const
Definition: X86Operand.h:209
llvm::X86Operand::MemOp::MaybeDirectBranchDest
bool MaybeDirectBranchDest
If false, then this operand must be a memory operand for an indirect branch instruction.
Definition: X86Operand.h:79
Casting.h
llvm::X86Operand::isMemOffs64_8
bool isMemOffs64_8() const
Definition: X86Operand.h:464
llvm::X86Operand::isMem128
bool isMem128() const
Definition: X86Operand.h:324
llvm::X86Operand::MemOp::FrontendSize
unsigned FrontendSize
If the memory operand is unsized and there are multiple instruction matches, prefer the one with this...
Definition: X86Operand.h:74
llvm::X86Operand::addGR32orGR64Operands
void addGR32orGR64Operands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:540
llvm::X86Operand::isMem512
bool isMem512() const
Definition: X86Operand.h:330
llvm::X86Operand::isMemOffs16_8
bool isMemOffs16_8() const
Definition: X86Operand.h:443
llvm::X86Operand::isSrcIdx16
bool isSrcIdx16() const
Definition: X86Operand.h:408
llvm::X86Operand::AddressOf
bool AddressOf
Definition: X86Operand.h:38
llvm::X86Operand::CreateToken
static std::unique_ptr< X86Operand > CreateToken(StringRef Str, SMLoc Loc)
Definition: X86Operand.h:633
llvm::X86Operand::getToken
StringRef getToken() const
Definition: X86Operand.h:160
llvm::X86Operand::isDstIdx8
bool isDstIdx8() const
Definition: X86Operand.h:425
llvm::X86Operand::getMemBaseReg
unsigned getMemBaseReg() const
Definition: X86Operand.h:193
llvm::X86Operand::Immediate
@ Immediate
Definition: X86Operand.h:32
llvm::X86Operand::isMem256
bool isMem256() const
Definition: X86Operand.h:327
llvm::X86Operand::MemOp::DefaultBaseReg
unsigned DefaultBaseReg
Definition: X86Operand.h:66
llvm::X86Operand::MemOp::SegReg
unsigned SegReg
Definition: X86Operand.h:63
llvm::X86Operand::getMemFrontendSize
unsigned getMemFrontendSize() const
Definition: X86Operand.h:213
llvm::X86Operand::PrefOp
Definition: X86Operand.h:53
llvm::X86Operand::print
void print(raw_ostream &OS) const override
print - Print a debug representation of the operand to the given stream.
Definition: X86Operand.h:110
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
llvm::X86Operand::MemOp
Definition: X86Operand.h:62
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::X86Operand::EndLoc
SMLoc EndLoc
Definition: X86Operand.h:34
N
#define N
llvm::X86Operand::needAddressOf
bool needAddressOf() const override
needAddressOf - Do we need to emit code to get the address of the variable/label? Only valid when par...
Definition: X86Operand.h:303
llvm::MCExpr::Constant
@ Constant
Constant expressions.
Definition: MCExpr.h:39
llvm::X86Operand::isVK4Pair
bool isVK4Pair() const
Definition: X86Operand.h:512
llvm::X86Operand::CreateReg
static std::unique_ptr< X86Operand > CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, bool AddressOf=false, SMLoc OffsetOfLoc=SMLoc(), StringRef SymName=StringRef(), void *OpDecl=nullptr)
Definition: X86Operand.h:642
llvm::X86Operand::isMemOffs
bool isMemOffs() const
Definition: X86Operand.h:438
llvm::X86Operand::ImmOp
Definition: X86Operand.h:57
llvm::StringRef::data
const LLVM_NODISCARD char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:149
llvm::X86Operand::isMemOffs32_16
bool isMemOffs32_16() const
Definition: X86Operand.h:455
llvm::SMLoc::getFromPointer
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
llvm::X86Operand::isPrefix
bool isPrefix() const
Definition: X86Operand.h:477
llvm::isImmSExti64i32Value
bool isImmSExti64i32Value(uint64_t Value)
Definition: X86AsmParserCommon.h:30
llvm::X86Operand::isMem512_RC256X
bool isMem512_RC256X() const
Definition: X86Operand.h:377
llvm::X86Operand::getSymName
StringRef getSymName() override
Definition: X86Operand.h:94
llvm::X86Operand::MemOp::BaseReg
unsigned BaseReg
Definition: X86Operand.h:65
llvm::X86Operand::isMemUnsized
bool isMemUnsized() const
Definition: X86Operand.h:306
llvm::X86Operand::Token
@ Token
Definition: X86Operand.h:32
llvm::X86Operand::getOffsetOfLoc
SMLoc getOffsetOfLoc() const override
getOffsetOfLoc - Get the location of the offset operator.
Definition: X86Operand.h:108
llvm::X86Operand::isMem128_RC256
bool isMem128_RC256() const
Definition: X86Operand.h:349
llvm::X86Operand::isMemOffs16_32
bool isMemOffs16_32() const
Definition: X86Operand.h:449
MCExpr.h
X86AsmParserCommon.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::X86Operand::getMemSegReg
unsigned getMemSegReg() const
Definition: X86Operand.h:189
llvm::X86Operand::isImmUnsignedi4
bool isImmUnsignedi4() const
Definition: X86Operand.h:283
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::X86Operand::RegOp
Definition: X86Operand.h:49
llvm::X86Operand::Reg
struct RegOp Reg
Definition: X86Operand.h:84
llvm::X86Operand::isMemOffs32_64
bool isMemOffs32_64() const
Definition: X86Operand.h:461
llvm::X86Operand::isMemOffs32_32
bool isMemOffs32_32() const
Definition: X86Operand.h:458
llvm::X86Operand::isToken
bool isToken() const override
isToken - Is this a token operand?
Definition: X86Operand.h:222
llvm::X86Operand::setTokenValue
void setTokenValue(StringRef Value)
Definition: X86Operand.h:164
llvm::X86Operand::isVK8Pair
bool isVK8Pair() const
Definition: X86Operand.h:517
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::X86Operand::isOffsetOfLocal
bool isOffsetOfLocal() const override
isOffsetOfLocal - Do we need to emit code to get the offset of the local variable,...
Definition: X86Operand.h:301
llvm::X86Operand::isAbsMem
bool isAbsMem() const
Definition: X86Operand.h:384