9#ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
10#define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
112 auto PrintImmValue = [&](
const MCExpr *Val,
const char *VName) {
114 if (
auto Imm = cast<MCConstantExpr>(Val)->getValue())
117 if (
auto *SRE = dyn_cast<MCSymbolRefExpr>(Val)) {
119 if (
const char *SymNameStr =
Sym.getName().data())
120 OS << VName << SymNameStr;
136 PrintImmValue(
Imm.
Val,
"Imm:");
153 PrintImmValue(
Mem.
Disp,
",Disp=");
284 if (!
isImm())
return false;
288 if (!CE)
return false;
293 if (!
isImm())
return false;
297 if (!CE)
return true;
437 cast<MCConstantExpr>(
getMemDisp())->getValue() == 0;
457 cast<MCConstantExpr>(
getMemDisp())->getValue() == 0;
517 (X86MCRegisterClasses[X86::GR32RegClassID].contains(
getReg()) ||
518 X86MCRegisterClasses[X86::GR64RegClassID].contains(
getReg()));
523 (X86MCRegisterClasses[X86::GR16RegClassID].contains(
getReg()) ||
524 X86MCRegisterClasses[X86::GR32RegClassID].contains(
getReg()) ||
525 X86MCRegisterClasses[X86::GR64RegClassID].contains(
getReg()));
530 (X86MCRegisterClasses[X86::VR64RegClassID].contains(
getReg()) ||
531 X86MCRegisterClasses[X86::VR128XRegClassID].contains(
getReg()) ||
532 X86MCRegisterClasses[X86::VR256XRegClassID].contains(
getReg()) ||
533 X86MCRegisterClasses[X86::VR512RegClassID].contains(
getReg()));
538 X86MCRegisterClasses[X86::VK1RegClassID].contains(
getReg());
543 X86MCRegisterClasses[X86::VK2RegClassID].contains(
getReg());
548 X86MCRegisterClasses[X86::VK4RegClassID].contains(
getReg());
553 X86MCRegisterClasses[X86::VK8RegClassID].contains(
getReg());
558 X86MCRegisterClasses[X86::VK16RegClassID].contains(
getReg());
570 assert(
N == 1 &&
"Invalid number of operands!");
575 assert(
N == 1 &&
"Invalid number of operands!");
577 if (X86MCRegisterClasses[X86::GR64RegClassID].
contains(RegNo))
583 assert(
N == 1 &&
"Invalid number of operands!");
585 if (X86MCRegisterClasses[X86::GR32RegClassID].
contains(RegNo) ||
586 X86MCRegisterClasses[X86::GR64RegClassID].
contains(RegNo))
592 assert(
N == 1 &&
"Invalid number of operands!");
597 assert(
N == 1 &&
"Invalid number of operands!");
602 assert(
N == 1 &&
"Invalid number of operands!");
626 assert((
N == 5) &&
"Invalid number of operands!");
638 assert((
N == 1) &&
"Invalid number of operands!");
647 assert((
N == 2) &&
"Invalid number of operands!");
653 assert((
N == 1) &&
"Invalid number of operands!");
658 assert((
N == 2) &&
"Invalid number of operands!");
669 auto Res = std::make_unique<X86Operand>(
Token, Loc,
EndLoc);
670 Res->Tok.Data = Str.data();
671 Res->Tok.Length = Str.size();
675 static std::unique_ptr<X86Operand>
680 Res->Reg.RegNo = RegNo;
688 static std::unique_ptr<X86Operand>
693 static std::unique_ptr<X86Operand>
696 Res->Pref.Prefixes = Prefixes;
704 bool GlobalRef =
true) {
707 Res->Imm.LocalRef = !GlobalRef;
710 Res->AddressOf =
true;
715 static std::unique_ptr<X86Operand>
718 void *
OpDecl =
nullptr,
unsigned FrontendSize = 0,
719 bool UseUpRegs =
false,
bool MaybeDirectBranchDest =
true) {
722 Res->Mem.Disp = Disp;
723 Res->Mem.BaseReg = 0;
724 Res->Mem.DefaultBaseReg = 0;
725 Res->Mem.IndexReg = 0;
727 Res->Mem.Size =
Size;
728 Res->Mem.ModeSize = ModeSize;
729 Res->Mem.FrontendSize = FrontendSize;
730 Res->Mem.MaybeDirectBranchDest = MaybeDirectBranchDest;
734 Res->AddressOf =
false;
739 static std::unique_ptr<X86Operand>
741 unsigned BaseReg,
unsigned IndexReg,
unsigned Scale,
SMLoc StartLoc,
743 unsigned DefaultBaseReg = X86::NoRegister,
745 unsigned FrontendSize = 0,
bool UseUpRegs =
false,
746 bool MaybeDirectBranchDest =
true) {
749 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
750 "Invalid memory operand!");
753 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
756 Res->Mem.SegReg = SegReg;
757 Res->Mem.Disp = Disp;
758 Res->Mem.BaseReg = BaseReg;
759 Res->Mem.DefaultBaseReg = DefaultBaseReg;
760 Res->Mem.IndexReg = IndexReg;
761 Res->Mem.Scale = Scale;
762 Res->Mem.Size =
Size;
763 Res->Mem.ModeSize = ModeSize;
764 Res->Mem.FrontendSize = FrontendSize;
765 Res->Mem.MaybeDirectBranchDest = MaybeDirectBranchDest;
769 Res->AddressOf =
false;
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Base class for the full range of assembler expressions which are needed for parsing.
@ Constant
Constant expressions.
@ SymbolRef
References to labels and assigned expressions.
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Wrapper class representing physical registers. Should be passed by value.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Wrapper class representing virtual and physical registers.
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
constexpr const char * getPointer() const
Represents a range in source code.
StringRef - Represent a constant reference to a string, i.e.
LLVM Value Representation.
static const char * getRegisterName(MCRegister Reg)
This class implements an extremely fast bulk output stream that can only output to a stream.
This class provides various memory handling functions that manipulate MemoryBlock instances.
This is an optimization pass for GlobalISel generic memory operations.
bool isImmSExti64i32Value(uint64_t Value)
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
bool isImmUnsignedi4Value(uint64_t Value)
bool isImmSExti64i8Value(uint64_t Value)
bool isImmUnsignedi8Value(uint64_t Value)
bool isImmSExti16i8Value(uint64_t Value)
bool isImmSExti32i8Value(uint64_t Value)
bool MaybeDirectBranchDest
If false, then this operand must be a memory operand for an indirect branch instruction.
unsigned FrontendSize
If the memory operand is unsized and there are multiple instruction matches, prefer the one with this...
X86Operand - Instances of this class represent a parsed X86 machine instruction.
bool isMemOffs64_64() const
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, unsigned DefaultBaseReg=X86::NoRegister, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0, bool UseUpRegs=false, bool MaybeDirectBranchDest=true)
Create a generalized memory operand.
SMLoc getStartLoc() const override
getStartLoc - Get the location of the first token of this operand.
enum llvm::X86Operand::KindTy Kind
void addAVX512RCOperands(MCInst &Inst, unsigned N) const
bool isImm() const override
isImm - Is this an immediate operand?
bool isMemUseUpRegs() const override
isMemUseUpRegs - Is memory operand use up regs, for example, intel MS inline asm may use ARR[baseReg ...
bool isMemOffs64_32() const
static std::unique_ptr< X86Operand > CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc, StringRef SymName=StringRef(), void *OpDecl=nullptr, bool GlobalRef=true)
void addMaskPairOperands(MCInst &Inst, unsigned N) const
void addExpr(MCInst &Inst, const MCExpr *Expr) const
bool isMem256_RC128() const
bool isImmSExti64i32() const
X86Operand(KindTy K, SMLoc Start, SMLoc End)
bool isOffsetOfLocal() const override
isOffsetOfLocal - Do we need to emit code to get the offset of the local variable,...
unsigned getMemDefaultBaseReg() const
void addGR16orGR32orGR64Operands(MCInst &Inst, unsigned N) const
bool isMem512_GR16() const
static std::unique_ptr< X86Operand > CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc)
bool isMemOffs32_32() const
static std::unique_ptr< X86Operand > CreateDXReg(SMLoc StartLoc, SMLoc EndLoc)
bool UseUpRegs
This used for inline asm which may specify base reg and index reg for MemOp.
bool isImmSExti64i8() const
bool isMaybeDirectBranchDest() const
void addAbsMemOperands(MCInst &Inst, unsigned N) const
unsigned getMemSegReg() const
bool isGR32orGR64() const
void addImmOperands(MCInst &Inst, unsigned N) const
void setTokenValue(StringRef Value)
bool isMem512_GR64() const
void addMemOffsOperands(MCInst &Inst, unsigned N) const
bool isImmUnsignedi8() const
void addSrcIdxOperands(MCInst &Inst, unsigned N) const
void * getOpDecl() override
bool isMemOffs32_8() const
bool isMem128_RC256() const
bool isMem256_RC256() const
bool isMemOffs64_8() const
bool isImmSExti16i8() const
void print(raw_ostream &OS) const override
print - Print a debug representation of the operand to the given stream.
SMRange getLocRange() const
getLocRange - Get the range between the first and last token of this operand.
bool isMem256_RC128X() const
unsigned getMemScale() const
SMLoc getEndLoc() const override
getEndLoc - Get the location of the last token of this operand.
bool isReg() const override
isReg - Is this a register operand?
bool isMem() const override
isMem - Is this a memory operand?
bool isImmUnsignedi4() const
const MCExpr * getMemDisp() const
bool isMemOffs16_8() const
unsigned getPrefix() const
bool isMem512_GR32() const
unsigned getReg() const override
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0, bool UseUpRegs=false, bool MaybeDirectBranchDest=true)
Create an absolute memory operand.
bool isImmSExti32i8() const
bool isMem256_RC256X() const
void addGR32orGR64Operands(MCInst &Inst, unsigned N) const
bool isMem128_RC256X() const
bool isMem64_RC128() const
bool isMemIndexReg(unsigned LowR, unsigned HighR) const
bool isMemOffs32_16() const
void addMemOperands(MCInst &Inst, unsigned N) const
void addRegOperands(MCInst &Inst, unsigned N) const
void addDstIdxOperands(MCInst &Inst, unsigned N) const
unsigned getMemModeSize() const
bool isMem128_RC128() const
bool isMemOffs64_16() const
bool needAddressOf() const override
needAddressOf - Do we need to emit code to get the address of the variable/label? Only valid when par...
bool isMem128_RC128X() const
static std::unique_ptr< X86Operand > CreateToken(StringRef Str, SMLoc Loc)
bool isMemUnsized() const
const MCExpr * getImm() const
SMLoc getOffsetOfLoc() const override
getOffsetOfLoc - Get the location of the offset operator.
bool isMem256_RC512() const
bool isMemOffs16_16() const
unsigned getMemBaseReg() const
unsigned getMemIndexReg() const
StringRef getToken() const
unsigned getMemFrontendSize() const
bool isMem512_RC512() const
bool isMemOffs16_32() const
bool isMemOffs32_64() const
bool isMem512_RC256X() const
bool isToken() const override
isToken - Is this a token operand?
bool isMem64_RC128X() const
static std::unique_ptr< X86Operand > CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, bool AddressOf=false, SMLoc OffsetOfLoc=SMLoc(), StringRef SymName=StringRef(), void *OpDecl=nullptr)
StringRef getSymName() override
bool isGR16orGR32orGR64() const