LLVM  14.0.0git
X86BaseInfo.h
Go to the documentation of this file.
1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the X86 target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
17 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18 
19 #include "X86MCTargetDesc.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Support/DataTypes.h"
23 
24 namespace llvm {
25 
26 namespace X86 {
27  // Enums for memory operand decoding. Each memory operand is represented with
28  // a 5 operand sequence in the form:
29  // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
30  // These enums help decode this.
31  enum {
35  AddrDisp = 3,
36 
37  /// AddrSegmentReg - The operand # of the segment in the memory operand.
39 
40  /// AddrNumOperands - Total number of operands in a memory reference.
42  };
43 
44  /// AVX512 static rounding constants. These need to match the values in
45  /// avx512fintrin.h.
50  TO_ZERO = 3,
52  NO_EXC = 8
53  };
54 
55  /// The constants to describe instr prefixes if there are
56  enum IPREFIXES {
58  IP_HAS_OP_SIZE = 1U << 0,
59  IP_HAS_AD_SIZE = 1U << 1,
60  IP_HAS_REPEAT_NE = 1U << 2,
61  IP_HAS_REPEAT = 1U << 3,
62  IP_HAS_LOCK = 1U << 4,
63  IP_HAS_NOTRACK = 1U << 5,
64  IP_USE_VEX = 1U << 6,
65  IP_USE_VEX2 = 1U << 7,
66  IP_USE_VEX3 = 1U << 8,
67  IP_USE_EVEX = 1U << 9,
68  IP_USE_DISP8 = 1U << 10,
69  IP_USE_DISP32 = 1U << 11,
70  };
71 
72  enum OperandType : unsigned {
73  /// AVX512 embedded rounding control. This should only have values 0-3.
76  };
77 
78  // X86 specific condition code. These correspond to X86_*_COND in
79  // X86InstrInfo.td. They must be kept in synch.
80  enum CondCode {
81  COND_O = 0,
82  COND_NO = 1,
83  COND_B = 2,
84  COND_AE = 3,
85  COND_E = 4,
86  COND_NE = 5,
87  COND_BE = 6,
88  COND_A = 7,
89  COND_S = 8,
90  COND_NS = 9,
91  COND_P = 10,
92  COND_NP = 11,
93  COND_L = 12,
94  COND_GE = 13,
95  COND_LE = 14,
96  COND_G = 15,
98 
99  // Artificial condition codes. These are used by analyzeBranch
100  // to indicate a block terminated with two conditional branches that together
101  // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
102  // which can't be represented on x86 with a single condition. These
103  // are never used in MachineInstrs and are inverses of one another.
106 
108  };
109 
110  // The classification for the first instruction in macro fusion.
112  // TEST
113  Test,
114  // CMP
115  Cmp,
116  // AND
117  And,
118  // FIXME: Zen 3 support branch fusion for OR/XOR.
119  // ADD, SUB
120  AddSub,
121  // INC, DEC
122  IncDec,
123  // Not valid as a first macro fusion instruction
124  Invalid
125  };
126 
128  // JA, JB and variants.
129  AB,
130  // JE, JL, JG and variants.
131  ELG,
132  // JS, JP, JO and variants
133  SPO,
134  // Not a fusible jump.
135  Invalid,
136  };
137 
138  /// \returns the type of the first instruction in macro-fusion.
141  switch (Opcode) {
142  default:
144  // TEST
145  case X86::TEST16i16:
146  case X86::TEST16mr:
147  case X86::TEST16ri:
148  case X86::TEST16rr:
149  case X86::TEST32i32:
150  case X86::TEST32mr:
151  case X86::TEST32ri:
152  case X86::TEST32rr:
153  case X86::TEST64i32:
154  case X86::TEST64mr:
155  case X86::TEST64ri32:
156  case X86::TEST64rr:
157  case X86::TEST8i8:
158  case X86::TEST8mr:
159  case X86::TEST8ri:
160  case X86::TEST8rr:
162  case X86::AND16i16:
163  case X86::AND16ri:
164  case X86::AND16ri8:
165  case X86::AND16rm:
166  case X86::AND16rr:
167  case X86::AND16rr_REV:
168  case X86::AND32i32:
169  case X86::AND32ri:
170  case X86::AND32ri8:
171  case X86::AND32rm:
172  case X86::AND32rr:
173  case X86::AND32rr_REV:
174  case X86::AND64i32:
175  case X86::AND64ri32:
176  case X86::AND64ri8:
177  case X86::AND64rm:
178  case X86::AND64rr:
179  case X86::AND64rr_REV:
180  case X86::AND8i8:
181  case X86::AND8ri:
182  case X86::AND8ri8:
183  case X86::AND8rm:
184  case X86::AND8rr:
185  case X86::AND8rr_REV:
187  // FIXME: Zen 3 support branch fusion for OR/XOR.
188  // CMP
189  case X86::CMP16i16:
190  case X86::CMP16mr:
191  case X86::CMP16ri:
192  case X86::CMP16ri8:
193  case X86::CMP16rm:
194  case X86::CMP16rr:
195  case X86::CMP16rr_REV:
196  case X86::CMP32i32:
197  case X86::CMP32mr:
198  case X86::CMP32ri:
199  case X86::CMP32ri8:
200  case X86::CMP32rm:
201  case X86::CMP32rr:
202  case X86::CMP32rr_REV:
203  case X86::CMP64i32:
204  case X86::CMP64mr:
205  case X86::CMP64ri32:
206  case X86::CMP64ri8:
207  case X86::CMP64rm:
208  case X86::CMP64rr:
209  case X86::CMP64rr_REV:
210  case X86::CMP8i8:
211  case X86::CMP8mr:
212  case X86::CMP8ri:
213  case X86::CMP8ri8:
214  case X86::CMP8rm:
215  case X86::CMP8rr:
216  case X86::CMP8rr_REV:
218  // ADD
219  case X86::ADD16i16:
220  case X86::ADD16ri:
221  case X86::ADD16ri8:
222  case X86::ADD16rm:
223  case X86::ADD16rr:
224  case X86::ADD16rr_REV:
225  case X86::ADD32i32:
226  case X86::ADD32ri:
227  case X86::ADD32ri8:
228  case X86::ADD32rm:
229  case X86::ADD32rr:
230  case X86::ADD32rr_REV:
231  case X86::ADD64i32:
232  case X86::ADD64ri32:
233  case X86::ADD64ri8:
234  case X86::ADD64rm:
235  case X86::ADD64rr:
236  case X86::ADD64rr_REV:
237  case X86::ADD8i8:
238  case X86::ADD8ri:
239  case X86::ADD8ri8:
240  case X86::ADD8rm:
241  case X86::ADD8rr:
242  case X86::ADD8rr_REV:
243  // SUB
244  case X86::SUB16i16:
245  case X86::SUB16ri:
246  case X86::SUB16ri8:
247  case X86::SUB16rm:
248  case X86::SUB16rr:
249  case X86::SUB16rr_REV:
250  case X86::SUB32i32:
251  case X86::SUB32ri:
252  case X86::SUB32ri8:
253  case X86::SUB32rm:
254  case X86::SUB32rr:
255  case X86::SUB32rr_REV:
256  case X86::SUB64i32:
257  case X86::SUB64ri32:
258  case X86::SUB64ri8:
259  case X86::SUB64rm:
260  case X86::SUB64rr:
261  case X86::SUB64rr_REV:
262  case X86::SUB8i8:
263  case X86::SUB8ri:
264  case X86::SUB8ri8:
265  case X86::SUB8rm:
266  case X86::SUB8rr:
267  case X86::SUB8rr_REV:
269  // INC
270  case X86::INC16r:
271  case X86::INC16r_alt:
272  case X86::INC32r:
273  case X86::INC32r_alt:
274  case X86::INC64r:
275  case X86::INC8r:
276  // DEC
277  case X86::DEC16r:
278  case X86::DEC16r_alt:
279  case X86::DEC32r:
280  case X86::DEC32r_alt:
281  case X86::DEC64r:
282  case X86::DEC8r:
284  }
285  }
286 
287  /// \returns the type of the second instruction in macro-fusion.
290  if (CC == X86::COND_INVALID)
292 
293  switch (CC) {
294  default:
296  // JE,JZ
297  case X86::COND_E:
298  // JNE,JNZ
299  case X86::COND_NE:
300  // JL,JNGE
301  case X86::COND_L:
302  // JLE,JNG
303  case X86::COND_LE:
304  // JG,JNLE
305  case X86::COND_G:
306  // JGE,JNL
307  case X86::COND_GE:
309  // JB,JC
310  case X86::COND_B:
311  // JNA,JBE
312  case X86::COND_BE:
313  // JA,JNBE
314  case X86::COND_A:
315  // JAE,JNC,JNB
316  case X86::COND_AE:
318  // JS
319  case X86::COND_S:
320  // JNS
321  case X86::COND_NS:
322  // JP,JPE
323  case X86::COND_P:
324  // JNP,JPO
325  case X86::COND_NP:
326  // JO
327  case X86::COND_O:
328  // JNO
329  case X86::COND_NO:
331  }
332  }
333 
334  /// \param FirstKind kind of the first instruction in macro fusion.
335  /// \param SecondKind kind of the second instruction in macro fusion.
336  ///
337  /// \returns true if the two instruction can be macro fused.
338  inline bool isMacroFused(FirstMacroFusionInstKind FirstKind,
339  SecondMacroFusionInstKind SecondKind) {
340  switch (FirstKind) {
343  return true;
346  return SecondKind == X86::SecondMacroFusionInstKind::AB ||
349  return SecondKind == X86::SecondMacroFusionInstKind::ELG;
351  return false;
352  }
353  llvm_unreachable("unknown fusion type");
354  }
355 
356  /// Defines the possible values of the branch boundary alignment mask.
357  enum AlignBranchBoundaryKind : uint8_t {
359  AlignBranchFused = 1U << 0,
360  AlignBranchJcc = 1U << 1,
361  AlignBranchJmp = 1U << 2,
362  AlignBranchCall = 1U << 3,
363  AlignBranchRet = 1U << 4,
365  };
366 
367  /// Defines the encoding values for segment override prefix.
369  CS_Encoding = 0x2E,
370  DS_Encoding = 0x3E,
371  ES_Encoding = 0x26,
372  FS_Encoding = 0x64,
373  GS_Encoding = 0x65,
374  SS_Encoding = 0x36
375  };
376 
377  /// Given a segment register, return the encoding of the segment override
378  /// prefix for it.
381  switch (Reg) {
382  default:
383  llvm_unreachable("Unknown segment register!");
384  case X86::CS:
385  return CS_Encoding;
386  case X86::DS:
387  return DS_Encoding;
388  case X86::ES:
389  return ES_Encoding;
390  case X86::FS:
391  return FS_Encoding;
392  case X86::GS:
393  return GS_Encoding;
394  case X86::SS:
395  return SS_Encoding;
396  }
397  }
398 
399 } // end namespace X86;
400 
401 /// X86II - This namespace holds all of the target specific flags that
402 /// instruction info tracks.
403 ///
404 namespace X86II {
405  /// Target Operand Flag enum.
406  enum TOF {
407  //===------------------------------------------------------------------===//
408  // X86 Specific MachineOperand flags.
409 
411 
412  /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
413  /// relocation of:
414  /// SYMBOL_LABEL + [. - PICBASELABEL]
416 
417  /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
418  /// immediate should get the value of the symbol minus the PIC base label:
419  /// SYMBOL_LABEL - PICBASELABEL
421 
422  /// MO_GOT - On a symbol operand this indicates that the immediate is the
423  /// offset to the GOT entry for the symbol name from the base of the GOT.
424  ///
425  /// See the X86-64 ELF ABI supplement for more details.
426  /// SYMBOL_LABEL @GOT
428 
429  /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
430  /// the offset to the location of the symbol name from the base of the GOT.
431  ///
432  /// See the X86-64 ELF ABI supplement for more details.
433  /// SYMBOL_LABEL @GOTOFF
435 
436  /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
437  /// offset to the GOT entry for the symbol name from the current code
438  /// location.
439  ///
440  /// See the X86-64 ELF ABI supplement for more details.
441  /// SYMBOL_LABEL @GOTPCREL
443 
444  /// MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL
445  /// relocations are guaranteed to be emitted by the integrated assembler
446  /// instead of the relaxable R_X86_64[_REX]_GOTPCRELX relocations.
448 
449  /// MO_PLT - On a symbol operand this indicates that the immediate is
450  /// offset to the PLT entry of symbol name from the current code location.
451  ///
452  /// See the X86-64 ELF ABI supplement for more details.
453  /// SYMBOL_LABEL @PLT
455 
456  /// MO_TLSGD - On a symbol operand this indicates that the immediate is
457  /// the offset of the GOT entry with the TLS index structure that contains
458  /// the module number and variable offset for the symbol. Used in the
459  /// general dynamic TLS access model.
460  ///
461  /// See 'ELF Handling for Thread-Local Storage' for more details.
462  /// SYMBOL_LABEL @TLSGD
464 
465  /// MO_TLSLD - On a symbol operand this indicates that the immediate is
466  /// the offset of the GOT entry with the TLS index for the module that
467  /// contains the symbol. When this index is passed to a call to
468  /// __tls_get_addr, the function will return the base address of the TLS
469  /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
470  ///
471  /// See 'ELF Handling for Thread-Local Storage' for more details.
472  /// SYMBOL_LABEL @TLSLD
474 
475  /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
476  /// the offset of the GOT entry with the TLS index for the module that
477  /// contains the symbol. When this index is passed to a call to
478  /// ___tls_get_addr, the function will return the base address of the TLS
479  /// block for the symbol. Used in the IA32 local dynamic TLS access model.
480  ///
481  /// See 'ELF Handling for Thread-Local Storage' for more details.
482  /// SYMBOL_LABEL @TLSLDM
484 
485  /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
486  /// the offset of the GOT entry with the thread-pointer offset for the
487  /// symbol. Used in the x86-64 initial exec TLS access model.
488  ///
489  /// See 'ELF Handling for Thread-Local Storage' for more details.
490  /// SYMBOL_LABEL @GOTTPOFF
492 
493  /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
494  /// the absolute address of the GOT entry with the negative thread-pointer
495  /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
496  /// model.
497  ///
498  /// See 'ELF Handling for Thread-Local Storage' for more details.
499  /// SYMBOL_LABEL @INDNTPOFF
501 
502  /// MO_TPOFF - On a symbol operand this indicates that the immediate is
503  /// the thread-pointer offset for the symbol. Used in the x86-64 local
504  /// exec TLS access model.
505  ///
506  /// See 'ELF Handling for Thread-Local Storage' for more details.
507  /// SYMBOL_LABEL @TPOFF
509 
510  /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
511  /// the offset of the GOT entry with the TLS offset of the symbol. Used
512  /// in the local dynamic TLS access model.
513  ///
514  /// See 'ELF Handling for Thread-Local Storage' for more details.
515  /// SYMBOL_LABEL @DTPOFF
517 
518  /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
519  /// the negative thread-pointer offset for the symbol. Used in the IA32
520  /// local exec TLS access model.
521  ///
522  /// See 'ELF Handling for Thread-Local Storage' for more details.
523  /// SYMBOL_LABEL @NTPOFF
525 
526  /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
527  /// the offset of the GOT entry with the negative thread-pointer offset for
528  /// the symbol. Used in the PIC IA32 initial exec TLS access model.
529  ///
530  /// See 'ELF Handling for Thread-Local Storage' for more details.
531  /// SYMBOL_LABEL @GOTNTPOFF
533 
534  /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
535  /// reference is actually to the "__imp_FOO" symbol. This is used for
536  /// dllimport linkage on windows.
538 
539  /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
540  /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
541  /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
543 
544  /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
545  /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
546  /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
548 
549  /// MO_TLVP - On a symbol operand this indicates that the immediate is
550  /// some TLS offset.
551  ///
552  /// This is the TLS offset for the Darwin TLS mechanism.
554 
555  /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
556  /// is some TLS offset from the picbase.
557  ///
558  /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
560 
561  /// MO_SECREL - On a symbol operand this indicates that the immediate is
562  /// the offset from beginning of section.
563  ///
564  /// This is the TLS offset for the COFF/Windows TLS mechanism.
566 
567  /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
568  /// to be an absolute symbol in range [0,128), so we can use the @ABS8
569  /// symbol modifier.
571 
572  /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
573  /// reference is actually to the ".refptr.FOO" symbol. This is used for
574  /// stub symbols on windows.
576  };
577 
578  enum : uint64_t {
579  //===------------------------------------------------------------------===//
580  // Instruction encodings. These are the standard/most common forms for X86
581  // instructions.
582  //
583 
584  // PseudoFrm - This represents an instruction that is a pseudo instruction
585  // or one that has not been implemented yet. It is illegal to code generate
586  // it, but tolerated for intermediate implementation stages.
587  Pseudo = 0,
588 
589  /// Raw - This form is for instructions that don't have any operands, so
590  /// they are just a fixed opcode value, like 'leave'.
591  RawFrm = 1,
592 
593  /// AddRegFrm - This form is used for instructions like 'push r32' that have
594  /// their one register operand added to their opcode.
596 
597  /// RawFrmMemOffs - This form is for instructions that store an absolute
598  /// memory offset as an immediate with a possible segment override.
600 
601  /// RawFrmSrc - This form is for instructions that use the source index
602  /// register SI/ESI/RSI with a possible segment override.
604 
605  /// RawFrmDst - This form is for instructions that use the destination index
606  /// register DI/EDI/RDI.
608 
609  /// RawFrmDstSrc - This form is for instructions that use the source index
610  /// register SI/ESI/RSI with a possible segment override, and also the
611  /// destination index register DI/EDI/RDI.
613 
614  /// RawFrmImm8 - This is used for the ENTER instruction, which has two
615  /// immediates, the first of which is a 16-bit immediate (specified by
616  /// the imm encoding) and the second is a 8-bit fixed value.
618 
619  /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
620  /// immediates, the first of which is a 16 or 32-bit immediate (specified by
621  /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
622  /// manual, this operand is described as pntr16:32 and pntr16:16
624 
625  /// AddCCFrm - This form is used for Jcc that encode the condition code
626  /// in the lower 4 bits of the opcode.
627  AddCCFrm = 9,
628 
629  /// PrefixByte - This form is used for instructions that represent a prefix
630  /// byte like data16 or rep.
632 
633  /// MRM[0-7][rm] - These forms are used to represent instructions that use
634  /// a Mod/RM byte, and use the middle field to hold extended opcode
635  /// information. In the intel manual these are represented as /0, /1, ...
636  ///
637 
638  // Instructions operate on a register Reg/Opcode operand not the r/m field.
639  MRMr0 = 21,
640 
641  /// MRMSrcMem - But force to use the SIB field.
643 
644  /// MRMDestMem - But force to use the SIB field.
646 
647  /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
648  /// to specify a destination, which in this case is memory.
649  ///
651 
652  /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
653  /// to specify a source, which in this case is memory.
654  ///
655  MRMSrcMem = 25,
656 
657  /// MRMSrcMem4VOp3 - This form is used for instructions that encode
658  /// operand 3 with VEX.VVVV and load from memory.
659  ///
661 
662  /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
663  /// byte to specify the fourth source, which in this case is memory.
664  ///
666 
667  /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM
668  /// byte to specify the operands and also encodes a condition code.
669  ///
671 
672  /// MRMXm - This form is used for instructions that use the Mod/RM byte
673  /// to specify a memory source, but doesn't use the middle field. And has
674  /// a condition code.
675  ///
676  MRMXmCC = 30,
677 
678  /// MRMXm - This form is used for instructions that use the Mod/RM byte
679  /// to specify a memory source, but doesn't use the middle field.
680  ///
681  MRMXm = 31,
682 
683  // Next, instructions that operate on a memory r/m operand...
684  MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35, // Format /0 /1 /2 /3
685  MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39, // Format /4 /5 /6 /7
686 
687  /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
688  /// to specify a destination, which in this case is a register.
689  ///
691 
692  /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
693  /// to specify a source, which in this case is a register.
694  ///
695  MRMSrcReg = 41,
696 
697  /// MRMSrcReg4VOp3 - This form is used for instructions that encode
698  /// operand 3 with VEX.VVVV and do not load from memory.
699  ///
701 
702  /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
703  /// byte to specify the fourth source, which in this case is a register.
704  ///
706 
707  /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM
708  /// byte to specify the operands and also encodes a condition code
709  ///
711 
712  /// MRMXCCr - This form is used for instructions that use the Mod/RM byte
713  /// to specify a register source, but doesn't use the middle field. And has
714  /// a condition code.
715  ///
716  MRMXrCC = 46,
717 
718  /// MRMXr - This form is used for instructions that use the Mod/RM byte
719  /// to specify a register source, but doesn't use the middle field.
720  ///
721  MRMXr = 47,
722 
723  // Instructions that operate on a register r/m operand...
724  MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, // Format /0 /1 /2 /3
725  MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, // Format /4 /5 /6 /7
726 
727  // Instructions that operate that have mod=11 and an opcode but ignore r/m.
728  MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59, // Format /0 /1 /2 /3
729  MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63, // Format /4 /5 /6 /7
730 
731  /// MRM_XX - A mod/rm byte of exactly 0xXX.
732  MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67,
733  MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71,
734  MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75,
735  MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79,
736  MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83,
737  MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87,
738  MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91,
739  MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95,
740  MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99,
741  MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103,
742  MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107,
743  MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111,
744  MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115,
745  MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119,
746  MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123,
747  MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127,
748 
749  FormMask = 127,
750 
751  //===------------------------------------------------------------------===//
752  // Actual flags...
753 
754  // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
755  // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
756  // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
757  // prefix in 16-bit mode.
760 
764 
765  // AsSize - AdSizeX implies this instruction determines its need of 0x67
766  // prefix from a normal ModRM memory operand. The other types indicate that
767  // an operand is encoded with a specific width and a prefix is needed if
768  // it differs from the current mode.
771 
776 
777  //===------------------------------------------------------------------===//
778  // OpPrefix - There are several prefix bytes that are used as opcode
779  // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
780  // no prefix.
781  //
784 
785  // PD - Prefix code for packed double precision vector floating point
786  // operations performed in the SSE registers.
788 
789  // XS, XD - These prefix codes are for single and double precision scalar
790  // floating point operations performed in the SSE registers.
792 
793  //===------------------------------------------------------------------===//
794  // OpMap - This field determines which opcode map this instruction
795  // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
796  //
799 
800  // OB - OneByte - Set if this instruction has a one byte opcode.
801  OB = 0 << OpMapShift,
802 
803  // TB - TwoByte - Set if this instruction has a two byte opcode, which
804  // starts with a 0x0F byte before the real opcode.
805  TB = 1 << OpMapShift,
806 
807  // T8, TA - Prefix after the 0x0F prefix.
808  T8 = 2 << OpMapShift, TA = 3 << OpMapShift,
809 
810  // XOP8 - Prefix to include use of imm byte.
811  XOP8 = 4 << OpMapShift,
812 
813  // XOP9 - Prefix to exclude use of imm byte.
814  XOP9 = 5 << OpMapShift,
815 
816  // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
817  XOPA = 6 << OpMapShift,
818 
819  /// ThreeDNow - This indicates that the instruction uses the
820  /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
821  /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
822  /// storing a classifier in the imm8 field. To simplify our implementation,
823  /// we handle this by storeing the classifier in the opcode field and using
824  /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
826 
827  // MAP5, MAP6 - Prefix after the 0x0F prefix.
830 
831  //===------------------------------------------------------------------===//
832  // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
833  // They are used to specify GPRs and SSE registers, 64-bit operand size,
834  // etc. We only cares about REX.W and REX.R bits and only the former is
835  // statically determined.
836  //
838  REX_W = 1 << REXShift,
839 
840  //===------------------------------------------------------------------===//
841  // This three-bit field describes the size of an immediate operand. Zero is
842  // unused so that we can tell if we forgot to set a value.
844  ImmMask = 15 << ImmShift,
845  Imm8 = 1 << ImmShift,
848  Imm16 = 4 << ImmShift,
850  Imm32 = 6 << ImmShift,
852  Imm32S = 8 << ImmShift,
853  Imm64 = 9 << ImmShift,
854 
855  //===------------------------------------------------------------------===//
856  // FP Instruction Classification... Zero is non-fp instruction.
857 
858  // FPTypeMask - Mask for all of the FP types...
861 
862  // NotFP - The default, set for instructions that do not use FP registers.
864 
865  // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
867 
868  // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
870 
871  // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
872  // result back to ST(0). For example, fcos, fsqrt, etc.
873  //
875 
876  // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
877  // explicit argument, storing the result to either ST(0) or the implicit
878  // argument. For example: fadd, fsub, fmul, etc...
880 
881  // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
882  // explicit argument, but have no destination. Example: fucom, fucomi, ...
884 
885  // CondMovFP - "2 operand" floating point conditional move instructions.
887 
888  // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
890 
891  // Lock prefix
893  LOCK = 1 << LOCKShift,
894 
895  // REP prefix
897  REP = 1 << REPShift,
898 
899  // Execution domain for SSE instructions.
900  // 0 means normal, non-SSE instruction.
902 
903  // Encoding
906 
907  // VEX - encoding using 0xC4/0xC5
909 
910  /// XOP - Opcode prefix used by XOP instructions.
912 
913  // VEX_EVEX - Specifies that this instruction use EVEX form which provides
914  // syntax support up to 32 512-bit register operands and up to 7 16-bit
915  // mask operands as well as source operand data swizzling/memory operand
916  // conversion, eviction hint, and rounding mode.
918 
919  // Opcode
921 
922  /// VEX_W - Has a opcode specific functionality, but is used in the same
923  /// way as REX_W is for regular SSE instructions.
925  VEX_W = 1ULL << VEX_WShift,
926 
927  /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
928  /// address instructions in SSE are represented as 3 address ones in AVX
929  /// and the additional register is encoded in VEX_VVVV prefix.
931  VEX_4V = 1ULL << VEX_4VShift,
932 
933  /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
934  /// instruction uses 256-bit wide registers. This is usually auto detected
935  /// if a VR256 register is used, but some AVX instructions also have this
936  /// field marked when using a f256 memory references.
938  VEX_L = 1ULL << VEX_LShift,
939 
940  // EVEX_K - Set if this instruction requires masking
942  EVEX_K = 1ULL << EVEX_KShift,
943 
944  // EVEX_Z - Set if this instruction has EVEX.Z field set.
946  EVEX_Z = 1ULL << EVEX_ZShift,
947 
948  // EVEX_L2 - Set if this instruction has EVEX.L' field set.
951 
952  // EVEX_B - Set if this instruction has EVEX.B field set.
954  EVEX_B = 1ULL << EVEX_BShift,
955 
956  // The scaling factor for the AVX512's 8-bit compressed displacement.
959 
960  /// Explicitly specified rounding control
963 
964  // NOTRACK prefix
967 
968  // Force VEX encoding
971  };
972 
973  /// \returns true if the instruction with given opcode is a prefix.
974  inline bool isPrefix(uint64_t TSFlags) {
975  return (TSFlags & X86II::FormMask) == PrefixByte;
976  }
977 
978  /// \returns true if the instruction with given opcode is a pseudo.
979  inline bool isPseudo(uint64_t TSFlags) {
980  return (TSFlags & X86II::FormMask) == Pseudo;
981  }
982 
983  /// \returns the "base" X86 opcode for the specified machine
984  /// instruction.
985  inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) {
986  return TSFlags >> X86II::OpcodeShift;
987  }
988 
989  inline bool hasImm(uint64_t TSFlags) {
990  return (TSFlags & X86II::ImmMask) != 0;
991  }
992 
993  /// Decode the "size of immediate" field from the TSFlags field of the
994  /// specified instruction.
995  inline unsigned getSizeOfImm(uint64_t TSFlags) {
996  switch (TSFlags & X86II::ImmMask) {
997  default: llvm_unreachable("Unknown immediate size");
998  case X86II::Imm8:
999  case X86II::Imm8PCRel:
1000  case X86II::Imm8Reg: return 1;
1001  case X86II::Imm16:
1002  case X86II::Imm16PCRel: return 2;
1003  case X86II::Imm32:
1004  case X86II::Imm32S:
1005  case X86II::Imm32PCRel: return 4;
1006  case X86II::Imm64: return 8;
1007  }
1008  }
1009 
1010  /// \returns true if the immediate of the specified instruction's TSFlags
1011  /// indicates that it is pc relative.
1012  inline bool isImmPCRel(uint64_t TSFlags) {
1013  switch (TSFlags & X86II::ImmMask) {
1014  default: llvm_unreachable("Unknown immediate size");
1015  case X86II::Imm8PCRel:
1016  case X86II::Imm16PCRel:
1017  case X86II::Imm32PCRel:
1018  return true;
1019  case X86II::Imm8:
1020  case X86II::Imm8Reg:
1021  case X86II::Imm16:
1022  case X86II::Imm32:
1023  case X86II::Imm32S:
1024  case X86II::Imm64:
1025  return false;
1026  }
1027  }
1028 
1029  /// \returns true if the immediate of the specified instruction's
1030  /// TSFlags indicates that it is signed.
1031  inline bool isImmSigned(uint64_t TSFlags) {
1032  switch (TSFlags & X86II::ImmMask) {
1033  default: llvm_unreachable("Unknown immediate signedness");
1034  case X86II::Imm32S:
1035  return true;
1036  case X86II::Imm8:
1037  case X86II::Imm8PCRel:
1038  case X86II::Imm8Reg:
1039  case X86II::Imm16:
1040  case X86II::Imm16PCRel:
1041  case X86II::Imm32:
1042  case X86II::Imm32PCRel:
1043  case X86II::Imm64:
1044  return false;
1045  }
1046  }
1047 
1048  /// Compute whether all of the def operands are repeated in the uses and
1049  /// therefore should be skipped.
1050  /// This determines the start of the unique operand list. We need to determine
1051  /// if all of the defs have a corresponding tied operand in the uses.
1052  /// Unfortunately, the tied operand information is encoded in the uses not
1053  /// the defs so we have to use some heuristics to find which operands to
1054  /// query.
1055  inline unsigned getOperandBias(const MCInstrDesc& Desc) {
1056  unsigned NumDefs = Desc.getNumDefs();
1057  unsigned NumOps = Desc.getNumOperands();
1058  switch (NumDefs) {
1059  default: llvm_unreachable("Unexpected number of defs");
1060  case 0:
1061  return 0;
1062  case 1:
1063  // Common two addr case.
1064  if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
1065  return 1;
1066  // Check for AVX-512 scatter which has a TIED_TO in the second to last
1067  // operand.
1068  if (NumOps == 8 &&
1069  Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0)
1070  return 1;
1071  return 0;
1072  case 2:
1073  // XCHG/XADD have two destinations and two sources.
1074  if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
1075  Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
1076  return 2;
1077  // Check for gather. AVX-512 has the second tied operand early. AVX2
1078  // has it as the last op.
1079  if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
1080  (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 ||
1081  Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1))
1082  return 2;
1083  return 0;
1084  }
1085  }
1086 
1087  /// The function returns the MCInst operand # for the first field of the
1088  /// memory operand. If the instruction doesn't have a
1089  /// memory operand, this returns -1.
1090  ///
1091  /// Note that this ignores tied operands. If there is a tied register which
1092  /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
1093  /// counted as one operand.
1094  ///
1095  inline int getMemoryOperandNo(uint64_t TSFlags) {
1096  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1097  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1098 
1099  switch (TSFlags & X86II::FormMask) {
1100  default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
1101  case X86II::Pseudo:
1102  case X86II::RawFrm:
1103  case X86II::AddRegFrm:
1104  case X86II::RawFrmImm8:
1105  case X86II::RawFrmImm16:
1106  case X86II::RawFrmMemOffs:
1107  case X86II::RawFrmSrc:
1108  case X86II::RawFrmDst:
1109  case X86II::RawFrmDstSrc:
1110  case X86II::AddCCFrm:
1111  case X86II::PrefixByte:
1112  return -1;
1113  case X86II::MRMDestMem:
1114  case X86II::MRMDestMemFSIB:
1115  return 0;
1116  case X86II::MRMSrcMem:
1117  case X86II::MRMSrcMemFSIB:
1118  // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1119  // mask register.
1120  return 1 + HasVEX_4V + HasEVEX_K;
1121  case X86II::MRMSrcMem4VOp3:
1122  // Skip registers encoded in reg.
1123  return 1 + HasEVEX_K;
1124  case X86II::MRMSrcMemOp4:
1125  // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
1126  return 3;
1127  case X86II::MRMSrcMemCC:
1128  // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1129  // mask register.
1130  return 1;
1131  case X86II::MRMDestReg:
1132  case X86II::MRMSrcReg:
1133  case X86II::MRMSrcReg4VOp3:
1134  case X86II::MRMSrcRegOp4:
1135  case X86II::MRMSrcRegCC:
1136  case X86II::MRMXrCC:
1137  case X86II::MRMr0:
1138  case X86II::MRMXr:
1139  case X86II::MRM0r: case X86II::MRM1r:
1140  case X86II::MRM2r: case X86II::MRM3r:
1141  case X86II::MRM4r: case X86II::MRM5r:
1142  case X86II::MRM6r: case X86II::MRM7r:
1143  return -1;
1144  case X86II::MRM0X: case X86II::MRM1X:
1145  case X86II::MRM2X: case X86II::MRM3X:
1146  case X86II::MRM4X: case X86II::MRM5X:
1147  case X86II::MRM6X: case X86II::MRM7X:
1148  return -1;
1149  case X86II::MRMXmCC:
1150  case X86II::MRMXm:
1151  case X86II::MRM0m: case X86II::MRM1m:
1152  case X86II::MRM2m: case X86II::MRM3m:
1153  case X86II::MRM4m: case X86II::MRM5m:
1154  case X86II::MRM6m: case X86II::MRM7m:
1155  // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
1156  return 0 + HasVEX_4V + HasEVEX_K;
1157  case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
1158  case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
1159  case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
1160  case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
1161  case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
1162  case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
1163  case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
1164  case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
1165  case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
1166  case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
1167  case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
1168  case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
1169  case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
1170  case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
1171  case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
1172  case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
1173  case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
1174  case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
1175  case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
1176  case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
1177  case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
1178  case X86II::MRM_FF:
1179  return -1;
1180  }
1181  }
1182 
1183  /// \returns true if the MachineOperand is a x86-64 extended (r8 or
1184  /// higher) register, e.g. r8, xmm8, xmm13, etc.
1185  inline bool isX86_64ExtendedReg(unsigned RegNo) {
1186  if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
1187  (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) ||
1188  (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
1189  return true;
1190 
1191  switch (RegNo) {
1192  default: break;
1193  case X86::R8: case X86::R9: case X86::R10: case X86::R11:
1194  case X86::R12: case X86::R13: case X86::R14: case X86::R15:
1195  case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
1196  case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
1197  case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
1198  case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
1199  case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
1200  case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
1201  case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
1202  case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
1203  case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11:
1204  case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15:
1205  return true;
1206  }
1207  return false;
1208  }
1209 
1210  /// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher)
1211  /// registers, e.g. zmm21, etc.
1212  static inline bool is32ExtendedReg(unsigned RegNo) {
1213  return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
1214  (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
1215  (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
1216  }
1217 
1218 
1219  inline bool isX86_64NonExtLowByteReg(unsigned reg) {
1220  return (reg == X86::SPL || reg == X86::BPL ||
1221  reg == X86::SIL || reg == X86::DIL);
1222  }
1223 
1224  /// \returns true if this is a masked instruction.
1225  inline bool isKMasked(uint64_t TSFlags) {
1226  return (TSFlags & X86II::EVEX_K) != 0;
1227  }
1228 
1229  /// \returns true if this is a merge masked instruction.
1230  inline bool isKMergeMasked(uint64_t TSFlags) {
1231  return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
1232  }
1233 }
1234 
1235 } // end namespace llvm;
1236 
1237 #endif
llvm::X86II::MRMSrcReg
@ MRMSrcReg
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition: X86BaseInfo.h:695
llvm::X86II::MRM_DD
@ MRM_DD
Definition: X86BaseInfo.h:739
llvm::X86II::OpPrefixShift
@ OpPrefixShift
Definition: X86BaseInfo.h:782
llvm::X86II::MO_TLVP
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:553
llvm::X86II::MO_DARWIN_NONLAZY
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:542
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
llvm::X86II::MRM_CD
@ MRM_CD
Definition: X86BaseInfo.h:735
llvm::X86II::XD
@ XD
Definition: X86BaseInfo.h:791
llvm::X86II::MRM_FE
@ MRM_FE
Definition: X86BaseInfo.h:747
llvm::X86II::MRM_F8
@ MRM_F8
Definition: X86BaseInfo.h:746
llvm::X86II::MO_GOTTPOFF
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:491
llvm::X86II::MRMSrcMemOp4
@ MRMSrcMemOp4
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:665
llvm::X86::CS_Encoding
@ CS_Encoding
Definition: X86BaseInfo.h:369
llvm::X86II::MRMXm
@ MRMXm
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition: X86BaseInfo.h:681
llvm::X86::FirstMacroFusionInstKind::And
@ And
llvm::X86::GS_Encoding
@ GS_Encoding
Definition: X86BaseInfo.h:373
llvm::X86II::ExplicitVEXPrefix
@ ExplicitVEXPrefix
Definition: X86BaseInfo.h:970
llvm::X86II::Imm8PCRel
@ Imm8PCRel
Definition: X86BaseInfo.h:846
llvm::X86II::MRM_F0
@ MRM_F0
Definition: X86BaseInfo.h:744
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::X86II::getMemoryOperandNo
int getMemoryOperandNo(uint64_t TSFlags)
The function returns the MCInst operand # for the first field of the memory operand.
Definition: X86BaseInfo.h:1095
Reg
unsigned Reg
Definition: MachineSink.cpp:1563
llvm::X86II::Imm32S
@ Imm32S
Definition: X86BaseInfo.h:852
llvm::X86II::AdSize32
@ AdSize32
Definition: X86BaseInfo.h:774
llvm::X86II::MRM3X
@ MRM3X
Definition: X86BaseInfo.h:728
llvm::X86II::isImmPCRel
bool isImmPCRel(uint64_t TSFlags)
Definition: X86BaseInfo.h:1012
llvm::X86II::MRM5r
@ MRM5r
Definition: X86BaseInfo.h:725
llvm::X86II::VEX_4V
@ VEX_4V
Definition: X86BaseInfo.h:931
MCInstrDesc.h
llvm::X86II::MRM_C4
@ MRM_C4
Definition: X86BaseInfo.h:733
llvm::X86II::Pseudo
@ Pseudo
Definition: X86BaseInfo.h:587
llvm::X86II::MRM_CA
@ MRM_CA
Definition: X86BaseInfo.h:734
llvm::X86II::RawFrmImm8
@ RawFrmImm8
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:617
llvm::X86::TO_POS_INF
@ TO_POS_INF
Definition: X86BaseInfo.h:49
llvm::X86II::OpMapMask
@ OpMapMask
Definition: X86BaseInfo.h:798
llvm::X86::IP_HAS_OP_SIZE
@ IP_HAS_OP_SIZE
Definition: X86BaseInfo.h:58
llvm::X86II::MO_INDNTPOFF
@ MO_INDNTPOFF
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:500
llvm::X86II::MRM6X
@ MRM6X
Definition: X86BaseInfo.h:729
llvm::X86II::MRM_E5
@ MRM_E5
Definition: X86BaseInfo.h:741
llvm::X86::FS_Encoding
@ FS_Encoding
Definition: X86BaseInfo.h:372
llvm::X86II::VEX_L
@ VEX_L
Definition: X86BaseInfo.h:938
llvm::X86::COND_BE
@ COND_BE
Definition: X86BaseInfo.h:87
llvm::X86II::MRM_F1
@ MRM_F1
Definition: X86BaseInfo.h:744
llvm::X86II::MRM_D7
@ MRM_D7
Definition: X86BaseInfo.h:737
llvm::X86II::SSEDomainShift
@ SSEDomainShift
Definition: X86BaseInfo.h:901
llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
Definition: X86BaseInfo.h:415
llvm::X86II::MO_TLSGD
@ MO_TLSGD
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:463
ErrorHandling.h
llvm::X86::SecondMacroFusionInstKind::AB
@ AB
llvm::X86::COND_P
@ COND_P
Definition: X86BaseInfo.h:91
llvm::X86II::MO_TLSLDM
@ MO_TLSLDM
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:483
llvm::X86::COND_GE
@ COND_GE
Definition: X86BaseInfo.h:94
llvm::X86::AlignBranchRet
@ AlignBranchRet
Definition: X86BaseInfo.h:363
llvm::X86II::MRM_C2
@ MRM_C2
Definition: X86BaseInfo.h:732
llvm::X86II::MRMSrcMemCC
@ MRMSrcMemCC
MRMSrcMemCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition: X86BaseInfo.h:670
llvm::X86II::MRM1X
@ MRM1X
Definition: X86BaseInfo.h:728
llvm::X86II::CD8_Scale_Shift
@ CD8_Scale_Shift
Definition: X86BaseInfo.h:957
llvm::X86II::EVEX
@ EVEX
Definition: X86BaseInfo.h:917
llvm::X86II::MRM0r
@ MRM0r
Definition: X86BaseInfo.h:724
llvm::X86II::FPTypeShift
@ FPTypeShift
Definition: X86BaseInfo.h:859
llvm::X86II::EVEX_L2Shift
@ EVEX_L2Shift
Definition: X86BaseInfo.h:949
llvm::X86II::MRM2X
@ MRM2X
Definition: X86BaseInfo.h:728
llvm::X86II::ExplicitVEXShift
@ ExplicitVEXShift
Definition: X86BaseInfo.h:969
llvm::X86II::RawFrmSrc
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:603
llvm::X86::COND_L
@ COND_L
Definition: X86BaseInfo.h:93
llvm::X86::IP_HAS_LOCK
@ IP_HAS_LOCK
Definition: X86BaseInfo.h:62
llvm::X86II::VEX_LShift
@ VEX_LShift
VEX_L - Stands for a bit in the VEX opcode prefix meaning the current instruction uses 256-bit wide r...
Definition: X86BaseInfo.h:937
llvm::X86II::MRM6m
@ MRM6m
Definition: X86BaseInfo.h:685
llvm::X86II::RawFrm
@ RawFrm
Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:591
llvm::X86II::getBaseOpcodeFor
uint8_t getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:985
llvm::X86::IP_USE_DISP8
@ IP_USE_DISP8
Definition: X86BaseInfo.h:68
llvm::X86::AlignBranchFused
@ AlignBranchFused
Definition: X86BaseInfo.h:359
llvm::X86II::MO_SECREL
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:565
llvm::X86II::OneArgFP
@ OneArgFP
Definition: X86BaseInfo.h:869
llvm::X86II::MO_TPOFF
@ MO_TPOFF
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:508
llvm::X86II::MRM_DA
@ MRM_DA
Definition: X86BaseInfo.h:738
llvm::X86II::RawFrmImm16
@ RawFrmImm16
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:623
llvm::X86II::MRM7m
@ MRM7m
Definition: X86BaseInfo.h:685
llvm::X86II::T_MAP6
@ T_MAP6
Definition: X86BaseInfo.h:829
llvm::X86II::MRM_D6
@ MRM_D6
Definition: X86BaseInfo.h:737
llvm::X86::ES_Encoding
@ ES_Encoding
Definition: X86BaseInfo.h:371
llvm::X86II::XOP
@ XOP
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:911
llvm::X86II::MRM_F4
@ MRM_F4
Definition: X86BaseInfo.h:745
llvm::X86::CondCode
CondCode
Definition: X86BaseInfo.h:80
llvm::X86II::MRM_C0
@ MRM_C0
MRM_XX - A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:732
llvm::X86::AddrNumOperands
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
llvm::X86::COND_INVALID
@ COND_INVALID
Definition: X86BaseInfo.h:107
llvm::X86II::MRM4X
@ MRM4X
Definition: X86BaseInfo.h:729
llvm::X86::AddrIndexReg
@ AddrIndexReg
Definition: X86BaseInfo.h:34
llvm::X86II::MRM_CE
@ MRM_CE
Definition: X86BaseInfo.h:735
llvm::X86II::MO_GOTOFF
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:434
llvm::X86II::MRM1m
@ MRM1m
Definition: X86BaseInfo.h:684
llvm::X86::COND_S
@ COND_S
Definition: X86BaseInfo.h:89
llvm::X86II::MRM_C8
@ MRM_C8
Definition: X86BaseInfo.h:734
llvm::X86II::AdSizeShift
@ AdSizeShift
Definition: X86BaseInfo.h:769
llvm::X86II::MRM0X
@ MRM0X
Definition: X86BaseInfo.h:728
llvm::X86II::MRM_D5
@ MRM_D5
Definition: X86BaseInfo.h:737
llvm::X86II::MRM_E2
@ MRM_E2
Definition: X86BaseInfo.h:740
llvm::X86::IP_HAS_NOTRACK
@ IP_HAS_NOTRACK
Definition: X86BaseInfo.h:63
llvm::X86II::MRM_C9
@ MRM_C9
Definition: X86BaseInfo.h:734
llvm::X86II::MRM4r
@ MRM4r
Definition: X86BaseInfo.h:725
llvm::X86II::MRMSrcReg4VOp3
@ MRMSrcReg4VOp3
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition: X86BaseInfo.h:700
llvm::X86::COND_O
@ COND_O
Definition: X86BaseInfo.h:81
llvm::X86II::LOCKShift
@ LOCKShift
Definition: X86BaseInfo.h:892
llvm::X86II::MO_GOT
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:427
llvm::X86II::OpPrefixMask
@ OpPrefixMask
Definition: X86BaseInfo.h:783
llvm::X86::FirstMacroFusionInstKind::Test
@ Test
llvm::X86II::MRM_C3
@ MRM_C3
Definition: X86BaseInfo.h:732
llvm::X86II::MRM_F3
@ MRM_F3
Definition: X86BaseInfo.h:744
llvm::X86::COND_NE_OR_P
@ COND_NE_OR_P
Definition: X86BaseInfo.h:104
llvm::X86II::MRM2r
@ MRM2r
Definition: X86BaseInfo.h:724
llvm::X86II::RawFrmMemOffs
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:599
llvm::X86II::MRM2m
@ MRM2m
Definition: X86BaseInfo.h:684
llvm::X86II::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: X86BaseInfo.h:575
llvm::X86II::TwoArgFP
@ TwoArgFP
Definition: X86BaseInfo.h:879
llvm::X86II::MRM_E0
@ MRM_E0
Definition: X86BaseInfo.h:740
llvm::X86II::hasImm
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:989
llvm::X86II::MO_PLT
@ MO_PLT
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:454
llvm::X86::IP_HAS_AD_SIZE
@ IP_HAS_AD_SIZE
Definition: X86BaseInfo.h:59
llvm::X86::AddrScaleAmt
@ AddrScaleAmt
Definition: X86BaseInfo.h:33
llvm::X86II::MRM_DB
@ MRM_DB
Definition: X86BaseInfo.h:738
llvm::X86II::OB
@ OB
Definition: X86BaseInfo.h:801
llvm::X86II::MRM_FB
@ MRM_FB
Definition: X86BaseInfo.h:746
llvm::X86::AddrSegmentReg
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
llvm::X86::IP_USE_EVEX
@ IP_USE_EVEX
Definition: X86BaseInfo.h:67
llvm::X86::AlignBranchCall
@ AlignBranchCall
Definition: X86BaseInfo.h:362
llvm::X86II::MO_GOTPCREL
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:442
llvm::X86::FirstMacroFusionInstKind::AddSub
@ AddSub
llvm::X86II::CondMovFP
@ CondMovFP
Definition: X86BaseInfo.h:886
llvm::X86II::MRMDestReg
@ MRMDestReg
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition: X86BaseInfo.h:690
llvm::X86II::OpSizeMask
@ OpSizeMask
Definition: X86BaseInfo.h:759
llvm::X86::AlignBranchJcc
@ AlignBranchJcc
Definition: X86BaseInfo.h:360
llvm::X86II::MRMXrCC
@ MRMXrCC
MRMXCCr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition: X86BaseInfo.h:716
llvm::X86II::isX86_64ExtendedReg
bool isX86_64ExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1185
llvm::X86II::MRM1r
@ MRM1r
Definition: X86BaseInfo.h:724
llvm::X86II::NotFP
@ NotFP
Definition: X86BaseInfo.h:863
llvm::X86II::ImmMask
@ ImmMask
Definition: X86BaseInfo.h:844
llvm::X86II::MRM_E4
@ MRM_E4
Definition: X86BaseInfo.h:741
llvm::X86II::OpcodeShift
@ OpcodeShift
Definition: X86BaseInfo.h:920
llvm::X86II::CompareFP
@ CompareFP
Definition: X86BaseInfo.h:883
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::X86II::VEX
@ VEX
Definition: X86BaseInfo.h:908
llvm::X86II::MO_NO_FLAG
@ MO_NO_FLAG
Definition: X86BaseInfo.h:410
llvm::X86::COND_A
@ COND_A
Definition: X86BaseInfo.h:88
llvm::X86II::MO_GOTPCREL_NORELAX
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
Definition: X86BaseInfo.h:447
llvm::X86II::FPTypeMask
@ FPTypeMask
Definition: X86BaseInfo.h:860
llvm::X86II::MRMSrcMem
@ MRMSrcMem
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition: X86BaseInfo.h:655
llvm::X86II::MRM_F9
@ MRM_F9
Definition: X86BaseInfo.h:746
llvm::X86::TO_NEG_INF
@ TO_NEG_INF
Definition: X86BaseInfo.h:48
llvm::X86II::T_MAP5
@ T_MAP5
Definition: X86BaseInfo.h:828
llvm::X86II::MRM7r
@ MRM7r
Definition: X86BaseInfo.h:725
llvm::X86II::MO_TLVP_PIC_BASE
@ MO_TLVP_PIC_BASE
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:559
llvm::X86II::MRMXr
@ MRMXr
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition: X86BaseInfo.h:721
llvm::X86::AlignBranchIndirect
@ AlignBranchIndirect
Definition: X86BaseInfo.h:364
llvm::X86::classifyFirstOpcodeInMacroFusion
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
Definition: X86BaseInfo.h:140
llvm::X86II::MRM_CC
@ MRM_CC
Definition: X86BaseInfo.h:735
llvm::X86::SecondMacroFusionInstKind::SPO
@ SPO
llvm::X86II::OpMapShift
@ OpMapShift
Definition: X86BaseInfo.h:797
llvm::X86II::MRM_C1
@ MRM_C1
Definition: X86BaseInfo.h:732
llvm::X86II::MRM_E8
@ MRM_E8
Definition: X86BaseInfo.h:742
llvm::X86::IP_USE_DISP32
@ IP_USE_DISP32
Definition: X86BaseInfo.h:69
llvm::X86II::MRMSrcMemFSIB
@ MRMSrcMemFSIB
MRMSrcMem - But force to use the SIB field.
Definition: X86BaseInfo.h:642
llvm::X86II::XS
@ XS
Definition: X86BaseInfo.h:791
llvm::X86II::MRM_E7
@ MRM_E7
Definition: X86BaseInfo.h:741
llvm::X86II::MRM_FA
@ MRM_FA
Definition: X86BaseInfo.h:746
llvm::X86II::SpecialFP
@ SpecialFP
Definition: X86BaseInfo.h:889
llvm::X86II::MRM_ED
@ MRM_ED
Definition: X86BaseInfo.h:743
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::X86II::MRM_D3
@ MRM_D3
Definition: X86BaseInfo.h:736
llvm::X86II::MRM_F6
@ MRM_F6
Definition: X86BaseInfo.h:745
llvm::X86II::MRM3r
@ MRM3r
Definition: X86BaseInfo.h:724
llvm::X86II::MRM_EB
@ MRM_EB
Definition: X86BaseInfo.h:742
llvm::X86II::EncodingShift
@ EncodingShift
Definition: X86BaseInfo.h:904
llvm::X86II::MRM_EC
@ MRM_EC
Definition: X86BaseInfo.h:743
llvm::X86II::REXShift
@ REXShift
Definition: X86BaseInfo.h:837
llvm::X86II::isImmSigned
bool isImmSigned(uint64_t TSFlags)
Definition: X86BaseInfo.h:1031
llvm::X86II::OpSizeFixed
@ OpSizeFixed
Definition: X86BaseInfo.h:761
llvm::X86II::AdSizeX
@ AdSizeX
Definition: X86BaseInfo.h:772
llvm::X86::COND_NO
@ COND_NO
Definition: X86BaseInfo.h:82
llvm::X86II::EVEX_L2
@ EVEX_L2
Definition: X86BaseInfo.h:950
llvm::X86II::MRMDestMem
@ MRMDestMem
MRMDestMem - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition: X86BaseInfo.h:650
llvm::X86II::MRM_CF
@ MRM_CF
Definition: X86BaseInfo.h:735
llvm::X86II::MRMSrcRegCC
@ MRMSrcRegCC
MRMSrcRegCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition: X86BaseInfo.h:710
llvm::X86::FirstMacroFusionInstKind::IncDec
@ IncDec
llvm::X86II::MO_DARWIN_NONLAZY_PIC_BASE
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:547
llvm::X86II::MRM_D8
@ MRM_D8
Definition: X86BaseInfo.h:738
llvm::X86II::getOperandBias
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
Definition: X86BaseInfo.h:1055
llvm::X86II::VEX_W
@ VEX_W
Definition: X86BaseInfo.h:925
X86MCTargetDesc.h
llvm::X86::COND_AE
@ COND_AE
Definition: X86BaseInfo.h:84
llvm::X86II::AddRegFrm
@ AddRegFrm
AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand a...
Definition: X86BaseInfo.h:595
llvm::X86::IP_HAS_REPEAT
@ IP_HAS_REPEAT
Definition: X86BaseInfo.h:61
llvm::X86II::MRM_E9
@ MRM_E9
Definition: X86BaseInfo.h:742
uint64_t
llvm::X86::IPREFIXES
IPREFIXES
The constants to describe instr prefixes if there are.
Definition: X86BaseInfo.h:56
llvm::X86II::EVEX_RCShift
@ EVEX_RCShift
Explicitly specified rounding control.
Definition: X86BaseInfo.h:961
llvm::X86II::MO_GOTNTPOFF
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:532
llvm::X86II::MO_PIC_BASE_OFFSET
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:420
llvm::X86II::MRM3m
@ MRM3m
Definition: X86BaseInfo.h:684
llvm::X86II::MRM_CB
@ MRM_CB
Definition: X86BaseInfo.h:734
llvm::X86II::Imm8Reg
@ Imm8Reg
Definition: X86BaseInfo.h:847
llvm::X86II::MRM_D0
@ MRM_D0
Definition: X86BaseInfo.h:736
llvm::X86::AddrBaseReg
@ AddrBaseReg
Definition: X86BaseInfo.h:32
llvm::X86II::OpSize32
@ OpSize32
Definition: X86BaseInfo.h:763
llvm::X86II::MRM_F7
@ MRM_F7
Definition: X86BaseInfo.h:745
llvm::X86II::MRM_E3
@ MRM_E3
Definition: X86BaseInfo.h:740
llvm::X86II::MO_DTPOFF
@ MO_DTPOFF
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:516
llvm::X86II::MRM6r
@ MRM6r
Definition: X86BaseInfo.h:725
llvm::X86::IP_NO_PREFIX
@ IP_NO_PREFIX
Definition: X86BaseInfo.h:57
llvm::X86II::EVEX_ZShift
@ EVEX_ZShift
Definition: X86BaseInfo.h:945
llvm::X86II::MRM_D1
@ MRM_D1
Definition: X86BaseInfo.h:736
llvm::X86II::AdSizeMask
@ AdSizeMask
Definition: X86BaseInfo.h:770
llvm::X86II::MRM_FF
@ MRM_FF
Definition: X86BaseInfo.h:747
llvm::X86II::ThreeDNow
@ ThreeDNow
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow!...
Definition: X86BaseInfo.h:825
llvm::X86II::LOCK
@ LOCK
Definition: X86BaseInfo.h:893
llvm::X86II::OpSizeShift
@ OpSizeShift
Definition: X86BaseInfo.h:758
llvm::X86::COND_B
@ COND_B
Definition: X86BaseInfo.h:83
llvm::X86::OPERAND_COND_CODE
@ OPERAND_COND_CODE
Definition: X86BaseInfo.h:75
llvm::X86::IP_USE_VEX3
@ IP_USE_VEX3
Definition: X86BaseInfo.h:66
llvm::X86::COND_NS
@ COND_NS
Definition: X86BaseInfo.h:90
llvm::X86II::MRM_EF
@ MRM_EF
Definition: X86BaseInfo.h:743
llvm::X86II::NOTRACK
@ NOTRACK
Definition: X86BaseInfo.h:966
llvm::X86::COND_G
@ COND_G
Definition: X86BaseInfo.h:96
llvm::X86II::PD
@ PD
Definition: X86BaseInfo.h:787
llvm::X86AS::GS
@ GS
Definition: X86.h:187
llvm::X86::COND_LE
@ COND_LE
Definition: X86BaseInfo.h:95
llvm::X86::IP_USE_VEX
@ IP_USE_VEX
Definition: X86BaseInfo.h:64
llvm::X86II::EncodingMask
@ EncodingMask
Definition: X86BaseInfo.h:905
llvm::X86II::EVEX_K
@ EVEX_K
Definition: X86BaseInfo.h:942
llvm::X86II::MRM_E6
@ MRM_E6
Definition: X86BaseInfo.h:741
llvm::X86II::NoTrackShift
@ NoTrackShift
Definition: X86BaseInfo.h:965
llvm::X86::STATIC_ROUNDING
STATIC_ROUNDING
AVX512 static rounding constants.
Definition: X86BaseInfo.h:46
llvm::X86II::MRM_DF
@ MRM_DF
Definition: X86BaseInfo.h:739
llvm::X86II::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:537
llvm::X86II::PrefixByte
@ PrefixByte
PrefixByte - This form is used for instructions that represent a prefix byte like data16 or rep.
Definition: X86BaseInfo.h:631
llvm::X86II::MRM_EA
@ MRM_EA
Definition: X86BaseInfo.h:742
llvm::X86II::isPrefix
bool isPrefix(uint64_t TSFlags)
Definition: X86BaseInfo.h:974
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::X86::classifySecondCondCodeInMacroFusion
SecondMacroFusionInstKind classifySecondCondCodeInMacroFusion(X86::CondCode CC)
Definition: X86BaseInfo.h:289
llvm::X86II::TA
@ TA
Definition: X86BaseInfo.h:808
llvm::X86::AlignBranchBoundaryKind
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
Definition: X86BaseInfo.h:357
llvm::X86II::OneArgFPRW
@ OneArgFPRW
Definition: X86BaseInfo.h:874
llvm::X86II::MRM_C7
@ MRM_C7
Definition: X86BaseInfo.h:733
llvm::X86II::VEX_4VShift
@ VEX_4VShift
VEX_4V - Used to specify an additional AVX/SSE register.
Definition: X86BaseInfo.h:930
llvm::X86II::Imm64
@ Imm64
Definition: X86BaseInfo.h:853
llvm::X86::NO_EXC
@ NO_EXC
Definition: X86BaseInfo.h:52
llvm::X86::COND_E_AND_NP
@ COND_E_AND_NP
Definition: X86BaseInfo.h:105
llvm::X86II::is32ExtendedReg
static bool is32ExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1212
llvm::X86II::Imm8
@ Imm8
Definition: X86BaseInfo.h:845
llvm::X86::IP_USE_VEX2
@ IP_USE_VEX2
Definition: X86BaseInfo.h:65
llvm::X86::SecondMacroFusionInstKind::Invalid
@ Invalid
llvm::X86::OperandType
OperandType
Definition: X86BaseInfo.h:72
llvm::X86II::isPseudo
bool isPseudo(uint64_t TSFlags)
Definition: X86BaseInfo.h:979
llvm::X86::isMacroFused
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
Definition: X86BaseInfo.h:338
llvm::X86II::MRM_F2
@ MRM_F2
Definition: X86BaseInfo.h:744
llvm::X86II::MRM_FD
@ MRM_FD
Definition: X86BaseInfo.h:747
llvm::X86II::TB
@ TB
Definition: X86BaseInfo.h:805
llvm::X86II::OpSize16
@ OpSize16
Definition: X86BaseInfo.h:762
llvm::X86II::getSizeOfImm
unsigned getSizeOfImm(uint64_t TSFlags)
Decode the "size of immediate" field from the TSFlags field of the specified instruction.
Definition: X86BaseInfo.h:995
llvm::X86II::MRM_D9
@ MRM_D9
Definition: X86BaseInfo.h:738
llvm::X86II::MRM_DE
@ MRM_DE
Definition: X86BaseInfo.h:739
llvm::X86II::MRM_C5
@ MRM_C5
Definition: X86BaseInfo.h:733
llvm::X86II::ImmShift
@ ImmShift
Definition: X86BaseInfo.h:843
llvm::X86II::TOF
TOF
Target Operand Flag enum.
Definition: X86BaseInfo.h:406
llvm::X86II::AdSize64
@ AdSize64
Definition: X86BaseInfo.h:775
llvm::X86::DS_Encoding
@ DS_Encoding
Definition: X86BaseInfo.h:370
llvm::X86II::AddCCFrm
@ AddCCFrm
AddCCFrm - This form is used for Jcc that encode the condition code in the lower 4 bits of the opcode...
Definition: X86BaseInfo.h:627
llvm::X86::TO_ZERO
@ TO_ZERO
Definition: X86BaseInfo.h:50
llvm::X86II::MRM_D4
@ MRM_D4
Definition: X86BaseInfo.h:737
llvm::X86::FirstMacroFusionInstKind::Cmp
@ Cmp
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:60
llvm::X86II::EVEX_B
@ EVEX_B
Definition: X86BaseInfo.h:954
llvm::X86::AlignBranchJmp
@ AlignBranchJmp
Definition: X86BaseInfo.h:361
llvm::X86II::isKMasked
bool isKMasked(uint64_t TSFlags)
Definition: X86BaseInfo.h:1225
llvm::X86II::MO_TLSLD
@ MO_TLSLD
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:473
llvm::X86::IP_HAS_REPEAT_NE
@ IP_HAS_REPEAT_NE
Definition: X86BaseInfo.h:60
llvm::X86II::XOP9
@ XOP9
Definition: X86BaseInfo.h:814
llvm::X86II::Imm32
@ Imm32
Definition: X86BaseInfo.h:850
llvm::X86::SS_Encoding
@ SS_Encoding
Definition: X86BaseInfo.h:374
llvm::X86II::RawFrmDst
@ RawFrmDst
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI.
Definition: X86BaseInfo.h:607
llvm::X86II::EVEX_KShift
@ EVEX_KShift
Definition: X86BaseInfo.h:941
llvm::X86::SecondMacroFusionInstKind
SecondMacroFusionInstKind
Definition: X86BaseInfo.h:127
llvm::X86II::MRMXmCC
@ MRMXmCC
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition: X86BaseInfo.h:676
llvm::X86::getSegmentOverridePrefixForReg
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
Definition: X86BaseInfo.h:380
llvm::X86II::Imm16PCRel
@ Imm16PCRel
Definition: X86BaseInfo.h:849
llvm::X86II::MRM_C6
@ MRM_C6
Definition: X86BaseInfo.h:733
llvm::X86II::REX_W
@ REX_W
Definition: X86BaseInfo.h:838
llvm::X86II::MRM_FC
@ MRM_FC
Definition: X86BaseInfo.h:747
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:76
llvm::X86II::Imm32PCRel
@ Imm32PCRel
Definition: X86BaseInfo.h:851
llvm::X86::EncodingOfSegmentOverridePrefix
EncodingOfSegmentOverridePrefix
Defines the encoding values for segment override prefix.
Definition: X86BaseInfo.h:368
llvm::X86::CUR_DIRECTION
@ CUR_DIRECTION
Definition: X86BaseInfo.h:51
llvm::X86II::MRM5m
@ MRM5m
Definition: X86BaseInfo.h:685
llvm::X86II::EVEX_BShift
@ EVEX_BShift
Definition: X86BaseInfo.h:953
llvm::X86II::isKMergeMasked
bool isKMergeMasked(uint64_t TSFlags)
Definition: X86BaseInfo.h:1230
llvm::X86::FirstMacroFusionInstKind::Invalid
@ Invalid
llvm::X86II::MRM0m
@ MRM0m
Definition: X86BaseInfo.h:684
llvm::X86II::MRM_DC
@ MRM_DC
Definition: X86BaseInfo.h:739
llvm::X86II::ZeroArgFP
@ ZeroArgFP
Definition: X86BaseInfo.h:866
llvm::X86II::MRM_F5
@ MRM_F5
Definition: X86BaseInfo.h:745
llvm::X86::SecondMacroFusionInstKind::ELG
@ ELG
llvm::X86II::MRM7X
@ MRM7X
Definition: X86BaseInfo.h:729
llvm::X86II::CD8_Scale_Mask
@ CD8_Scale_Mask
Definition: X86BaseInfo.h:958
llvm::X86II::MRMr0
@ MRMr0
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte,...
Definition: X86BaseInfo.h:639
llvm::X86II::MRMSrcMem4VOp3
@ MRMSrcMem4VOp3
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition: X86BaseInfo.h:660
llvm::X86::AddrDisp
@ AddrDisp
Definition: X86BaseInfo.h:35
llvm::X86::TO_NEAREST_INT
@ TO_NEAREST_INT
Definition: X86BaseInfo.h:47
llvm::X86::AlignBranchNone
@ AlignBranchNone
Definition: X86BaseInfo.h:358
llvm::X86II::FormMask
@ FormMask
Definition: X86BaseInfo.h:749
llvm::X86II::isX86_64NonExtLowByteReg
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:1219
llvm::X86::FirstMacroFusionInstKind
FirstMacroFusionInstKind
Definition: X86BaseInfo.h:111
llvm::X86II::Imm16
@ Imm16
Definition: X86BaseInfo.h:848
llvm::X86II::MRM4m
@ MRM4m
Definition: X86BaseInfo.h:685
llvm::X86II::EVEX_Z
@ EVEX_Z
Definition: X86BaseInfo.h:946
DataTypes.h
llvm::X86II::AdSize16
@ AdSize16
Definition: X86BaseInfo.h:773
llvm::X86II::MRMDestMemFSIB
@ MRMDestMemFSIB
MRMDestMem - But force to use the SIB field.
Definition: X86BaseInfo.h:645
llvm::X86II::XOPA
@ XOPA
Definition: X86BaseInfo.h:817
llvm::X86AS::SS
@ SS
Definition: X86.h:189
llvm::X86II::MO_ABS8
@ MO_ABS8
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:570
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:34
llvm::X86II::T8
@ T8
Definition: X86BaseInfo.h:808
llvm::X86II::XOP8
@ XOP8
Definition: X86BaseInfo.h:811
llvm::X86II::VEX_WShift
@ VEX_WShift
VEX_W - Has a opcode specific functionality, but is used in the same way as REX_W is for regular SSE ...
Definition: X86BaseInfo.h:924
llvm::X86II::MO_NTPOFF
@ MO_NTPOFF
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:524
llvm::X86II::EVEX_RC
@ EVEX_RC
Definition: X86BaseInfo.h:962
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
llvm::X86::COND_E
@ COND_E
Definition: X86BaseInfo.h:85
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:210
llvm::X86II::MRM_EE
@ MRM_EE
Definition: X86BaseInfo.h:743
llvm::X86II::MRM_E1
@ MRM_E1
Definition: X86BaseInfo.h:740
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::X86::LAST_VALID_COND
@ LAST_VALID_COND
Definition: X86BaseInfo.h:97
llvm::X86II::MRM_D2
@ MRM_D2
Definition: X86BaseInfo.h:736
llvm::X86::OPERAND_ROUNDING_CONTROL
@ OPERAND_ROUNDING_CONTROL
AVX512 embedded rounding control. This should only have values 0-3.
Definition: X86BaseInfo.h:74
llvm::X86::COND_NP
@ COND_NP
Definition: X86BaseInfo.h:92
llvm::X86II::REP
@ REP
Definition: X86BaseInfo.h:897
llvm::X86::COND_NE
@ COND_NE
Definition: X86BaseInfo.h:86
llvm::X86II::RawFrmDstSrc
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
Definition: X86BaseInfo.h:612
llvm::X86II::MRM5X
@ MRM5X
Definition: X86BaseInfo.h:729
llvm::X86II::MRMSrcRegOp4
@ MRMSrcRegOp4
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:705
llvm::X86II::REPShift
@ REPShift
Definition: X86BaseInfo.h:896