LLVM 17.0.0git
X86BaseInfo.h
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1//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone helper functions and enum definitions for
10// the X86 target useful for the compiler back-end and the MC libraries.
11// As such, it deliberately does not include references to LLVM core
12// code gen types, passes, etc..
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
17#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18
19#include "X86MCTargetDesc.h"
20#include "llvm/MC/MCInstrDesc.h"
23
24namespace llvm {
25
26namespace X86 {
27 // Enums for memory operand decoding. Each memory operand is represented with
28 // a 5 operand sequence in the form:
29 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
30 // These enums help decode this.
31 enum {
36
37 /// AddrSegmentReg - The operand # of the segment in the memory operand.
39
40 /// AddrNumOperands - Total number of operands in a memory reference.
42 };
43
44 /// AVX512 static rounding constants. These need to match the values in
45 /// avx512fintrin.h.
52 NO_EXC = 8
53 };
54
55 /// The constants to describe instr prefixes if there are
56 enum IPREFIXES {
58 IP_HAS_OP_SIZE = 1U << 0,
59 IP_HAS_AD_SIZE = 1U << 1,
61 IP_HAS_REPEAT = 1U << 3,
62 IP_HAS_LOCK = 1U << 4,
63 IP_HAS_NOTRACK = 1U << 5,
64 IP_USE_VEX = 1U << 6,
65 IP_USE_VEX2 = 1U << 7,
66 IP_USE_VEX3 = 1U << 8,
67 IP_USE_EVEX = 1U << 9,
68 IP_USE_DISP8 = 1U << 10,
69 IP_USE_DISP32 = 1U << 11,
70 };
71
72 enum OperandType : unsigned {
73 /// AVX512 embedded rounding control. This should only have values 0-3.
76 };
77
78 // X86 specific condition code. These correspond to X86_*_COND in
79 // X86InstrInfo.td. They must be kept in synch.
80 enum CondCode {
81 COND_O = 0,
83 COND_B = 2,
85 COND_E = 4,
88 COND_A = 7,
89 COND_S = 8,
91 COND_P = 10,
92 COND_NP = 11,
93 COND_L = 12,
94 COND_GE = 13,
95 COND_LE = 14,
96 COND_G = 15,
98
99 // Artificial condition codes. These are used by analyzeBranch
100 // to indicate a block terminated with two conditional branches that together
101 // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
102 // which can't be represented on x86 with a single condition. These
103 // are never used in MachineInstrs and are inverses of one another.
106
108 };
109
110 // The classification for the first instruction in macro fusion.
112 // TEST
113 Test,
114 // CMP
115 Cmp,
116 // AND
117 And,
118 // FIXME: Zen 3 support branch fusion for OR/XOR.
119 // ADD, SUB
120 AddSub,
121 // INC, DEC
122 IncDec,
123 // Not valid as a first macro fusion instruction
124 Invalid
125 };
126
128 // JA, JB and variants.
129 AB,
130 // JE, JL, JG and variants.
131 ELG,
132 // JS, JP, JO and variants
133 SPO,
134 // Not a fusible jump.
135 Invalid,
136 };
137
138 /// \returns the type of the first instruction in macro-fusion.
141 switch (Opcode) {
142 default:
144 // TEST
145 case X86::TEST16i16:
146 case X86::TEST16mr:
147 case X86::TEST16ri:
148 case X86::TEST16rr:
149 case X86::TEST32i32:
150 case X86::TEST32mr:
151 case X86::TEST32ri:
152 case X86::TEST32rr:
153 case X86::TEST64i32:
154 case X86::TEST64mr:
155 case X86::TEST64ri32:
156 case X86::TEST64rr:
157 case X86::TEST8i8:
158 case X86::TEST8mr:
159 case X86::TEST8ri:
160 case X86::TEST8rr:
162 case X86::AND16i16:
163 case X86::AND16ri:
164 case X86::AND16ri8:
165 case X86::AND16rm:
166 case X86::AND16rr:
167 case X86::AND16rr_REV:
168 case X86::AND32i32:
169 case X86::AND32ri:
170 case X86::AND32ri8:
171 case X86::AND32rm:
172 case X86::AND32rr:
173 case X86::AND32rr_REV:
174 case X86::AND64i32:
175 case X86::AND64ri32:
176 case X86::AND64ri8:
177 case X86::AND64rm:
178 case X86::AND64rr:
179 case X86::AND64rr_REV:
180 case X86::AND8i8:
181 case X86::AND8ri:
182 case X86::AND8ri8:
183 case X86::AND8rm:
184 case X86::AND8rr:
185 case X86::AND8rr_REV:
187 // FIXME: Zen 3 support branch fusion for OR/XOR.
188 // CMP
189 case X86::CMP16i16:
190 case X86::CMP16mr:
191 case X86::CMP16ri:
192 case X86::CMP16ri8:
193 case X86::CMP16rm:
194 case X86::CMP16rr:
195 case X86::CMP16rr_REV:
196 case X86::CMP32i32:
197 case X86::CMP32mr:
198 case X86::CMP32ri:
199 case X86::CMP32ri8:
200 case X86::CMP32rm:
201 case X86::CMP32rr:
202 case X86::CMP32rr_REV:
203 case X86::CMP64i32:
204 case X86::CMP64mr:
205 case X86::CMP64ri32:
206 case X86::CMP64ri8:
207 case X86::CMP64rm:
208 case X86::CMP64rr:
209 case X86::CMP64rr_REV:
210 case X86::CMP8i8:
211 case X86::CMP8mr:
212 case X86::CMP8ri:
213 case X86::CMP8ri8:
214 case X86::CMP8rm:
215 case X86::CMP8rr:
216 case X86::CMP8rr_REV:
218 // ADD
219 case X86::ADD16i16:
220 case X86::ADD16ri:
221 case X86::ADD16ri8:
222 case X86::ADD16rm:
223 case X86::ADD16rr:
224 case X86::ADD16rr_REV:
225 case X86::ADD32i32:
226 case X86::ADD32ri:
227 case X86::ADD32ri8:
228 case X86::ADD32rm:
229 case X86::ADD32rr:
230 case X86::ADD32rr_REV:
231 case X86::ADD64i32:
232 case X86::ADD64ri32:
233 case X86::ADD64ri8:
234 case X86::ADD64rm:
235 case X86::ADD64rr:
236 case X86::ADD64rr_REV:
237 case X86::ADD8i8:
238 case X86::ADD8ri:
239 case X86::ADD8ri8:
240 case X86::ADD8rm:
241 case X86::ADD8rr:
242 case X86::ADD8rr_REV:
243 // SUB
244 case X86::SUB16i16:
245 case X86::SUB16ri:
246 case X86::SUB16ri8:
247 case X86::SUB16rm:
248 case X86::SUB16rr:
249 case X86::SUB16rr_REV:
250 case X86::SUB32i32:
251 case X86::SUB32ri:
252 case X86::SUB32ri8:
253 case X86::SUB32rm:
254 case X86::SUB32rr:
255 case X86::SUB32rr_REV:
256 case X86::SUB64i32:
257 case X86::SUB64ri32:
258 case X86::SUB64ri8:
259 case X86::SUB64rm:
260 case X86::SUB64rr:
261 case X86::SUB64rr_REV:
262 case X86::SUB8i8:
263 case X86::SUB8ri:
264 case X86::SUB8ri8:
265 case X86::SUB8rm:
266 case X86::SUB8rr:
267 case X86::SUB8rr_REV:
269 // INC
270 case X86::INC16r:
271 case X86::INC16r_alt:
272 case X86::INC32r:
273 case X86::INC32r_alt:
274 case X86::INC64r:
275 case X86::INC8r:
276 // DEC
277 case X86::DEC16r:
278 case X86::DEC16r_alt:
279 case X86::DEC32r:
280 case X86::DEC32r_alt:
281 case X86::DEC64r:
282 case X86::DEC8r:
284 }
285 }
286
287 /// \returns the type of the second instruction in macro-fusion.
290 if (CC == X86::COND_INVALID)
292
293 switch (CC) {
294 default:
296 // JE,JZ
297 case X86::COND_E:
298 // JNE,JNZ
299 case X86::COND_NE:
300 // JL,JNGE
301 case X86::COND_L:
302 // JLE,JNG
303 case X86::COND_LE:
304 // JG,JNLE
305 case X86::COND_G:
306 // JGE,JNL
307 case X86::COND_GE:
309 // JB,JC
310 case X86::COND_B:
311 // JNA,JBE
312 case X86::COND_BE:
313 // JA,JNBE
314 case X86::COND_A:
315 // JAE,JNC,JNB
316 case X86::COND_AE:
318 // JS
319 case X86::COND_S:
320 // JNS
321 case X86::COND_NS:
322 // JP,JPE
323 case X86::COND_P:
324 // JNP,JPO
325 case X86::COND_NP:
326 // JO
327 case X86::COND_O:
328 // JNO
329 case X86::COND_NO:
331 }
332 }
333
334 /// \param FirstKind kind of the first instruction in macro fusion.
335 /// \param SecondKind kind of the second instruction in macro fusion.
336 ///
337 /// \returns true if the two instruction can be macro fused.
339 SecondMacroFusionInstKind SecondKind) {
340 switch (FirstKind) {
343 return true;
346 return SecondKind == X86::SecondMacroFusionInstKind::AB ||
349 return SecondKind == X86::SecondMacroFusionInstKind::ELG;
351 return false;
352 }
353 llvm_unreachable("unknown fusion type");
354 }
355
356 /// Defines the possible values of the branch boundary alignment mask.
357 enum AlignBranchBoundaryKind : uint8_t {
360 AlignBranchJcc = 1U << 1,
361 AlignBranchJmp = 1U << 2,
363 AlignBranchRet = 1U << 4,
364 AlignBranchIndirect = 1U << 5
365 };
366
367 /// Defines the encoding values for segment override prefix.
374 SS_Encoding = 0x36
375 };
376
377 /// Given a segment register, return the encoding of the segment override
378 /// prefix for it.
381 switch (Reg) {
382 default:
383 llvm_unreachable("Unknown segment register!");
384 case X86::CS:
385 return CS_Encoding;
386 case X86::DS:
387 return DS_Encoding;
388 case X86::ES:
389 return ES_Encoding;
390 case X86::FS:
391 return FS_Encoding;
392 case X86::GS:
393 return GS_Encoding;
394 case X86::SS:
395 return SS_Encoding;
396 }
397 }
398
399} // end namespace X86;
400
401/// X86II - This namespace holds all of the target specific flags that
402/// instruction info tracks.
403///
404namespace X86II {
405 /// Target Operand Flag enum.
406 enum TOF {
407 //===------------------------------------------------------------------===//
408 // X86 Specific MachineOperand flags.
409
411
412 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
413 /// relocation of:
414 /// SYMBOL_LABEL + [. - PICBASELABEL]
416
417 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
418 /// immediate should get the value of the symbol minus the PIC base label:
419 /// SYMBOL_LABEL - PICBASELABEL
421
422 /// MO_GOT - On a symbol operand this indicates that the immediate is the
423 /// offset to the GOT entry for the symbol name from the base of the GOT.
424 ///
425 /// See the X86-64 ELF ABI supplement for more details.
426 /// SYMBOL_LABEL @GOT
428
429 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
430 /// the offset to the location of the symbol name from the base of the GOT.
431 ///
432 /// See the X86-64 ELF ABI supplement for more details.
433 /// SYMBOL_LABEL @GOTOFF
435
436 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
437 /// offset to the GOT entry for the symbol name from the current code
438 /// location.
439 ///
440 /// See the X86-64 ELF ABI supplement for more details.
441 /// SYMBOL_LABEL @GOTPCREL
443
444 /// MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL
445 /// relocations are guaranteed to be emitted by the integrated assembler
446 /// instead of the relaxable R_X86_64[_REX]_GOTPCRELX relocations.
448
449 /// MO_PLT - On a symbol operand this indicates that the immediate is
450 /// offset to the PLT entry of symbol name from the current code location.
451 ///
452 /// See the X86-64 ELF ABI supplement for more details.
453 /// SYMBOL_LABEL @PLT
455
456 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
457 /// the offset of the GOT entry with the TLS index structure that contains
458 /// the module number and variable offset for the symbol. Used in the
459 /// general dynamic TLS access model.
460 ///
461 /// See 'ELF Handling for Thread-Local Storage' for more details.
462 /// SYMBOL_LABEL @TLSGD
464
465 /// MO_TLSLD - On a symbol operand this indicates that the immediate is
466 /// the offset of the GOT entry with the TLS index for the module that
467 /// contains the symbol. When this index is passed to a call to
468 /// __tls_get_addr, the function will return the base address of the TLS
469 /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
470 ///
471 /// See 'ELF Handling for Thread-Local Storage' for more details.
472 /// SYMBOL_LABEL @TLSLD
474
475 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
476 /// the offset of the GOT entry with the TLS index for the module that
477 /// contains the symbol. When this index is passed to a call to
478 /// ___tls_get_addr, the function will return the base address of the TLS
479 /// block for the symbol. Used in the IA32 local dynamic TLS access model.
480 ///
481 /// See 'ELF Handling for Thread-Local Storage' for more details.
482 /// SYMBOL_LABEL @TLSLDM
484
485 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
486 /// the offset of the GOT entry with the thread-pointer offset for the
487 /// symbol. Used in the x86-64 initial exec TLS access model.
488 ///
489 /// See 'ELF Handling for Thread-Local Storage' for more details.
490 /// SYMBOL_LABEL @GOTTPOFF
492
493 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
494 /// the absolute address of the GOT entry with the negative thread-pointer
495 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
496 /// model.
497 ///
498 /// See 'ELF Handling for Thread-Local Storage' for more details.
499 /// SYMBOL_LABEL @INDNTPOFF
501
502 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
503 /// the thread-pointer offset for the symbol. Used in the x86-64 local
504 /// exec TLS access model.
505 ///
506 /// See 'ELF Handling for Thread-Local Storage' for more details.
507 /// SYMBOL_LABEL @TPOFF
509
510 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
511 /// the offset of the GOT entry with the TLS offset of the symbol. Used
512 /// in the local dynamic TLS access model.
513 ///
514 /// See 'ELF Handling for Thread-Local Storage' for more details.
515 /// SYMBOL_LABEL @DTPOFF
517
518 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
519 /// the negative thread-pointer offset for the symbol. Used in the IA32
520 /// local exec TLS access model.
521 ///
522 /// See 'ELF Handling for Thread-Local Storage' for more details.
523 /// SYMBOL_LABEL @NTPOFF
525
526 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
527 /// the offset of the GOT entry with the negative thread-pointer offset for
528 /// the symbol. Used in the PIC IA32 initial exec TLS access model.
529 ///
530 /// See 'ELF Handling for Thread-Local Storage' for more details.
531 /// SYMBOL_LABEL @GOTNTPOFF
533
534 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
535 /// reference is actually to the "__imp_FOO" symbol. This is used for
536 /// dllimport linkage on windows.
538
539 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
540 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
541 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
543
544 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
545 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
546 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
548
549 /// MO_TLVP - On a symbol operand this indicates that the immediate is
550 /// some TLS offset.
551 ///
552 /// This is the TLS offset for the Darwin TLS mechanism.
554
555 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
556 /// is some TLS offset from the picbase.
557 ///
558 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
560
561 /// MO_SECREL - On a symbol operand this indicates that the immediate is
562 /// the offset from beginning of section.
563 ///
564 /// This is the TLS offset for the COFF/Windows TLS mechanism.
566
567 /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
568 /// to be an absolute symbol in range [0,128), so we can use the @ABS8
569 /// symbol modifier.
571
572 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
573 /// reference is actually to the ".refptr.FOO" symbol. This is used for
574 /// stub symbols on windows.
576 };
577
578 enum : uint64_t {
579 //===------------------------------------------------------------------===//
580 // Instruction encodings. These are the standard/most common forms for X86
581 // instructions.
582 //
583
584 // PseudoFrm - This represents an instruction that is a pseudo instruction
585 // or one that has not been implemented yet. It is illegal to code generate
586 // it, but tolerated for intermediate implementation stages.
588
589 /// Raw - This form is for instructions that don't have any operands, so
590 /// they are just a fixed opcode value, like 'leave'.
592
593 /// AddRegFrm - This form is used for instructions like 'push r32' that have
594 /// their one register operand added to their opcode.
596
597 /// RawFrmMemOffs - This form is for instructions that store an absolute
598 /// memory offset as an immediate with a possible segment override.
600
601 /// RawFrmSrc - This form is for instructions that use the source index
602 /// register SI/ESI/RSI with a possible segment override.
604
605 /// RawFrmDst - This form is for instructions that use the destination index
606 /// register DI/EDI/RDI.
608
609 /// RawFrmDstSrc - This form is for instructions that use the source index
610 /// register SI/ESI/RSI with a possible segment override, and also the
611 /// destination index register DI/EDI/RDI.
613
614 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
615 /// immediates, the first of which is a 16-bit immediate (specified by
616 /// the imm encoding) and the second is a 8-bit fixed value.
618
619 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
620 /// immediates, the first of which is a 16 or 32-bit immediate (specified by
621 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
622 /// manual, this operand is described as pntr16:32 and pntr16:16
624
625 /// AddCCFrm - This form is used for Jcc that encode the condition code
626 /// in the lower 4 bits of the opcode.
628
629 /// PrefixByte - This form is used for instructions that represent a prefix
630 /// byte like data16 or rep.
632
633 /// MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM
634 /// byte to specify a destination which in this case is memory and operand 3
635 /// with VEX.VVVV, and also encodes a condition code.
637
638 /// MRM[0-7][rm] - These forms are used to represent instructions that use
639 /// a Mod/RM byte, and use the middle field to hold extended opcode
640 /// information. In the intel manual these are represented as /0, /1, ...
641 ///
642
643 // Instructions operate on a register Reg/Opcode operand not the r/m field.
644 MRMr0 = 21,
645
646 /// MRMSrcMem - But force to use the SIB field.
648
649 /// MRMDestMem - But force to use the SIB field.
651
652 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
653 /// to specify a destination, which in this case is memory.
654 ///
656
657 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
658 /// to specify a source, which in this case is memory.
659 ///
661
662 /// MRMSrcMem4VOp3 - This form is used for instructions that encode
663 /// operand 3 with VEX.VVVV and load from memory.
664 ///
666
667 /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
668 /// byte to specify the fourth source, which in this case is memory.
669 ///
671
672 /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM
673 /// byte to specify the operands and also encodes a condition code.
674 ///
676
677 /// MRMXm - This form is used for instructions that use the Mod/RM byte
678 /// to specify a memory source, but doesn't use the middle field. And has
679 /// a condition code.
680 ///
682
683 /// MRMXm - This form is used for instructions that use the Mod/RM byte
684 /// to specify a memory source, but doesn't use the middle field.
685 ///
686 MRMXm = 31,
687
688 // Next, instructions that operate on a memory r/m operand...
689 MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35, // Format /0 /1 /2 /3
690 MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39, // Format /4 /5 /6 /7
691
692 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
693 /// to specify a destination, which in this case is a register.
694 ///
696
697 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
698 /// to specify a source, which in this case is a register.
699 ///
701
702 /// MRMSrcReg4VOp3 - This form is used for instructions that encode
703 /// operand 3 with VEX.VVVV and do not load from memory.
704 ///
706
707 /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
708 /// byte to specify the fourth source, which in this case is a register.
709 ///
711
712 /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM
713 /// byte to specify the operands and also encodes a condition code
714 ///
716
717 /// MRMXCCr - This form is used for instructions that use the Mod/RM byte
718 /// to specify a register source, but doesn't use the middle field. And has
719 /// a condition code.
720 ///
722
723 /// MRMXr - This form is used for instructions that use the Mod/RM byte
724 /// to specify a register source, but doesn't use the middle field.
725 ///
726 MRMXr = 47,
727
728 // Instructions that operate on a register r/m operand...
729 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, // Format /0 /1 /2 /3
730 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, // Format /4 /5 /6 /7
731
732 // Instructions that operate that have mod=11 and an opcode but ignore r/m.
733 MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59, // Format /0 /1 /2 /3
734 MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63, // Format /4 /5 /6 /7
735
736 /// MRM_XX - A mod/rm byte of exactly 0xXX.
737 MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67,
738 MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71,
739 MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75,
740 MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79,
741 MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83,
742 MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87,
743 MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91,
744 MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95,
745 MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99,
746 MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103,
747 MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107,
748 MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111,
749 MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115,
750 MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119,
751 MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123,
752 MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127,
753
754 FormMask = 127,
755
756 //===------------------------------------------------------------------===//
757 // Actual flags...
758
759 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
760 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
761 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
762 // prefix in 16-bit mode.
765
769
770 // AsSize - AdSizeX implies this instruction determines its need of 0x67
771 // prefix from a normal ModRM memory operand. The other types indicate that
772 // an operand is encoded with a specific width and a prefix is needed if
773 // it differs from the current mode.
776
781
782 //===------------------------------------------------------------------===//
783 // OpPrefix - There are several prefix bytes that are used as opcode
784 // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
785 // no prefix.
786 //
789
790 // PD - Prefix code for packed double precision vector floating point
791 // operations performed in the SSE registers.
793
794 // XS, XD - These prefix codes are for single and double precision scalar
795 // floating point operations performed in the SSE registers.
797
798 //===------------------------------------------------------------------===//
799 // OpMap - This field determines which opcode map this instruction
800 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
801 //
804
805 // OB - OneByte - Set if this instruction has a one byte opcode.
807
808 // TB - TwoByte - Set if this instruction has a two byte opcode, which
809 // starts with a 0x0F byte before the real opcode.
811
812 // T8, TA - Prefix after the 0x0F prefix.
813 T8 = 2 << OpMapShift, TA = 3 << OpMapShift,
814
815 // XOP8 - Prefix to include use of imm byte.
817
818 // XOP9 - Prefix to exclude use of imm byte.
820
821 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
823
824 /// ThreeDNow - This indicates that the instruction uses the
825 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
826 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
827 /// storing a classifier in the imm8 field. To simplify our implementation,
828 /// we handle this by storeing the classifier in the opcode field and using
829 /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
831
832 // MAP5, MAP6 - Prefix after the 0x0F prefix.
835
836 //===------------------------------------------------------------------===//
837 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
838 // They are used to specify GPRs and SSE registers, 64-bit operand size,
839 // etc. We only cares about REX.W and REX.R bits and only the former is
840 // statically determined.
841 //
844
845 //===------------------------------------------------------------------===//
846 // This three-bit field describes the size of an immediate operand. Zero is
847 // unused so that we can tell if we forgot to set a value.
859
860 //===------------------------------------------------------------------===//
861 // FP Instruction Classification... Zero is non-fp instruction.
862
863 // FPTypeMask - Mask for all of the FP types...
866
867 // NotFP - The default, set for instructions that do not use FP registers.
869
870 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
872
873 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
875
876 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
877 // result back to ST(0). For example, fcos, fsqrt, etc.
878 //
880
881 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
882 // explicit argument, storing the result to either ST(0) or the implicit
883 // argument. For example: fadd, fsub, fmul, etc...
885
886 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
887 // explicit argument, but have no destination. Example: fucom, fucomi, ...
889
890 // CondMovFP - "2 operand" floating point conditional move instructions.
892
893 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
895
896 // Lock prefix
899
900 // REP prefix
902 REP = 1 << REPShift,
903
904 // Execution domain for SSE instructions.
905 // 0 means normal, non-SSE instruction.
907
908 // Encoding
911
912 // VEX - encoding using 0xC4/0xC5
914
915 /// XOP - Opcode prefix used by XOP instructions.
917
918 // VEX_EVEX - Specifies that this instruction use EVEX form which provides
919 // syntax support up to 32 512-bit register operands and up to 7 16-bit
920 // mask operands as well as source operand data swizzling/memory operand
921 // conversion, eviction hint, and rounding mode.
923
924 // Opcode
926
927 /// VEX_W - Has a opcode specific functionality, but is used in the same
928 /// way as REX_W is for regular SSE instructions.
930 VEX_W = 1ULL << VEX_WShift,
931
932 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
933 /// address instructions in SSE are represented as 3 address ones in AVX
934 /// and the additional register is encoded in VEX_VVVV prefix.
937
938 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
939 /// instruction uses 256-bit wide registers. This is usually auto detected
940 /// if a VR256 register is used, but some AVX instructions also have this
941 /// field marked when using a f256 memory references.
943 VEX_L = 1ULL << VEX_LShift,
944
945 // EVEX_K - Set if this instruction requires masking
948
949 // EVEX_Z - Set if this instruction has EVEX.Z field set.
952
953 // EVEX_L2 - Set if this instruction has EVEX.L' field set.
956
957 // EVEX_B - Set if this instruction has EVEX.B field set.
960
961 // The scaling factor for the AVX512's 8-bit compressed displacement.
964
965 /// Explicitly specified rounding control
968
969 // NOTRACK prefix
972
973 // Force VEX encoding
976 };
977
978 /// \returns true if the instruction with given opcode is a prefix.
979 inline bool isPrefix(uint64_t TSFlags) {
980 return (TSFlags & X86II::FormMask) == PrefixByte;
981 }
982
983 /// \returns true if the instruction with given opcode is a pseudo.
984 inline bool isPseudo(uint64_t TSFlags) {
985 return (TSFlags & X86II::FormMask) == Pseudo;
986 }
987
988 /// \returns the "base" X86 opcode for the specified machine
989 /// instruction.
991 return TSFlags >> X86II::OpcodeShift;
992 }
993
994 inline bool hasImm(uint64_t TSFlags) {
995 return (TSFlags & X86II::ImmMask) != 0;
996 }
997
998 /// Decode the "size of immediate" field from the TSFlags field of the
999 /// specified instruction.
1000 inline unsigned getSizeOfImm(uint64_t TSFlags) {
1001 switch (TSFlags & X86II::ImmMask) {
1002 default: llvm_unreachable("Unknown immediate size");
1003 case X86II::Imm8:
1004 case X86II::Imm8PCRel:
1005 case X86II::Imm8Reg: return 1;
1006 case X86II::Imm16:
1007 case X86II::Imm16PCRel: return 2;
1008 case X86II::Imm32:
1009 case X86II::Imm32S:
1010 case X86II::Imm32PCRel: return 4;
1011 case X86II::Imm64: return 8;
1012 }
1013 }
1014
1015 /// \returns true if the immediate of the specified instruction's TSFlags
1016 /// indicates that it is pc relative.
1018 switch (TSFlags & X86II::ImmMask) {
1019 default: llvm_unreachable("Unknown immediate size");
1020 case X86II::Imm8PCRel:
1021 case X86II::Imm16PCRel:
1022 case X86II::Imm32PCRel:
1023 return true;
1024 case X86II::Imm8:
1025 case X86II::Imm8Reg:
1026 case X86II::Imm16:
1027 case X86II::Imm32:
1028 case X86II::Imm32S:
1029 case X86II::Imm64:
1030 return false;
1031 }
1032 }
1033
1034 /// \returns true if the immediate of the specified instruction's
1035 /// TSFlags indicates that it is signed.
1037 switch (TSFlags & X86II::ImmMask) {
1038 default: llvm_unreachable("Unknown immediate signedness");
1039 case X86II::Imm32S:
1040 return true;
1041 case X86II::Imm8:
1042 case X86II::Imm8PCRel:
1043 case X86II::Imm8Reg:
1044 case X86II::Imm16:
1045 case X86II::Imm16PCRel:
1046 case X86II::Imm32:
1047 case X86II::Imm32PCRel:
1048 case X86II::Imm64:
1049 return false;
1050 }
1051 }
1052
1053 /// Compute whether all of the def operands are repeated in the uses and
1054 /// therefore should be skipped.
1055 /// This determines the start of the unique operand list. We need to determine
1056 /// if all of the defs have a corresponding tied operand in the uses.
1057 /// Unfortunately, the tied operand information is encoded in the uses not
1058 /// the defs so we have to use some heuristics to find which operands to
1059 /// query.
1060 inline unsigned getOperandBias(const MCInstrDesc& Desc) {
1061 unsigned NumDefs = Desc.getNumDefs();
1062 unsigned NumOps = Desc.getNumOperands();
1063 switch (NumDefs) {
1064 default: llvm_unreachable("Unexpected number of defs");
1065 case 0:
1066 return 0;
1067 case 1:
1068 // Common two addr case.
1069 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
1070 return 1;
1071 // Check for AVX-512 scatter which has a TIED_TO in the second to last
1072 // operand.
1073 if (NumOps == 8 &&
1074 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0)
1075 return 1;
1076 return 0;
1077 case 2:
1078 // XCHG/XADD have two destinations and two sources.
1079 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
1080 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
1081 return 2;
1082 // Check for gather. AVX-512 has the second tied operand early. AVX2
1083 // has it as the last op.
1084 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
1085 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 ||
1086 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1))
1087 return 2;
1088 return 0;
1089 }
1090 }
1091
1092 /// The function returns the MCInst operand # for the first field of the
1093 /// memory operand. If the instruction doesn't have a
1094 /// memory operand, this returns -1.
1095 ///
1096 /// Note that this ignores tied operands. If there is a tied register which
1097 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
1098 /// counted as one operand.
1099 ///
1101 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1102 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1103
1104 switch (TSFlags & X86II::FormMask) {
1105 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
1106 case X86II::Pseudo:
1107 case X86II::RawFrm:
1108 case X86II::AddRegFrm:
1109 case X86II::RawFrmImm8:
1110 case X86II::RawFrmImm16:
1112 case X86II::RawFrmSrc:
1113 case X86II::RawFrmDst:
1115 case X86II::AddCCFrm:
1116 case X86II::PrefixByte:
1117 return -1;
1118 case X86II::MRMDestMem:
1120 return 0;
1121 case X86II::MRMSrcMem:
1123 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1124 // mask register.
1125 return 1 + HasVEX_4V + HasEVEX_K;
1127 // Skip registers encoded in reg.
1128 return 1 + HasEVEX_K;
1130 // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
1131 return 3;
1132 case X86II::MRMSrcMemCC:
1134 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1135 // mask register.
1136 return 1;
1137 case X86II::MRMDestReg:
1138 case X86II::MRMSrcReg:
1141 case X86II::MRMSrcRegCC:
1142 case X86II::MRMXrCC:
1143 case X86II::MRMr0:
1144 case X86II::MRMXr:
1145 case X86II::MRM0r: case X86II::MRM1r:
1146 case X86II::MRM2r: case X86II::MRM3r:
1147 case X86II::MRM4r: case X86II::MRM5r:
1148 case X86II::MRM6r: case X86II::MRM7r:
1149 return -1;
1150 case X86II::MRM0X: case X86II::MRM1X:
1151 case X86II::MRM2X: case X86II::MRM3X:
1152 case X86II::MRM4X: case X86II::MRM5X:
1153 case X86II::MRM6X: case X86II::MRM7X:
1154 return -1;
1155 case X86II::MRMXmCC:
1156 case X86II::MRMXm:
1157 case X86II::MRM0m: case X86II::MRM1m:
1158 case X86II::MRM2m: case X86II::MRM3m:
1159 case X86II::MRM4m: case X86II::MRM5m:
1160 case X86II::MRM6m: case X86II::MRM7m:
1161 // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
1162 return 0 + HasVEX_4V + HasEVEX_K;
1163 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
1164 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
1165 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
1166 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
1167 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
1168 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
1169 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
1170 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
1171 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
1172 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
1173 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
1174 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
1175 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
1176 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
1177 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
1178 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
1179 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
1180 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
1181 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
1182 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
1183 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
1184 case X86II::MRM_FF:
1185 return -1;
1186 }
1187 }
1188
1189 /// \returns true if the MachineOperand is a x86-64 extended (r8 or
1190 /// higher) register, e.g. r8, xmm8, xmm13, etc.
1191 inline bool isX86_64ExtendedReg(unsigned RegNo) {
1192 if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
1193 (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) ||
1194 (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
1195 return true;
1196
1197 switch (RegNo) {
1198 default: break;
1199 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
1200 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
1201 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
1202 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
1203 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
1204 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
1205 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
1206 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
1207 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
1208 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
1209 case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11:
1210 case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15:
1211 return true;
1212 }
1213 return false;
1214 }
1215
1216 /// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher)
1217 /// registers, e.g. zmm21, etc.
1218 static inline bool is32ExtendedReg(unsigned RegNo) {
1219 return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
1220 (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
1221 (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
1222 }
1223
1224
1225 inline bool isX86_64NonExtLowByteReg(unsigned reg) {
1226 return (reg == X86::SPL || reg == X86::BPL ||
1227 reg == X86::SIL || reg == X86::DIL);
1228 }
1229
1230 /// \returns true if this is a masked instruction.
1232 return (TSFlags & X86II::EVEX_K) != 0;
1233 }
1234
1235 /// \returns true if this is a merge masked instruction.
1237 return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
1238 }
1239}
1240
1241} // end namespace llvm;
1242
1243#endif
unsigned Reg
uint64_t TSFlags
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:247
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:219
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
@ X86
Windows x64, Windows Itanium (IA-64)
bool isKMergeMasked(uint64_t TSFlags)
Definition: X86BaseInfo.h:1236
bool isX86_64ExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1191
bool isPrefix(uint64_t TSFlags)
Definition: X86BaseInfo.h:979
@ RawFrm
Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:591
@ VEX_LShift
VEX_L - Stands for a bit in the VEX opcode prefix meaning the current instruction uses 256-bit wide r...
Definition: X86BaseInfo.h:942
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
Definition: X86BaseInfo.h:612
@ MRMSrcMemCC
MRMSrcMemCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition: X86BaseInfo.h:675
@ MRM_C0
MRM_XX - A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:737
@ RawFrmDst
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI.
Definition: X86BaseInfo.h:607
@ MRMDestMem4VOp3CC
MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM byte to specify a destinat...
Definition: X86BaseInfo.h:636
@ AddCCFrm
AddCCFrm - This form is used for Jcc that encode the condition code in the lower 4 bits of the opcode...
Definition: X86BaseInfo.h:627
@ PrefixByte
PrefixByte - This form is used for instructions that represent a prefix byte like data16 or rep.
Definition: X86BaseInfo.h:631
@ MRMr0
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte,...
Definition: X86BaseInfo.h:644
@ MRMXm
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition: X86BaseInfo.h:686
@ MRMDestMemFSIB
MRMDestMem - But force to use the SIB field.
Definition: X86BaseInfo.h:650
@ AddRegFrm
AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand a...
Definition: X86BaseInfo.h:595
@ RawFrmImm8
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:617
@ XOP
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:916
@ MRMXr
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition: X86BaseInfo.h:726
@ MRMSrcMem4VOp3
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition: X86BaseInfo.h:665
@ MRMDestMem
MRMDestMem - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition: X86BaseInfo.h:655
@ MRMSrcMemFSIB
MRMSrcMem - But force to use the SIB field.
Definition: X86BaseInfo.h:647
@ EVEX_RCShift
Explicitly specified rounding control.
Definition: X86BaseInfo.h:966
@ MRMSrcRegOp4
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:710
@ MRMXrCC
MRMXCCr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition: X86BaseInfo.h:721
@ MRMXmCC
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition: X86BaseInfo.h:681
@ RawFrmImm16
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:623
@ MRMSrcReg
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition: X86BaseInfo.h:700
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:603
@ MRMDestReg
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition: X86BaseInfo.h:695
@ MRMSrcMem
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition: X86BaseInfo.h:660
@ MRMSrcMemOp4
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:670
@ VEX_4VShift
VEX_4V - Used to specify an additional AVX/SSE register.
Definition: X86BaseInfo.h:935
@ VEX_WShift
VEX_W - Has a opcode specific functionality, but is used in the same way as REX_W is for regular SSE ...
Definition: X86BaseInfo.h:929
@ MRMSrcRegCC
MRMSrcRegCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition: X86BaseInfo.h:715
@ ThreeDNow
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow!...
Definition: X86BaseInfo.h:830
@ MRMSrcReg4VOp3
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition: X86BaseInfo.h:705
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:599
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:994
TOF
Target Operand Flag enum.
Definition: X86BaseInfo.h:406
@ MO_TLSLD
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:473
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
Definition: X86BaseInfo.h:447
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:434
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:547
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
Definition: X86BaseInfo.h:415
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: X86BaseInfo.h:575
@ MO_NTPOFF
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:524
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:542
@ MO_INDNTPOFF
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:500
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:532
@ MO_TPOFF
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:508
@ MO_TLVP_PIC_BASE
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:559
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:427
@ MO_ABS8
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:570
@ MO_PLT
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:454
@ MO_TLSGD
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:463
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:553
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:537
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:491
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:565
@ MO_DTPOFF
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:516
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:420
@ MO_TLSLDM
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:483
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:442
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:1225
bool isPseudo(uint64_t TSFlags)
Definition: X86BaseInfo.h:984
bool isImmPCRel(uint64_t TSFlags)
Definition: X86BaseInfo.h:1017
unsigned getSizeOfImm(uint64_t TSFlags)
Decode the "size of immediate" field from the TSFlags field of the specified instruction.
Definition: X86BaseInfo.h:1000
uint8_t getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:990
bool isKMasked(uint64_t TSFlags)
Definition: X86BaseInfo.h:1231
int getMemoryOperandNo(uint64_t TSFlags)
The function returns the MCInst operand # for the first field of the memory operand.
Definition: X86BaseInfo.h:1100
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
Definition: X86BaseInfo.h:1060
static bool is32ExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1218
bool isImmSigned(uint64_t TSFlags)
Definition: X86BaseInfo.h:1036
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
Definition: X86BaseInfo.h:140
@ OPERAND_COND_CODE
Definition: X86BaseInfo.h:75
@ OPERAND_ROUNDING_CONTROL
AVX512 embedded rounding control. This should only have values 0-3.
Definition: X86BaseInfo.h:74
@ LAST_VALID_COND
Definition: X86BaseInfo.h:97
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
Definition: X86BaseInfo.h:357
@ AlignBranchJmp
Definition: X86BaseInfo.h:361
@ AlignBranchIndirect
Definition: X86BaseInfo.h:364
@ AlignBranchJcc
Definition: X86BaseInfo.h:360
@ AlignBranchCall
Definition: X86BaseInfo.h:362
@ AlignBranchRet
Definition: X86BaseInfo.h:363
@ AlignBranchNone
Definition: X86BaseInfo.h:358
@ AlignBranchFused
Definition: X86BaseInfo.h:359
STATIC_ROUNDING
AVX512 static rounding constants.
Definition: X86BaseInfo.h:46
@ TO_NEAREST_INT
Definition: X86BaseInfo.h:47
@ CUR_DIRECTION
Definition: X86BaseInfo.h:51
EncodingOfSegmentOverridePrefix
Defines the encoding values for segment override prefix.
Definition: X86BaseInfo.h:368
SecondMacroFusionInstKind
Definition: X86BaseInfo.h:127
FirstMacroFusionInstKind
Definition: X86BaseInfo.h:111
IPREFIXES
The constants to describe instr prefixes if there are.
Definition: X86BaseInfo.h:56
@ IP_HAS_NOTRACK
Definition: X86BaseInfo.h:63
@ IP_USE_DISP8
Definition: X86BaseInfo.h:68
@ IP_HAS_AD_SIZE
Definition: X86BaseInfo.h:59
@ IP_HAS_REPEAT
Definition: X86BaseInfo.h:61
@ IP_USE_DISP32
Definition: X86BaseInfo.h:69
@ IP_HAS_OP_SIZE
Definition: X86BaseInfo.h:58
@ IP_NO_PREFIX
Definition: X86BaseInfo.h:57
@ IP_HAS_REPEAT_NE
Definition: X86BaseInfo.h:60
SecondMacroFusionInstKind classifySecondCondCodeInMacroFusion(X86::CondCode CC)
Definition: X86BaseInfo.h:289
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
Definition: X86BaseInfo.h:380
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
Definition: X86BaseInfo.h:338
@ AddrScaleAmt
Definition: X86BaseInfo.h:33
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
@ AddrIndexReg
Definition: X86BaseInfo.h:34
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18