36#define GET_REGINFO_MC_DESC
37#include "X86GenRegisterInfo.inc"
39#define GET_INSTRINFO_MC_DESC
40#define GET_INSTRINFO_MC_HELPERS
41#define ENABLE_INSTR_PREDICATE_VERIFIER
42#include "X86GenInstrInfo.inc"
44#define GET_SUBTARGETINFO_MC_DESC
45#include "X86GenSubtargetInfo.inc"
52 FS =
"+64bit-mode,-32bit-mode,-16bit-mode,+sse2";
54 FS =
"-64bit-mode,+32bit-mode,-16bit-mode";
56 FS =
"-64bit-mode,-32bit-mode,+16bit-mode";
100 if (
Base.isReg() &&
Base.getReg() == X86::EIP) {
101 assert(
Index.isReg() &&
Index.getReg() == 0 &&
"Invalid eip-based address");
104 if (
Index.isReg() &&
Index.getReg() == X86::EIZ)
119 bool Is16BitMode = STI.
hasFeature(X86::Is16Bit);
120 bool Is32BitMode = STI.
hasFeature(X86::Is32Bit);
121 bool Is64BitMode = STI.
hasFeature(X86::Is64Bit);
131 unsigned siReg =
MI.getOperand(1).getReg();
132 assert(((siReg == X86::SI &&
MI.getOperand(0).getReg() == X86::DI) ||
133 (siReg == X86::ESI &&
MI.getOperand(0).getReg() == X86::EDI) ||
134 (siReg == X86::RSI &&
MI.getOperand(0).getReg() == X86::RDI)) &&
135 "SI and DI register sizes do not match");
136 return (!Is32BitMode && siReg == X86::ESI) ||
137 (Is32BitMode && siReg == X86::SI);
140 unsigned siReg =
MI.getOperand(0).getReg();
141 return (!Is32BitMode && siReg == X86::ESI) ||
142 (Is32BitMode && siReg == X86::SI);
145 unsigned siReg =
MI.getOperand(0).getReg();
146 return (!Is32BitMode && siReg == X86::EDI) ||
147 (Is32BitMode && siReg == X86::DI);
152 if (MemoryOperand < 0)
170 for (
unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
171 unsigned SEH =
MRI->getEncodingValue(Reg);
172 MRI->mapLLVMRegToSEHReg(Reg, SEH);
176 static const struct {
180 {codeview::RegisterId::AL, X86::AL},
181 {codeview::RegisterId::CL, X86::CL},
182 {codeview::RegisterId::DL, X86::DL},
183 {codeview::RegisterId::BL, X86::BL},
184 {codeview::RegisterId::AH, X86::AH},
185 {codeview::RegisterId::CH, X86::CH},
186 {codeview::RegisterId::DH, X86::DH},
187 {codeview::RegisterId::BH, X86::BH},
188 {codeview::RegisterId::AX, X86::AX},
189 {codeview::RegisterId::CX, X86::CX},
190 {codeview::RegisterId::DX, X86::DX},
191 {codeview::RegisterId::BX, X86::BX},
192 {codeview::RegisterId::SP, X86::SP},
193 {codeview::RegisterId::BP, X86::BP},
194 {codeview::RegisterId::SI, X86::SI},
195 {codeview::RegisterId::DI, X86::DI},
196 {codeview::RegisterId::EAX, X86::EAX},
197 {codeview::RegisterId::ECX, X86::ECX},
198 {codeview::RegisterId::EDX, X86::EDX},
199 {codeview::RegisterId::EBX, X86::EBX},
200 {codeview::RegisterId::ESP, X86::ESP},
201 {codeview::RegisterId::EBP, X86::EBP},
202 {codeview::RegisterId::ESI, X86::ESI},
203 {codeview::RegisterId::EDI, X86::EDI},
205 {codeview::RegisterId::EFLAGS, X86::EFLAGS},
207 {codeview::RegisterId::ST0, X86::ST0},
208 {codeview::RegisterId::ST1, X86::ST1},
209 {codeview::RegisterId::ST2, X86::ST2},
210 {codeview::RegisterId::ST3, X86::ST3},
211 {codeview::RegisterId::ST4, X86::ST4},
212 {codeview::RegisterId::ST5, X86::ST5},
213 {codeview::RegisterId::ST6, X86::ST6},
214 {codeview::RegisterId::ST7, X86::ST7},
216 {codeview::RegisterId::ST0, X86::FP0},
217 {codeview::RegisterId::ST1, X86::FP1},
218 {codeview::RegisterId::ST2, X86::FP2},
219 {codeview::RegisterId::ST3, X86::FP3},
220 {codeview::RegisterId::ST4, X86::FP4},
221 {codeview::RegisterId::ST5, X86::FP5},
222 {codeview::RegisterId::ST6, X86::FP6},
223 {codeview::RegisterId::ST7, X86::FP7},
225 {codeview::RegisterId::MM0, X86::MM0},
226 {codeview::RegisterId::MM1, X86::MM1},
227 {codeview::RegisterId::MM2, X86::MM2},
228 {codeview::RegisterId::MM3, X86::MM3},
229 {codeview::RegisterId::MM4, X86::MM4},
230 {codeview::RegisterId::MM5, X86::MM5},
231 {codeview::RegisterId::MM6, X86::MM6},
232 {codeview::RegisterId::MM7, X86::MM7},
234 {codeview::RegisterId::XMM0, X86::XMM0},
235 {codeview::RegisterId::XMM1, X86::XMM1},
236 {codeview::RegisterId::XMM2, X86::XMM2},
237 {codeview::RegisterId::XMM3, X86::XMM3},
238 {codeview::RegisterId::XMM4, X86::XMM4},
239 {codeview::RegisterId::XMM5, X86::XMM5},
240 {codeview::RegisterId::XMM6, X86::XMM6},
241 {codeview::RegisterId::XMM7, X86::XMM7},
243 {codeview::RegisterId::XMM8, X86::XMM8},
244 {codeview::RegisterId::XMM9, X86::XMM9},
245 {codeview::RegisterId::XMM10, X86::XMM10},
246 {codeview::RegisterId::XMM11, X86::XMM11},
247 {codeview::RegisterId::XMM12, X86::XMM12},
248 {codeview::RegisterId::XMM13, X86::XMM13},
249 {codeview::RegisterId::XMM14, X86::XMM14},
250 {codeview::RegisterId::XMM15, X86::XMM15},
252 {codeview::RegisterId::SIL, X86::SIL},
253 {codeview::RegisterId::DIL, X86::DIL},
254 {codeview::RegisterId::BPL, X86::BPL},
255 {codeview::RegisterId::SPL, X86::SPL},
256 {codeview::RegisterId::RAX, X86::RAX},
257 {codeview::RegisterId::RBX, X86::RBX},
258 {codeview::RegisterId::RCX, X86::RCX},
259 {codeview::RegisterId::RDX, X86::RDX},
260 {codeview::RegisterId::RSI, X86::RSI},
261 {codeview::RegisterId::RDI, X86::RDI},
262 {codeview::RegisterId::RBP, X86::RBP},
263 {codeview::RegisterId::RSP, X86::RSP},
264 {codeview::RegisterId::R8, X86::R8},
265 {codeview::RegisterId::R9, X86::R9},
266 {codeview::RegisterId::R10, X86::R10},
267 {codeview::RegisterId::R11, X86::R11},
268 {codeview::RegisterId::R12, X86::R12},
269 {codeview::RegisterId::R13, X86::R13},
270 {codeview::RegisterId::R14, X86::R14},
271 {codeview::RegisterId::R15, X86::R15},
272 {codeview::RegisterId::R8B, X86::R8B},
273 {codeview::RegisterId::R9B, X86::R9B},
274 {codeview::RegisterId::R10B, X86::R10B},
275 {codeview::RegisterId::R11B, X86::R11B},
276 {codeview::RegisterId::R12B, X86::R12B},
277 {codeview::RegisterId::R13B, X86::R13B},
278 {codeview::RegisterId::R14B, X86::R14B},
279 {codeview::RegisterId::R15B, X86::R15B},
280 {codeview::RegisterId::R8W, X86::R8W},
281 {codeview::RegisterId::R9W, X86::R9W},
282 {codeview::RegisterId::R10W, X86::R10W},
283 {codeview::RegisterId::R11W, X86::R11W},
284 {codeview::RegisterId::R12W, X86::R12W},
285 {codeview::RegisterId::R13W, X86::R13W},
286 {codeview::RegisterId::R14W, X86::R14W},
287 {codeview::RegisterId::R15W, X86::R15W},
288 {codeview::RegisterId::R8D, X86::R8D},
289 {codeview::RegisterId::R9D, X86::R9D},
290 {codeview::RegisterId::R10D, X86::R10D},
291 {codeview::RegisterId::R11D, X86::R11D},
292 {codeview::RegisterId::R12D, X86::R12D},
293 {codeview::RegisterId::R13D, X86::R13D},
294 {codeview::RegisterId::R14D, X86::R14D},
295 {codeview::RegisterId::R15D, X86::R15D},
296 {codeview::RegisterId::AMD64_YMM0, X86::YMM0},
297 {codeview::RegisterId::AMD64_YMM1, X86::YMM1},
298 {codeview::RegisterId::AMD64_YMM2, X86::YMM2},
299 {codeview::RegisterId::AMD64_YMM3, X86::YMM3},
300 {codeview::RegisterId::AMD64_YMM4, X86::YMM4},
301 {codeview::RegisterId::AMD64_YMM5, X86::YMM5},
302 {codeview::RegisterId::AMD64_YMM6, X86::YMM6},
303 {codeview::RegisterId::AMD64_YMM7, X86::YMM7},
304 {codeview::RegisterId::AMD64_YMM8, X86::YMM8},
305 {codeview::RegisterId::AMD64_YMM9, X86::YMM9},
306 {codeview::RegisterId::AMD64_YMM10, X86::YMM10},
307 {codeview::RegisterId::AMD64_YMM11, X86::YMM11},
308 {codeview::RegisterId::AMD64_YMM12, X86::YMM12},
309 {codeview::RegisterId::AMD64_YMM13, X86::YMM13},
310 {codeview::RegisterId::AMD64_YMM14, X86::YMM14},
311 {codeview::RegisterId::AMD64_YMM15, X86::YMM15},
312 {codeview::RegisterId::AMD64_YMM16, X86::YMM16},
313 {codeview::RegisterId::AMD64_YMM17, X86::YMM17},
314 {codeview::RegisterId::AMD64_YMM18, X86::YMM18},
315 {codeview::RegisterId::AMD64_YMM19, X86::YMM19},
316 {codeview::RegisterId::AMD64_YMM20, X86::YMM20},
317 {codeview::RegisterId::AMD64_YMM21, X86::YMM21},
318 {codeview::RegisterId::AMD64_YMM22, X86::YMM22},
319 {codeview::RegisterId::AMD64_YMM23, X86::YMM23},
320 {codeview::RegisterId::AMD64_YMM24, X86::YMM24},
321 {codeview::RegisterId::AMD64_YMM25, X86::YMM25},
322 {codeview::RegisterId::AMD64_YMM26, X86::YMM26},
323 {codeview::RegisterId::AMD64_YMM27, X86::YMM27},
324 {codeview::RegisterId::AMD64_YMM28, X86::YMM28},
325 {codeview::RegisterId::AMD64_YMM29, X86::YMM29},
326 {codeview::RegisterId::AMD64_YMM30, X86::YMM30},
327 {codeview::RegisterId::AMD64_YMM31, X86::YMM31},
328 {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0},
329 {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1},
330 {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2},
331 {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3},
332 {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4},
333 {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5},
334 {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6},
335 {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7},
336 {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8},
337 {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9},
338 {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10},
339 {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11},
340 {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12},
341 {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13},
342 {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14},
343 {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15},
344 {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16},
345 {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17},
346 {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18},
347 {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19},
348 {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20},
349 {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21},
350 {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22},
351 {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23},
352 {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24},
353 {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25},
354 {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26},
355 {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27},
356 {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28},
357 {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29},
358 {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30},
359 {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31},
360 {codeview::RegisterId::AMD64_K0, X86::K0},
361 {codeview::RegisterId::AMD64_K1, X86::K1},
362 {codeview::RegisterId::AMD64_K2, X86::K2},
363 {codeview::RegisterId::AMD64_K3, X86::K3},
364 {codeview::RegisterId::AMD64_K4, X86::K4},
365 {codeview::RegisterId::AMD64_K5, X86::K5},
366 {codeview::RegisterId::AMD64_K6, X86::K6},
367 {codeview::RegisterId::AMD64_K7, X86::K7},
368 {codeview::RegisterId::AMD64_XMM16, X86::XMM16},
369 {codeview::RegisterId::AMD64_XMM17, X86::XMM17},
370 {codeview::RegisterId::AMD64_XMM18, X86::XMM18},
371 {codeview::RegisterId::AMD64_XMM19, X86::XMM19},
372 {codeview::RegisterId::AMD64_XMM20, X86::XMM20},
373 {codeview::RegisterId::AMD64_XMM21, X86::XMM21},
374 {codeview::RegisterId::AMD64_XMM22, X86::XMM22},
375 {codeview::RegisterId::AMD64_XMM23, X86::XMM23},
376 {codeview::RegisterId::AMD64_XMM24, X86::XMM24},
377 {codeview::RegisterId::AMD64_XMM25, X86::XMM25},
378 {codeview::RegisterId::AMD64_XMM26, X86::XMM26},
379 {codeview::RegisterId::AMD64_XMM27, X86::XMM27},
380 {codeview::RegisterId::AMD64_XMM28, X86::XMM28},
381 {codeview::RegisterId::AMD64_XMM29, X86::XMM29},
382 {codeview::RegisterId::AMD64_XMM30, X86::XMM30},
383 {codeview::RegisterId::AMD64_XMM31, X86::XMM31},
386 for (
const auto &
I : RegMap)
387 MRI->mapLLVMRegToCVReg(
I.Reg,
static_cast<int>(
I.CVReg));
393 assert(!ArchFS.empty() &&
"Failed to parse X86 triple");
395 ArchFS = (
Twine(ArchFS) +
"," + FS).str();
400 return createX86MCSubtargetInfoImpl(TT, CPU, CPU, ArchFS);
405 InitX86MCInstrInfo(
X);
437 if (
Options.getAssemblyLanguage().equals_insensitive(
"masm"))
451 int stackGrowth =
is64Bit ? -8 : -4;
454 unsigned StackPtr =
is64Bit ? X86::RSP : X86::ESP;
456 nullptr,
MRI.getDwarfRegNum(StackPtr,
true), -stackGrowth);
460 unsigned InstPtr =
is64Bit ? X86::RIP : X86::EIP;
462 nullptr,
MRI.getDwarfRegNum(InstPtr,
true), stackGrowth);
469 unsigned SyntaxVariant,
473 if (SyntaxVariant == 0)
475 if (SyntaxVariant == 1)
497#define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
498#include "X86GenSubtargetInfo.inc"
501 APInt &Mask)
const override;
502 std::vector<std::pair<uint64_t, uint64_t>>
505 const Triple &TargetTriple)
const override;
509 std::optional<uint64_t>
512 std::optional<uint64_t>
517#define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
518#include "X86GenSubtargetInfo.inc"
526 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
527 "Unexpected number of bits in the mask!");
537 auto ClearsSuperReg = [=](
unsigned RegID) {
546 if (!HasEVEX && !HasVEX && !HasXOP)
557 for (
unsigned I = 0,
E = NumDefs;
I <
E; ++
I) {
559 if (ClearsSuperReg(Op.getReg()))
563 for (
unsigned I = 0,
E = NumImplicitDefs;
I <
E; ++
I) {
565 if (ClearsSuperReg(Reg))
566 Mask.setBit(NumDefs +
I);
569 return Mask.getBoolValue();
572static std::vector<std::pair<uint64_t, uint64_t>>
576 std::vector<std::pair<uint64_t, uint64_t>> Result;
577 for (
uint64_t Byte = 0, End = PltContents.
size(); Byte + 6 < End; ) {
579 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) {
584 std::make_pair(PltSectionVA + Byte, GotPltSectionVA + Imm));
586 }
else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
590 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
598static std::vector<std::pair<uint64_t, uint64_t>>
601 std::vector<std::pair<uint64_t, uint64_t>> Result;
602 for (
uint64_t Byte = 0, End = PltContents.
size(); Byte + 6 < End; ) {
604 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
609 std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm));
620 switch (TargetTriple.
getArch()) {
645 if (MemOpStart == -1)
659 if (BaseReg.
getReg() == X86::RIP)
665std::optional<uint64_t>
672 if (MemOpStart == -1)
681 if (BaseReg.
getReg() != X86::RIP || SegReg.
getReg() != 0 ||
685 assert(
Size > 4 &&
"invalid instruction size for rip-relative lea");
752 default:
return X86::NoRegister;
753 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
755 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
757 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
759 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
764 default:
return X86::NoRegister;
765 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
767 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
769 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
771 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
773 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
775 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
777 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
779 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
781 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
783 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
785 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
787 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
789 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
791 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
793 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
795 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
801 default:
return X86::NoRegister;
802 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
804 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
806 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
808 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
810 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
812 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
814 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
816 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
818 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
820 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
822 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
824 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
826 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
828 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
830 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
832 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
837 default:
return X86::NoRegister;
838 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
840 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
842 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
844 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
846 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
848 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
850 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
852 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
854 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
856 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
858 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
860 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
862 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
864 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
866 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
868 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
873 default:
return X86::NoRegister;
874 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
876 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
878 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
880 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
882 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
884 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
886 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
888 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
890 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
892 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
894 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
896 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
898 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
900 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
902 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
904 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
unsigned const MachineRegisterInfo * MRI
This file implements a class to represent arbitrary precision integral constant values and operations...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
static bool is64Bit(const char *name)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86TargetMC()
static MCRelocationInfo * createX86MCRelocationInfo(const Triple &TheTriple, MCContext &Ctx)
static MCInstrInfo * createX86MCInstrInfo()
static MCRegisterInfo * createX86MCRegisterInfo(const Triple &TT)
static MCInstPrinter * createX86MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static MCInstrAnalysis * createX86MCInstrAnalysis(const MCInstrInfo *Info)
static MCAsmInfo * createX86MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID)
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
This class is intended to be used as a base class for asm properties and features specific to the tar...
void addInitialFrameState(const MCCFIInstruction &Inst)
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Context object for machine code objects.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
MCRegisterClass - Base class of TargetRegisterClass.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Create MCExprs from relocations found in an object file.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
bool isWindowsCoreCLREnvironment() const
ArchType getArch() const
Get the parsed architecture type of this triple.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
bool isWindowsItaniumEnvironment() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const override
Given a branch instruction try to get the address the branch targets.
X86MCInstrAnalysis(const MCInstrInfo *MCII)
std::vector< std::pair< uint64_t, uint64_t > > findPltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotSectionVA, const Triple &TargetTriple) const override
Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
std::optional< uint64_t > evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, uint64_t Size) const override
Given an instruction tries to get the address of a memory operand.
std::optional< uint64_t > getMemoryOperandRelocationOffset(const MCInst &Inst, uint64_t Size) const override
Given an instruction with a memory operand that could require relocation, returns the offset within t...
bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Mask) const override
Returns true if at least one of the register writes performed by.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
@ RawFrmDst
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI.
@ XOP
XOP - Opcode prefix used by XOP instructions.
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
int getMemoryOperandNo(uint64_t TSFlags)
The function returns the MCInst operand # for the first field of the memory operand.
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
bool is32BitMemOperand(const MCInst &MI, unsigned Op)
bool is16BitMemOperand(const MCInst &MI, unsigned Op, const MCSubtargetInfo &STI)
bool hasLockPrefix(const MCInst &MI)
Returns true if this instruction has a LOCK prefix.
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
static std::vector< std::pair< uint64_t, uint64_t > > findX86PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotPltSectionVA)
static std::vector< std::pair< uint64_t, uint64_t > > findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents)
bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)
Returns true if this instruction needs an Address-Size override prefix.
std::string ParseX86Triple(const Triple &TT)
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
bool is64BitMemOperand(const MCInst &MI, unsigned Op)
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
uint32_t read32le(const void *P)
This is an optimization pass for GlobalISel generic memory operations.
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Target & getTheX86_32Target()
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files.
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrinter, bool IsVerboseAsm)
Implements X86-only directives for assembly emission.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target & getTheX86_64Target()
MCTargetStreamer * createX86NullTargetStreamer(MCStreamer &S)
Implements X86-only null emission.
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target.