LLVM  14.0.0git
X86TargetParser.cpp
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1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise X86 hardware features.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Triple.h"
16 #include <numeric>
17 
18 using namespace llvm;
19 using namespace llvm::X86;
20 
21 namespace {
22 
23 /// Container class for CPU features.
24 /// This is a constexpr reimplementation of a subset of std::bitset. It would be
25 /// nice to use std::bitset directly, but it doesn't support constant
26 /// initialization.
27 class FeatureBitset {
28  static constexpr unsigned NUM_FEATURE_WORDS =
29  (X86::CPU_FEATURE_MAX + 31) / 32;
30 
31  // This cannot be a std::array, operator[] is not constexpr until C++17.
32  uint32_t Bits[NUM_FEATURE_WORDS] = {};
33 
34 public:
35  constexpr FeatureBitset() = default;
36  constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
37  for (auto I : Init)
38  set(I);
39  }
40 
41  bool any() const {
42  return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
43  }
44 
45  constexpr FeatureBitset &set(unsigned I) {
46  // GCC <6.2 crashes if this is written in a single statement.
47  uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
48  Bits[I / 32] = NewBits;
49  return *this;
50  }
51 
52  constexpr bool operator[](unsigned I) const {
53  uint32_t Mask = uint32_t(1) << (I % 32);
54  return (Bits[I / 32] & Mask) != 0;
55  }
56 
57  constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
58  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
59  // GCC <6.2 crashes if this is written in a single statement.
60  uint32_t NewBits = Bits[I] & RHS.Bits[I];
61  Bits[I] = NewBits;
62  }
63  return *this;
64  }
65 
66  constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
67  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
68  // GCC <6.2 crashes if this is written in a single statement.
69  uint32_t NewBits = Bits[I] | RHS.Bits[I];
70  Bits[I] = NewBits;
71  }
72  return *this;
73  }
74 
75  // gcc 5.3 miscompiles this if we try to write this using operator&=.
76  constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
78  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
79  Result.Bits[I] = Bits[I] & RHS.Bits[I];
80  return Result;
81  }
82 
83  // gcc 5.3 miscompiles this if we try to write this using operator&=.
84  constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
86  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
87  Result.Bits[I] = Bits[I] | RHS.Bits[I];
88  return Result;
89  }
90 
91  constexpr FeatureBitset operator~() const {
93  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
94  Result.Bits[I] = ~Bits[I];
95  return Result;
96  }
97 
98  constexpr bool operator!=(const FeatureBitset &RHS) const {
99  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
100  if (Bits[I] != RHS.Bits[I])
101  return true;
102  return false;
103  }
104 };
105 
106 struct ProcInfo {
109  unsigned KeyFeature;
110  FeatureBitset Features;
111 };
112 
113 struct FeatureInfo {
115  FeatureBitset ImpliedFeatures;
116 };
117 
118 } // end anonymous namespace
119 
120 #define X86_FEATURE(ENUM, STRING) \
121  constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
122 #include "llvm/Support/X86TargetParser.def"
123 
124 // Pentium with MMX.
126  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
127 
128 // Pentium 2 and 3.
130  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
132 
133 // Pentium 4 CPUs
137  FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
138 
139 // Basic 64-bit capable CPU.
140 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
141 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
142  FeaturePOPCNT | FeatureCRC32 |
143  FeatureSSE4_2 | FeatureCMPXCHG16B;
145  FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
146  FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
148  FeatureAVX512BW | FeatureAVX512CD |
149  FeatureAVX512DQ | FeatureAVX512VL;
150 
151 // Intel Core CPUs
153  FeaturesNocona | FeatureSAHF | FeatureSSSE3;
154 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
156  FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
157 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
159  FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
161  FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
163  FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
164  FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
166  FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
167 
168 // Intel Knights Landing and Knights Mill
169 // Knights Landing has feature parity with Broadwell.
171  FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
172  FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
173 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
174 
175 // Intel Skylake processors.
177  FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
178  FeatureXSAVES | FeatureSGX;
179 // SkylakeServer inherits all SkylakeClient features except SGX.
180 // FIXME: That doesn't match gcc.
182  (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
183  FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
184  FeaturePKU;
186  FeaturesSkylakeServer | FeatureAVX512VNNI;
188  FeaturesCascadeLake | FeatureAVX512BF16;
189 
190 // Intel 10nm processors.
192  FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
193  FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
194  FeaturePKU | FeatureSHA;
196  FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
197  FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
198  FeatureVAES | FeatureVPCLMULQDQ;
201  FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
203  FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
204  FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
206  FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
207  FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVX512VP2INTERSECT |
208  FeatureAVXVNNI | FeatureCLDEMOTE | FeatureENQCMD | FeatureMOVDIR64B |
209  FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE | FeatureSHSTK |
210  FeatureTSXLDTRK | FeatureUINTR | FeatureWAITPKG;
211 
212 // Intel Atom processors.
213 // Bonnell has feature parity with Core2 and adds MOVBE.
214 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
215 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
217  FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
219  FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
220  FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
221  FeatureXSAVEOPT | FeatureXSAVES;
223  FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
225  FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
227  FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
228  FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
229  FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
230  FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
231  FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
232 
233 // Geode Processor.
235  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
236 
237 // K6 processor.
238 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
239 
240 // K7 and K8 architecture processors.
242  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
244  FeaturesAthlon | FeatureFXSR | FeatureSSE;
246  FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
247 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
249  FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
250  FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
251 
252 // Bobcat architecture processors.
254  FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
255  FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
256  FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
257  FeatureSAHF;
259  FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
260  FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
261 
262 // AMD Bulldozer architecture processors.
264  FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
265  FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
266  FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
267  FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
268  FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
269  FeatureXOP | FeatureXSAVE;
271  FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
273  FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
274 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
275  FeatureBMI2 | FeatureMOVBE |
276  FeatureMWAITX | FeatureRDRND;
277 
278 // AMD Zen architecture processors.
280  FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
281  FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
282  FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
283  FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
284  FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
285  FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
286  FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
287  FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
288  FeatureXSAVEOPT | FeatureXSAVES;
290  FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
292  FeatureINVPCID | FeaturePKU |
293  FeatureVAES | FeatureVPCLMULQDQ;
294 
295 constexpr ProcInfo Processors[] = {
296  // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
297  { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
298  // i386-generation processors.
299  { {"i386"}, CK_i386, ~0U, FeatureX87 },
300  // i486-generation processors.
301  { {"i486"}, CK_i486, ~0U, FeatureX87 },
302  { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
303  { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
304  { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
305  // i586-generation processors, P5 microarchitecture based.
306  { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
307  { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
308  { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
309  // i686-generation processors, P6 / Pentium M microarchitecture based.
310  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
311  { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
312  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
313  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
314  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
315  { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
316  { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
317  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
318  // Netburst microarchitecture based processors.
319  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
320  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
321  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
322  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
323  // Core microarchitecture based processors.
324  { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
325  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
326  // Atom processors
327  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
328  { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
329  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
330  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
331  { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
332  { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
333  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
334  // Nehalem microarchitecture based processors.
335  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
336  { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
337  // Westmere microarchitecture based processors.
338  { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
339  // Sandy Bridge microarchitecture based processors.
340  { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
341  { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
342  // Ivy Bridge microarchitecture based processors.
343  { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
344  { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
345  // Haswell microarchitecture based processors.
346  { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
347  { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
348  // Broadwell microarchitecture based processors.
349  { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
350  // Skylake client microarchitecture based processors.
351  { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
352  // Skylake server microarchitecture based processors.
353  { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
354  { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
355  // Cascadelake Server microarchitecture based processors.
356  { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
357  // Cooperlake Server microarchitecture based processors.
358  { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
359  // Cannonlake client microarchitecture based processors.
360  { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
361  // Icelake client microarchitecture based processors.
362  { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
363  // Rocketlake microarchitecture based processors.
364  { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake },
365  // Icelake server microarchitecture based processors.
366  { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
367  // Tigerlake microarchitecture based processors.
368  { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
369  // Sapphire Rapids microarchitecture based processors.
370  { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
371  // Alderlake microarchitecture based processors.
372  { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
373  // Knights Landing processor.
374  { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
375  // Knights Mill processor.
376  { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
377  // Lakemont microarchitecture based processors.
378  { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
379  // K6 architecture processors.
380  { {"k6"}, CK_K6, ~0U, FeaturesK6 },
381  { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
382  { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
383  // K7 architecture processors.
384  { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
385  { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
386  { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
387  { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
388  { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
389  // K8 architecture processors.
390  { {"k8"}, CK_K8, ~0U, FeaturesK8 },
391  { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
392  { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
393  { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
394  { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
395  { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
396  { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
397  { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
398  { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
399  // Bobcat architecture processors.
400  { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
401  { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
402  // Bulldozer architecture processors.
403  { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
404  { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
405  { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
406  { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
407  // Zen architecture processors.
408  { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
409  { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
410  { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 },
411  // Generic 64-bit processor.
412  { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
413  { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
414  { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
415  { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
416  // Geode processors.
417  { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
418 };
419 
420 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
421 
423  for (const auto &P : Processors)
424  if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
425  return P.Kind;
426 
427  return CK_None;
428 }
429 
431  if (llvm::is_contained(NoTuneList, CPU))
432  return CK_None;
433  return parseArchX86(CPU, Only64Bit);
434 }
435 
437  bool Only64Bit) {
438  for (const auto &P : Processors)
439  if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
440  Values.emplace_back(P.Name);
441 }
442 
444  bool Only64Bit) {
445  for (const ProcInfo &P : Processors)
446  if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) &&
448  Values.emplace_back(P.Name);
449 }
450 
452  // FIXME: Can we avoid a linear search here? The table might be sorted by
453  // CPUKind so we could binary search?
454  for (const auto &P : Processors) {
455  if (P.Kind == Kind) {
456  assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
457  return static_cast<ProcessorFeatures>(P.KeyFeature);
458  }
459  }
460 
461  llvm_unreachable("Unable to find CPU kind!");
462 }
463 
464 // Features with no dependencies.
509 
510 // Not really CPU features, but need to be in the table because clang uses
511 // target features to communicate them to the backend.
517 
518 // XSAVE features are dependent on basic XSAVE.
519 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
520 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
521 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
522 
523 // MMX->3DNOW->3DNOWA chain.
525 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
526 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
527 
528 // SSE/AVX/AVX512F chain.
530 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
531 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
532 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
533 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
534 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
535 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
536 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
538  FeatureAVX2 | FeatureF16C | FeatureFMA;
539 
540 // Vector extensions that build on SSE or AVX.
541 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
542 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
543 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
544 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
545 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
546 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
547 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
548 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
549 
550 // AVX512 features.
551 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
552 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
553 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
554 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
555 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
556 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
557 
558 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
559 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
560 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
561 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
563 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
564 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
566 
567 // FIXME: These two aren't really implemented and just exist in the feature
568 // list for __builtin_cpu_supports. So omit their dependencies.
571 
572 // SSE4_A->FMA4->XOP chain.
573 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
574 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
575 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
576 
577 // AMX Features
579 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
580 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
582 
584  FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
585 // Key Locker Features
586 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
587 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
588 
589 // AVXVNNI Features
590 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
591 
592 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
593 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
594 #include "llvm/Support/X86TargetParser.def"
595 };
596 
598  SmallVectorImpl<StringRef> &EnabledFeatures) {
599  auto I = llvm::find_if(Processors,
600  [&](const ProcInfo &P) { return P.Name == CPU; });
601  assert(I != std::end(Processors) && "Processor not found!");
602 
603  FeatureBitset Bits = I->Features;
604 
605  // Remove the 64-bit feature which we only use to validate if a CPU can
606  // be used with 64-bit mode.
607  Bits &= ~Feature64BIT;
608 
609  // Add the string version of all set bits.
610  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
611  if (Bits[i] && !FeatureInfos[i].Name.empty())
612  EnabledFeatures.push_back(FeatureInfos[i].Name);
613 }
614 
615 // For each feature that is (transitively) implied by this feature, set it.
617  const FeatureBitset &Implies) {
618  // Fast path: Implies is often empty.
619  if (!Implies.any())
620  return;
621  FeatureBitset Prev;
622  Bits |= Implies;
623  do {
624  Prev = Bits;
625  for (unsigned i = CPU_FEATURE_MAX; i;)
626  if (Bits[--i])
627  Bits |= FeatureInfos[i].ImpliedFeatures;
628  } while (Prev != Bits);
629 }
630 
631 /// Create bit vector of features that are implied disabled if the feature
632 /// passed in Value is disabled.
634  // Check all features looking for any dependent on this feature. If we find
635  // one, mark it and recursively find any feature that depend on it.
636  FeatureBitset Prev;
637  Bits.set(Value);
638  do {
639  Prev = Bits;
640  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
641  if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
642  Bits.set(i);
643  } while (Prev != Bits);
644 }
645 
647  StringRef Feature, bool Enabled,
648  StringMap<bool> &Features) {
649  auto I = llvm::find_if(
650  FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
651  if (I == std::end(FeatureInfos)) {
652  // FIXME: This shouldn't happen, but may not have all features in the table
653  // yet.
654  return;
655  }
656 
657  FeatureBitset ImpliedBits;
658  if (Enabled)
659  getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
660  else
661  getImpliedDisabledFeatures(ImpliedBits,
662  std::distance(std::begin(FeatureInfos), I));
663 
664  // Update the map entry for all implied features.
665  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
666  if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
667  Features[FeatureInfos[i].Name] = Enabled;
668 }
669 
671  // Processor features and mapping to processor feature value.
672  uint64_t FeaturesMask = 0;
673  for (const StringRef &FeatureStr : FeatureStrs) {
674  unsigned Feature = StringSwitch<unsigned>(FeatureStr)
675 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
676  .Case(STR, llvm::X86::FEATURE_##ENUM)
677 #include "llvm/Support/X86TargetParser.def"
678  ;
679  FeaturesMask |= (1ULL << Feature);
680  }
681  return FeaturesMask;
682 }
683 
685 #ifndef NDEBUG
686  // Check that priorities are set properly in the .def file. We expect that
687  // "compat" features are assigned non-duplicate consecutive priorities
688  // starting from zero (0, 1, ..., num_features - 1).
689 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
690  unsigned Priorities[] = {
691 #include "llvm/Support/X86TargetParser.def"
692  std::numeric_limits<unsigned>::max() // Need to consume last comma.
693  };
694  std::array<unsigned, array_lengthof(Priorities) - 1> HelperList;
695  std::iota(HelperList.begin(), HelperList.end(), 0);
696  assert(std::is_permutation(HelperList.begin(), HelperList.end(),
697  std::begin(Priorities),
698  std::prev(std::end(Priorities))) &&
699  "Priorities don't form consecutive range!");
700 #endif
701 
702  switch (Feat) {
703 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
704  case X86::FEATURE_##ENUM: \
705  return PRIORITY;
706 #include "llvm/Support/X86TargetParser.def"
707  default:
708  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
709  }
710 }
i
i
Definition: README.txt:29
FeaturesBonnell
constexpr FeatureBitset FeaturesBonnell
Definition: X86TargetParser.cpp:214
set
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic and others It is also currently not done for read modify write instructions It is also current not done if the OF or CF flags are needed The shift operators have the complication that when the shift count is EFLAGS is not set
Definition: README.txt:1277
FeaturesZNVER3
static constexpr FeatureBitset FeaturesZNVER3
Definition: X86TargetParser.cpp:291
llvm::X86::CK_Prescott
@ CK_Prescott
Definition: X86TargetParser.h:81
ImpliedFeaturesUINTR
constexpr FeatureBitset ImpliedFeaturesUINTR
Definition: X86TargetParser.cpp:503
ImpliedFeaturesCLZERO
constexpr FeatureBitset ImpliedFeaturesCLZERO
Definition: X86TargetParser.cpp:472
ImpliedFeaturesMOVDIR64B
constexpr FeatureBitset ImpliedFeaturesMOVDIR64B
Definition: X86TargetParser.cpp:485
FeaturesIvyBridge
constexpr FeatureBitset FeaturesIvyBridge
Definition: X86TargetParser.cpp:160
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::X86::CPUKind
CPUKind
Definition: X86TargetParser.h:63
ImpliedFeaturesWBNOINVD
constexpr FeatureBitset ImpliedFeaturesWBNOINVD
Definition: X86TargetParser.cpp:505
ImpliedFeaturesMOVBE
constexpr FeatureBitset ImpliedFeaturesMOVBE
Definition: X86TargetParser.cpp:484
FeaturesPentium3
constexpr FeatureBitset FeaturesPentium3
Definition: X86TargetParser.cpp:131
llvm::X86::CK_IcelakeClient
@ CK_IcelakeClient
Definition: X86TargetParser.h:101
FeaturesPentium2
constexpr FeatureBitset FeaturesPentium2
Definition: X86TargetParser.cpp:129
ImpliedFeaturesSHA
constexpr FeatureBitset ImpliedFeaturesSHA
Definition: X86TargetParser.cpp:546
ImpliedFeaturesAVX512CD
constexpr FeatureBitset ImpliedFeaturesAVX512CD
Definition: X86TargetParser.cpp:551
FeaturesICLServer
constexpr FeatureBitset FeaturesICLServer
Definition: X86TargetParser.cpp:200
llvm::X86::CK_Athlon
@ CK_Athlon
Definition: X86TargetParser.h:113
ImpliedFeaturesTSXLDTRK
constexpr FeatureBitset ImpliedFeaturesTSXLDTRK
Definition: X86TargetParser.cpp:502
llvm::X86::CK_C3_2
@ CK_C3_2
Definition: X86TargetParser.h:78
ImpliedFeaturesLZCNT
constexpr FeatureBitset ImpliedFeaturesLZCNT
Definition: X86TargetParser.cpp:482
FeaturesBroadwell
constexpr FeatureBitset FeaturesBroadwell
Definition: X86TargetParser.cpp:165
ImpliedFeaturesAVX512FP16
static constexpr FeatureBitset ImpliedFeaturesAVX512FP16
Definition: X86TargetParser.cpp:583
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
ImpliedFeaturesAVXVNNI
constexpr FeatureBitset ImpliedFeaturesAVXVNNI
Definition: X86TargetParser.cpp:590
FeaturesPenryn
constexpr FeatureBitset FeaturesPenryn
Definition: X86TargetParser.cpp:154
FeaturesAthlon
constexpr FeatureBitset FeaturesAthlon
Definition: X86TargetParser.cpp:241
ImpliedFeaturesGFNI
constexpr FeatureBitset ImpliedFeaturesGFNI
Definition: X86TargetParser.cpp:544
getImpliedDisabledFeatures
static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value)
Create bit vector of features that are implied disabled if the feature passed in Value is disabled.
Definition: X86TargetParser.cpp:633
getImpliedEnabledFeatures
static void getImpliedEnabledFeatures(FeatureBitset &Bits, const FeatureBitset &Implies)
Definition: X86TargetParser.cpp:616
llvm::X86::CK_BDVER2
@ CK_BDVER2
Definition: X86TargetParser.h:121
llvm::X86::CK_x86_64_v2
@ CK_x86_64_v2
Definition: X86TargetParser.h:128
ImpliedFeaturesCMPXCHG16B
constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B
Definition: X86TargetParser.cpp:474
ImpliedFeaturesMWAITX
constexpr FeatureBitset ImpliedFeaturesMWAITX
Definition: X86TargetParser.cpp:483
FeaturesBDVER3
constexpr FeatureBitset FeaturesBDVER3
Definition: X86TargetParser.cpp:272
ImpliedFeaturesAES
constexpr FeatureBitset ImpliedFeaturesAES
Definition: X86TargetParser.cpp:541
llvm::X86::CK_SkylakeClient
@ CK_SkylakeClient
Definition: X86TargetParser.h:96
llvm::X86::CK_i686
@ CK_i686
Definition: X86TargetParser.h:74
FeaturesNehalem
constexpr FeatureBitset FeaturesNehalem
Definition: X86TargetParser.cpp:155
llvm::X86::CK_PentiumPro
@ CK_PentiumPro
Definition: X86TargetParser.h:73
ImpliedFeatures64BIT
constexpr FeatureBitset ImpliedFeatures64BIT
Definition: X86TargetParser.cpp:465
llvm::X86::CK_SkylakeServer
@ CK_SkylakeServer
Definition: X86TargetParser.h:97
llvm::X86
Define some predicates that are used for node matching.
Definition: X86TargetParser.h:23
ImpliedFeaturesRDRND
constexpr FeatureBitset ImpliedFeaturesRDRND
Definition: X86TargetParser.cpp:494
llvm::X86::CK_K6
@ CK_K6
Definition: X86TargetParser.h:110
FeaturesCore2
constexpr FeatureBitset FeaturesCore2
Definition: X86TargetParser.cpp:152
llvm::X86::CK_KNL
@ CK_KNL
Definition: X86TargetParser.h:107
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::X86::getCpuSupportsMask
uint64_t getCpuSupportsMask(ArrayRef< StringRef > FeatureStrs)
Definition: X86TargetParser.cpp:670
ImpliedFeaturesBMI
constexpr FeatureBitset ImpliedFeaturesBMI
Definition: X86TargetParser.cpp:467
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
llvm::X86::getKeyFeature
ProcessorFeatures getKeyFeature(CPUKind Kind)
Get the key feature prioritizing target multiversioning.
Definition: X86TargetParser.cpp:451
llvm::operator!=
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:1976
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
FeaturesK8
constexpr FeatureBitset FeaturesK8
Definition: X86TargetParser.cpp:245
ImpliedFeaturesXSAVEOPT
constexpr FeatureBitset ImpliedFeaturesXSAVEOPT
Definition: X86TargetParser.cpp:520
llvm::X86::CK_SandyBridge
@ CK_SandyBridge
Definition: X86TargetParser.h:92
ImpliedFeaturesXSAVES
constexpr FeatureBitset ImpliedFeaturesXSAVES
Definition: X86TargetParser.cpp:521
ImpliedFeaturesMOVDIRI
constexpr FeatureBitset ImpliedFeaturesMOVDIRI
Definition: X86TargetParser.cpp:486
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
FeaturesNocona
constexpr FeatureBitset FeaturesNocona
Definition: X86TargetParser.cpp:136
llvm::LegalityPredicates::any
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
Definition: LegalizerInfo.h:241
ImpliedFeaturesAVX512VPOPCNTDQ
constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ
Definition: X86TargetParser.cpp:562
llvm::X86::CK_Nocona
@ CK_Nocona
Definition: X86TargetParser.h:82
llvm::X86::CK_Bonnell
@ CK_Bonnell
Definition: X86TargetParser.h:85
llvm::X86::CK_Lakemont
@ CK_Lakemont
Definition: X86TargetParser.h:109
FeaturesK6
constexpr FeatureBitset FeaturesK6
Definition: X86TargetParser.cpp:238
ImpliedFeaturesVZEROUPPER
constexpr FeatureBitset ImpliedFeaturesVZEROUPPER
Definition: X86TargetParser.cpp:506
ImpliedFeaturesAVX512BW
constexpr FeatureBitset ImpliedFeaturesAVX512BW
Definition: X86TargetParser.cpp:552
llvm::X86::CK_PentiumMMX
@ CK_PentiumMMX
Definition: X86TargetParser.h:72
llvm::X86::CK_GoldmontPlus
@ CK_GoldmontPlus
Definition: X86TargetParser.h:88
llvm::operator&=
bool operator&=(SparseBitVector< ElementSize > *LHS, const SparseBitVector< ElementSize > &RHS)
Definition: SparseBitVector.h:834
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:891
llvm::X86::parseArchX86
CPUKind parseArchX86(StringRef CPU, bool Only64Bit=false)
Parse CPU string into a CPUKind.
Definition: X86TargetParser.cpp:422
llvm::X86::CK_KNM
@ CK_KNM
Definition: X86TargetParser.h:108
llvm::X86::CK_x86_64
@ CK_x86_64
Definition: X86TargetParser.h:127
llvm::X86::CK_None
@ CK_None
Definition: X86TargetParser.h:64
ImpliedFeaturesXOP
constexpr FeatureBitset ImpliedFeaturesXOP
Definition: X86TargetParser.cpp:575
ImpliedFeaturesF16C
constexpr FeatureBitset ImpliedFeaturesF16C
Definition: X86TargetParser.cpp:542
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::X86::CPU_FEATURE_MAX
@ CPU_FEATURE_MAX
Definition: X86TargetParser.h:60
llvm::X86::CK_ZNVER1
@ CK_ZNVER1
Definition: X86TargetParser.h:124
ImpliedFeaturesAVX512BF16
constexpr FeatureBitset ImpliedFeaturesAVX512BF16
Definition: X86TargetParser.cpp:558
llvm::X86::getFeaturePriority
unsigned getFeaturePriority(ProcessorFeatures Feat)
Definition: X86TargetParser.cpp:684
FeaturesZNVER1
constexpr FeatureBitset FeaturesZNVER1
Definition: X86TargetParser.cpp:279
llvm::X86::CK_WinChip2
@ CK_WinChip2
Definition: X86TargetParser.h:68
ImpliedFeaturesCRC32
constexpr FeatureBitset ImpliedFeaturesCRC32
Definition: X86TargetParser.cpp:476
llvm::X86::CK_C3
@ CK_C3
Definition: X86TargetParser.h:69
llvm::X86::fillValidCPUArchList
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid CPU names.
Definition: X86TargetParser.cpp:436
FeaturesPentiumMMX
constexpr FeatureBitset FeaturesPentiumMMX
Definition: X86TargetParser.cpp:125
ImpliedFeaturesSSE2
constexpr FeatureBitset ImpliedFeaturesSSE2
Definition: X86TargetParser.cpp:530
FeaturesICLClient
constexpr FeatureBitset FeaturesICLClient
Definition: X86TargetParser.cpp:195
FeaturesX86_64_V3
constexpr FeatureBitset FeaturesX86_64_V3
Definition: X86TargetParser.cpp:144
ImpliedFeaturesINVPCID
constexpr FeatureBitset ImpliedFeaturesINVPCID
Definition: X86TargetParser.cpp:480
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
ImpliedFeatures3DNOW
constexpr FeatureBitset ImpliedFeatures3DNOW
Definition: X86TargetParser.cpp:525
FeaturesRocketlake
constexpr FeatureBitset FeaturesRocketlake
Definition: X86TargetParser.cpp:199
ImpliedFeaturesAVX512ER
constexpr FeatureBitset ImpliedFeaturesAVX512ER
Definition: X86TargetParser.cpp:554
ImpliedFeaturesXSAVEC
constexpr FeatureBitset ImpliedFeaturesXSAVEC
Definition: X86TargetParser.cpp:519
ImpliedFeaturesFSGSBASE
constexpr FeatureBitset ImpliedFeaturesFSGSBASE
Definition: X86TargetParser.cpp:478
ImpliedFeaturesXSAVE
constexpr FeatureBitset ImpliedFeaturesXSAVE
Definition: X86TargetParser.cpp:508
FeaturesAthlonXP
constexpr FeatureBitset FeaturesAthlonXP
Definition: X86TargetParser.cpp:243
ImpliedFeaturesMMX
constexpr FeatureBitset ImpliedFeaturesMMX
Definition: X86TargetParser.cpp:524
ImpliedFeaturesVAES
constexpr FeatureBitset ImpliedFeaturesVAES
Definition: X86TargetParser.cpp:547
ImpliedFeaturesFMA4
constexpr FeatureBitset ImpliedFeaturesFMA4
Definition: X86TargetParser.cpp:574
ImpliedFeaturesLWP
constexpr FeatureBitset ImpliedFeaturesLWP
Definition: X86TargetParser.cpp:481
ImpliedFeaturesAVX512VNNI
constexpr FeatureBitset ImpliedFeaturesAVX512VNNI
Definition: X86TargetParser.cpp:561
FeaturesPentium4
constexpr FeatureBitset FeaturesPentium4
Definition: X86TargetParser.cpp:134
FeaturesGeode
constexpr FeatureBitset FeaturesGeode
Definition: X86TargetParser.cpp:234
FeaturesTigerlake
constexpr FeatureBitset FeaturesTigerlake
Definition: X86TargetParser.cpp:202
llvm::X86::CK_K8SSE3
@ CK_K8SSE3
Definition: X86TargetParser.h:116
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1392
ImpliedFeaturesENQCMD
constexpr FeatureBitset ImpliedFeaturesENQCMD
Definition: X86TargetParser.cpp:477
ImpliedFeaturesPKU
constexpr FeatureBitset ImpliedFeaturesPKU
Definition: X86TargetParser.cpp:489
llvm::X86::CK_PentiumM
@ CK_PentiumM
Definition: X86TargetParser.h:77
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
FeaturesHaswell
constexpr FeatureBitset FeaturesHaswell
Definition: X86TargetParser.cpp:162
FeaturesCooperLake
constexpr FeatureBitset FeaturesCooperLake
Definition: X86TargetParser.cpp:187
ImpliedFeaturesPTWRITE
constexpr FeatureBitset ImpliedFeaturesPTWRITE
Definition: X86TargetParser.cpp:492
llvm::StringMap< bool >
FeaturesCannonlake
constexpr FeatureBitset FeaturesCannonlake
Definition: X86TargetParser.cpp:191
ImpliedFeaturesAMX_TILE
constexpr FeatureBitset ImpliedFeaturesAMX_TILE
Definition: X86TargetParser.cpp:578
llvm::X86::CK_Nehalem
@ CK_Nehalem
Definition: X86TargetParser.h:90
FeaturesK8SSE3
constexpr FeatureBitset FeaturesK8SSE3
Definition: X86TargetParser.cpp:247
ImpliedFeaturesSSE4_2
constexpr FeatureBitset ImpliedFeaturesSSE4_2
Definition: X86TargetParser.cpp:534
ImpliedFeaturesSGX
constexpr FeatureBitset ImpliedFeaturesSGX
Definition: X86TargetParser.cpp:499
ImpliedFeaturesSSE
constexpr FeatureBitset ImpliedFeaturesSSE
Definition: X86TargetParser.cpp:529
llvm::X86::CK_Cannonlake
@ CK_Cannonlake
Definition: X86TargetParser.h:100
ImpliedFeaturesAVX512F
constexpr FeatureBitset ImpliedFeaturesAVX512F
Definition: X86TargetParser.cpp:537
ImpliedFeaturesPCONFIG
constexpr FeatureBitset ImpliedFeaturesPCONFIG
Definition: X86TargetParser.cpp:487
FeaturesAlderlake
constexpr FeatureBitset FeaturesAlderlake
Definition: X86TargetParser.cpp:226
ImpliedFeaturesWAITPKG
constexpr FeatureBitset ImpliedFeaturesWAITPKG
Definition: X86TargetParser.cpp:504
X86TargetParser.h
llvm::X86::CK_Haswell
@ CK_Haswell
Definition: X86TargetParser.h:94
llvm::AMDGPU::FEATURE_FMA
@ FEATURE_FMA
Definition: TargetParser.h:117
FeaturesX86_64_V2
constexpr FeatureBitset FeaturesX86_64_V2
Definition: X86TargetParser.cpp:141
ImpliedFeaturesFMA
constexpr FeatureBitset ImpliedFeaturesFMA
Definition: X86TargetParser.cpp:543
llvm::operator|
APInt operator|(APInt a, const APInt &b)
Definition: APInt.h:2006
llvm::X86::CK_ZNVER3
@ CK_ZNVER3
Definition: X86TargetParser.h:126
ImpliedFeaturesTBM
constexpr FeatureBitset ImpliedFeaturesTBM
Definition: X86TargetParser.cpp:501
ImpliedFeaturesPREFETCHWT1
constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1
Definition: X86TargetParser.cpp:490
uint64_t
ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES
Definition: X86TargetParser.cpp:513
FeaturesBTVER2
constexpr FeatureBitset FeaturesBTVER2
Definition: X86TargetParser.cpp:258
ImpliedFeaturesAVX512PF
constexpr FeatureBitset ImpliedFeaturesAVX512PF
Definition: X86TargetParser.cpp:555
llvm::X86::CK_BDVER3
@ CK_BDVER3
Definition: X86TargetParser.h:122
ImpliedFeaturesADX
constexpr FeatureBitset ImpliedFeaturesADX
Definition: X86TargetParser.cpp:466
llvm::X86::CK_Pentium
@ CK_Pentium
Definition: X86TargetParser.h:71
llvm::X86::updateImpliedFeatures
void updateImpliedFeatures(StringRef Feature, bool Enabled, StringMap< bool > &Features)
Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature.
Definition: X86TargetParser.cpp:646
FeaturesSapphireRapids
constexpr FeatureBitset FeaturesSapphireRapids
Definition: X86TargetParser.cpp:205
llvm::X86::CK_BDVER4
@ CK_BDVER4
Definition: X86TargetParser.h:123
llvm::X86::CK_AMDFAM10
@ CK_AMDFAM10
Definition: X86TargetParser.h:117
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1614
ImpliedFeaturesCLWB
constexpr FeatureBitset ImpliedFeaturesCLWB
Definition: X86TargetParser.cpp:471
ImpliedFeaturesAVX512VL
constexpr FeatureBitset ImpliedFeaturesAVX512VL
Definition: X86TargetParser.cpp:556
ImpliedFeaturesLVI_CFI
constexpr FeatureBitset ImpliedFeaturesLVI_CFI
Definition: X86TargetParser.cpp:515
FeaturesBDVER4
constexpr FeatureBitset FeaturesBDVER4
Definition: X86TargetParser.cpp:274
ImpliedFeaturesAVX2
constexpr FeatureBitset ImpliedFeaturesAVX2
Definition: X86TargetParser.cpp:536
llvm::X86::getFeaturesForCPU
void getFeaturesForCPU(StringRef CPU, SmallVectorImpl< StringRef > &Features)
Fill in the features that CPU supports into Features.
Definition: X86TargetParser.cpp:597
ImpliedFeaturesAVX512VP2INTERSECT
constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT
Definition: X86TargetParser.cpp:565
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FeaturesGoldmont
constexpr FeatureBitset FeaturesGoldmont
Definition: X86TargetParser.cpp:218
ImpliedFeaturesSHSTK
constexpr FeatureBitset ImpliedFeaturesSHSTK
Definition: X86TargetParser.cpp:500
ImpliedFeaturesFXSR
constexpr FeatureBitset ImpliedFeaturesFXSR
Definition: X86TargetParser.cpp:479
llvm::X86::CK_Westmere
@ CK_Westmere
Definition: X86TargetParser.h:91
llvm::X86::CK_Rocketlake
@ CK_Rocketlake
Definition: X86TargetParser.h:102
llvm::X86::CK_Broadwell
@ CK_Broadwell
Definition: X86TargetParser.h:95
llvm::X86::CK_K8
@ CK_K8
Definition: X86TargetParser.h:115
llvm::X86::CK_WinChipC6
@ CK_WinChipC6
Definition: X86TargetParser.h:67
llvm::X86::CK_BDVER1
@ CK_BDVER1
Definition: X86TargetParser.h:120
Triple.h
ImpliedFeaturesRTM
constexpr FeatureBitset ImpliedFeaturesRTM
Definition: X86TargetParser.cpp:496
llvm::X86::CK_x86_64_v3
@ CK_x86_64_v3
Definition: X86TargetParser.h:129
llvm::X86::CK_SapphireRapids
@ CK_SapphireRapids
Definition: X86TargetParser.h:105
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
ImpliedFeaturesSSE4_1
constexpr FeatureBitset ImpliedFeaturesSSE4_1
Definition: X86TargetParser.cpp:533
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1556
llvm::X86::CK_K6_3
@ CK_K6_3
Definition: X86TargetParser.h:112
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::X86::CK_Silvermont
@ CK_Silvermont
Definition: X86TargetParser.h:86
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::operator|=
bool operator|=(SparseBitVector< ElementSize > &LHS, const SparseBitVector< ElementSize > *RHS)
Definition: SparseBitVector.h:822
ImpliedFeaturesAMX_BF16
constexpr FeatureBitset ImpliedFeaturesAMX_BF16
Definition: X86TargetParser.cpp:579
uint32_t
llvm::X86::CK_Pentium2
@ CK_Pentium2
Definition: X86TargetParser.h:75
FeaturesSilvermont
constexpr FeatureBitset FeaturesSilvermont
Definition: X86TargetParser.cpp:216
FeaturesKNM
constexpr FeatureBitset FeaturesKNM
Definition: X86TargetParser.cpp:173
FeaturesBDVER2
constexpr FeatureBitset FeaturesBDVER2
Definition: X86TargetParser.cpp:270
FeaturesX86_64_V4
constexpr FeatureBitset FeaturesX86_64_V4
Definition: X86TargetParser.cpp:147
ImpliedFeaturesVPCLMULQDQ
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ
Definition: X86TargetParser.cpp:548
ImpliedFeaturesSSE4_A
constexpr FeatureBitset ImpliedFeaturesSSE4_A
Definition: X86TargetParser.cpp:573
llvm::X86::CK_IcelakeServer
@ CK_IcelakeServer
Definition: X86TargetParser.h:103
llvm::X86::ProcessorFeatures
ProcessorFeatures
Definition: X86TargetParser.h:57
llvm::X86::CK_Tigerlake
@ CK_Tigerlake
Definition: X86TargetParser.h:104
llvm::Init
Definition: Record.h:271
ImpliedFeaturesRDSEED
constexpr FeatureBitset ImpliedFeaturesRDSEED
Definition: X86TargetParser.cpp:495
llvm::X86::CK_x86_64_v4
@ CK_x86_64_v4
Definition: X86TargetParser.h:130
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1576
ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK
Definition: X86TargetParser.cpp:512
FeaturesGoldmontPlus
constexpr FeatureBitset FeaturesGoldmontPlus
Definition: X86TargetParser.cpp:222
llvm::operator~
APInt operator~(APInt v)
Unary bitwise complement operator.
Definition: APInt.h:1981
ImpliedFeaturesBMI2
constexpr FeatureBitset ImpliedFeaturesBMI2
Definition: X86TargetParser.cpp:468
llvm::operator&
APInt operator&(APInt a, const APInt &b)
Definition: APInt.h:1986
llvm::X86::CK_BTVER1
@ CK_BTVER1
Definition: X86TargetParser.h:118
ImpliedFeaturesSERIALIZE
constexpr FeatureBitset ImpliedFeaturesSERIALIZE
Definition: X86TargetParser.cpp:498
ImpliedFeaturesLVI_LOAD_HARDENING
constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING
Definition: X86TargetParser.cpp:516
llvm::X86::CK_i486
@ CK_i486
Definition: X86TargetParser.h:66
ImpliedFeaturesAVX512IFMA
constexpr FeatureBitset ImpliedFeaturesAVX512IFMA
Definition: X86TargetParser.cpp:560
FeaturesPrescott
constexpr FeatureBitset FeaturesPrescott
Definition: X86TargetParser.cpp:135
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
ImpliedFeaturesPRFCHW
constexpr FeatureBitset ImpliedFeaturesPRFCHW
Definition: X86TargetParser.cpp:491
FeaturesKNL
constexpr FeatureBitset FeaturesKNL
Definition: X86TargetParser.cpp:170
llvm::X86::CK_K6_2
@ CK_K6_2
Definition: X86TargetParser.h:111
Processors
constexpr ProcInfo Processors[]
Definition: X86TargetParser.cpp:295
ImpliedFeaturesAVX
constexpr FeatureBitset ImpliedFeaturesAVX
Definition: X86TargetParser.cpp:535
Enabled
static bool Enabled
Definition: Statistic.cpp:46
FeaturesZNVER2
constexpr FeatureBitset FeaturesZNVER2
Definition: X86TargetParser.cpp:289
FeaturesSkylakeClient
constexpr FeatureBitset FeaturesSkylakeClient
Definition: X86TargetParser.cpp:176
llvm::X86::CK_Goldmont
@ CK_Goldmont
Definition: X86TargetParser.h:87
llvm::X86::CK_BTVER2
@ CK_BTVER2
Definition: X86TargetParser.h:119
FeaturesWestmere
constexpr FeatureBitset FeaturesWestmere
Definition: X86TargetParser.cpp:157
llvm::X86::CK_ZNVER2
@ CK_ZNVER2
Definition: X86TargetParser.h:125
ImpliedFeaturesCLFLUSHOPT
constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT
Definition: X86TargetParser.cpp:470
FeatureInfos
constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX]
Definition: X86TargetParser.cpp:592
FeaturesCascadeLake
constexpr FeatureBitset FeaturesCascadeLake
Definition: X86TargetParser.cpp:185
StringSwitch.h
ImpliedFeaturesAVX5124FMAPS
constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS
Definition: X86TargetParser.cpp:569
ImpliedFeaturesSSE3
constexpr FeatureBitset ImpliedFeaturesSSE3
Definition: X86TargetParser.cpp:531
FeaturesSkylakeServer
constexpr FeatureBitset FeaturesSkylakeServer
Definition: X86TargetParser.cpp:181
llvm::X86::CK_i586
@ CK_i586
Definition: X86TargetParser.h:70
llvm::X86::CK_Pentium4
@ CK_Pentium4
Definition: X86TargetParser.h:80
llvm::X86::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid -mtune names.
Definition: X86TargetParser.cpp:443
ImpliedFeaturesPOPCNT
constexpr FeatureBitset ImpliedFeaturesPOPCNT
Definition: X86TargetParser.cpp:488
llvm::X86::CK_Core2
@ CK_Core2
Definition: X86TargetParser.h:83
ImpliedFeaturesKL
constexpr FeatureBitset ImpliedFeaturesKL
Definition: X86TargetParser.cpp:586
llvm::X86::parseTuneCPU
CPUKind parseTuneCPU(StringRef CPU, bool Only64Bit=false)
Definition: X86TargetParser.cpp:430
ImpliedFeaturesHRESET
constexpr FeatureBitset ImpliedFeaturesHRESET
Definition: X86TargetParser.cpp:581
FeaturesX86_64
constexpr FeatureBitset FeaturesX86_64
Definition: X86TargetParser.cpp:140
ImpliedFeaturesCLDEMOTE
constexpr FeatureBitset ImpliedFeaturesCLDEMOTE
Definition: X86TargetParser.cpp:469
ImpliedFeaturesX87
constexpr FeatureBitset ImpliedFeaturesX87
Definition: X86TargetParser.cpp:507
llvm::X86::CK_IvyBridge
@ CK_IvyBridge
Definition: X86TargetParser.h:93
ImpliedFeaturesSAHF
constexpr FeatureBitset ImpliedFeaturesSAHF
Definition: X86TargetParser.cpp:497
NoTuneList
constexpr const char * NoTuneList[]
Definition: X86TargetParser.cpp:420
ImpliedFeaturesRETPOLINE_INDIRECT_CALLS
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS
Definition: X86TargetParser.cpp:514
FeaturesAMDFAM10
constexpr FeatureBitset FeaturesAMDFAM10
Definition: X86TargetParser.cpp:248
ImpliedFeaturesAVX512VBMI
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI
Definition: X86TargetParser.cpp:563
ImpliedFeaturesSSSE3
constexpr FeatureBitset ImpliedFeaturesSSSE3
Definition: X86TargetParser.cpp:532
FeaturesTremont
constexpr FeatureBitset FeaturesTremont
Definition: X86TargetParser.cpp:224
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
ImpliedFeaturesAVX5124VNNIW
constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW
Definition: X86TargetParser.cpp:570
llvm::X86::CK_Tremont
@ CK_Tremont
Definition: X86TargetParser.h:89
llvm::X86::CK_Alderlake
@ CK_Alderlake
Definition: X86TargetParser.h:106
ImpliedFeaturesAMX_INT8
constexpr FeatureBitset ImpliedFeaturesAMX_INT8
Definition: X86TargetParser.cpp:580
llvm::SmallVectorImpl< StringRef >
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::X86::CK_Cascadelake
@ CK_Cascadelake
Definition: X86TargetParser.h:98
FeaturesSandyBridge
constexpr FeatureBitset FeaturesSandyBridge
Definition: X86TargetParser.cpp:158
llvm::X86::CK_Penryn
@ CK_Penryn
Definition: X86TargetParser.h:84
ImpliedFeaturesAVX512VBMI2
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2
Definition: X86TargetParser.cpp:564
ImpliedFeaturesAVX512DQ
constexpr FeatureBitset ImpliedFeaturesAVX512DQ
Definition: X86TargetParser.cpp:553
llvm::X86::CK_Cooperlake
@ CK_Cooperlake
Definition: X86TargetParser.h:99
llvm::X86::CK_AthlonXP
@ CK_AthlonXP
Definition: X86TargetParser.h:114
llvm::X86::CK_i386
@ CK_i386
Definition: X86TargetParser.h:65
ImpliedFeaturesCMPXCHG8B
constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B
Definition: X86TargetParser.cpp:475
llvm::FeatureBitset::any
bool any() const
Definition: SubtargetFeature.h:94
llvm::X86::CK_Pentium3
@ CK_Pentium3
Definition: X86TargetParser.h:76
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
FeaturesBDVER1
constexpr FeatureBitset FeaturesBDVER1
Definition: X86TargetParser.cpp:263
ImpliedFeaturesWIDEKL
constexpr FeatureBitset ImpliedFeaturesWIDEKL
Definition: X86TargetParser.cpp:587
ImpliedFeaturesRDPID
constexpr FeatureBitset ImpliedFeaturesRDPID
Definition: X86TargetParser.cpp:493
FeaturesBTVER1
constexpr FeatureBitset FeaturesBTVER1
Definition: X86TargetParser.cpp:253
ImpliedFeaturesAVX512BITALG
constexpr FeatureBitset ImpliedFeaturesAVX512BITALG
Definition: X86TargetParser.cpp:559
ImpliedFeaturesPCLMUL
constexpr FeatureBitset ImpliedFeaturesPCLMUL
Definition: X86TargetParser.cpp:545
ImpliedFeaturesCMOV
constexpr FeatureBitset ImpliedFeaturesCMOV
Definition: X86TargetParser.cpp:473
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:908
llvm::X86::CK_Yonah
@ CK_Yonah
Definition: X86TargetParser.h:79
ImpliedFeatures3DNOWA
constexpr FeatureBitset ImpliedFeatures3DNOWA
Definition: X86TargetParser.cpp:526
llvm::X86::CK_Geode
@ CK_Geode
Definition: X86TargetParser.h:131