LLVM  16.0.0git
X86TargetParser.cpp
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1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise X86 hardware features.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/StringSwitch.h"
15 #include <numeric>
16 
17 using namespace llvm;
18 using namespace llvm::X86;
19 
20 namespace {
21 
22 /// Container class for CPU features.
23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be
24 /// nice to use std::bitset directly, but it doesn't support constant
25 /// initialization.
26 class FeatureBitset {
27  static constexpr unsigned NUM_FEATURE_WORDS =
28  (X86::CPU_FEATURE_MAX + 31) / 32;
29 
30  // This cannot be a std::array, operator[] is not constexpr until C++17.
31  uint32_t Bits[NUM_FEATURE_WORDS] = {};
32 
33 public:
34  constexpr FeatureBitset() = default;
35  constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
36  for (auto I : Init)
37  set(I);
38  }
39 
40  bool any() const {
41  return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
42  }
43 
44  constexpr FeatureBitset &set(unsigned I) {
45  // GCC <6.2 crashes if this is written in a single statement.
46  uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
47  Bits[I / 32] = NewBits;
48  return *this;
49  }
50 
51  constexpr bool operator[](unsigned I) const {
52  uint32_t Mask = uint32_t(1) << (I % 32);
53  return (Bits[I / 32] & Mask) != 0;
54  }
55 
56  constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
57  for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
58  // GCC <6.2 crashes if this is written in a single statement.
59  uint32_t NewBits = Bits[I] & RHS.Bits[I];
60  Bits[I] = NewBits;
61  }
62  return *this;
63  }
64 
65  constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
66  for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
67  // GCC <6.2 crashes if this is written in a single statement.
68  uint32_t NewBits = Bits[I] | RHS.Bits[I];
69  Bits[I] = NewBits;
70  }
71  return *this;
72  }
73 
74  // gcc 5.3 miscompiles this if we try to write this using operator&=.
75  constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
77  for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
78  Result.Bits[I] = Bits[I] & RHS.Bits[I];
79  return Result;
80  }
81 
82  // gcc 5.3 miscompiles this if we try to write this using operator&=.
83  constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
85  for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
86  Result.Bits[I] = Bits[I] | RHS.Bits[I];
87  return Result;
88  }
89 
90  constexpr FeatureBitset operator~() const {
92  for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
93  Result.Bits[I] = ~Bits[I];
94  return Result;
95  }
96 
97  constexpr bool operator!=(const FeatureBitset &RHS) const {
98  for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
99  if (Bits[I] != RHS.Bits[I])
100  return true;
101  return false;
102  }
103 };
104 
105 struct ProcInfo {
108  unsigned KeyFeature;
109  FeatureBitset Features;
110 };
111 
112 struct FeatureInfo {
114  FeatureBitset ImpliedFeatures;
115 };
116 
117 } // end anonymous namespace
118 
119 #define X86_FEATURE(ENUM, STRING) \
120  constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
121 #include "llvm/Support/X86TargetParser.def"
122 
123 // Pentium with MMX.
125  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
126 
127 // Pentium 2 and 3.
129  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
131 
132 // Pentium 4 CPUs
136  FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
137 
138 // Basic 64-bit capable CPU.
139 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
140 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
141  FeaturePOPCNT | FeatureCRC32 |
142  FeatureSSE4_2 | FeatureCMPXCHG16B;
144  FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
145  FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
147  FeatureAVX512BW | FeatureAVX512CD |
148  FeatureAVX512DQ | FeatureAVX512VL;
149 
150 // Intel Core CPUs
152  FeaturesNocona | FeatureSAHF | FeatureSSSE3;
153 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
155  FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
156 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
158  FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
160  FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
162  FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
163  FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
165  FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
166 
167 // Intel Knights Landing and Knights Mill
168 // Knights Landing has feature parity with Broadwell.
170  FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
171  FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
172 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
173 
174 // Intel Skylake processors.
176  FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
177  FeatureXSAVES | FeatureSGX;
178 // SkylakeServer inherits all SkylakeClient features except SGX.
179 // FIXME: That doesn't match gcc.
181  (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
182  FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
183  FeaturePKU;
185  FeaturesSkylakeServer | FeatureAVX512VNNI;
187  FeaturesCascadeLake | FeatureAVX512BF16;
188 
189 // Intel 10nm processors.
191  FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
192  FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
193  FeaturePKU | FeatureSHA;
195  FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
196  FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
197  FeatureVAES | FeatureVPCLMULQDQ;
200  FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
202  FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
203  FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
205  FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
206  FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
207  FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
208  FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
209  FeatureWAITPKG;
211  FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
212 
213 // Intel Atom processors.
214 // Bonnell has feature parity with Core2 and adds MOVBE.
215 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
216 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
218  FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
220  FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
221  FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
222  FeatureXSAVEOPT | FeatureXSAVES;
224  FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
226  FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
228  FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
229  FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
230  FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
231  FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
232  FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
234  FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA |
235  FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
237  FeaturesSierraforest | FeatureRAOINT;
238 
239 // Geode Processor.
241  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
242 
243 // K6 processor.
244 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
245 
246 // K7 and K8 architecture processors.
248  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
250  FeaturesAthlon | FeatureFXSR | FeatureSSE;
252  FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
253 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
255  FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
256  FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
257 
258 // Bobcat architecture processors.
260  FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
261  FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
262  FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
263  FeatureSAHF;
265  FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
266  FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
267 
268 // AMD Bulldozer architecture processors.
270  FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
271  FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
272  FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
273  FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
274  FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
275  FeatureXOP | FeatureXSAVE;
277  FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
279  FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
280 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
281  FeatureBMI2 | FeatureMOVBE |
282  FeatureMWAITX | FeatureRDRND;
283 
284 // AMD Zen architecture processors.
286  FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
287  FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
288  FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
289  FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
290  FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
291  FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
292  FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
293  FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
294  FeatureXSAVEOPT | FeatureXSAVES;
295 constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
296  FeatureRDPID | FeatureRDPRU |
297  FeatureWBNOINVD;
299  FeatureINVPCID | FeaturePKU |
300  FeatureVAES | FeatureVPCLMULQDQ;
301 
302 constexpr ProcInfo Processors[] = {
303  // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
304  { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
305  // i386-generation processors.
306  { {"i386"}, CK_i386, ~0U, FeatureX87 },
307  // i486-generation processors.
308  { {"i486"}, CK_i486, ~0U, FeatureX87 },
309  { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
310  { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
311  { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
312  // i586-generation processors, P5 microarchitecture based.
313  { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
314  { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
315  { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
316  // i686-generation processors, P6 / Pentium M microarchitecture based.
317  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
318  { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
319  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
320  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
321  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
322  { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
323  { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
324  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
325  // Netburst microarchitecture based processors.
326  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
327  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
328  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
329  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
330  // Core microarchitecture based processors.
331  { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2 },
332  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
333  // Atom processors
334  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
335  { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
336  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
337  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
338  { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
339  { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
340  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
341  // Nehalem microarchitecture based processors.
342  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
343  { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
344  // Westmere microarchitecture based processors.
345  { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
346  // Sandy Bridge microarchitecture based processors.
347  { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
348  { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
349  // Ivy Bridge microarchitecture based processors.
350  { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
351  { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
352  // Haswell microarchitecture based processors.
353  { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
354  { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
355  // Broadwell microarchitecture based processors.
356  { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
357  // Skylake client microarchitecture based processors.
358  { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
359  // Skylake server microarchitecture based processors.
360  { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
361  { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
362  // Cascadelake Server microarchitecture based processors.
363  { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
364  // Cooperlake Server microarchitecture based processors.
365  { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
366  // Cannonlake client microarchitecture based processors.
367  { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
368  // Icelake client microarchitecture based processors.
369  { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
370  // Rocketlake microarchitecture based processors.
371  { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake },
372  // Icelake server microarchitecture based processors.
373  { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
374  // Tigerlake microarchitecture based processors.
375  { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
376  // Sapphire Rapids microarchitecture based processors.
377  { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids },
378  // Alderlake microarchitecture based processors.
379  { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
380  // Raptorlake microarchitecture based processors.
381  { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake },
382  // Meteorlake microarchitecture based processors.
383  { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake },
384  // Sierraforest microarchitecture based processors.
385  { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest },
386  // Grandridge microarchitecture based processors.
387  { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge },
388  // Graniterapids microarchitecture based processors.
389  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids },
390  // Knights Landing processor.
391  { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
392  // Knights Mill processor.
393  { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
394  // Lakemont microarchitecture based processors.
395  { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
396  // K6 architecture processors.
397  { {"k6"}, CK_K6, ~0U, FeaturesK6 },
398  { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
399  { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
400  // K7 architecture processors.
401  { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
402  { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
403  { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
404  { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
405  { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
406  // K8 architecture processors.
407  { {"k8"}, CK_K8, ~0U, FeaturesK8 },
408  { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
409  { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
410  { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
411  { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
412  { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
413  { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
414  { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
415  { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
416  // Bobcat architecture processors.
417  { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
418  { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
419  // Bulldozer architecture processors.
420  { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
421  { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
422  { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
423  { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
424  // Zen architecture processors.
425  { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
426  { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
427  { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 },
428  // Generic 64-bit processor.
429  { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
430  { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
431  { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
432  { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
433  // Geode processors.
434  { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
435 };
436 
437 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
438 
440  for (const auto &P : Processors)
441  if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
442  return P.Kind;
443 
444  return CK_None;
445 }
446 
448  if (llvm::is_contained(NoTuneList, CPU))
449  return CK_None;
450  return parseArchX86(CPU, Only64Bit);
451 }
452 
454  bool Only64Bit) {
455  for (const auto &P : Processors)
456  if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
457  Values.emplace_back(P.Name);
458 }
459 
461  bool Only64Bit) {
462  for (const ProcInfo &P : Processors)
463  if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) &&
465  Values.emplace_back(P.Name);
466 }
467 
469  // FIXME: Can we avoid a linear search here? The table might be sorted by
470  // CPUKind so we could binary search?
471  for (const auto &P : Processors) {
472  if (P.Kind == Kind) {
473  assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
474  return static_cast<ProcessorFeatures>(P.KeyFeature);
475  }
476  }
477 
478  llvm_unreachable("Unable to find CPU kind!");
479 }
480 
481 // Features with no dependencies.
527 
528 // Not really CPU features, but need to be in the table because clang uses
529 // target features to communicate them to the backend.
535 
536 // XSAVE features are dependent on basic XSAVE.
537 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
538 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
539 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
540 
541 // MMX->3DNOW->3DNOWA chain.
543 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
544 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
545 
546 // SSE/AVX/AVX512F chain.
548 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
549 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
550 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
551 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
552 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
553 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
554 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
556  FeatureAVX2 | FeatureF16C | FeatureFMA;
557 
558 // Vector extensions that build on SSE or AVX.
559 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
560 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
561 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
562 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
563 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
564 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
565 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
566 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
567 
568 // AVX512 features.
569 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
570 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
571 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
572 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
573 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
574 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
575 
576 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
577 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
578 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
579 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
581 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
582 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
584 
585 // FIXME: These two aren't really implemented and just exist in the feature
586 // list for __builtin_cpu_supports. So omit their dependencies.
589 
590 // SSE4_A->FMA4->XOP chain.
591 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
592 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
593 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
594 
595 // AMX Features
597 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
598 constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
599 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
601 
606 constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
609  FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
610 // Key Locker Features
611 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
612 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
613 
614 // AVXVNNI Features
615 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
616 
617 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
618 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
619 #include "llvm/Support/X86TargetParser.def"
620 };
621 
623  SmallVectorImpl<StringRef> &EnabledFeatures) {
624  auto I = llvm::find_if(Processors,
625  [&](const ProcInfo &P) { return P.Name == CPU; });
626  assert(I != std::end(Processors) && "Processor not found!");
627 
628  FeatureBitset Bits = I->Features;
629 
630  // Remove the 64-bit feature which we only use to validate if a CPU can
631  // be used with 64-bit mode.
632  Bits &= ~Feature64BIT;
633 
634  // Add the string version of all set bits.
635  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
636  if (Bits[i] && !FeatureInfos[i].Name.empty())
637  EnabledFeatures.push_back(FeatureInfos[i].Name);
638 }
639 
640 // For each feature that is (transitively) implied by this feature, set it.
642  const FeatureBitset &Implies) {
643  // Fast path: Implies is often empty.
644  if (!Implies.any())
645  return;
646  FeatureBitset Prev;
647  Bits |= Implies;
648  do {
649  Prev = Bits;
650  for (unsigned i = CPU_FEATURE_MAX; i;)
651  if (Bits[--i])
652  Bits |= FeatureInfos[i].ImpliedFeatures;
653  } while (Prev != Bits);
654 }
655 
656 /// Create bit vector of features that are implied disabled if the feature
657 /// passed in Value is disabled.
659  // Check all features looking for any dependent on this feature. If we find
660  // one, mark it and recursively find any feature that depend on it.
661  FeatureBitset Prev;
662  Bits.set(Value);
663  do {
664  Prev = Bits;
665  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
666  if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
667  Bits.set(i);
668  } while (Prev != Bits);
669 }
670 
672  StringRef Feature, bool Enabled,
673  StringMap<bool> &Features) {
674  auto I = llvm::find_if(
675  FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
676  if (I == std::end(FeatureInfos)) {
677  // FIXME: This shouldn't happen, but may not have all features in the table
678  // yet.
679  return;
680  }
681 
682  FeatureBitset ImpliedBits;
683  if (Enabled)
684  getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
685  else
686  getImpliedDisabledFeatures(ImpliedBits,
687  std::distance(std::begin(FeatureInfos), I));
688 
689  // Update the map entry for all implied features.
690  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
691  if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
692  Features[FeatureInfos[i].Name] = Enabled;
693 }
694 
696  // Processor features and mapping to processor feature value.
697  uint64_t FeaturesMask = 0;
698  for (const StringRef &FeatureStr : FeatureStrs) {
699  unsigned Feature = StringSwitch<unsigned>(FeatureStr)
700 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
701  .Case(STR, llvm::X86::FEATURE_##ENUM)
702 #include "llvm/Support/X86TargetParser.def"
703  ;
704  FeaturesMask |= (1ULL << Feature);
705  }
706  return FeaturesMask;
707 }
708 
710 #ifndef NDEBUG
711  // Check that priorities are set properly in the .def file. We expect that
712  // "compat" features are assigned non-duplicate consecutive priorities
713  // starting from zero (0, 1, ..., num_features - 1).
714 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
715  unsigned Priorities[] = {
716 #include "llvm/Support/X86TargetParser.def"
717  std::numeric_limits<unsigned>::max() // Need to consume last comma.
718  };
719  std::array<unsigned, std::size(Priorities) - 1> HelperList;
720  std::iota(HelperList.begin(), HelperList.end(), 0);
721  assert(std::is_permutation(HelperList.begin(), HelperList.end(),
722  std::begin(Priorities),
723  std::prev(std::end(Priorities))) &&
724  "Priorities don't form consecutive range!");
725 #endif
726 
727  switch (Feat) {
728 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
729  case X86::FEATURE_##ENUM: \
730  return PRIORITY;
731 #include "llvm/Support/X86TargetParser.def"
732  default:
733  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
734  }
735 }
i
i
Definition: README.txt:29
FeaturesBonnell
constexpr FeatureBitset FeaturesBonnell
Definition: X86TargetParser.cpp:215
set
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic and others It is also currently not done for read modify write instructions It is also current not done if the OF or CF flags are needed The shift operators have the complication that when the shift count is EFLAGS is not set
Definition: README.txt:1277
FeaturesZNVER3
static constexpr FeatureBitset FeaturesZNVER3
Definition: X86TargetParser.cpp:298
llvm::X86::CK_Prescott
@ CK_Prescott
Definition: X86TargetParser.h:81
ImpliedFeaturesUINTR
constexpr FeatureBitset ImpliedFeaturesUINTR
Definition: X86TargetParser.cpp:521
ImpliedFeaturesCLZERO
constexpr FeatureBitset ImpliedFeaturesCLZERO
Definition: X86TargetParser.cpp:489
ImpliedFeaturesMOVDIR64B
constexpr FeatureBitset ImpliedFeaturesMOVDIR64B
Definition: X86TargetParser.cpp:502
FeaturesIvyBridge
constexpr FeatureBitset FeaturesIvyBridge
Definition: X86TargetParser.cpp:159
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::X86::CPUKind
CPUKind
Definition: X86TargetParser.h:63
ImpliedFeaturesWBNOINVD
constexpr FeatureBitset ImpliedFeaturesWBNOINVD
Definition: X86TargetParser.cpp:523
ImpliedFeaturesAVXNECONVERT
constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT
Definition: X86TargetParser.cpp:607
FeaturesGraniteRapids
constexpr FeatureBitset FeaturesGraniteRapids
Definition: X86TargetParser.cpp:210
ImpliedFeaturesMOVBE
constexpr FeatureBitset ImpliedFeaturesMOVBE
Definition: X86TargetParser.cpp:501
FeaturesPentium3
constexpr FeatureBitset FeaturesPentium3
Definition: X86TargetParser.cpp:130
llvm::X86::CK_IcelakeClient
@ CK_IcelakeClient
Definition: X86TargetParser.h:101
FeaturesPentium2
constexpr FeatureBitset FeaturesPentium2
Definition: X86TargetParser.cpp:128
ImpliedFeaturesSHA
constexpr FeatureBitset ImpliedFeaturesSHA
Definition: X86TargetParser.cpp:564
ImpliedFeaturesAVX512CD
constexpr FeatureBitset ImpliedFeaturesAVX512CD
Definition: X86TargetParser.cpp:569
FeaturesICLServer
constexpr FeatureBitset FeaturesICLServer
Definition: X86TargetParser.cpp:199
llvm::X86::CK_Athlon
@ CK_Athlon
Definition: X86TargetParser.h:118
ImpliedFeaturesTSXLDTRK
constexpr FeatureBitset ImpliedFeaturesTSXLDTRK
Definition: X86TargetParser.cpp:520
llvm::X86::CK_C3_2
@ CK_C3_2
Definition: X86TargetParser.h:78
ImpliedFeaturesLZCNT
constexpr FeatureBitset ImpliedFeaturesLZCNT
Definition: X86TargetParser.cpp:499
FeaturesBroadwell
constexpr FeatureBitset FeaturesBroadwell
Definition: X86TargetParser.cpp:164
ImpliedFeaturesAVX512FP16
constexpr FeatureBitset ImpliedFeaturesAVX512FP16
Definition: X86TargetParser.cpp:608
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
ImpliedFeaturesAVXVNNI
constexpr FeatureBitset ImpliedFeaturesAVXVNNI
Definition: X86TargetParser.cpp:615
FeaturesPenryn
constexpr FeatureBitset FeaturesPenryn
Definition: X86TargetParser.cpp:153
llvm::X86::CK_Raptorlake
@ CK_Raptorlake
Definition: X86TargetParser.h:107
FeaturesAthlon
constexpr FeatureBitset FeaturesAthlon
Definition: X86TargetParser.cpp:247
ImpliedFeaturesGFNI
constexpr FeatureBitset ImpliedFeaturesGFNI
Definition: X86TargetParser.cpp:562
getImpliedDisabledFeatures
static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value)
Create bit vector of features that are implied disabled if the feature passed in Value is disabled.
Definition: X86TargetParser.cpp:658
getImpliedEnabledFeatures
static void getImpliedEnabledFeatures(FeatureBitset &Bits, const FeatureBitset &Implies)
Definition: X86TargetParser.cpp:641
llvm::X86::CK_BDVER2
@ CK_BDVER2
Definition: X86TargetParser.h:126
llvm::X86::CK_x86_64_v2
@ CK_x86_64_v2
Definition: X86TargetParser.h:133
ImpliedFeaturesCMPXCHG16B
constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B
Definition: X86TargetParser.cpp:491
ImpliedFeaturesMWAITX
constexpr FeatureBitset ImpliedFeaturesMWAITX
Definition: X86TargetParser.cpp:500
FeaturesBDVER3
constexpr FeatureBitset FeaturesBDVER3
Definition: X86TargetParser.cpp:278
ImpliedFeaturesAES
constexpr FeatureBitset ImpliedFeaturesAES
Definition: X86TargetParser.cpp:559
llvm::X86::CK_SkylakeClient
@ CK_SkylakeClient
Definition: X86TargetParser.h:96
llvm::X86::CK_i686
@ CK_i686
Definition: X86TargetParser.h:74
FeaturesNehalem
constexpr FeatureBitset FeaturesNehalem
Definition: X86TargetParser.cpp:154
llvm::X86::CK_PentiumPro
@ CK_PentiumPro
Definition: X86TargetParser.h:73
ImpliedFeatures64BIT
constexpr FeatureBitset ImpliedFeatures64BIT
Definition: X86TargetParser.cpp:482
llvm::X86::CK_SkylakeServer
@ CK_SkylakeServer
Definition: X86TargetParser.h:97
llvm::X86
Define some predicates that are used for node matching.
Definition: X86TargetParser.h:23
ImpliedFeaturesRDRND
constexpr FeatureBitset ImpliedFeaturesRDRND
Definition: X86TargetParser.cpp:512
llvm::X86::CK_K6
@ CK_K6
Definition: X86TargetParser.h:115
FeaturesCore2
constexpr FeatureBitset FeaturesCore2
Definition: X86TargetParser.cpp:151
llvm::X86::CK_KNL
@ CK_KNL
Definition: X86TargetParser.h:112
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::X86::getCpuSupportsMask
uint64_t getCpuSupportsMask(ArrayRef< StringRef > FeatureStrs)
Definition: X86TargetParser.cpp:695
ImpliedFeaturesBMI
constexpr FeatureBitset ImpliedFeaturesBMI
Definition: X86TargetParser.cpp:484
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::X86::getKeyFeature
ProcessorFeatures getKeyFeature(CPUKind Kind)
Get the key feature prioritizing target multiversioning.
Definition: X86TargetParser.cpp:468
llvm::operator!=
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:2012
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
FeaturesK8
constexpr FeatureBitset FeaturesK8
Definition: X86TargetParser.cpp:251
ImpliedFeaturesXSAVEOPT
constexpr FeatureBitset ImpliedFeaturesXSAVEOPT
Definition: X86TargetParser.cpp:538
llvm::X86::CK_SandyBridge
@ CK_SandyBridge
Definition: X86TargetParser.h:92
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
ImpliedFeaturesXSAVES
constexpr FeatureBitset ImpliedFeaturesXSAVES
Definition: X86TargetParser.cpp:539
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
ImpliedFeaturesRAOINT
constexpr FeatureBitset ImpliedFeaturesRAOINT
Definition: X86TargetParser.cpp:604
ImpliedFeaturesCMPCCXADD
constexpr FeatureBitset ImpliedFeaturesCMPCCXADD
Definition: X86TargetParser.cpp:603
ImpliedFeaturesMOVDIRI
constexpr FeatureBitset ImpliedFeaturesMOVDIRI
Definition: X86TargetParser.cpp:503
FeaturesNocona
constexpr FeatureBitset FeaturesNocona
Definition: X86TargetParser.cpp:135
llvm::LegalityPredicates::any
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
Definition: LegalizerInfo.h:241
ImpliedFeaturesAVX512VPOPCNTDQ
constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ
Definition: X86TargetParser.cpp:580
llvm::X86::CK_Nocona
@ CK_Nocona
Definition: X86TargetParser.h:82
llvm::X86::CK_Bonnell
@ CK_Bonnell
Definition: X86TargetParser.h:85
llvm::X86::CK_Lakemont
@ CK_Lakemont
Definition: X86TargetParser.h:114
FeaturesK6
constexpr FeatureBitset FeaturesK6
Definition: X86TargetParser.cpp:244
ImpliedFeaturesVZEROUPPER
constexpr FeatureBitset ImpliedFeaturesVZEROUPPER
Definition: X86TargetParser.cpp:524
ImpliedFeaturesAVX512BW
constexpr FeatureBitset ImpliedFeaturesAVX512BW
Definition: X86TargetParser.cpp:570
llvm::X86::CK_PentiumMMX
@ CK_PentiumMMX
Definition: X86TargetParser.h:72
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::X86::CK_GoldmontPlus
@ CK_GoldmontPlus
Definition: X86TargetParser.h:88
llvm::operator&=
bool operator&=(SparseBitVector< ElementSize > *LHS, const SparseBitVector< ElementSize > &RHS)
Definition: SparseBitVector.h:835
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:845
llvm::X86::parseArchX86
CPUKind parseArchX86(StringRef CPU, bool Only64Bit=false)
Parse CPU string into a CPUKind.
Definition: X86TargetParser.cpp:439
llvm::X86::CK_KNM
@ CK_KNM
Definition: X86TargetParser.h:113
llvm::X86::CK_x86_64
@ CK_x86_64
Definition: X86TargetParser.h:132
llvm::X86::CK_None
@ CK_None
Definition: X86TargetParser.h:64
llvm::X86::CK_Sierraforest
@ CK_Sierraforest
Definition: X86TargetParser.h:109
ImpliedFeaturesXOP
constexpr FeatureBitset ImpliedFeaturesXOP
Definition: X86TargetParser.cpp:593
ImpliedFeaturesF16C
constexpr FeatureBitset ImpliedFeaturesF16C
Definition: X86TargetParser.cpp:560
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::X86::CPU_FEATURE_MAX
@ CPU_FEATURE_MAX
Definition: X86TargetParser.h:60
llvm::X86::CK_ZNVER1
@ CK_ZNVER1
Definition: X86TargetParser.h:129
ImpliedFeaturesAVX512BF16
constexpr FeatureBitset ImpliedFeaturesAVX512BF16
Definition: X86TargetParser.cpp:576
llvm::X86::getFeaturePriority
unsigned getFeaturePriority(ProcessorFeatures Feat)
Definition: X86TargetParser.cpp:709
FeaturesZNVER1
constexpr FeatureBitset FeaturesZNVER1
Definition: X86TargetParser.cpp:285
llvm::X86::CK_WinChip2
@ CK_WinChip2
Definition: X86TargetParser.h:68
ImpliedFeaturesCRC32
constexpr FeatureBitset ImpliedFeaturesCRC32
Definition: X86TargetParser.cpp:493
llvm::X86::CK_C3
@ CK_C3
Definition: X86TargetParser.h:69
llvm::X86::fillValidCPUArchList
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid CPU names.
Definition: X86TargetParser.cpp:453
FeaturesPentiumMMX
constexpr FeatureBitset FeaturesPentiumMMX
Definition: X86TargetParser.cpp:124
ImpliedFeaturesSSE2
constexpr FeatureBitset ImpliedFeaturesSSE2
Definition: X86TargetParser.cpp:548
FeaturesICLClient
constexpr FeatureBitset FeaturesICLClient
Definition: X86TargetParser.cpp:194
FeaturesX86_64_V3
constexpr FeatureBitset FeaturesX86_64_V3
Definition: X86TargetParser.cpp:143
ImpliedFeaturesINVPCID
constexpr FeatureBitset ImpliedFeaturesINVPCID
Definition: X86TargetParser.cpp:497
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
ImpliedFeatures3DNOW
constexpr FeatureBitset ImpliedFeatures3DNOW
Definition: X86TargetParser.cpp:543
FeaturesRocketlake
constexpr FeatureBitset FeaturesRocketlake
Definition: X86TargetParser.cpp:198
ImpliedFeaturesAVX512ER
constexpr FeatureBitset ImpliedFeaturesAVX512ER
Definition: X86TargetParser.cpp:572
ImpliedFeaturesXSAVEC
constexpr FeatureBitset ImpliedFeaturesXSAVEC
Definition: X86TargetParser.cpp:537
ImpliedFeaturesFSGSBASE
constexpr FeatureBitset ImpliedFeaturesFSGSBASE
Definition: X86TargetParser.cpp:495
ImpliedFeaturesXSAVE
constexpr FeatureBitset ImpliedFeaturesXSAVE
Definition: X86TargetParser.cpp:526
FeaturesAthlonXP
constexpr FeatureBitset FeaturesAthlonXP
Definition: X86TargetParser.cpp:249
ImpliedFeaturesMMX
constexpr FeatureBitset ImpliedFeaturesMMX
Definition: X86TargetParser.cpp:542
ImpliedFeaturesVAES
constexpr FeatureBitset ImpliedFeaturesVAES
Definition: X86TargetParser.cpp:565
ImpliedFeaturesFMA4
constexpr FeatureBitset ImpliedFeaturesFMA4
Definition: X86TargetParser.cpp:592
FeaturesGrandridge
constexpr FeatureBitset FeaturesGrandridge
Definition: X86TargetParser.cpp:236
ImpliedFeaturesLWP
constexpr FeatureBitset ImpliedFeaturesLWP
Definition: X86TargetParser.cpp:498
ImpliedFeaturesAVX512VNNI
constexpr FeatureBitset ImpliedFeaturesAVX512VNNI
Definition: X86TargetParser.cpp:579
FeaturesPentium4
constexpr FeatureBitset FeaturesPentium4
Definition: X86TargetParser.cpp:133
FeaturesSierraforest
constexpr FeatureBitset FeaturesSierraforest
Definition: X86TargetParser.cpp:233
FeaturesGeode
constexpr FeatureBitset FeaturesGeode
Definition: X86TargetParser.cpp:240
FeaturesTigerlake
constexpr FeatureBitset FeaturesTigerlake
Definition: X86TargetParser.cpp:201
llvm::X86::CK_K8SSE3
@ CK_K8SSE3
Definition: X86TargetParser.h:121
ImpliedFeaturesENQCMD
constexpr FeatureBitset ImpliedFeaturesENQCMD
Definition: X86TargetParser.cpp:494
ImpliedFeaturesPKU
constexpr FeatureBitset ImpliedFeaturesPKU
Definition: X86TargetParser.cpp:506
llvm::X86::CK_PentiumM
@ CK_PentiumM
Definition: X86TargetParser.h:77
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
FeaturesHaswell
constexpr FeatureBitset FeaturesHaswell
Definition: X86TargetParser.cpp:161
FeaturesCooperLake
constexpr FeatureBitset FeaturesCooperLake
Definition: X86TargetParser.cpp:186
ImpliedFeaturesPTWRITE
constexpr FeatureBitset ImpliedFeaturesPTWRITE
Definition: X86TargetParser.cpp:509
llvm::StringMap< bool >
FeaturesCannonlake
constexpr FeatureBitset FeaturesCannonlake
Definition: X86TargetParser.cpp:190
ImpliedFeaturesAMX_TILE
constexpr FeatureBitset ImpliedFeaturesAMX_TILE
Definition: X86TargetParser.cpp:596
llvm::X86::CK_Nehalem
@ CK_Nehalem
Definition: X86TargetParser.h:90
FeaturesK8SSE3
constexpr FeatureBitset FeaturesK8SSE3
Definition: X86TargetParser.cpp:253
ImpliedFeaturesSSE4_2
constexpr FeatureBitset ImpliedFeaturesSSE4_2
Definition: X86TargetParser.cpp:552
ImpliedFeaturesSGX
constexpr FeatureBitset ImpliedFeaturesSGX
Definition: X86TargetParser.cpp:517
ImpliedFeaturesSSE
constexpr FeatureBitset ImpliedFeaturesSSE
Definition: X86TargetParser.cpp:547
llvm::X86::CK_Cannonlake
@ CK_Cannonlake
Definition: X86TargetParser.h:100
ImpliedFeaturesAVX512F
constexpr FeatureBitset ImpliedFeaturesAVX512F
Definition: X86TargetParser.cpp:555
ImpliedFeaturesPCONFIG
constexpr FeatureBitset ImpliedFeaturesPCONFIG
Definition: X86TargetParser.cpp:504
FeaturesAlderlake
constexpr FeatureBitset FeaturesAlderlake
Definition: X86TargetParser.cpp:227
ImpliedFeaturesWAITPKG
constexpr FeatureBitset ImpliedFeaturesWAITPKG
Definition: X86TargetParser.cpp:522
X86TargetParser.h
llvm::X86::CK_Haswell
@ CK_Haswell
Definition: X86TargetParser.h:94
llvm::AMDGPU::FEATURE_FMA
@ FEATURE_FMA
Definition: TargetParser.h:125
FeaturesX86_64_V2
constexpr FeatureBitset FeaturesX86_64_V2
Definition: X86TargetParser.cpp:140
ImpliedFeaturesFMA
constexpr FeatureBitset ImpliedFeaturesFMA
Definition: X86TargetParser.cpp:561
llvm::operator|
APInt operator|(APInt a, const APInt &b)
Definition: APInt.h:2042
llvm::X86::CK_ZNVER3
@ CK_ZNVER3
Definition: X86TargetParser.h:131
ImpliedFeaturesTBM
constexpr FeatureBitset ImpliedFeaturesTBM
Definition: X86TargetParser.cpp:519
ImpliedFeaturesPREFETCHWT1
constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1
Definition: X86TargetParser.cpp:507
uint64_t
ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES
Definition: X86TargetParser.cpp:531
FeaturesBTVER2
constexpr FeatureBitset FeaturesBTVER2
Definition: X86TargetParser.cpp:264
ImpliedFeaturesAVX512PF
constexpr FeatureBitset ImpliedFeaturesAVX512PF
Definition: X86TargetParser.cpp:573
llvm::X86::CK_BDVER3
@ CK_BDVER3
Definition: X86TargetParser.h:127
ImpliedFeaturesADX
constexpr FeatureBitset ImpliedFeaturesADX
Definition: X86TargetParser.cpp:483
llvm::X86::CK_Pentium
@ CK_Pentium
Definition: X86TargetParser.h:71
llvm::X86::updateImpliedFeatures
void updateImpliedFeatures(StringRef Feature, bool Enabled, StringMap< bool > &Features)
Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature.
Definition: X86TargetParser.cpp:671
FeaturesSapphireRapids
constexpr FeatureBitset FeaturesSapphireRapids
Definition: X86TargetParser.cpp:204
llvm::X86::CK_BDVER4
@ CK_BDVER4
Definition: X86TargetParser.h:128
llvm::X86::CK_AMDFAM10
@ CK_AMDFAM10
Definition: X86TargetParser.h:122
I
#define I(x, y, z)
Definition: MD5.cpp:58
size
i< reg-> size
Definition: README.txt:166
llvm::X86::CK_Meteorlake
@ CK_Meteorlake
Definition: X86TargetParser.h:108
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1868
ImpliedFeaturesCLWB
constexpr FeatureBitset ImpliedFeaturesCLWB
Definition: X86TargetParser.cpp:488
ImpliedFeaturesAVX512VL
constexpr FeatureBitset ImpliedFeaturesAVX512VL
Definition: X86TargetParser.cpp:574
ImpliedFeaturesLVI_CFI
constexpr FeatureBitset ImpliedFeaturesLVI_CFI
Definition: X86TargetParser.cpp:533
FeaturesBDVER4
constexpr FeatureBitset FeaturesBDVER4
Definition: X86TargetParser.cpp:280
ImpliedFeaturesAVX2
constexpr FeatureBitset ImpliedFeaturesAVX2
Definition: X86TargetParser.cpp:554
llvm::X86::CK_Grandridge
@ CK_Grandridge
Definition: X86TargetParser.h:110
llvm::X86::getFeaturesForCPU
void getFeaturesForCPU(StringRef CPU, SmallVectorImpl< StringRef > &Features)
Fill in the features that CPU supports into Features.
Definition: X86TargetParser.cpp:622
ImpliedFeaturesAVX512VP2INTERSECT
constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT
Definition: X86TargetParser.cpp:583
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FeaturesGoldmont
constexpr FeatureBitset FeaturesGoldmont
Definition: X86TargetParser.cpp:219
ImpliedFeaturesSHSTK
constexpr FeatureBitset ImpliedFeaturesSHSTK
Definition: X86TargetParser.cpp:518
ImpliedFeaturesFXSR
constexpr FeatureBitset ImpliedFeaturesFXSR
Definition: X86TargetParser.cpp:496
llvm::X86::CK_Westmere
@ CK_Westmere
Definition: X86TargetParser.h:91
llvm::X86::CK_Rocketlake
@ CK_Rocketlake
Definition: X86TargetParser.h:102
llvm::X86::CK_Broadwell
@ CK_Broadwell
Definition: X86TargetParser.h:95
llvm::X86::CK_K8
@ CK_K8
Definition: X86TargetParser.h:120
llvm::X86::CK_WinChipC6
@ CK_WinChipC6
Definition: X86TargetParser.h:67
llvm::X86::CK_BDVER1
@ CK_BDVER1
Definition: X86TargetParser.h:125
ImpliedFeaturesRTM
constexpr FeatureBitset ImpliedFeaturesRTM
Definition: X86TargetParser.cpp:514
llvm::X86::CK_x86_64_v3
@ CK_x86_64_v3
Definition: X86TargetParser.h:134
llvm::X86::CK_SapphireRapids
@ CK_SapphireRapids
Definition: X86TargetParser.h:105
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
ImpliedFeaturesSSE4_1
constexpr FeatureBitset ImpliedFeaturesSSE4_1
Definition: X86TargetParser.cpp:551
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1741
llvm::X86::CK_K6_3
@ CK_K6_3
Definition: X86TargetParser.h:117
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::X86::CK_Silvermont
@ CK_Silvermont
Definition: X86TargetParser.h:86
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::operator|=
bool operator|=(SparseBitVector< ElementSize > &LHS, const SparseBitVector< ElementSize > *RHS)
Definition: SparseBitVector.h:823
ImpliedFeaturesAMX_BF16
constexpr FeatureBitset ImpliedFeaturesAMX_BF16
Definition: X86TargetParser.cpp:597
uint32_t
llvm::X86::CK_Pentium2
@ CK_Pentium2
Definition: X86TargetParser.h:75
FeaturesSilvermont
constexpr FeatureBitset FeaturesSilvermont
Definition: X86TargetParser.cpp:217
llvm::X86::CK_Graniterapids
@ CK_Graniterapids
Definition: X86TargetParser.h:111
FeaturesKNM
constexpr FeatureBitset FeaturesKNM
Definition: X86TargetParser.cpp:172
FeaturesBDVER2
constexpr FeatureBitset FeaturesBDVER2
Definition: X86TargetParser.cpp:276
FeaturesX86_64_V4
constexpr FeatureBitset FeaturesX86_64_V4
Definition: X86TargetParser.cpp:146
ImpliedFeaturesVPCLMULQDQ
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ
Definition: X86TargetParser.cpp:566
ImpliedFeaturesSSE4_A
constexpr FeatureBitset ImpliedFeaturesSSE4_A
Definition: X86TargetParser.cpp:591
llvm::X86::CK_IcelakeServer
@ CK_IcelakeServer
Definition: X86TargetParser.h:103
llvm::X86::ProcessorFeatures
ProcessorFeatures
Definition: X86TargetParser.h:57
llvm::X86::CK_Tigerlake
@ CK_Tigerlake
Definition: X86TargetParser.h:104
llvm::Init
Definition: Record.h:282
ImpliedFeaturesRDSEED
constexpr FeatureBitset ImpliedFeaturesRDSEED
Definition: X86TargetParser.cpp:513
llvm::X86::CK_x86_64_v4
@ CK_x86_64_v4
Definition: X86TargetParser.h:135
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1761
ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK
Definition: X86TargetParser.cpp:530
FeaturesGoldmontPlus
constexpr FeatureBitset FeaturesGoldmontPlus
Definition: X86TargetParser.cpp:223
llvm::operator~
APInt operator~(APInt v)
Unary bitwise complement operator.
Definition: APInt.h:2017
ImpliedFeaturesBMI2
constexpr FeatureBitset ImpliedFeaturesBMI2
Definition: X86TargetParser.cpp:485
llvm::operator&
APInt operator&(APInt a, const APInt &b)
Definition: APInt.h:2022
llvm::X86::CK_BTVER1
@ CK_BTVER1
Definition: X86TargetParser.h:123
ImpliedFeaturesSERIALIZE
constexpr FeatureBitset ImpliedFeaturesSERIALIZE
Definition: X86TargetParser.cpp:516
ImpliedFeaturesLVI_LOAD_HARDENING
constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING
Definition: X86TargetParser.cpp:534
llvm::X86::CK_i486
@ CK_i486
Definition: X86TargetParser.h:66
ImpliedFeaturesAVX512IFMA
constexpr FeatureBitset ImpliedFeaturesAVX512IFMA
Definition: X86TargetParser.cpp:578
FeaturesPrescott
constexpr FeatureBitset FeaturesPrescott
Definition: X86TargetParser.cpp:134
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
ImpliedFeaturesPRFCHW
constexpr FeatureBitset ImpliedFeaturesPRFCHW
Definition: X86TargetParser.cpp:508
FeaturesKNL
constexpr FeatureBitset FeaturesKNL
Definition: X86TargetParser.cpp:169
llvm::X86::CK_K6_2
@ CK_K6_2
Definition: X86TargetParser.h:116
Processors
constexpr ProcInfo Processors[]
Definition: X86TargetParser.cpp:302
ImpliedFeaturesAVX
constexpr FeatureBitset ImpliedFeaturesAVX
Definition: X86TargetParser.cpp:553
Enabled
static bool Enabled
Definition: Statistic.cpp:46
FeaturesZNVER2
constexpr FeatureBitset FeaturesZNVER2
Definition: X86TargetParser.cpp:295
FeaturesSkylakeClient
constexpr FeatureBitset FeaturesSkylakeClient
Definition: X86TargetParser.cpp:175
llvm::X86::CK_Goldmont
@ CK_Goldmont
Definition: X86TargetParser.h:87
ImpliedFeaturesPREFETCHI
constexpr FeatureBitset ImpliedFeaturesPREFETCHI
Definition: X86TargetParser.cpp:602
llvm::X86::CK_BTVER2
@ CK_BTVER2
Definition: X86TargetParser.h:124
FeaturesWestmere
constexpr FeatureBitset FeaturesWestmere
Definition: X86TargetParser.cpp:156
llvm::X86::CK_ZNVER2
@ CK_ZNVER2
Definition: X86TargetParser.h:130
ImpliedFeaturesAVXVNNIINT8
constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8
Definition: X86TargetParser.cpp:605
ImpliedFeaturesCLFLUSHOPT
constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT
Definition: X86TargetParser.cpp:487
FeatureInfos
constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX]
Definition: X86TargetParser.cpp:617
FeaturesCascadeLake
constexpr FeatureBitset FeaturesCascadeLake
Definition: X86TargetParser.cpp:184
StringSwitch.h
ImpliedFeaturesAVX5124FMAPS
constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS
Definition: X86TargetParser.cpp:587
ImpliedFeaturesSSE3
constexpr FeatureBitset ImpliedFeaturesSSE3
Definition: X86TargetParser.cpp:549
FeaturesSkylakeServer
constexpr FeatureBitset FeaturesSkylakeServer
Definition: X86TargetParser.cpp:180
llvm::X86::CK_i586
@ CK_i586
Definition: X86TargetParser.h:70
llvm::X86::CK_Pentium4
@ CK_Pentium4
Definition: X86TargetParser.h:80
llvm::X86::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid -mtune names.
Definition: X86TargetParser.cpp:460
ImpliedFeaturesPOPCNT
constexpr FeatureBitset ImpliedFeaturesPOPCNT
Definition: X86TargetParser.cpp:505
llvm::X86::CK_Core2
@ CK_Core2
Definition: X86TargetParser.h:83
ImpliedFeaturesKL
constexpr FeatureBitset ImpliedFeaturesKL
Definition: X86TargetParser.cpp:611
llvm::X86::parseTuneCPU
CPUKind parseTuneCPU(StringRef CPU, bool Only64Bit=false)
Definition: X86TargetParser.cpp:447
ImpliedFeaturesHRESET
constexpr FeatureBitset ImpliedFeaturesHRESET
Definition: X86TargetParser.cpp:600
FeaturesX86_64
constexpr FeatureBitset FeaturesX86_64
Definition: X86TargetParser.cpp:139
ImpliedFeaturesCLDEMOTE
constexpr FeatureBitset ImpliedFeaturesCLDEMOTE
Definition: X86TargetParser.cpp:486
ImpliedFeaturesX87
constexpr FeatureBitset ImpliedFeaturesX87
Definition: X86TargetParser.cpp:525
llvm::X86::CK_IvyBridge
@ CK_IvyBridge
Definition: X86TargetParser.h:93
ImpliedFeaturesSAHF
constexpr FeatureBitset ImpliedFeaturesSAHF
Definition: X86TargetParser.cpp:515
NoTuneList
constexpr const char * NoTuneList[]
Definition: X86TargetParser.cpp:437
ImpliedFeaturesRETPOLINE_INDIRECT_CALLS
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS
Definition: X86TargetParser.cpp:532
FeaturesAMDFAM10
constexpr FeatureBitset FeaturesAMDFAM10
Definition: X86TargetParser.cpp:254
ImpliedFeaturesAVX512VBMI
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI
Definition: X86TargetParser.cpp:581
ImpliedFeaturesSSSE3
constexpr FeatureBitset ImpliedFeaturesSSSE3
Definition: X86TargetParser.cpp:550
FeaturesTremont
constexpr FeatureBitset FeaturesTremont
Definition: X86TargetParser.cpp:225
ImpliedFeaturesAVX5124VNNIW
constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW
Definition: X86TargetParser.cpp:588
ImpliedFeaturesAVXIFMA
constexpr FeatureBitset ImpliedFeaturesAVXIFMA
Definition: X86TargetParser.cpp:606
llvm::X86::CK_Tremont
@ CK_Tremont
Definition: X86TargetParser.h:89
llvm::X86::CK_Alderlake
@ CK_Alderlake
Definition: X86TargetParser.h:106
ImpliedFeaturesAMX_INT8
constexpr FeatureBitset ImpliedFeaturesAMX_INT8
Definition: X86TargetParser.cpp:599
llvm::SmallVectorImpl< StringRef >
ImpliedFeaturesRDPRU
constexpr FeatureBitset ImpliedFeaturesRDPRU
Definition: X86TargetParser.cpp:511
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
llvm::X86::CK_Cascadelake
@ CK_Cascadelake
Definition: X86TargetParser.h:98
FeaturesSandyBridge
constexpr FeatureBitset FeaturesSandyBridge
Definition: X86TargetParser.cpp:157
llvm::X86::CK_Penryn
@ CK_Penryn
Definition: X86TargetParser.h:84
ImpliedFeaturesAVX512VBMI2
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2
Definition: X86TargetParser.cpp:582
ImpliedFeaturesAVX512DQ
constexpr FeatureBitset ImpliedFeaturesAVX512DQ
Definition: X86TargetParser.cpp:571
llvm::X86::CK_Cooperlake
@ CK_Cooperlake
Definition: X86TargetParser.h:99
llvm::X86::CK_AthlonXP
@ CK_AthlonXP
Definition: X86TargetParser.h:119
ImpliedFeaturesAMX_FP16
constexpr FeatureBitset ImpliedFeaturesAMX_FP16
Definition: X86TargetParser.cpp:598
llvm::X86::CK_i386
@ CK_i386
Definition: X86TargetParser.h:65
ImpliedFeaturesCMPXCHG8B
constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B
Definition: X86TargetParser.cpp:492
llvm::FeatureBitset::any
bool any() const
Definition: SubtargetFeature.h:91
llvm::X86::CK_Pentium3
@ CK_Pentium3
Definition: X86TargetParser.h:76
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
FeaturesBDVER1
constexpr FeatureBitset FeaturesBDVER1
Definition: X86TargetParser.cpp:269
ImpliedFeaturesWIDEKL
constexpr FeatureBitset ImpliedFeaturesWIDEKL
Definition: X86TargetParser.cpp:612
ImpliedFeaturesRDPID
constexpr FeatureBitset ImpliedFeaturesRDPID
Definition: X86TargetParser.cpp:510
FeaturesBTVER1
constexpr FeatureBitset FeaturesBTVER1
Definition: X86TargetParser.cpp:259
ImpliedFeaturesAVX512BITALG
constexpr FeatureBitset ImpliedFeaturesAVX512BITALG
Definition: X86TargetParser.cpp:577
ImpliedFeaturesPCLMUL
constexpr FeatureBitset ImpliedFeaturesPCLMUL
Definition: X86TargetParser.cpp:563
ImpliedFeaturesCMOV
constexpr FeatureBitset ImpliedFeaturesCMOV
Definition: X86TargetParser.cpp:490
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
llvm::X86::CK_Yonah
@ CK_Yonah
Definition: X86TargetParser.h:79
ImpliedFeatures3DNOWA
constexpr FeatureBitset ImpliedFeatures3DNOWA
Definition: X86TargetParser.cpp:544
llvm::X86::CK_Geode
@ CK_Geode
Definition: X86TargetParser.h:136