LLVM  13.0.0git
Enumerations | Functions
llvm::X86 Namespace Reference

Define some predicates that are used for node matching. More...

Enumerations

enum  ProcessorVendors : unsigned { VENDOR_DUMMY, VENDOR_OTHER }
 
enum  ProcessorTypes : unsigned { CPU_TYPE_DUMMY, CPU_TYPE_MAX }
 
enum  ProcessorSubtypes : unsigned { CPU_SUBTYPE_DUMMY, CPU_SUBTYPE_MAX }
 
enum  ProcessorFeatures { CPU_FEATURE_MAX }
 
enum  CPUKind {
  CK_None, CK_i386, CK_i486, CK_WinChipC6,
  CK_WinChip2, CK_C3, CK_i586, CK_Pentium,
  CK_PentiumMMX, CK_PentiumPro, CK_i686, CK_Pentium2,
  CK_Pentium3, CK_PentiumM, CK_C3_2, CK_Yonah,
  CK_Pentium4, CK_Prescott, CK_Nocona, CK_Core2,
  CK_Penryn, CK_Bonnell, CK_Silvermont, CK_Goldmont,
  CK_GoldmontPlus, CK_Tremont, CK_Nehalem, CK_Westmere,
  CK_SandyBridge, CK_IvyBridge, CK_Haswell, CK_Broadwell,
  CK_SkylakeClient, CK_SkylakeServer, CK_Cascadelake, CK_Cooperlake,
  CK_Cannonlake, CK_IcelakeClient, CK_Rocketlake, CK_IcelakeServer,
  CK_Tigerlake, CK_SapphireRapids, CK_Alderlake, CK_KNL,
  CK_KNM, CK_Lakemont, CK_K6, CK_K6_2,
  CK_K6_3, CK_Athlon, CK_AthlonXP, CK_K8,
  CK_K8SSE3, CK_AMDFAM10, CK_BTVER1, CK_BTVER2,
  CK_BDVER1, CK_BDVER2, CK_BDVER3, CK_BDVER4,
  CK_ZNVER1, CK_ZNVER2, CK_ZNVER3, CK_x86_64,
  CK_x86_64_v2, CK_x86_64_v3, CK_x86_64_v4, CK_Geode
}
 
enum  {
  BX_SI = 500, BX_DI = 501, BP_SI = 502, BP_DI = 503,
  sib = 504, sib64 = 505
}
 
enum  {
  AddrBaseReg = 0, AddrScaleAmt = 1, AddrIndexReg = 2, AddrDisp = 3,
  AddrSegmentReg = 4, AddrNumOperands = 5
}
 
enum  STATIC_ROUNDING {
  TO_NEAREST_INT = 0, TO_NEG_INF = 1, TO_POS_INF = 2, TO_ZERO = 3,
  CUR_DIRECTION = 4, NO_EXC = 8
}
 AVX512 static rounding constants. More...
 
enum  IPREFIXES {
  IP_NO_PREFIX = 0, IP_HAS_OP_SIZE = 1U << 0, IP_HAS_AD_SIZE = 1U << 1, IP_HAS_REPEAT_NE = 1U << 2,
  IP_HAS_REPEAT = 1U << 3, IP_HAS_LOCK = 1U << 4, IP_HAS_NOTRACK = 1U << 5, IP_USE_VEX = 1U << 6,
  IP_USE_VEX2 = 1U << 7, IP_USE_VEX3 = 1U << 8, IP_USE_EVEX = 1U << 9, IP_USE_DISP8 = 1U << 10,
  IP_USE_DISP32 = 1U << 11
}
 The constants to describe instr prefixes if there are. More...
 
enum  OperandType : unsigned { OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET, OPERAND_COND_CODE }
 
enum  CondCode {
  COND_O = 0, COND_NO = 1, COND_B = 2, COND_AE = 3,
  COND_E = 4, COND_NE = 5, COND_BE = 6, COND_A = 7,
  COND_S = 8, COND_NS = 9, COND_P = 10, COND_NP = 11,
  COND_L = 12, COND_GE = 13, COND_LE = 14, COND_G = 15,
  LAST_VALID_COND = COND_G, COND_NE_OR_P, COND_E_AND_NP, COND_INVALID
}
 
enum  FirstMacroFusionInstKind {
  FirstMacroFusionInstKind::Test, FirstMacroFusionInstKind::Cmp, FirstMacroFusionInstKind::And, FirstMacroFusionInstKind::AddSub,
  FirstMacroFusionInstKind::IncDec, FirstMacroFusionInstKind::Invalid
}
 
enum  SecondMacroFusionInstKind { SecondMacroFusionInstKind::AB, SecondMacroFusionInstKind::ELG, SecondMacroFusionInstKind::SPO, SecondMacroFusionInstKind::Invalid }
 
enum  AlignBranchBoundaryKind : uint8_t {
  AlignBranchNone = 0, AlignBranchFused = 1U << 0, AlignBranchJcc = 1U << 1, AlignBranchJmp = 1U << 2,
  AlignBranchCall = 1U << 3, AlignBranchRet = 1U << 4, AlignBranchIndirect = 1U << 5
}
 Defines the possible values of the branch boundary alignment mask. More...
 
enum  EncodingOfSegmentOverridePrefix : uint8_t {
  CS_Encoding = 0x2E, DS_Encoding = 0x3E, ES_Encoding = 0x26, FS_Encoding = 0x64,
  GS_Encoding = 0x65, SS_Encoding = 0x36
}
 Defines the encoding values for segment override prefix. More...
 
enum  Fixups {
  reloc_riprel_4byte = FirstTargetFixupKind, reloc_riprel_4byte_movq_load, reloc_riprel_4byte_relax, reloc_riprel_4byte_relax_rex,
  reloc_signed_4byte, reloc_signed_4byte_relax, reloc_global_offset_table, reloc_global_offset_table8,
  reloc_branch_4byte_pcrel, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
}
 
enum  AsmComments { AC_EVEX_2_VEX = MachineInstr::TAsmComments }
 
enum  { MaxShuffleCombineDepth = 8 }
 

Functions

CPUKind parseArchX86 (StringRef CPU, bool Only64Bit=false)
 Parse CPU string into a CPUKind. More...
 
CPUKind parseTuneCPU (StringRef CPU, bool Only64Bit=false)
 
void fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
 Provide a list of valid CPU names. More...
 
void fillValidTuneCPUList (SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
 Provide a list of valid -mtune names. More...
 
ProcessorFeatures getKeyFeature (CPUKind Kind)
 Get the key feature prioritizing target multiversioning. More...
 
void getFeaturesForCPU (StringRef CPU, SmallVectorImpl< StringRef > &Features)
 Fill in the features that CPU supports into Features. More...
 
void updateImpliedFeatures (StringRef Feature, bool Enabled, StringMap< bool > &Features)
 Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature. More...
 
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion (unsigned Opcode)
 
SecondMacroFusionInstKind classifySecondCondCodeInMacroFusion (X86::CondCode CC)
 
bool isMacroFused (FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
 
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg (unsigned Reg)
 Given a segment register, return the encoding of the segment override prefix for it. More...
 
std::pair< CondCode, bool > getX86ConditionCode (CmpInst::Predicate Predicate)
 Return a pair of condition code for the given predicate and whether the instruction operands should be swaped to match the condition code. More...
 
unsigned getSETOpc (bool HasMemoryOperand=false)
 Return a setcc opcode based on whether it has a memory operand. More...
 
unsigned getCMovOpcode (unsigned RegBytes, bool HasMemoryOperand=false)
 Return a cmov opcode for the given register size in bytes, and operand type. More...
 
CondCode getCondFromBranch (const MachineInstr &MI)
 
CondCode getCondFromSETCC (const MachineInstr &MI)
 Return condition code of a SETCC opcode. More...
 
CondCode getCondFromCMov (const MachineInstr &MI)
 Return condition code of a CMov opcode. More...
 
CondCode GetOppositeBranchCondition (CondCode CC)
 GetOppositeBranchCondition - Return the inverse of the specified cond, e.g. More...
 
unsigned getVPCMPImmForCond (ISD::CondCode CC)
 Get the VPCMP immediate for the given condition. More...
 
unsigned getSwappedVPCMPImm (unsigned Imm)
 Get the VPCMP immediate if the opcodes are swapped. More...
 
unsigned getSwappedVPCOMImm (unsigned Imm)
 Get the VPCOM immediate if the opcodes are swapped. More...
 
unsigned getSwappedVCMPImm (unsigned Imm)
 Get the VCMP immediate if the opcodes are swapped. More...
 
bool isConstantSplat (SDValue Op, APInt &SplatVal, bool AllowPartialUndefs=true)
 If Op is a constant whose elements are all the same constant or undefined, return true and return the constant value in SplatVal. More...
 
bool isZeroNode (SDValue Elt)
 Returns true if Elt is a constant zero or floating point constant +0.0. More...
 
bool isOffsetSuitableForCodeModel (int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement)
 Returns true of the given offset can be fit into displacement field of the instruction. More...
 
bool isCalleePop (CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
 Determines whether the callee is required to pop its own arguments. More...
 
FastISelcreateFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
 

Detailed Description

Define some predicates that are used for node matching.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
BX_SI 
BX_DI 
BP_SI 
BP_DI 
sib 
sib64 

Definition at line 1658 of file X86Disassembler.cpp.

◆ anonymous enum

anonymous enum
Enumerator
AddrBaseReg 
AddrScaleAmt 
AddrIndexReg 
AddrDisp 
AddrSegmentReg 

AddrSegmentReg - The operand # of the segment in the memory operand.

AddrNumOperands 

AddrNumOperands - Total number of operands in a memory reference.

Definition at line 31 of file X86BaseInfo.h.

◆ anonymous enum

anonymous enum
Enumerator
MaxShuffleCombineDepth 

Definition at line 36452 of file X86ISelLowering.cpp.

◆ AlignBranchBoundaryKind

Defines the possible values of the branch boundary alignment mask.

Enumerator
AlignBranchNone 
AlignBranchFused 
AlignBranchJcc 
AlignBranchJmp 
AlignBranchCall 
AlignBranchRet 
AlignBranchIndirect 

Definition at line 357 of file X86BaseInfo.h.

◆ AsmComments

Enumerator
AC_EVEX_2_VEX 

Definition at line 31 of file X86InstrInfo.h.

◆ CondCode

Enumerator
COND_O 
COND_NO 
COND_B 
COND_AE 
COND_E 
COND_NE 
COND_BE 
COND_A 
COND_S 
COND_NS 
COND_P 
COND_NP 
COND_L 
COND_GE 
COND_LE 
COND_G 
LAST_VALID_COND 
COND_NE_OR_P 
COND_E_AND_NP 
COND_INVALID 

Definition at line 80 of file X86BaseInfo.h.

◆ CPUKind

Enumerator
CK_None 
CK_i386 
CK_i486 
CK_WinChipC6 
CK_WinChip2 
CK_C3 
CK_i586 
CK_Pentium 
CK_PentiumMMX 
CK_PentiumPro 
CK_i686 
CK_Pentium2 
CK_Pentium3 
CK_PentiumM 
CK_C3_2 
CK_Yonah 
CK_Pentium4 
CK_Prescott 
CK_Nocona 
CK_Core2 
CK_Penryn 
CK_Bonnell 
CK_Silvermont 
CK_Goldmont 
CK_GoldmontPlus 
CK_Tremont 
CK_Nehalem 
CK_Westmere 
CK_SandyBridge 
CK_IvyBridge 
CK_Haswell 
CK_Broadwell 
CK_SkylakeClient 
CK_SkylakeServer 
CK_Cascadelake 
CK_Cooperlake 
CK_Cannonlake 
CK_IcelakeClient 
CK_Rocketlake 
CK_IcelakeServer 
CK_Tigerlake 
CK_SapphireRapids 
CK_Alderlake 
CK_KNL 
CK_KNM 
CK_Lakemont 
CK_K6 
CK_K6_2 
CK_K6_3 
CK_Athlon 
CK_AthlonXP 
CK_K8 
CK_K8SSE3 
CK_AMDFAM10 
CK_BTVER1 
CK_BTVER2 
CK_BDVER1 
CK_BDVER2 
CK_BDVER3 
CK_BDVER4 
CK_ZNVER1 
CK_ZNVER2 
CK_ZNVER3 
CK_x86_64 
CK_x86_64_v2 
CK_x86_64_v3 
CK_x86_64_v4 
CK_Geode 

Definition at line 62 of file X86TargetParser.h.

◆ EncodingOfSegmentOverridePrefix

Defines the encoding values for segment override prefix.

Enumerator
CS_Encoding 
DS_Encoding 
ES_Encoding 
FS_Encoding 
GS_Encoding 
SS_Encoding 

Definition at line 368 of file X86BaseInfo.h.

◆ FirstMacroFusionInstKind

Enumerator
Test 
Cmp 
And 
AddSub 
IncDec 
Invalid 

Definition at line 111 of file X86BaseInfo.h.

◆ Fixups

Enumerator
reloc_riprel_4byte 
reloc_riprel_4byte_movq_load 
reloc_riprel_4byte_relax 
reloc_riprel_4byte_relax_rex 
reloc_signed_4byte 
reloc_signed_4byte_relax 
reloc_global_offset_table 
reloc_global_offset_table8 
reloc_branch_4byte_pcrel 
LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 16 of file X86FixupKinds.h.

◆ IPREFIXES

The constants to describe instr prefixes if there are.

Enumerator
IP_NO_PREFIX 
IP_HAS_OP_SIZE 
IP_HAS_AD_SIZE 
IP_HAS_REPEAT_NE 
IP_HAS_REPEAT 
IP_HAS_LOCK 
IP_HAS_NOTRACK 
IP_USE_VEX 
IP_USE_VEX2 
IP_USE_VEX3 
IP_USE_EVEX 
IP_USE_DISP8 
IP_USE_DISP32 

Definition at line 56 of file X86BaseInfo.h.

◆ OperandType

enum llvm::X86::OperandType : unsigned
Enumerator
OPERAND_ROUNDING_CONTROL 

AVX512 embedded rounding control. This should only have values 0-3.

OPERAND_COND_CODE 

Definition at line 72 of file X86BaseInfo.h.

◆ ProcessorFeatures

Enumerator
CPU_FEATURE_MAX 

Definition at line 56 of file X86TargetParser.h.

◆ ProcessorSubtypes

Enumerator
CPU_SUBTYPE_DUMMY 
CPU_SUBTYPE_MAX 

Definition at line 46 of file X86TargetParser.h.

◆ ProcessorTypes

enum llvm::X86::ProcessorTypes : unsigned
Enumerator
CPU_TYPE_DUMMY 
CPU_TYPE_MAX 

Definition at line 36 of file X86TargetParser.h.

◆ ProcessorVendors

enum llvm::X86::ProcessorVendors : unsigned
Enumerator
VENDOR_DUMMY 
VENDOR_OTHER 

Definition at line 26 of file X86TargetParser.h.

◆ SecondMacroFusionInstKind

Enumerator
AB 
ELG 
SPO 
Invalid 

Definition at line 127 of file X86BaseInfo.h.

◆ STATIC_ROUNDING

AVX512 static rounding constants.

These need to match the values in avx512fintrin.h.

Enumerator
TO_NEAREST_INT 
TO_NEG_INF 
TO_POS_INF 
TO_ZERO 
CUR_DIRECTION 
NO_EXC 

Definition at line 46 of file X86BaseInfo.h.

Function Documentation

◆ classifyFirstOpcodeInMacroFusion()

FirstMacroFusionInstKind llvm::X86::classifyFirstOpcodeInMacroFusion ( unsigned  Opcode)
inline
Returns
the type of the first instruction in macro-fusion.

Definition at line 140 of file X86BaseInfo.h.

References AddSub, And, Cmp, IncDec, Invalid, and Test.

Referenced by classifyFirst(), and isFirstMacroFusibleInst().

◆ classifySecondCondCodeInMacroFusion()

SecondMacroFusionInstKind llvm::X86::classifySecondCondCodeInMacroFusion ( X86::CondCode  CC)
inline
Returns
the type of the second instruction in macro-fusion.

Definition at line 289 of file X86BaseInfo.h.

References AB, COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_G, COND_GE, COND_INVALID, COND_L, COND_LE, COND_NE, COND_NO, COND_NP, COND_NS, COND_O, COND_P, COND_S, ELG, Invalid, and SPO.

Referenced by classifySecond(), and classifySecondInstInMacroFusion().

◆ createFastISel()

FastISel * llvm::X86::createFastISel ( FunctionLoweringInfo funcInfo,
const TargetLibraryInfo libInfo 
)

Definition at line 3980 of file X86FastISel.cpp.

Referenced by llvm::X86TargetLowering::createFastISel().

◆ fillValidCPUArchList()

void llvm::X86::fillValidCPUArchList ( SmallVectorImpl< StringRef > &  Values,
bool  Only64Bit = false 
)

Provide a list of valid CPU names.

If Only64Bit is true, the list will only contain 64-bit capable CPUs.

Definition at line 433 of file X86TargetParser.cpp.

References llvm::SmallVectorImpl< T >::emplace_back(), P, Processors, and llvm::RISCV::RISCVCPUInfo.

◆ fillValidTuneCPUList()

void llvm::X86::fillValidTuneCPUList ( SmallVectorImpl< StringRef > &  Values,
bool  Only64Bit = false 
)

Provide a list of valid -mtune names.

Definition at line 440 of file X86TargetParser.cpp.

References llvm::SmallVectorImpl< T >::emplace_back(), llvm::is_contained(), NoTuneList, P, and Processors.

◆ getCMovOpcode()

unsigned llvm::X86::getCMovOpcode ( unsigned  RegBytes,
bool  HasMemoryOperand = false 
)

Return a cmov opcode for the given register size in bytes, and operand type.

Definition at line 2791 of file X86InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::X86InstrInfo::insertSelect().

◆ getCondFromBranch()

X86::CondCode llvm::X86::getCondFromBranch ( const MachineInstr MI)

◆ getCondFromCMov()

X86::CondCode llvm::X86::getCondFromCMov ( const MachineInstr MI)

Return condition code of a CMov opcode.

Definition at line 2693 of file X86InstrInfo.cpp.

References COND_INVALID, and MI.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr(), and packCmovGroup().

◆ getCondFromSETCC()

X86::CondCode llvm::X86::getCondFromSETCC ( const MachineInstr MI)

Return condition code of a SETCC opcode.

Definition at line 2683 of file X86InstrInfo.cpp.

References COND_INVALID, and MI.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

◆ getFeaturesForCPU()

void llvm::X86::getFeaturesForCPU ( StringRef  CPU,
SmallVectorImpl< StringRef > &  Features 
)

Fill in the features that CPU supports into Features.

Definition at line 591 of file X86TargetParser.cpp.

References assert(), llvm::tgtok::Bits, CPU_FEATURE_MAX, llvm::sys::path::end(), FeatureInfos, llvm::find_if(), i, I, P, and Processors.

◆ getKeyFeature()

ProcessorFeatures llvm::X86::getKeyFeature ( X86::CPUKind  Kind)

Get the key feature prioritizing target multiversioning.

Definition at line 448 of file X86TargetParser.cpp.

References assert(), llvm_unreachable, P, and Processors.

◆ GetOppositeBranchCondition()

X86::CondCode llvm::X86::GetOppositeBranchCondition ( X86::CondCode  CC)

GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.

Return the inverse of the specified condition, e.g.

turning COND_E to COND_NE.

Definition at line 2705 of file X86InstrInfo.cpp.

References COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_E_AND_NP, COND_G, COND_GE, COND_L, COND_LE, COND_NE, COND_NE_OR_P, COND_NO, COND_NP, COND_NS, COND_O, COND_P, COND_S, and llvm_unreachable.

Referenced by checkBoolTestSetCCCombine(), combineCMov(), llvm::X86InstrInfo::commuteInstructionImpl(), createPHIsForCMOVsInSinkBB(), and foldXor1SetCC().

◆ getSegmentOverridePrefixForReg()

EncodingOfSegmentOverridePrefix llvm::X86::getSegmentOverridePrefixForReg ( unsigned  Reg)
inline

Given a segment register, return the encoding of the segment override prefix for it.

Definition at line 380 of file X86BaseInfo.h.

References CS_Encoding, llvm::SIInstrFlags::DS, DS_Encoding, ES_Encoding, llvm::X86AS::FS, FS_Encoding, llvm::X86AS::GS, GS_Encoding, llvm_unreachable, Reg, llvm::X86AS::SS, and SS_Encoding.

◆ getSETOpc()

unsigned llvm::X86::getSETOpc ( bool  HasMemoryOperand = false)

Return a setcc opcode based on whether it has a memory operand.

Return a setcc opcode based on whether it has memory operand.

Definition at line 2786 of file X86InstrInfo.cpp.

◆ getSwappedVCMPImm()

unsigned llvm::X86::getSwappedVCMPImm ( unsigned  Imm)

Get the VCMP immediate if the opcodes are swapped.

Get the VCMP immediate if the operands are swapped.

Definition at line 2854 of file X86InstrInfo.cpp.

References llvm_unreachable, and x3.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

◆ getSwappedVPCMPImm()

unsigned llvm::X86::getSwappedVPCMPImm ( unsigned  Imm)

Get the VPCMP immediate if the opcodes are swapped.

Get the VPCMP immediate if the operands are swapped.

Definition at line 2818 of file X86InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

◆ getSwappedVPCOMImm()

unsigned llvm::X86::getSwappedVPCOMImm ( unsigned  Imm)

Get the VPCOM immediate if the opcodes are swapped.

Get the VPCOM immediate if the operands are swapped.

Definition at line 2836 of file X86InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

◆ getVPCMPImmForCond()

unsigned llvm::X86::getVPCMPImmForCond ( ISD::CondCode  CC)

◆ getX86ConditionCode()

std::pair< X86::CondCode, bool > llvm::X86::getX86ConditionCode ( CmpInst::Predicate  Predicate)

◆ isCalleePop()

bool llvm::X86::isCalleePop ( CallingConv::ID  CallingConv,
bool  is64Bit,
bool  IsVarArg,
bool  GuaranteeTCO 
)

Determines whether the callee is required to pop its own arguments.

Callee pop is necessary to support tail calls.

Definition at line 4927 of file X86ISelLowering.cpp.

References is64Bit(), shouldGuaranteeTCO(), llvm::CallingConv::X86_FastCall, llvm::CallingConv::X86_StdCall, llvm::CallingConv::X86_ThisCall, and llvm::CallingConv::X86_VectorCall.

◆ isConstantSplat()

bool llvm::X86::isConstantSplat ( SDValue  Op,
APInt SplatVal,
bool  AllowPartialUndefs = true 
)

If Op is a constant whose elements are all the same constant or undefined, return true and return the constant value in SplatVal.

If we have undef bits that don't cover an entire element, we treat these as zero if AllowPartialUndefs is set, else we fail and return false.

Definition at line 6800 of file X86ISelLowering.cpp.

References llvm::numbers::e, getTargetConstantBitsFromNode(), and i.

Referenced by LowerFunnelShift(), LowerRotate(), and LowerScalarImmediateShift().

◆ isMacroFused()

bool llvm::X86::isMacroFused ( FirstMacroFusionInstKind  FirstKind,
SecondMacroFusionInstKind  SecondKind 
)
inline
Parameters
FirstKindkind of the first instruction in macro fusion.
SecondKindkind of the second instruction in macro fusion.
Returns
true if the two instruction can be macro fused.

Definition at line 338 of file X86BaseInfo.h.

References AB, AddSub, And, Cmp, ELG, IncDec, Invalid, llvm_unreachable, and Test.

Referenced by shouldScheduleAdjacent().

◆ isOffsetSuitableForCodeModel()

bool llvm::X86::isOffsetSuitableForCodeModel ( int64_t  Offset,
CodeModel::Model  M,
bool  hasSymbolicDisplacement 
)

Returns true of the given offset can be fit into displacement field of the instruction.

Definition at line 4895 of file X86ISelLowering.cpp.

References llvm::isInt< 32 >(), llvm::CodeModel::Kernel, M, Offset, and llvm::CodeModel::Small.

Referenced by llvm::X86TargetLowering::isLegalAddressingMode().

◆ isZeroNode()

bool llvm::X86::isZeroNode ( SDValue  Elt)

Returns true if Elt is a constant zero or floating point constant +0.0.

Returns true if Elt is a constant zero or a floating point constant +0.0.

Definition at line 5737 of file X86ISelLowering.cpp.

References llvm::isNullConstant(), and llvm::isNullFPConstant().

Referenced by combineADC(), combineAddOrSubToADCOrSBB(), computeZeroableShuffleElements(), EltsFromConsecutiveLoads(), getFauxShuffleMask(), getMaskNode(), getTargetShuffleAndZeroables(), LowerBuildVectorv4x32(), and LowerSCALAR_TO_VECTOR().

◆ parseArchX86()

X86::CPUKind llvm::X86::parseArchX86 ( StringRef  CPU,
bool  Only64Bit = false 
)

Parse CPU string into a CPUKind.

Will only accept 64-bit capable CPUs if Only64Bit is true.

Definition at line 419 of file X86TargetParser.cpp.

References CK_None, P, and Processors.

Referenced by parseTuneCPU().

◆ parseTuneCPU()

X86::CPUKind llvm::X86::parseTuneCPU ( StringRef  CPU,
bool  Only64Bit = false 
)

Definition at line 427 of file X86TargetParser.cpp.

References CK_None, llvm::is_contained(), NoTuneList, and parseArchX86().

◆ updateImpliedFeatures()

void llvm::X86::updateImpliedFeatures ( StringRef  Feature,
bool  Enabled,
StringMap< bool > &  Features 
)

Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature.

Definition at line 640 of file X86TargetParser.cpp.

References llvm::sys::path::begin(), CPU_FEATURE_MAX, Enabled, llvm::sys::path::end(), FeatureInfos, llvm::find_if(), getImpliedDisabledFeatures(), getImpliedEnabledFeatures(), i, and I.