llvm::AMDGPU::Hwreg Namespace Reference

Classes
struct	HwregSize

Typedefs
using	HwregId = EncodingField<5, 0>
using	HwregOffset = EncodingField<10, 6>
using	HwregEncoding = EncodingFields<HwregId, HwregOffset, HwregSize>

Enumerations
enum	Id {   ID_MODE = 1 , ID_STATUS = 2 , ID_TRAPSTS = 3 , ID_HW_ID = 4 ,   ID_GPR_ALLOC = 5 , ID_LDS_ALLOC = 6 , ID_IB_STS = 7 , ID_PERF_SNAPSHOT_DATA_gfx12 = 10 ,   ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11 , ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12 , ID_MEM_BASES = 15 , ID_TBA_LO = 16 ,   ID_TBA_HI = 17 , ID_TMA_LO = 18 , ID_TMA_HI = 19 , ID_FLAT_SCR_LO = 20 ,   ID_FLAT_SCR_HI = 21 , ID_XNACK_MASK = 22 , ID_HW_ID1 = 23 , ID_HW_ID2 = 24 ,   ID_POPS_PACKER = 25 , ID_PERF_SNAPSHOT_DATA_gfx11 = 27 , ID_IB_STS2 = 28 , ID_SHADER_CYCLES = 29 ,   ID_SHADER_CYCLES_HI = 30 , ID_DVGPR_ALLOC_LO = 31 , ID_DVGPR_ALLOC_HI = 32 , ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18 ,   ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19 , ID_STATE_PRIV = 4 , ID_PERF_SNAPSHOT_DATA1 = 15 , ID_PERF_SNAPSHOT_DATA2 = 16 ,   ID_EXCP_FLAG_PRIV = 17 , ID_EXCP_FLAG_USER = 18 , ID_TRAP_CTRL = 19 , ID_XCC_ID = 20 ,   ID_SQ_PERF_SNAPSHOT_DATA = 21 , ID_SQ_PERF_SNAPSHOT_DATA1 = 22 , ID_SQ_PERF_SNAPSHOT_PC_LO = 23 , ID_SQ_PERF_SNAPSHOT_PC_HI = 24 ,   ID_XNACK_STATE_PRIV = 33 , ID_XNACK_MASK_gfx1250 = 34 }
enum	Offset : unsigned { OFFSET_MEM_VIOL = 8 , OFFSET_ME_ID = 8 }
enum	ModeRegisterMasks : uint32_t {   FP_ROUND_MASK = 0xf << 0 , FP_DENORM_MASK = 0xf << 4 , DX10_CLAMP_MASK = 1 << 8 , IEEE_MODE_MASK = 1 << 9 ,   LOD_CLAMP_MASK = 1 << 10 , DEBUG_MASK = 1 << 11 , EXCP_EN_INVALID_MASK = 1 << 12 , EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13 ,   EXCP_EN_FLOAT_DIV0_MASK = 1 << 14 , EXCP_EN_OVERFLOW_MASK = 1 << 15 , EXCP_EN_UNDERFLOW_MASK = 1 << 16 , EXCP_EN_INEXACT_MASK = 1 << 17 ,   EXCP_EN_INT_DIV0_MASK = 1 << 18 , GPR_IDX_EN_MASK = 1 << 27 , VSKIP_MASK = 1 << 28 , CSP_MASK = 0x7u << 29 ,   DST_VGPR_MSB = 1 << 12 , SRC0_VGPR_MSB = 1 << 13 , SRC1_VGPR_MSB = 1 << 14 , SRC2_VGPR_MSB = 1 << 15 ,   VGPR_MSB_MASK = 0xf << 12 , REPLAY_MODE = 1 << 25 , FLAT_SCRATCH_IS_NV = 1 << 26 }

Functions
int64_t	getHwregId (StringRef Name, const MCSubtargetInfo &STI)
StringRef	getHwreg (uint64_t Encoding, const MCSubtargetInfo &STI)

Variables
static constexpr CustomOperand	Operands []

Typedef Documentation

HwregEncoding

using llvm::AMDGPU::Hwreg::HwregEncoding = EncodingFields<HwregId, HwregOffset, HwregSize>

Definition at line 1260 of file AMDGPUBaseInfo.h.

HwregId

using llvm::AMDGPU::Hwreg::HwregId = EncodingField<5, 0>

Definition at line 1251 of file AMDGPUBaseInfo.h.

HwregOffset

using llvm::AMDGPU::Hwreg::HwregOffset = EncodingField<10, 6>

Definition at line 1252 of file AMDGPUBaseInfo.h.

Enumeration Type Documentation

Id

enum llvm::AMDGPU::Hwreg::Id

Enumerator
ID_MODE
ID_STATUS
ID_TRAPSTS
ID_HW_ID
ID_GPR_ALLOC
ID_LDS_ALLOC
ID_IB_STS
ID_PERF_SNAPSHOT_DATA_gfx12
ID_PERF_SNAPSHOT_PC_LO_gfx12
ID_PERF_SNAPSHOT_PC_HI_gfx12
ID_MEM_BASES
ID_TBA_LO
ID_TBA_HI
ID_TMA_LO
ID_TMA_HI
ID_FLAT_SCR_LO
ID_FLAT_SCR_HI
ID_XNACK_MASK
ID_HW_ID1
ID_HW_ID2
ID_POPS_PACKER
ID_PERF_SNAPSHOT_DATA_gfx11
ID_IB_STS2
ID_SHADER_CYCLES
ID_SHADER_CYCLES_HI
ID_DVGPR_ALLOC_LO
ID_DVGPR_ALLOC_HI
ID_PERF_SNAPSHOT_PC_LO_gfx11
ID_PERF_SNAPSHOT_PC_HI_gfx11
ID_STATE_PRIV
ID_PERF_SNAPSHOT_DATA1
ID_PERF_SNAPSHOT_DATA2
ID_EXCP_FLAG_PRIV
ID_EXCP_FLAG_USER
ID_TRAP_CTRL
ID_XCC_ID
ID_SQ_PERF_SNAPSHOT_DATA
ID_SQ_PERF_SNAPSHOT_DATA1
ID_SQ_PERF_SNAPSHOT_PC_LO
ID_SQ_PERF_SNAPSHOT_PC_HI
ID_XNACK_STATE_PRIV
ID_XNACK_MASK_gfx1250

Definition at line 501 of file SIDefines.h.

ModeRegisterMasks

enum llvm::AMDGPU::Hwreg::ModeRegisterMasks : uint32_t

Enumerator
FP_ROUND_MASK
FP_DENORM_MASK
DX10_CLAMP_MASK
IEEE_MODE_MASK
LOD_CLAMP_MASK
DEBUG_MASK
EXCP_EN_INVALID_MASK
EXCP_EN_INPUT_DENORMAL_MASK
EXCP_EN_FLOAT_DIV0_MASK
EXCP_EN_OVERFLOW_MASK
EXCP_EN_UNDERFLOW_MASK
EXCP_EN_INEXACT_MASK
EXCP_EN_INT_DIV0_MASK
GPR_IDX_EN_MASK
VSKIP_MASK
CSP_MASK
DST_VGPR_MSB
SRC0_VGPR_MSB
SRC1_VGPR_MSB
SRC2_VGPR_MSB
VGPR_MSB_MASK
REPLAY_MODE
FLAT_SCRATCH_IS_NV

Definition at line 559 of file SIDefines.h.

Offset

enum llvm::AMDGPU::Hwreg::Offset : unsigned

Enumerator
OFFSET_MEM_VIOL
OFFSET_ME_ID

Definition at line 554 of file SIDefines.h.

Function Documentation

getHwreg()

StringRef llvm::AMDGPU::Hwreg::getHwreg	(	uint64_t	Encoding,
		const MCSubtargetInfo &	STI )

Definition at line 242 of file AMDGPUAsmUtils.cpp.

References llvm::AMDGPU::getNameFromOperandTable(), and Operands.

Referenced by llvm::AMDGPUInstPrinter::printHwreg().

getHwregId()

int64_t llvm::AMDGPU::Hwreg::getHwregId	(	StringRef	Name,
		const MCSubtargetInfo &	STI )

Definition at line 238 of file AMDGPUAsmUtils.cpp.

References llvm::AMDGPU::getEncodingFromOperandTable(), and Operands.

Variable Documentation

Operands

CustomOperand llvm::AMDGPU::Hwreg::Operands[]

staticconstexpr

Definition at line 171 of file AMDGPUAsmUtils.cpp.

Referenced by getHwreg(), and getHwregId().