LLVM  14.0.0git
AMDGPUBaseInfo.h
Go to the documentation of this file.
1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 3 or 4,
51 /// false otherwise.
52 bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI);
53 
55  unsigned Format;
56  unsigned BitsPerComp;
57  unsigned NumComponents;
58  unsigned NumFormat;
59  unsigned DataFormat;
60 };
61 
62 #define GET_MIMGBaseOpcode_DECL
63 #define GET_MIMGDim_DECL
64 #define GET_MIMGEncoding_DECL
65 #define GET_MIMGLZMapping_DECL
66 #define GET_MIMGMIPMapping_DECL
67 #include "AMDGPUGenSearchableTables.inc"
68 
69 namespace IsaInfo {
70 
71 enum {
72  // The closed Vulkan driver sets 96, which limits the wave count to 8 but
73  // doesn't spill SGPRs as much as when 80 is set.
76 };
77 
78 enum class TargetIDSetting {
80  Any,
81  Off,
82  On
83 };
84 
86 private:
87  const MCSubtargetInfo &STI;
88  TargetIDSetting XnackSetting;
89  TargetIDSetting SramEccSetting;
90 
91 public:
92  explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
93  ~AMDGPUTargetID() = default;
94 
95  /// \return True if the current xnack setting is not "Unsupported".
96  bool isXnackSupported() const {
97  return XnackSetting != TargetIDSetting::Unsupported;
98  }
99 
100  /// \returns True if the current xnack setting is "On" or "Any".
101  bool isXnackOnOrAny() const {
102  return XnackSetting == TargetIDSetting::On ||
103  XnackSetting == TargetIDSetting::Any;
104  }
105 
106  /// \returns True if current xnack setting is "On" or "Off",
107  /// false otherwise.
108  bool isXnackOnOrOff() const {
109  return getXnackSetting() == TargetIDSetting::On ||
111  }
112 
113  /// \returns The current xnack TargetIDSetting, possible options are
114  /// "Unsupported", "Any", "Off", and "On".
116  return XnackSetting;
117  }
118 
119  /// Sets xnack setting to \p NewXnackSetting.
120  void setXnackSetting(TargetIDSetting NewXnackSetting) {
121  XnackSetting = NewXnackSetting;
122  }
123 
124  /// \return True if the current sramecc setting is not "Unsupported".
125  bool isSramEccSupported() const {
126  return SramEccSetting != TargetIDSetting::Unsupported;
127  }
128 
129  /// \returns True if the current sramecc setting is "On" or "Any".
130  bool isSramEccOnOrAny() const {
131  return SramEccSetting == TargetIDSetting::On ||
132  SramEccSetting == TargetIDSetting::Any;
133  }
134 
135  /// \returns True if current sramecc setting is "On" or "Off",
136  /// false otherwise.
137  bool isSramEccOnOrOff() const {
140  }
141 
142  /// \returns The current sramecc TargetIDSetting, possible options are
143  /// "Unsupported", "Any", "Off", and "On".
145  return SramEccSetting;
146  }
147 
148  /// Sets sramecc setting to \p NewSramEccSetting.
149  void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
150  SramEccSetting = NewSramEccSetting;
151  }
152 
155 
156  /// \returns String representation of an object.
157  std::string toString() const;
158 };
159 
160 /// \returns Wavefront size for given subtarget \p STI.
161 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
162 
163 /// \returns Local memory size in bytes for given subtarget \p STI.
164 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
165 
166 /// \returns Number of execution units per compute unit for given subtarget \p
167 /// STI.
168 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
169 
170 /// \returns Maximum number of work groups per compute unit for given subtarget
171 /// \p STI and limited by given \p FlatWorkGroupSize.
172 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
173  unsigned FlatWorkGroupSize);
174 
175 /// \returns Minimum number of waves per execution unit for given subtarget \p
176 /// STI.
177 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
178 
179 /// \returns Maximum number of waves per execution unit for given subtarget \p
180 /// STI without any kind of limitation.
181 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
182 
183 /// \returns Number of waves per execution unit required to support the given \p
184 /// FlatWorkGroupSize.
185 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
186  unsigned FlatWorkGroupSize);
187 
188 /// \returns Minimum flat work group size for given subtarget \p STI.
189 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
190 
191 /// \returns Maximum flat work group size for given subtarget \p STI.
192 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
193 
194 /// \returns Number of waves per work group for given subtarget \p STI and
195 /// \p FlatWorkGroupSize.
196 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
197  unsigned FlatWorkGroupSize);
198 
199 /// \returns SGPR allocation granularity for given subtarget \p STI.
200 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
201 
202 /// \returns SGPR encoding granularity for given subtarget \p STI.
203 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
204 
205 /// \returns Total number of SGPRs for given subtarget \p STI.
206 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
207 
208 /// \returns Addressable number of SGPRs for given subtarget \p STI.
209 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
210 
211 /// \returns Minimum number of SGPRs that meets the given number of waves per
212 /// execution unit requirement for given subtarget \p STI.
213 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
214 
215 /// \returns Maximum number of SGPRs that meets the given number of waves per
216 /// execution unit requirement for given subtarget \p STI.
217 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
218  bool Addressable);
219 
220 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
221 /// STI when the given special registers are used.
222 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
223  bool FlatScrUsed, bool XNACKUsed);
224 
225 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
226 /// STI when the given special registers are used. XNACK is inferred from
227 /// \p STI.
228 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
229  bool FlatScrUsed);
230 
231 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
232 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
233 /// register counts.
234 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
235 
236 /// \returns VGPR allocation granularity for given subtarget \p STI.
237 ///
238 /// For subtargets which support it, \p EnableWavefrontSize32 should match
239 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
240 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
241  Optional<bool> EnableWavefrontSize32 = None);
242 
243 /// \returns VGPR encoding granularity for given subtarget \p STI.
244 ///
245 /// For subtargets which support it, \p EnableWavefrontSize32 should match
246 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
247 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
248  Optional<bool> EnableWavefrontSize32 = None);
249 
250 /// \returns Total number of VGPRs for given subtarget \p STI.
251 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
252 
253 /// \returns Addressable number of VGPRs for given subtarget \p STI.
254 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
255 
256 /// \returns Minimum number of VGPRs that meets given number of waves per
257 /// execution unit requirement for given subtarget \p STI.
258 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
259 
260 /// \returns Maximum number of VGPRs that meets given number of waves per
261 /// execution unit requirement for given subtarget \p STI.
262 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
263 
264 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
265 /// \p NumVGPRs are used.
266 ///
267 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
268 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
269 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
270  Optional<bool> EnableWavefrontSize32 = None);
271 
272 } // end namespace IsaInfo
273 
275 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
276 
278 int getSOPPWithRelaxation(uint16_t Opcode);
279 
281  MIMGBaseOpcode BaseOpcode;
282  bool Store;
283  bool Atomic;
284  bool AtomicX2;
285  bool Sampler;
286  bool Gather4;
287 
288  uint8_t NumExtraArgs;
289  bool Gradients;
290  bool G16;
293  bool HasD16;
294  bool MSAA;
295 };
296 
298 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
299 
300 struct MIMGDimInfo {
301  MIMGDim Dim;
302  uint8_t NumCoords;
303  uint8_t NumGradients;
304  bool MSAA;
305  bool DA;
306  uint8_t Encoding;
307  const char *AsmSuffix;
308 };
309 
311 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
312 
314 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
315 
318 
320  MIMGBaseOpcode L;
321  MIMGBaseOpcode LZ;
322 };
323 
325  MIMGBaseOpcode MIP;
326  MIMGBaseOpcode NONMIP;
327 };
328 
330  MIMGBaseOpcode G;
331  MIMGBaseOpcode G16;
332 };
333 
335 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
336 
338 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
339 
342 
344 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
345  unsigned VDataDwords, unsigned VAddrDwords);
346 
348 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
349 
351 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
352  const MIMGDimInfo *Dim, bool IsA16,
353  bool IsG16Supported);
354 
355 struct MIMGInfo {
358  uint8_t MIMGEncoding;
359  uint8_t VDataDwords;
360  uint8_t VAddrDwords;
361 };
362 
364 const MIMGInfo *getMIMGInfo(unsigned Opc);
365 
367 int getMTBUFBaseOpcode(unsigned Opc);
368 
370 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
371 
373 int getMTBUFElements(unsigned Opc);
374 
376 bool getMTBUFHasVAddr(unsigned Opc);
377 
379 bool getMTBUFHasSrsrc(unsigned Opc);
380 
382 bool getMTBUFHasSoffset(unsigned Opc);
383 
385 int getMUBUFBaseOpcode(unsigned Opc);
386 
388 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
389 
391 int getMUBUFElements(unsigned Opc);
392 
394 bool getMUBUFHasVAddr(unsigned Opc);
395 
397 bool getMUBUFHasSrsrc(unsigned Opc);
398 
400 bool getMUBUFHasSoffset(unsigned Opc);
401 
403 bool getMUBUFIsBufferInv(unsigned Opc);
404 
406 bool getSMEMIsBuffer(unsigned Opc);
407 
409 bool getVOP1IsSingle(unsigned Opc);
410 
412 bool getVOP2IsSingle(unsigned Opc);
413 
415 bool getVOP3IsSingle(unsigned Opc);
416 
418 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
419  uint8_t NumComponents,
420  uint8_t NumFormat,
421  const MCSubtargetInfo &STI);
423 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
424  const MCSubtargetInfo &STI);
425 
427 int getMCOpcode(uint16_t Opcode, unsigned Gen);
428 
430  const MCSubtargetInfo *STI);
431 
433  const MCSubtargetInfo *STI);
434 
435 bool isGroupSegment(const GlobalValue *GV);
436 bool isGlobalSegment(const GlobalValue *GV);
437 bool isReadOnlySegment(const GlobalValue *GV);
438 
439 /// \returns True if constants should be emitted to .text section for given
440 /// target triple \p TT, false otherwise.
442 
443 /// \returns Integer value requested using \p F's \p Name attribute.
444 ///
445 /// \returns \p Default if attribute is not present.
446 ///
447 /// \returns \p Default and emits error if requested value cannot be converted
448 /// to integer.
449 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
450 
451 /// \returns A pair of integer values requested using \p F's \p Name attribute
452 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
453 /// is false).
454 ///
455 /// \returns \p Default if attribute is not present.
456 ///
457 /// \returns \p Default and emits error if one of the requested values cannot be
458 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
459 /// not present.
460 std::pair<int, int> getIntegerPairAttribute(const Function &F,
461  StringRef Name,
462  std::pair<int, int> Default,
463  bool OnlyFirstRequired = false);
464 
465 /// Represents the counter values to wait for in an s_waitcnt instruction.
466 ///
467 /// Large values (including the maximum possible integer) can be used to
468 /// represent "don't care" waits.
469 struct Waitcnt {
470  unsigned VmCnt = ~0u;
471  unsigned ExpCnt = ~0u;
472  unsigned LgkmCnt = ~0u;
473  unsigned VsCnt = ~0u;
474 
475  Waitcnt() {}
476  Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
478 
479  static Waitcnt allZero(bool HasVscnt) {
480  return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
481  }
482  static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
483 
484  bool hasWait() const {
485  return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
486  }
487 
488  bool hasWaitExceptVsCnt() const {
489  return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
490  }
491 
492  bool hasWaitVsCnt() const {
493  return VsCnt != ~0u;
494  }
495 
496  bool dominates(const Waitcnt &Other) const {
497  return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
498  LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
499  }
500 
501  Waitcnt combined(const Waitcnt &Other) const {
502  return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
503  std::min(LgkmCnt, Other.LgkmCnt),
504  std::min(VsCnt, Other.VsCnt));
505  }
506 };
507 
508 /// \returns Vmcnt bit mask for given isa \p Version.
509 unsigned getVmcntBitMask(const IsaVersion &Version);
510 
511 /// \returns Expcnt bit mask for given isa \p Version.
512 unsigned getExpcntBitMask(const IsaVersion &Version);
513 
514 /// \returns Lgkmcnt bit mask for given isa \p Version.
515 unsigned getLgkmcntBitMask(const IsaVersion &Version);
516 
517 /// \returns Waitcnt bit mask for given isa \p Version.
518 unsigned getWaitcntBitMask(const IsaVersion &Version);
519 
520 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
521 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
522 
523 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
524 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
525 
526 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
527 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
528 
529 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
530 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
531 /// \p Lgkmcnt respectively.
532 ///
533 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
534 /// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9 only)
535 /// \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14] (gfx9+ only)
536 /// \p Expcnt = \p Waitcnt[6:4]
537 /// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10 only)
538 /// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10+ only)
539 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
540  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
541 
542 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
543 
544 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
545 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
546  unsigned Vmcnt);
547 
548 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
549 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
550  unsigned Expcnt);
551 
552 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
553 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
554  unsigned Lgkmcnt);
555 
556 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
557 /// \p Version.
558 ///
559 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
560 /// Waitcnt[3:0] = \p Vmcnt (pre-gfx9 only)
561 /// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9+ only)
562 /// Waitcnt[6:4] = \p Expcnt
563 /// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10 only)
564 /// Waitcnt[13:8] = \p Lgkmcnt (gfx10+ only)
565 /// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9+ only)
566 ///
567 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
568 /// isa \p Version.
569 unsigned encodeWaitcnt(const IsaVersion &Version,
570  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
571 
572 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
573 
574 namespace Hwreg {
575 
577 int64_t getHwregId(const StringRef Name);
578 
580 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
581 
583 bool isValidHwreg(int64_t Id);
584 
586 bool isValidHwregOffset(int64_t Offset);
587 
589 bool isValidHwregWidth(int64_t Width);
590 
592 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
593 
595 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
596 
597 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
598 
599 } // namespace Hwreg
600 
601 namespace Exp {
602 
603 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
604 
606 unsigned getTgtId(const StringRef Name);
607 
609 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
610 
611 } // namespace Exp
612 
613 namespace MTBUFFormat {
614 
616 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
617 
618 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
619 
620 int64_t getDfmt(const StringRef Name);
621 
622 StringRef getDfmtName(unsigned Id);
623 
624 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
625 
626 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
627 
628 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
629 
630 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
631 
632 int64_t getUnifiedFormat(const StringRef Name);
633 
634 StringRef getUnifiedFormatName(unsigned Id);
635 
636 bool isValidUnifiedFormat(unsigned Val);
637 
638 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
639 
640 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
641 
642 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
643 
644 } // namespace MTBUFFormat
645 
646 namespace SendMsg {
647 
649 int64_t getMsgId(const StringRef Name);
650 
652 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
653 
655 StringRef getMsgName(int64_t MsgId);
656 
658 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
659 
661 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
662 
664 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
665  bool Strict = true);
666 
668 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
669  const MCSubtargetInfo &STI, bool Strict = true);
670 
672 bool msgRequiresOp(int64_t MsgId);
673 
675 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
676 
677 void decodeMsg(unsigned Val,
678  uint16_t &MsgId,
679  uint16_t &OpId,
680  uint16_t &StreamId);
681 
683 uint64_t encodeMsg(uint64_t MsgId,
684  uint64_t OpId,
685  uint64_t StreamId);
686 
687 } // namespace SendMsg
688 
689 
690 unsigned getInitialPSInputAddr(const Function &F);
691 
692 bool getHasColorExport(const Function &F);
693 
694 bool getHasDepthExport(const Function &F);
695 
697 bool isShader(CallingConv::ID CC);
698 
700 bool isGraphics(CallingConv::ID CC);
701 
703 bool isCompute(CallingConv::ID CC);
704 
707 
708 // These functions are considered entrypoints into the current module, i.e. they
709 // are allowed to be called from outside the current module. This is different
710 // from isEntryFunctionCC, which is only true for functions that are entered by
711 // the hardware. Module entry points include all entry functions but also
712 // include functions that can be called from other functions inside or outside
713 // the current module. Module entry functions are allowed to allocate LDS.
716 
717 // FIXME: Remove this when calling conventions cleaned up
719 inline bool isKernel(CallingConv::ID CC) {
720  switch (CC) {
723  return true;
724  default:
725  return false;
726  }
727 }
728 
729 bool hasXNACK(const MCSubtargetInfo &STI);
730 bool hasSRAMECC(const MCSubtargetInfo &STI);
731 bool hasMIMG_R128(const MCSubtargetInfo &STI);
732 bool hasGFX10A16(const MCSubtargetInfo &STI);
733 bool hasG16(const MCSubtargetInfo &STI);
734 bool hasPackedD16(const MCSubtargetInfo &STI);
735 
736 bool isSI(const MCSubtargetInfo &STI);
737 bool isCI(const MCSubtargetInfo &STI);
738 bool isVI(const MCSubtargetInfo &STI);
739 bool isGFX9(const MCSubtargetInfo &STI);
740 bool isGFX9Plus(const MCSubtargetInfo &STI);
741 bool isGFX10(const MCSubtargetInfo &STI);
742 bool isGFX10Plus(const MCSubtargetInfo &STI);
743 bool isGCN3Encoding(const MCSubtargetInfo &STI);
744 bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
745 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
746 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
747 bool isGFX90A(const MCSubtargetInfo &STI);
749 
750 /// Is Reg - scalar register
751 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
752 
753 /// Is there any intersection between registers
754 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
755 
756 /// If \p Reg is a pseudo reg, return the correct hardware register given
757 /// \p STI otherwise return \p Reg.
758 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
759 
760 /// Convert hardware register \p Reg to a pseudo register
762 unsigned mc2PseudoReg(unsigned Reg);
763 
764 /// Can this operand also contain immediate values?
765 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
766 
767 /// Is this floating-point operand?
768 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
769 
770 /// Does this opearnd support only inlinable literals?
771 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
772 
773 /// Get the size in bits of a register from the register class \p RC.
774 unsigned getRegBitWidth(unsigned RCID);
775 
776 /// Get the size in bits of a register from the register class \p RC.
777 unsigned getRegBitWidth(const MCRegisterClass &RC);
778 
779 /// Get size of register operand
780 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
781  unsigned OpNo);
782 
784 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
785  switch (OpInfo.OperandType) {
796  return 4;
797 
803  return 8;
804 
817  return 2;
818 
819  default:
820  llvm_unreachable("unhandled operand type");
821  }
822 }
823 
825 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
826  return getOperandSize(Desc.OpInfo[OpNo]);
827 }
828 
829 /// Is this literal inlinable, and not one of the values intended for floating
830 /// point values.
832 inline bool isInlinableIntLiteral(int64_t Literal) {
833  return Literal >= -16 && Literal <= 64;
834 }
835 
836 /// Is this literal inlinable
838 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
839 
841 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
842 
844 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
845 
847 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
848 
850 bool isInlinableIntLiteralV216(int32_t Literal);
851 
853 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
854 
855 bool isArgPassedInSGPR(const Argument *Arg);
856 
859  int64_t EncodedOffset);
860 
863  int64_t EncodedOffset,
864  bool IsBuffer);
865 
866 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
867 /// offsets.
868 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
869 
870 /// \returns The encoding that will be used for \p ByteOffset in the
871 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
872 /// S_LOAD instructions have a signed offset, on other subtargets it is
873 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
875  int64_t ByteOffset, bool IsBuffer);
876 
877 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
878 /// instruction. This is only useful on CI.s
880  int64_t ByteOffset);
881 
882 /// For FLAT segment the offset must be positive;
883 /// MSB is ignored and forced to zero.
884 ///
885 /// \return The number of bits available for the offset field in flat
886 /// instructions.
887 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
888 
889 /// \returns true if this offset is small enough to fit in the SMRD
890 /// offset field. \p ByteOffset should be the offset in bytes and
891 /// not the encoded offset.
892 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
893 
894 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
895  const GCNSubtarget *Subtarget,
896  Align Alignment = Align(4));
897 
899 inline bool isLegal64BitDPPControl(unsigned DC) {
901 }
902 
903 /// \returns true if the intrinsic is divergent
904 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
905 
906 // Track defaults for fields in the MODE registser.
908  /// Floating point opcodes that support exception flag gathering quiet and
909  /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
910  /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
911  /// quieting.
912  bool IEEE : 1;
913 
914  /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
915  /// clamp NaN to zero; otherwise, pass NaN through.
916  bool DX10Clamp : 1;
917 
918  /// If this is set, neither input or output denormals are flushed for most f32
919  /// instructions.
922 
923  /// If this is set, neither input or output denormals are flushed for both f64
924  /// and f16/v2f16 instructions.
927 
929  IEEE(true),
930  DX10Clamp(true),
935 
937 
940  Mode.IEEE = !AMDGPU::isShader(CC);
941  return Mode;
942  }
943 
944  bool operator ==(const SIModeRegisterDefaults Other) const {
945  return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
946  FP32InputDenormals == Other.FP32InputDenormals &&
947  FP32OutputDenormals == Other.FP32OutputDenormals &&
948  FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
949  FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
950  }
951 
952  bool allFP32Denormals() const {
954  }
955 
956  bool allFP64FP16Denormals() const {
958  }
959 
960  /// Get the encoding value for the FP_DENORM bits of the mode register for the
961  /// FP32 denormal mode.
964  return FP_DENORM_FLUSH_NONE;
965  if (FP32InputDenormals)
966  return FP_DENORM_FLUSH_OUT;
968  return FP_DENORM_FLUSH_IN;
970  }
971 
972  /// Get the encoding value for the FP_DENORM bits of the mode register for the
973  /// FP64/FP16 denormal mode.
976  return FP_DENORM_FLUSH_NONE;
978  return FP_DENORM_FLUSH_OUT;
980  return FP_DENORM_FLUSH_IN;
982  }
983 
984  /// Returns true if a flag is compatible if it's enabled in the callee, but
985  /// disabled in the caller.
986  static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
987  return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
988  }
989 
990  // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
991  // be able to override.
993  if (DX10Clamp != CalleeMode.DX10Clamp)
994  return false;
995  if (IEEE != CalleeMode.IEEE)
996  return false;
997 
998  // Allow inlining denormals enabled into denormals flushed functions.
1003  }
1004 };
1005 
1006 } // end namespace AMDGPU
1007 
1008 raw_ostream &operator<<(raw_ostream &OS,
1010 
1011 } // end namespace llvm
1012 
1013 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:154
llvm::AMDGPU::Hwreg::encodeHwreg
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
Definition: AMDGPUBaseInfo.cpp:1036
FP_DENORM_FLUSH_OUT
#define FP_DENORM_FLUSH_OUT
Definition: SIDefines.h:890
llvm::AMDGPU::SIModeRegisterDefaults::fpDenormModeDPValue
uint32_t fpDenormModeDPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.
Definition: AMDGPUBaseInfo.h:974
llvm::AMDGPU::SendMsg::getMsgName
StringRef getMsgName(int64_t MsgId)
Definition: AMDGPUBaseInfo.cpp:1250
llvm::AMDGPU::getMUBUFIsBufferInv
bool getMUBUFIsBufferInv(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:289
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1543
llvm::AMDGPU::isHsaAbiVersion3
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:114
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::AMDGPUTargetID
AMDGPUTargetID(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:323
llvm::AMDGPU::getMIMGDimInfoByEncoding
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
llvm::AMDGPU::mc2PseudoReg
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
Definition: AMDGPUBaseInfo.cpp:1555
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4630
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:212
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::AMDGPU::IsaInfo::getSGPRAllocGranule
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:591
llvm::AMDGPU::getMUBUFHasSoffset
bool getMUBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:284
llvm::AMDGPU::MIMGBaseOpcodeInfo::HasD16
bool HasD16
Definition: AMDGPUBaseInfo.h:293
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AMDGPU::Waitcnt::allZeroExceptVsCnt
static Waitcnt allZeroExceptVsCnt()
Definition: AMDGPUBaseInfo.h:482
llvm::AMDGPU::MTBUFFormat::NumFormat
NumFormat
Definition: SIDefines.h:461
llvm::AMDGPU::Hwreg::getHwreg
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1042
llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1205
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:149
llvm::AMDGPU::MIMGBaseOpcodeInfo::Store
bool Store
Definition: AMDGPUBaseInfo.h:282
llvm::AMDGPU::MIMGDimInfo::AsmSuffix
const char * AsmSuffix
Definition: AMDGPUBaseInfo.h:307
llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients
bool Gradients
Definition: AMDGPUBaseInfo.h:289
llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumSGPRs
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
Definition: AMDGPUMetadata.h:253
llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip
bool LodOrClampOrMip
Definition: AMDGPUBaseInfo.h:292
llvm::AMDGPU::MTBUFFormat::getDfmtName
StringRef getDfmtName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1129
llvm::AMDGPU::SendMsg::encodeMsg
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
Definition: AMDGPUBaseInfo.cpp:1329
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
llvm::AMDGPU::decodeLgkmcnt
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:938
llvm::Function
Definition: Function.h:61
llvm::AMDGPU::getMUBUFBaseOpcode
int getMUBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:259
llvm::AMDGPU::SIModeRegisterDefaults::FP32OutputDenormals
bool FP32OutputDenormals
Definition: AMDGPUBaseInfo.h:921
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setXnackSetting
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
Definition: AMDGPUBaseInfo.h:120
llvm::AMDGPU::getSMRDEncodedOffset
Optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:1871
llvm::AMDGPU::getMCOpcode
int getMCOpcode(uint16_t Opcode, unsigned Gen)
Definition: AMDGPUBaseInfo.cpp:317
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccOnOrAny
bool isSramEccOnOrAny() const
Definition: AMDGPUBaseInfo.h:130
llvm::AMDGPU::decodeVmcnt
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:922
llvm::AMDGPU::hasSRAMECC
bool hasSRAMECC(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1411
llvm::AMDGPU::SIModeRegisterDefaults::IEEE
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:912
llvm::AMDGPU::hasXNACK
bool hasXNACK(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1407
llvm::AMDGPU::IsaInfo::TargetIDSetting::Unsupported
@ Unsupported
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:143
llvm::AMDGPU::IsaInfo::TargetIDSetting::On
@ On
llvm::AMDGPU::isGFX10_BEncoding
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1465
llvm::AMDGPU::isLegal64BitDPPControl
LLVM_READNONE bool isLegal64BitDPPControl(unsigned DC)
Definition: AMDGPUBaseInfo.h:899
llvm::AMDGPU::MIMGBaseOpcodeInfo::Gather4
bool Gather4
Definition: AMDGPUBaseInfo.h:286
llvm::AMDGPU::isGFX10_AEncoding
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1461
llvm::AMDGPU::getVOP2IsSingle
bool getVOP2IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:304
llvm::AMDGPU::MIMGDimInfo
Definition: AMDGPUBaseInfo.h:300
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::~AMDGPUTargetID
~AMDGPUTargetID()=default
llvm::AMDGPU::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1477
llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
Definition: AMDGPUBaseInfo.cpp:1167
llvm::AMDGPU::getHsaAbiVersion
Optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:91
FP_DENORM_FLUSH_IN
#define FP_DENORM_FLUSH_IN
Definition: SIDefines.h:891
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::AMDGPU::getSMRDEncodedLiteralOffset32
Optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
Definition: AMDGPUBaseInfo.cpp:1888
llvm::AMDGPU::getMIMGDimInfoByAsmSuffix
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix)
llvm::AMDGPU::MTBUFFormat::isValidNfmt
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1163
llvm::AMDGPU::OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:145
llvm::AMDGPU::IsaInfo::getNumExtraSGPRs
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
Definition: AMDGPUBaseInfo.cpp:657
llvm::AMDGPU::isGFX10
bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1451
llvm::AMDGPU::IsaInfo::getTotalNumVGPRs
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:720
llvm::AMDGPU::MTBUFFormat::getUnifiedFormat
int64_t getUnifiedFormat(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1176
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromTargetIDStream
void setTargetIDFromTargetIDStream(StringRef TargetID)
Definition: AMDGPUBaseInfo.cpp:400
llvm::AMDGPU::IsaInfo::getMinWavesPerEU
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:558
llvm::Optional< bool >
llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv
static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:938
llvm::AMDGPU::SIModeRegisterDefaults
Definition: AMDGPUBaseInfo.h:907
llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:920
llvm::AMDGPU::IsaInfo::TargetIDSetting::Any
@ Any
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::AMDGPU::getVmcntBitMask
unsigned getVmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:892
llvm::AMDGPU::SIModeRegisterDefaults::isInlineCompatible
bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const
Definition: AMDGPUBaseInfo.h:992
llvm::AMDGPU::isGlobalSegment
bool isGlobalSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:838
llvm::AMDGPU::MIMGDimInfo::Dim
MIMGDim Dim
Definition: AMDGPUBaseInfo.h:301
llvm::AMDGPU::SendMsg::getMsgId
int64_t getMsgId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1219
llvm::AMDGPU::hasGFX10_3Insts
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1469
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::AMDGPU::SIModeRegisterDefaults::oneWayCompatible
static bool oneWayCompatible(bool CallerMode, bool CalleeMode)
Returns true if a flag is compatible if it's enabled in the callee, but disabled in the caller.
Definition: AMDGPUBaseInfo.h:986
llvm::AMDGPU::IsaInfo::getMaxNumVGPRs
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:745
llvm::AMDGPU::getWaitcntBitMask
unsigned getWaitcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:909
llvm::AMDGPU::isIntrinsicSourceOfDivergence
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
Definition: AMDGPUBaseInfo.cpp:1998
llvm::AMDGPU::SendMsg::getMsgOpName
StringRef getMsgOpName(int64_t MsgId, int64_t OpId)
Definition: AMDGPUBaseInfo.cpp:1287
llvm::AMDGPU::MIMGDimInfo::NumGradients
uint8_t NumGradients
Definition: AMDGPUBaseInfo.h:303
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::AMDGPU::getMTBUFOpcode
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:234
llvm::AMDGPU::MIMGMIPMappingInfo::NONMIP
MIMGBaseOpcode NONMIP
Definition: AMDGPUBaseInfo.h:326
llvm::AMDGPU::MIMGInfo::VAddrDwords
uint8_t VAddrDwords
Definition: AMDGPUBaseInfo.h:360
llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:546
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1156
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::AMDGPU::isKernel
LLVM_READNONE bool isKernel(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:719
llvm::AMDGPU::IsaInfo::TargetIDSetting
TargetIDSetting
Definition: AMDGPUBaseInfo.h:78
llvm::AMDGPU::Hwreg::decodeHwreg
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
Definition: AMDGPUBaseInfo.cpp:1046
llvm::AMDGPU::GcnBufferFormatInfo::DataFormat
unsigned DataFormat
Definition: AMDGPUBaseInfo.h:59
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:83
llvm::AMDGPU::IsaInfo::getSGPREncodingGranule
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:600
llvm::AMDGPU::getSOPPWithRelaxation
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
llvm::AMDGPU::isGFX90A
bool isGFX90A(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1473
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:140
llvm::AMDGPU::SIModeRegisterDefaults::operator==
bool operator==(const SIModeRegisterDefaults Other) const
Definition: AMDGPUBaseInfo.h:944
llvm::AMDGPU::IsaInfo::AMDGPUTargetID
Definition: AMDGPUBaseInfo.h:85
llvm::AMDGPU::getMTBUFHasSrsrc
bool getMTBUFHasSrsrc(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:249
llvm::AMDGPU::isShader
bool isShader(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1358
llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:586
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:150
llvm::AMDGPU::getRegOperandSize
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
Definition: AMDGPUBaseInfo.cpp:1701
llvm::AMDGPU::Waitcnt::Waitcnt
Waitcnt()
Definition: AMDGPUBaseInfo.h:475
llvm::ReplacementType::Literal
@ Literal
llvm::AMDGPU::Hwreg::isValidHwreg
bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1018
llvm::AMDGPU::MIMGBaseOpcodeInfo
Definition: AMDGPUBaseInfo.h:280
llvm::AMDGPU::isInlinableIntLiteralV216
bool isInlinableIntLiteralV216(int32_t Literal)
Definition: AMDGPUBaseInfo.cpp:1785
llvm::AMDGPU::MIMGG16MappingInfo::G
MIMGBaseOpcode G
Definition: AMDGPUBaseInfo.h:330
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:163
llvm::AMDGPU::getMUBUFOpcode
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:264
llvm::AMDGPU::getSMEMIsBuffer
bool getSMEMIsBuffer(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:294
llvm::AMDGPU::MIMGDimInfo::Encoding
uint8_t Encoding
Definition: AMDGPUBaseInfo.h:306
llvm::AMDGPU::IsaInfo::getMaxNumSGPRs
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
Definition: AMDGPUBaseInfo.cpp:640
llvm::AMDGPU::isSGPR
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
Definition: AMDGPUBaseInfo.cpp:1481
llvm::AMDGPU::Hwreg::Id
Id
Definition: SIDefines.h:351
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrAny
bool isXnackOnOrAny() const
Definition: AMDGPUBaseInfo.h:101
llvm::AMDGPU::GcnBufferFormatInfo::NumFormat
unsigned NumFormat
Definition: AMDGPUBaseInfo.h:58
llvm::AMDGPU::decodeExpcnt
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:934
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::AMDGPU::hasGFX10A16
bool hasGFX10A16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1419
llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
Definition: AMDGPUBaseInfo.h:74
llvm::AMDGPU::MIMGLZMappingInfo
Definition: AMDGPUBaseInfo.h:319
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:141
llvm::AMDGPU::getMTBUFBaseOpcode
int getMTBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:229
llvm::AMDGPU::getInitialPSInputAddr
unsigned getInitialPSInputAddr(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1343
FP_DENORM_FLUSH_IN_FLUSH_OUT
#define FP_DENORM_FLUSH_IN_FLUSH_OUT
Definition: SIDefines.h:889
llvm::AMDGPU::getMTBUFHasSoffset
bool getMTBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:254
llvm::AMDGPU::Waitcnt::VsCnt
unsigned VsCnt
Definition: AMDGPUBaseInfo.h:473
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::AMDGPU::decodeWaitcnt
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
Definition: AMDGPUBaseInfo.cpp:943
llvm::AMDGPU::Waitcnt::dominates
bool dominates(const Waitcnt &Other) const
Definition: AMDGPUBaseInfo.h:496
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:146
llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:577
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getSramEccSetting
TargetIDSetting getSramEccSetting() const
Definition: AMDGPUBaseInfo.h:144
llvm::AMDGPU::getMIMGLZMappingInfo
const LLVM_READONLY MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
llvm::IndexedInstrProf::Version
const uint64_t Version
Definition: InstrProf.h:991
llvm::AMDGPU::getMUBUFHasSrsrc
bool getMUBUFHasSrsrc(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:279
llvm::AMDGPU::MIMGBaseOpcodeInfo::MSAA
bool MSAA
Definition: AMDGPUBaseInfo.h:294
llvm::AMDGPU::convertSMRDOffsetUnits
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
Definition: AMDGPUBaseInfo.cpp:1862
llvm::AMDGPU::IsaInfo::getEUsPerCU
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:535
llvm::AMDGPU::MIMGInfo::MIMGEncoding
uint8_t MIMGEncoding
Definition: AMDGPUBaseInfo.h:358
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:157
llvm::AMDGPU::IsaInfo::getLocalMemorySize
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:526
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPU::getMIMGOpcode
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
Definition: AMDGPUBaseInfo.cpp:138
llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat
bool isValidUnifiedFormat(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1188
llvm::AMDGPU::isCI
bool isCI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1435
llvm::AMDGPU::SendMsg::StreamId
StreamId
Definition: SIDefines.h:337
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1455
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1381
llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1201
llvm::AMDGPU::isHsaAbiVersion2
bool isHsaAbiVersion2(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:108
llvm::AMDGPU::hasPackedD16
bool hasPackedD16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1427
llvm::AMDGPU::Hwreg::isValidHwregWidth
bool isValidHwregWidth(int64_t Width)
Definition: AMDGPUBaseInfo.cpp:1032
llvm::AMDGPU::shouldEmitConstantsToTextSection
bool shouldEmitConstantsToTextSection(const Triple &TT)
Definition: AMDGPUBaseInfo.cpp:848
llvm::AMDGPU::isVI
bool isVI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1439
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::AMDGPU::isInlinableLiteralV216
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1770
llvm::AMDGPU::getMIMGDimInfo
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfo(unsigned DimEnum)
llvm::AMDGPU::getRegBitWidth
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Definition: AMDGPUBaseInfo.cpp:1606
llvm::AMDGPU::getExpcntBitMask
unsigned getExpcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:901
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::AMDGPU::isHsaAbiVersion4
bool isHsaAbiVersion4(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:120
llvm::AMDGPU::IsaInfo::getMinNumSGPRs
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:623
llvm::AMDGPU::isInlinableIntLiteral
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
Definition: AMDGPUBaseInfo.h:832
llvm::AMDGPU::hasG16
bool hasG16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1423
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:380
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:151
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:153
llvm::AMDGPU::isGFX9
bool isGFX9(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1443
llvm::AMDGPU::MIMGLZMappingInfo::L
MIMGBaseOpcode L
Definition: AMDGPUBaseInfo.h:320
llvm::AMDGPU::SIModeRegisterDefaults::allFP64FP16Denormals
bool allFP64FP16Denormals() const
Definition: AMDGPUBaseInfo.h:956
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
llvm::AMDGPU::initDefaultAMDKernelCodeT
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:764
llvm::AMDGPU::Waitcnt::combined
Waitcnt combined(const Waitcnt &Other) const
Definition: AMDGPUBaseInfo.h:501
llvm::AMDGPU::getIntegerAttribute
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
Definition: AMDGPUBaseInfo.cpp:852
llvm::AMDGPU::Waitcnt::hasWaitExceptVsCnt
bool hasWaitExceptVsCnt() const
Definition: AMDGPUBaseInfo.h:488
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccOnOrOff
bool isSramEccOnOrOff() const
Definition: AMDGPUBaseInfo.h:137
llvm::AMDGPU::GcnBufferFormatInfo::BitsPerComp
unsigned BitsPerComp
Definition: AMDGPUBaseInfo.h:56
FP_DENORM_FLUSH_NONE
#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:892
llvm::AMDGPU::getGcnBufferFormatInfo
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2002
llvm::AMDGPU::MIMGMIPMappingInfo
Definition: AMDGPUBaseInfo.h:324
llvm::AMDGPU::IsaInfo::getWavefrontSize
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:517
llvm::AMDGPU::isSISrcInlinableOperand
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this opearnd support only inlinable literals?
Definition: AMDGPUBaseInfo.cpp:1597
llvm::AMDGPU::Hwreg::isValidHwregOffset
bool isValidHwregOffset(int64_t Offset)
Definition: AMDGPUBaseInfo.cpp:1028
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:916
llvm::AMDGPU::encodeVmcnt
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
Definition: AMDGPUBaseInfo.cpp:958
llvm::AMDGPU::getAddrSizeMIMGOp
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
Definition: AMDGPUBaseInfo.cpp:158
llvm::AMDGPU::SendMsg::msgRequiresOp
bool msgRequiresOp(int64_t MsgId)
Definition: AMDGPUBaseInfo.cpp:1312
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getXnackSetting
TargetIDSetting getXnackSetting() const
Definition: AMDGPUBaseInfo.h:115
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:925
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:161
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::AMDGPU::Waitcnt::LgkmCnt
unsigned LgkmCnt
Definition: AMDGPUBaseInfo.h:472
llvm::AMDGPU::Exp::isSupportedTgtId
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1109
llvm::AMDGPU::IsaInfo::getTotalNumSGPRs
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:604
llvm::AMDGPU::getMIMGInfo
const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:155
llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:611
llvm::AMDGPU::MIMGBaseOpcodeInfo::AtomicX2
bool AtomicX2
Definition: AMDGPUBaseInfo.h:284
llvm::AMDGPU::IsaInfo::getNumSGPRBlocks
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
Definition: AMDGPUBaseInfo.cpp:687
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:164
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::AMDGPU::MIMGInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.h:357
llvm::AMDGPU::isInlinableLiteral16
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1751
llvm::AMDGPU::OPERAND_REG_IMM_INT16
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:139
llvm::AMDGPU::getMIMGBaseOpcodeInfo
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::AMDGPU::getMIMGMIPMappingInfo
const LLVM_READONLY MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:162
llvm::AMDGPU::SendMsg::msgSupportsStream
bool msgSupportsStream(int64_t MsgId, int64_t OpId)
Definition: AMDGPUBaseInfo.cpp:1316
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AMDGPU::MIMGLZMappingInfo::LZ
MIMGBaseOpcode LZ
Definition: AMDGPUBaseInfo.h:321
llvm::AMDGPU::Waitcnt::hasWait
bool hasWait() const
Definition: AMDGPUBaseInfo.h:484
llvm::AMDGPU::getVOP3IsSingle
bool getVOP3IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:309
llvm::AMDGPU::isModuleEntryFunctionCC
bool isModuleEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1398
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::AMDGPU::isCompute
bool isCompute(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1377
llvm::AMDGPU::IsaInfo::getVGPREncodingGranule
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:708
uint32_t
llvm::AMDGPU::IsaInfo::getNumVGPRBlocks
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:754
DC
static ManagedStatic< DebugCounter > DC
Definition: DebugCounter.cpp:70
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates
bool Coordinates
Definition: AMDGPUBaseInfo.h:291
llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
Definition: AMDGPUBaseInfo.cpp:1844
llvm::AMDGPU::isSISrcOperand
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:1563
llvm::AMDGPU::Waitcnt::hasWaitVsCnt
bool hasWaitVsCnt() const
Definition: AMDGPUBaseInfo.h:492
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1373
amd_kernel_code_t
AMD Kernel Code Object (amd_kernel_code_t).
Definition: AMDKernelCodeT.h:526
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackSupported
bool isXnackSupported() const
Definition: AMDGPUBaseInfo.h:96
llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:581
llvm::AMDGPU::Exp::getTgtName
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
Definition: AMDGPUBaseInfo.cpp:1075
llvm::AMDGPU::Waitcnt::VmCnt
unsigned VmCnt
Definition: AMDGPUBaseInfo.h:470
llvm::AMDGPU::getMTBUFHasVAddr
bool getMTBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:244
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt)
Definition: AMDGPUBaseInfo.cpp:1192
llvm::AMDGPU::MIMGBaseOpcodeInfo::BaseOpcode
MIMGBaseOpcode BaseOpcode
Definition: AMDGPUBaseInfo.h:281
llvm::AMDGPU::GcnBufferFormatInfo
Definition: AMDGPUBaseInfo.h:54
llvm::AMDGPU::GcnBufferFormatInfo::Format
unsigned Format
Definition: AMDGPUBaseInfo.h:55
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1447
llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:800
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:926
llvm::AMDGPU::isGroupSegment
bool isGroupSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:834
llvm::AMDGPU::Waitcnt::Waitcnt
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
Definition: AMDGPUBaseInfo.h:476
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setSramEccSetting
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
Definition: AMDGPUBaseInfo.h:149
CallingConv.h
llvm::AMDGPU::encodeWaitcnt
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
Definition: AMDGPUBaseInfo.cpp:980
llvm::AMDGPU::SendMsg::isValidMsgOp
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1267
llvm::AMDGPU::isSI
bool isSI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1431
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:165
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString
std::string toString() const
Definition: AMDGPUBaseInfo.cpp:412
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:205
Alignment.h
llvm::AMDGPU::isArgPassedInSGPR
bool isArgPassedInSGPR(const Argument *A)
Definition: AMDGPUBaseInfo.cpp:1809
llvm::AMDGPU::Waitcnt
Represents the counter values to wait for in an s_waitcnt instruction.
Definition: AMDGPUBaseInfo.h:469
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults
SIModeRegisterDefaults()
Definition: AMDGPUBaseInfo.h:928
llvm::AMDGPU::getMUBUFHasVAddr
bool getMUBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:274
llvm::AMDGPU::isInlinableLiteral64
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
Definition: AMDGPUBaseInfo.cpp:1708
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:144
uint16_t
llvm::AMDGPU::getMUBUFElements
int getMUBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:269
llvm::AMDGPU::SendMsg::getMsgOpId
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1255
SIDefines.h
llvm::AMDGPU::MIMGBaseOpcodeInfo::Atomic
bool Atomic
Definition: AMDGPUBaseInfo.h:283
llvm::FPOpFusion::Strict
@ Strict
Definition: TargetOptions.h:39
llvm::AMDGPU::isFoldableLiteralV216
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1796
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrOff
bool isXnackOnOrOff() const
Definition: AMDGPUBaseInfo.h:108
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:156
llvm::AMDGPU::MIMGInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.h:356
llvm::amdhsa::kernel_descriptor_t
Definition: AMDHSAKernelDescriptor.h:165
llvm::AMDGPU::getVOP1IsSingle
bool getVOP1IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:299
llvm::AMDGPU::splitMUBUFOffset
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
Definition: AMDGPUBaseInfo.cpp:1912
llvm::AMDGPU::MIMGInfo
Definition: AMDGPUBaseInfo.h:355
llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
Definition: AMDGPUBaseInfo.cpp:1171
llvm::AMDGPU::Exp::getTgtId
unsigned getTgtId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1086
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:158
llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:728
llvm::AMDGPU::SendMsg::decodeMsg
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId)
Definition: AMDGPUBaseInfo.cpp:1320
llvm::AMDGPU::SendMsg::isValidMsgStream
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1292
llvm::AMDGPU::MTBUFFormat::getNfmtName
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1151
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::AMDGPU::getLgkmcntBitMask
unsigned getLgkmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:905
llvm::AMDGPU::isLegalSMRDImmOffset
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs
uint8_t NumExtraArgs
Definition: AMDGPUBaseInfo.h:288
llvm::AMDGPU::isInlinableLiteral32
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1725
llvm::AMDGPU::GcnBufferFormatInfo::NumComponents
unsigned NumComponents
Definition: AMDGPUBaseInfo.h:57
llvm::AMDGPU::isSISrcFPOperand
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
Definition: AMDGPUBaseInfo.cpp:1570
llvm::AMDGPU::encodeExpcnt
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
Definition: AMDGPUBaseInfo.cpp:969
llvm::AMDGPU::isRegIntersect
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
Is there any intersection between registers.
Definition: AMDGPUBaseInfo.cpp:1488
llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName
StringRef getUnifiedFormatName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1184
llvm::AMDGPU::isGCN3Encoding
bool isGCN3Encoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1457
llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST
@ ROW_NEWBCAST_FIRST
Definition: SIDefines.h:709
llvm::AMDGPU::MTBUFFormat::getNfmt
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1142
llvm::AMDGPU::getOperandSize
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
Definition: AMDGPUBaseInfo.h:784
llvm::AMDGPU::SIModeRegisterDefaults::fpDenormModeSPValue
uint32_t fpDenormModeSPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode.
Definition: AMDGPUBaseInfo.h:962
llvm::AMDGPU::getNumFlatOffsetBits
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
Definition: AMDGPUBaseInfo.cpp:1897
llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:571
llvm::AMDGPU::MIMGDimInfo::DA
bool DA
Definition: AMDGPUBaseInfo.h:305
llvm::AMDGPU::IsaInfo::getMaxWavesPerEU
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:562
llvm::AMDGPU::IsaInfo::getMinNumVGPRs
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:734
llvm::AMDGPU::Hwreg::getHwregId
int64_t getHwregId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:999
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:137
llvm::AMDGPU::hasMIMG_R128
bool hasMIMG_R128(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1415
llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST
@ ROW_NEWBCAST_LAST
Definition: SIDefines.h:710
llvm::AMDGPU::MIMGBaseOpcodeInfo::G16
bool G16
Definition: AMDGPUBaseInfo.h:290
llvm::AMDGPU::MIMGMIPMappingInfo::MIP
MIMGBaseOpcode MIP
Definition: AMDGPUBaseInfo.h:325
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:152
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromFeaturesString
void setTargetIDFromFeaturesString(StringRef FS)
Definition: AMDGPUBaseInfo.cpp:332
llvm::AMDGPU::isReadOnlySegment
bool isReadOnlySegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:842
llvm::AMDGPU::MIMGDimInfo::MSAA
bool MSAA
Definition: AMDGPUBaseInfo.h:304
llvm::AMDGPU::MIMGG16MappingInfo
Definition: AMDGPUBaseInfo.h:329
llvm::AMDGPU::isLegalSMRDEncodedSignedOffset
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:1850
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:142
llvm::AMDGPU::encodeLgkmcnt
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
Definition: AMDGPUBaseInfo.cpp:974
llvm::AMDGPU::Waitcnt::allZero
static Waitcnt allZero(bool HasVscnt)
Definition: AMDGPUBaseInfo.h:479
llvm::AMDGPU::MIMGInfo::VDataDwords
uint8_t VDataDwords
Definition: AMDGPUBaseInfo.h:359
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:166
llvm::AMDGPU::MTBUFFormat::getDfmt
int64_t getDfmt(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1121
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:221
llvm::AMDGPU::isHsaAbiVersion3Or4
bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:126
llvm::AMDGPU::Waitcnt::ExpCnt
unsigned ExpCnt
Definition: AMDGPUBaseInfo.h:471
llvm::AMDGPU::getIntegerPairAttribute
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
Definition: AMDGPUBaseInfo.cpp:867
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccSupported
bool isSramEccSupported() const
Definition: AMDGPUBaseInfo.h:125
llvm::AMDGPU::getMIMGG16MappingInfo
const LLVM_READONLY MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1815
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:152
llvm::AMDGPU::SendMsg::isValidMsgId
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1227
llvm::AMDGPU::MIMGG16MappingInfo::G16
MIMGBaseOpcode G16
Definition: AMDGPUBaseInfo.h:331
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AMDGPU::SIModeRegisterDefaults::allFP32Denormals
bool allFP32Denormals() const
Definition: AMDGPUBaseInfo.h:952
llvm::AMDGPU::getHasColorExport
bool getHasColorExport(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1347
llvm::AMDGPU::getHasDepthExport
bool getHasDepthExport(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1354
llvm::AMDGPU::IsaInfo::getVGPRAllocGranule
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:693
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:138
llvm::AMDGPU::IsaInfo::TRAP_NUM_SGPRS
@ TRAP_NUM_SGPRS
Definition: AMDGPUBaseInfo.h:75
llvm::AMDGPU::getMaskedMIMGOp
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
Definition: AMDGPUBaseInfo.cpp:150
llvm::codeview::PublicSymFlags::Function
@ Function
llvm::AMDGPU::MIMGBaseOpcodeInfo::Sampler
bool Sampler
Definition: AMDGPUBaseInfo.h:285
llvm::AMDGPU::getMTBUFElements
int getMTBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:239
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1172
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:167
llvm::AMDGPU::MIMGDimInfo::NumCoords
uint8_t NumCoords
Definition: AMDGPUBaseInfo.h:302