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AMDGPUBaseInfo.h
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1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/ADT/Optional.h"
14 #include "llvm/IR/CallingConv.h"
15 #include "llvm/Support/Alignment.h"
16 #include <array>
17 #include <functional>
18 #include <utility>
19 
20 struct amd_kernel_code_t;
21 
22 namespace llvm {
23 
24 struct Align;
25 class Argument;
26 class Function;
27 class GCNSubtarget;
28 class GlobalValue;
29 class MCInstrInfo;
30 class MCRegisterClass;
31 class MCRegisterInfo;
32 class MCSubtargetInfo;
33 class StringRef;
34 class Triple;
35 
36 namespace amdhsa {
37 struct kernel_descriptor_t;
38 }
39 
40 namespace AMDGPU {
41 
42 struct IsaVersion;
43 
44 /// \returns HSA OS ABI Version identification.
45 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
46 /// \returns True if HSA OS ABI Version identification is 2,
47 /// false otherwise.
48 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
49 /// \returns True if HSA OS ABI Version identification is 3,
50 /// false otherwise.
51 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
52 /// \returns True if HSA OS ABI Version identification is 4,
53 /// false otherwise.
54 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
55 /// \returns True if HSA OS ABI Version identification is 5,
56 /// false otherwise.
57 bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
58 /// \returns True if HSA OS ABI Version identification is 3 and above,
59 /// false otherwise.
60 bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI);
61 
62 /// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
64 
65 /// \returns The offset of the hostcall pointer argument from implicitarg_ptr
67 
68 /// \returns Code object version.
70 
72  unsigned Format;
73  unsigned BitsPerComp;
74  unsigned NumComponents;
75  unsigned NumFormat;
76  unsigned DataFormat;
77 };
78 
79 struct MAIInstInfo {
81  bool is_dgemm;
83 };
84 
85 #define GET_MIMGBaseOpcode_DECL
86 #define GET_MIMGDim_DECL
87 #define GET_MIMGEncoding_DECL
88 #define GET_MIMGLZMapping_DECL
89 #define GET_MIMGMIPMapping_DECL
90 #define GET_MIMGBiASMapping_DECL
91 #define GET_MAIInstInfoTable_DECL
92 #include "AMDGPUGenSearchableTables.inc"
93 
94 namespace IsaInfo {
95 
96 enum {
97  // The closed Vulkan driver sets 96, which limits the wave count to 8 but
98  // doesn't spill SGPRs as much as when 80 is set.
101 };
102 
103 enum class TargetIDSetting {
104  Unsupported,
105  Any,
106  Off,
107  On
108 };
109 
111 private:
112  const MCSubtargetInfo &STI;
113  TargetIDSetting XnackSetting;
114  TargetIDSetting SramEccSetting;
115 
116 public:
117  explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
118  ~AMDGPUTargetID() = default;
119 
120  /// \return True if the current xnack setting is not "Unsupported".
121  bool isXnackSupported() const {
122  return XnackSetting != TargetIDSetting::Unsupported;
123  }
124 
125  /// \returns True if the current xnack setting is "On" or "Any".
126  bool isXnackOnOrAny() const {
127  return XnackSetting == TargetIDSetting::On ||
128  XnackSetting == TargetIDSetting::Any;
129  }
130 
131  /// \returns True if current xnack setting is "On" or "Off",
132  /// false otherwise.
133  bool isXnackOnOrOff() const {
134  return getXnackSetting() == TargetIDSetting::On ||
136  }
137 
138  /// \returns The current xnack TargetIDSetting, possible options are
139  /// "Unsupported", "Any", "Off", and "On".
141  return XnackSetting;
142  }
143 
144  /// Sets xnack setting to \p NewXnackSetting.
145  void setXnackSetting(TargetIDSetting NewXnackSetting) {
146  XnackSetting = NewXnackSetting;
147  }
148 
149  /// \return True if the current sramecc setting is not "Unsupported".
150  bool isSramEccSupported() const {
151  return SramEccSetting != TargetIDSetting::Unsupported;
152  }
153 
154  /// \returns True if the current sramecc setting is "On" or "Any".
155  bool isSramEccOnOrAny() const {
156  return SramEccSetting == TargetIDSetting::On ||
157  SramEccSetting == TargetIDSetting::Any;
158  }
159 
160  /// \returns True if current sramecc setting is "On" or "Off",
161  /// false otherwise.
162  bool isSramEccOnOrOff() const {
165  }
166 
167  /// \returns The current sramecc TargetIDSetting, possible options are
168  /// "Unsupported", "Any", "Off", and "On".
170  return SramEccSetting;
171  }
172 
173  /// Sets sramecc setting to \p NewSramEccSetting.
174  void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
175  SramEccSetting = NewSramEccSetting;
176  }
177 
180 
181  /// \returns String representation of an object.
182  std::string toString() const;
183 };
184 
185 /// \returns Wavefront size for given subtarget \p STI.
186 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
187 
188 /// \returns Local memory size in bytes for given subtarget \p STI.
189 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
190 
191 /// \returns Number of execution units per compute unit for given subtarget \p
192 /// STI.
193 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
194 
195 /// \returns Maximum number of work groups per compute unit for given subtarget
196 /// \p STI and limited by given \p FlatWorkGroupSize.
197 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
198  unsigned FlatWorkGroupSize);
199 
200 /// \returns Minimum number of waves per execution unit for given subtarget \p
201 /// STI.
202 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
203 
204 /// \returns Maximum number of waves per execution unit for given subtarget \p
205 /// STI without any kind of limitation.
206 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
207 
208 /// \returns Number of waves per execution unit required to support the given \p
209 /// FlatWorkGroupSize.
210 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
211  unsigned FlatWorkGroupSize);
212 
213 /// \returns Minimum flat work group size for given subtarget \p STI.
214 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
215 
216 /// \returns Maximum flat work group size for given subtarget \p STI.
217 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
218 
219 /// \returns Number of waves per work group for given subtarget \p STI and
220 /// \p FlatWorkGroupSize.
221 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
222  unsigned FlatWorkGroupSize);
223 
224 /// \returns SGPR allocation granularity for given subtarget \p STI.
225 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
226 
227 /// \returns SGPR encoding granularity for given subtarget \p STI.
228 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
229 
230 /// \returns Total number of SGPRs for given subtarget \p STI.
231 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
232 
233 /// \returns Addressable number of SGPRs for given subtarget \p STI.
234 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
235 
236 /// \returns Minimum number of SGPRs that meets the given number of waves per
237 /// execution unit requirement for given subtarget \p STI.
238 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
239 
240 /// \returns Maximum number of SGPRs that meets the given number of waves per
241 /// execution unit requirement for given subtarget \p STI.
242 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
243  bool Addressable);
244 
245 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
246 /// STI when the given special registers are used.
247 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
248  bool FlatScrUsed, bool XNACKUsed);
249 
250 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
251 /// STI when the given special registers are used. XNACK is inferred from
252 /// \p STI.
253 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
254  bool FlatScrUsed);
255 
256 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
257 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
258 /// register counts.
259 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
260 
261 /// \returns VGPR allocation granularity for given subtarget \p STI.
262 ///
263 /// For subtargets which support it, \p EnableWavefrontSize32 should match
264 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
265 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
266  Optional<bool> EnableWavefrontSize32 = None);
267 
268 /// \returns VGPR encoding granularity for given subtarget \p STI.
269 ///
270 /// For subtargets which support it, \p EnableWavefrontSize32 should match
271 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
272 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
273  Optional<bool> EnableWavefrontSize32 = None);
274 
275 /// \returns Total number of VGPRs for given subtarget \p STI.
276 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
277 
278 /// \returns Addressable number of VGPRs for given subtarget \p STI.
279 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
280 
281 /// \returns Minimum number of VGPRs that meets given number of waves per
282 /// execution unit requirement for given subtarget \p STI.
283 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
284 
285 /// \returns Maximum number of VGPRs that meets given number of waves per
286 /// execution unit requirement for given subtarget \p STI.
287 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
288 
289 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
290 /// \p NumVGPRs are used.
291 ///
292 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
293 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
294 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
295  Optional<bool> EnableWavefrontSize32 = None);
296 
297 } // end namespace IsaInfo
298 
300 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
301 
303 inline bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx) {
304  return getNamedOperandIdx(Opcode, NamedIdx) != -1;
305 }
306 
308 int getSOPPWithRelaxation(uint16_t Opcode);
309 
311  MIMGBaseOpcode BaseOpcode;
312  bool Store;
313  bool Atomic;
314  bool AtomicX2;
315  bool Sampler;
316  bool Gather4;
317 
318  uint8_t NumExtraArgs;
319  bool Gradients;
320  bool G16;
323  bool HasD16;
324  bool MSAA;
325  bool BVH;
326 };
327 
329 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
330 
332 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
333 
334 struct MIMGDimInfo {
335  MIMGDim Dim;
336  uint8_t NumCoords;
337  uint8_t NumGradients;
338  bool MSAA;
339  bool DA;
340  uint8_t Encoding;
341  const char *AsmSuffix;
342 };
343 
345 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
346 
348 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
349 
352 
354  MIMGBaseOpcode L;
355  MIMGBaseOpcode LZ;
356 };
357 
359  MIMGBaseOpcode MIP;
360  MIMGBaseOpcode NONMIP;
361 };
362 
364  MIMGBaseOpcode Bias;
365  MIMGBaseOpcode NoBias;
366 };
367 
369  MIMGBaseOpcode Offset;
370  MIMGBaseOpcode NoOffset;
371 };
372 
374  MIMGBaseOpcode G;
375  MIMGBaseOpcode G16;
376 };
377 
379 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
380 
382  unsigned Opcode2Addr;
383  unsigned Opcode3Addr;
384 };
385 
387 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
388 
390 const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
391 
393 const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);
394 
397 
399 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
400  unsigned VDataDwords, unsigned VAddrDwords);
401 
403 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
404 
406 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
407  const MIMGDimInfo *Dim, bool IsA16,
408  bool IsG16Supported);
409 
410 struct MIMGInfo {
413  uint8_t MIMGEncoding;
414  uint8_t VDataDwords;
415  uint8_t VAddrDwords;
416  uint8_t VAddrOperands;
417 };
418 
420 const MIMGInfo *getMIMGInfo(unsigned Opc);
421 
423 int getMTBUFBaseOpcode(unsigned Opc);
424 
426 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
427 
429 int getMTBUFElements(unsigned Opc);
430 
432 bool getMTBUFHasVAddr(unsigned Opc);
433 
435 bool getMTBUFHasSrsrc(unsigned Opc);
436 
438 bool getMTBUFHasSoffset(unsigned Opc);
439 
441 int getMUBUFBaseOpcode(unsigned Opc);
442 
444 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
445 
447 int getMUBUFElements(unsigned Opc);
448 
450 bool getMUBUFHasVAddr(unsigned Opc);
451 
453 bool getMUBUFHasSrsrc(unsigned Opc);
454 
456 bool getMUBUFHasSoffset(unsigned Opc);
457 
459 bool getMUBUFIsBufferInv(unsigned Opc);
460 
462 bool getSMEMIsBuffer(unsigned Opc);
463 
465 bool getVOP1IsSingle(unsigned Opc);
466 
468 bool getVOP2IsSingle(unsigned Opc);
469 
471 bool getVOP3IsSingle(unsigned Opc);
472 
474 bool isVOPC64DPP(unsigned Opc);
475 
476 /// Returns true if MAI operation is a double precision GEMM.
478 bool getMAIIsDGEMM(unsigned Opc);
479 
481 bool getMAIIsGFX940XDL(unsigned Opc);
482 
483 struct CanBeVOPD {
484  bool X;
485  bool Y;
486 };
487 
489 CanBeVOPD getCanBeVOPD(unsigned Opc);
490 
492 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
493  uint8_t NumComponents,
494  uint8_t NumFormat,
495  const MCSubtargetInfo &STI);
497 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
498  const MCSubtargetInfo &STI);
499 
501 int getMCOpcode(uint16_t Opcode, unsigned Gen);
502 
504 unsigned getVOPDOpcode(unsigned Opc);
505 
507 int getVOPDFull(unsigned OpX, unsigned OpY);
508 
510 bool isVOPD(unsigned Opc);
511 
512 namespace VOPD {
513 
514 enum Component : unsigned {
515  DST = 0,
519 
520  DST_NUM = 1,
523 };
524 
525 // Number of VGPR banks per VOPD component operand.
526 constexpr unsigned BANKS_NUM[] = {2, 4, 4, 2};
527 
528 enum ComponentIndex : unsigned { X = 0, Y = 1 };
530 constexpr unsigned COMPONENTS_NUM = 2;
531 
532 // Properties of VOPD components.
534 private:
535  unsigned SrcOperandsNum = 0;
536  Optional<unsigned> MandatoryLiteralIdx;
537  bool HasSrc2Acc = false;
538 
539 public:
540  ComponentProps() = default;
541  ComponentProps(const MCInstrDesc &OpDesc);
542 
543  // Return the total number of src operands this component has.
544  unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }
545 
546  // Return the number of src operands of this component visible to the parser.
547  unsigned getCompParsedSrcOperandsNum() const {
548  return SrcOperandsNum - HasSrc2Acc;
549  }
550 
551  // Return true iif this component has a mandatory literal.
552  bool hasMandatoryLiteral() const { return MandatoryLiteralIdx.has_value(); }
553 
554  // If this component has a mandatory literal, return component operand
555  // index of this literal (i.e. either Component::SRC1 or Component::SRC2).
558  return *MandatoryLiteralIdx;
559  }
560 
561  // Return true iif this component has operand
562  // with component index CompSrcIdx and this operand may be a register.
563  bool hasRegSrcOperand(unsigned CompSrcIdx) const {
564  assert(CompSrcIdx < Component::MAX_SRC_NUM);
565  return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
566  }
567 
568  // Return true iif this component has tied src2.
569  bool hasSrc2Acc() const { return HasSrc2Acc; }
570 
571 private:
572  bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
573  assert(CompSrcIdx < Component::MAX_SRC_NUM);
574  return hasMandatoryLiteral() &&
575  *MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;
576  }
577 };
578 
579 enum ComponentKind : unsigned {
580  SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.
581  COMPONENT_X, // A VOPD instruction, X component.
582  COMPONENT_Y, // A VOPD instruction, Y component.
584 };
585 
586 // Interface functions of this class map VOPD component operand indices
587 // to indices of operands in MachineInstr/MCInst or parsed operands array.
588 //
589 // Note that this class operates with 3 kinds of indices:
590 // - VOPD component operand indices (Component::DST, Component::SRC0, etc.);
591 // - MC operand indices (they refer operands in a MachineInstr/MCInst);
592 // - parsed operand indices (they refer operands in parsed operands array).
593 //
594 // For SINGLE components mapping between these indices is trivial.
595 // But things get more complicated for COMPONENT_X and
596 // COMPONENT_Y because these components share the same
597 // MachineInstr/MCInst and the same parsed operands array.
598 // Below is an example of component operand to parsed operand
599 // mapping for the following instruction:
600 //
601 // v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1
602 //
603 // PARSED COMPONENT PARSED
604 // COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX
605 // -------------------------------------------------------------------
606 // "v_dual_add_f32" 0
607 // v_dual_add_f32 v255 0 (DST) --> 1
608 // v4 1 (SRC0) --> 2
609 // v5 2 (SRC1) --> 3
610 // "::" 4
611 // "v_dual_mov_b32" 5
612 // v_dual_mov_b32 v6 0 (DST) --> 6
613 // v1 1 (SRC0) --> 7
614 // -------------------------------------------------------------------
615 //
617 private:
618  // Regular MachineInstr/MCInst operands are ordered as follows:
619  // dst, src0 [, other src operands]
620  // VOPD MachineInstr/MCInst operands are ordered as follows:
621  // dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
622  // Each ComponentKind has operand indices defined below.
623  static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
624  static constexpr unsigned FIRST_MC_SRC_IDX[] = {1, 2, 2 /* + OpX.MCSrcNum */};
625 
626  // Parsed operands of regular instructions are ordered as follows:
627  // Mnemo dst src0 [vsrc1 ...]
628  // Parsed VOPD operands are ordered as follows:
629  // OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'
630  // OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]
631  // Each ComponentKind has operand indices defined below.
632  static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
633  4 /* + OpX.ParsedSrcNum */};
634  static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
635  2, 2, 5 /* + OpX.ParsedSrcNum */};
636 
637 private:
638  const ComponentKind Kind;
639  const ComponentProps PrevComp;
640 
641 public:
642  // Create layout for COMPONENT_X or SINGLE component.
643  ComponentLayout(ComponentKind Kind) : Kind(Kind) {
645  }
646 
647  // Create layout for COMPONENT_Y which depends on COMPONENT_X layout.
649  : Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps) {}
650 
651 public:
652  // Return the index of dst operand in MCInst operands.
653  unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }
654 
655  // Return the index of the specified src operand in MCInst operands.
656  unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const {
657  assert(CompSrcIdx < Component::MAX_SRC_NUM);
658  return FIRST_MC_SRC_IDX[Kind] + getPrevCompSrcNum() + CompSrcIdx;
659  }
660 
661  // Return the index of dst operand in the parsed operands array.
662  unsigned getIndexOfDstInParsedOperands() const {
663  return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
664  }
665 
666  // Return the index of the specified src operand in the parsed operands array.
667  unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {
668  assert(CompSrcIdx < Component::MAX_SRC_NUM);
669  return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
670  }
671 
672 private:
673  unsigned getPrevCompSrcNum() const {
674  return PrevComp.getCompSrcOperandsNum();
675  }
676  unsigned getPrevCompParsedSrcNum() const {
677  return PrevComp.getCompParsedSrcOperandsNum();
678  }
679 };
680 
681 // Layout and properties of VOPD components.
683 public:
684  // Create ComponentInfo for COMPONENT_X or SINGLE component.
685  ComponentInfo(const MCInstrDesc &OpDesc,
687  : ComponentLayout(Kind), ComponentProps(OpDesc) {}
688 
689  // Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.
690  ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
691  : ComponentLayout(OpXProps), ComponentProps(OpDesc) {}
692 
693  // Map component operand index to parsed operand index.
694  // Return 0 if the specified operand does not exist.
695  unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;
696 };
697 
698 // Properties of VOPD instructions.
699 class InstInfo {
700 private:
701  const ComponentInfo CompInfo[COMPONENTS_NUM];
702 
703 public:
704  using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
705 
706  InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
707  : CompInfo{OpX, OpY} {}
708 
709  InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
710  : CompInfo{OprInfoX, OprInfoY} {}
711 
712  const ComponentInfo &operator[](size_t ComponentIdx) const {
713  assert(ComponentIdx < COMPONENTS_NUM);
714  return CompInfo[ComponentIdx];
715  }
716 
717  // Check VOPD operands constraints.
718  // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
719  // for the specified component and MC operand. The callback must return 0
720  // if the operand is not a register or not a VGPR.
722  std::function<unsigned(unsigned, unsigned)> GetRegIdx) const {
723  return getInvalidCompOperandIndex(GetRegIdx).has_value();
724  }
725 
726  // Check VOPD operands constraints.
727  // Return the index of an invalid component operand, if any.
729  std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
730 
731 private:
732  RegIndices
733  getRegIndices(unsigned ComponentIdx,
734  std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
735 };
736 
737 } // namespace VOPD
738 
740 std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
741 
743 // Get properties of 2 single VOP1/VOP2 instructions
744 // used as components to create a VOPD instruction.
745 VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
746 
748 // Get properties of VOPD X and Y components.
749 VOPD::InstInfo
750 getVOPDInstInfo(unsigned VOPDOpcode, const MCInstrInfo *InstrInfo);
751 
753 bool isTrue16Inst(unsigned Opc);
754 
756 unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
757 
759 unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
760 
762  const MCSubtargetInfo *STI);
763 
765  const MCSubtargetInfo *STI);
766 
767 bool isGroupSegment(const GlobalValue *GV);
768 bool isGlobalSegment(const GlobalValue *GV);
769 bool isReadOnlySegment(const GlobalValue *GV);
770 
771 /// \returns True if constants should be emitted to .text section for given
772 /// target triple \p TT, false otherwise.
774 
775 /// \returns Integer value requested using \p F's \p Name attribute.
776 ///
777 /// \returns \p Default if attribute is not present.
778 ///
779 /// \returns \p Default and emits error if requested value cannot be converted
780 /// to integer.
781 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
782 
783 /// \returns A pair of integer values requested using \p F's \p Name attribute
784 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
785 /// is false).
786 ///
787 /// \returns \p Default if attribute is not present.
788 ///
789 /// \returns \p Default and emits error if one of the requested values cannot be
790 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
791 /// not present.
792 std::pair<int, int> getIntegerPairAttribute(const Function &F,
793  StringRef Name,
794  std::pair<int, int> Default,
795  bool OnlyFirstRequired = false);
796 
797 /// Represents the counter values to wait for in an s_waitcnt instruction.
798 ///
799 /// Large values (including the maximum possible integer) can be used to
800 /// represent "don't care" waits.
801 struct Waitcnt {
802  unsigned VmCnt = ~0u;
803  unsigned ExpCnt = ~0u;
804  unsigned LgkmCnt = ~0u;
805  unsigned VsCnt = ~0u;
806 
807  Waitcnt() = default;
808  Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
810 
811  static Waitcnt allZero(bool HasVscnt) {
812  return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
813  }
814  static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
815 
816  bool hasWait() const {
817  return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
818  }
819 
820  bool hasWaitExceptVsCnt() const {
821  return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
822  }
823 
824  bool hasWaitVsCnt() const {
825  return VsCnt != ~0u;
826  }
827 
828  bool dominates(const Waitcnt &Other) const {
829  return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
830  LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
831  }
832 
833  Waitcnt combined(const Waitcnt &Other) const {
834  return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
835  std::min(LgkmCnt, Other.LgkmCnt),
836  std::min(VsCnt, Other.VsCnt));
837  }
838 };
839 
840 /// \returns Vmcnt bit mask for given isa \p Version.
841 unsigned getVmcntBitMask(const IsaVersion &Version);
842 
843 /// \returns Expcnt bit mask for given isa \p Version.
844 unsigned getExpcntBitMask(const IsaVersion &Version);
845 
846 /// \returns Lgkmcnt bit mask for given isa \p Version.
847 unsigned getLgkmcntBitMask(const IsaVersion &Version);
848 
849 /// \returns Waitcnt bit mask for given isa \p Version.
850 unsigned getWaitcntBitMask(const IsaVersion &Version);
851 
852 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
853 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
854 
855 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
856 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
857 
858 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
859 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
860 
861 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
862 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
863 /// \p Lgkmcnt respectively.
864 ///
865 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
866 /// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
867 /// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
868 /// \p Vmcnt = \p Waitcnt[15:10] (gfx11+)
869 /// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
870 /// \p Expcnt = \p Waitcnt[2:0] (gfx11+)
871 /// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
872 /// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
873 /// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11+)
874 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
875  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
876 
877 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
878 
879 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
880 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
881  unsigned Vmcnt);
882 
883 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
884 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
885  unsigned Expcnt);
886 
887 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
888 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
889  unsigned Lgkmcnt);
890 
891 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
892 /// \p Version.
893 ///
894 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
895 /// Waitcnt[2:0] = \p Expcnt (gfx11+)
896 /// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
897 /// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
898 /// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
899 /// Waitcnt[9:4] = \p Lgkmcnt (gfx11+)
900 /// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
901 /// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
902 /// Waitcnt[15:10] = \p Vmcnt (gfx11+)
903 /// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
904 ///
905 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
906 /// isa \p Version.
907 unsigned encodeWaitcnt(const IsaVersion &Version,
908  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
909 
910 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
911 
912 namespace Hwreg {
913 
915 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
916 
918 bool isValidHwreg(int64_t Id);
919 
921 bool isValidHwregOffset(int64_t Offset);
922 
924 bool isValidHwregWidth(int64_t Width);
925 
928 
930 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
931 
932 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
933 
934 } // namespace Hwreg
935 
936 namespace DepCtr {
937 
938 int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
939 int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
940  const MCSubtargetInfo &STI);
941 bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
942  const MCSubtargetInfo &STI);
943 bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
944  bool &IsDefault, const MCSubtargetInfo &STI);
945 
946 } // namespace DepCtr
947 
948 namespace Exp {
949 
950 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
951 
953 unsigned getTgtId(const StringRef Name);
954 
956 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
957 
958 } // namespace Exp
959 
960 namespace MTBUFFormat {
961 
963 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
964 
965 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
966 
967 int64_t getDfmt(const StringRef Name);
968 
969 StringRef getDfmtName(unsigned Id);
970 
971 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
972 
973 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
974 
975 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
976 
977 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
978 
979 int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
980 
981 StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
982 
983 bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
984 
985 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
986  const MCSubtargetInfo &STI);
987 
988 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
989 
990 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
991 
992 } // namespace MTBUFFormat
993 
994 namespace SendMsg {
995 
997 int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
998 
1000 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
1001 
1003 StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
1004 
1006 StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1007 
1009 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
1010 
1012 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1013  bool Strict = true);
1014 
1016 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1017  const MCSubtargetInfo &STI, bool Strict = true);
1018 
1020 bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
1021 
1023 bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1024 
1025 void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1026  uint16_t &StreamId, const MCSubtargetInfo &STI);
1027 
1030  uint64_t OpId,
1031  uint64_t StreamId);
1032 
1033 } // namespace SendMsg
1034 
1035 
1036 unsigned getInitialPSInputAddr(const Function &F);
1037 
1038 bool getHasColorExport(const Function &F);
1039 
1040 bool getHasDepthExport(const Function &F);
1041 
1044 
1047 
1050 
1053 
1054 // These functions are considered entrypoints into the current module, i.e. they
1055 // are allowed to be called from outside the current module. This is different
1056 // from isEntryFunctionCC, which is only true for functions that are entered by
1057 // the hardware. Module entry points include all entry functions but also
1058 // include functions that can be called from other functions inside or outside
1059 // the current module. Module entry functions are allowed to allocate LDS.
1062 
1063 bool isKernelCC(const Function *Func);
1064 
1065 // FIXME: Remove this when calling conventions cleaned up
1068  switch (CC) {
1071  return true;
1072  default:
1073  return false;
1074  }
1075 }
1076 
1077 bool hasXNACK(const MCSubtargetInfo &STI);
1078 bool hasSRAMECC(const MCSubtargetInfo &STI);
1079 bool hasMIMG_R128(const MCSubtargetInfo &STI);
1080 bool hasGFX10A16(const MCSubtargetInfo &STI);
1081 bool hasG16(const MCSubtargetInfo &STI);
1082 bool hasPackedD16(const MCSubtargetInfo &STI);
1083 
1084 bool isSI(const MCSubtargetInfo &STI);
1085 bool isCI(const MCSubtargetInfo &STI);
1086 bool isVI(const MCSubtargetInfo &STI);
1087 bool isGFX9(const MCSubtargetInfo &STI);
1088 bool isGFX9_GFX10(const MCSubtargetInfo &STI);
1089 bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
1090 bool isGFX8Plus(const MCSubtargetInfo &STI);
1091 bool isGFX9Plus(const MCSubtargetInfo &STI);
1092 bool isGFX10(const MCSubtargetInfo &STI);
1093 bool isGFX10Plus(const MCSubtargetInfo &STI);
1094 bool isNotGFX10Plus(const MCSubtargetInfo &STI);
1095 bool isGFX10Before1030(const MCSubtargetInfo &STI);
1096 bool isGFX11(const MCSubtargetInfo &STI);
1097 bool isGFX11Plus(const MCSubtargetInfo &STI);
1098 bool isNotGFX11Plus(const MCSubtargetInfo &STI);
1099 bool isGCN3Encoding(const MCSubtargetInfo &STI);
1100 bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
1101 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
1102 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
1103 bool isGFX90A(const MCSubtargetInfo &STI);
1104 bool isGFX940(const MCSubtargetInfo &STI);
1106 bool hasMAIInsts(const MCSubtargetInfo &STI);
1107 bool hasVOPD(const MCSubtargetInfo &STI);
1108 int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
1109 
1110 /// Is Reg - scalar register
1111 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
1112 
1113 /// If \p Reg is a pseudo reg, return the correct hardware register given
1114 /// \p STI otherwise return \p Reg.
1115 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
1116 
1117 /// Convert hardware register \p Reg to a pseudo register
1119 unsigned mc2PseudoReg(unsigned Reg);
1120 
1121 /// Can this operand also contain immediate values?
1122 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1123 
1124 /// Is this floating-point operand?
1125 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1126 
1127 /// Does this operand support only inlinable literals?
1128 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1129 
1130 /// Get the size in bits of a register from the register class \p RC.
1131 unsigned getRegBitWidth(unsigned RCID);
1132 
1133 /// Get the size in bits of a register from the register class \p RC.
1134 unsigned getRegBitWidth(const MCRegisterClass &RC);
1135 
1136 /// Get size of register operand
1137 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
1138  unsigned OpNo);
1139 
1141 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
1142  switch (OpInfo.OperandType) {
1155  case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
1156  return 4;
1157 
1163  return 8;
1164 
1178  return 2;
1179 
1180  default:
1181  llvm_unreachable("unhandled operand type");
1182  }
1183 }
1184 
1186 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
1187  return getOperandSize(Desc.OpInfo[OpNo]);
1188 }
1189 
1190 /// Is this literal inlinable, and not one of the values intended for floating
1191 /// point values.
1193 inline bool isInlinableIntLiteral(int64_t Literal) {
1194  return Literal >= -16 && Literal <= 64;
1195 }
1196 
1197 /// Is this literal inlinable
1199 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
1200 
1202 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
1203 
1205 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
1206 
1208 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
1209 
1211 bool isInlinableIntLiteralV216(int32_t Literal);
1212 
1214 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
1215 
1216 bool isArgPassedInSGPR(const Argument *Arg);
1217 
1220  int64_t EncodedOffset);
1221 
1224  int64_t EncodedOffset,
1225  bool IsBuffer);
1226 
1227 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
1228 /// offsets.
1230 
1231 /// \returns The encoding that will be used for \p ByteOffset in the
1232 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
1233 /// S_LOAD instructions have a signed offset, on other subtargets it is
1234 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
1236  int64_t ByteOffset, bool IsBuffer);
1237 
1238 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
1239 /// instruction. This is only useful on CI.s
1241  int64_t ByteOffset);
1242 
1243 /// For FLAT segment the offset must be positive;
1244 /// MSB is ignored and forced to zero.
1245 ///
1246 /// \return The number of bits available for the offset field in flat
1247 /// instructions.
1248 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
1249 
1250 /// \returns true if this offset is small enough to fit in the SMRD
1251 /// offset field. \p ByteOffset should be the offset in bytes and
1252 /// not the encoded offset.
1253 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
1254 
1255 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
1256  const GCNSubtarget *Subtarget,
1257  Align Alignment = Align(4));
1258 
1260 inline bool isLegal64BitDPPControl(unsigned DC) {
1261  return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
1262 }
1263 
1264 /// \returns true if the intrinsic is divergent
1265 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
1266 
1267 // Track defaults for fields in the MODE register.
1269  /// Floating point opcodes that support exception flag gathering quiet and
1270  /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
1271  /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
1272  /// quieting.
1273  bool IEEE : 1;
1274 
1275  /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
1276  /// clamp NaN to zero; otherwise, pass NaN through.
1277  bool DX10Clamp : 1;
1278 
1279  /// If this is set, neither input or output denormals are flushed for most f32
1280  /// instructions.
1283 
1284  /// If this is set, neither input or output denormals are flushed for both f64
1285  /// and f16/v2f16 instructions.
1288 
1290  IEEE(true),
1291  DX10Clamp(true),
1296 
1298 
1301  Mode.IEEE = !AMDGPU::isShader(CC);
1302  return Mode;
1303  }
1304 
1305  bool operator ==(const SIModeRegisterDefaults Other) const {
1306  return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
1307  FP32InputDenormals == Other.FP32InputDenormals &&
1308  FP32OutputDenormals == Other.FP32OutputDenormals &&
1309  FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
1310  FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
1311  }
1312 
1313  bool allFP32Denormals() const {
1315  }
1316 
1317  bool allFP64FP16Denormals() const {
1319  }
1320 
1321  /// Get the encoding value for the FP_DENORM bits of the mode register for the
1322  /// FP32 denormal mode.
1325  return FP_DENORM_FLUSH_NONE;
1326  if (FP32InputDenormals)
1327  return FP_DENORM_FLUSH_OUT;
1328  if (FP32OutputDenormals)
1329  return FP_DENORM_FLUSH_IN;
1331  }
1332 
1333  /// Get the encoding value for the FP_DENORM bits of the mode register for the
1334  /// FP64/FP16 denormal mode.
1337  return FP_DENORM_FLUSH_NONE;
1339  return FP_DENORM_FLUSH_OUT;
1341  return FP_DENORM_FLUSH_IN;
1343  }
1344 
1345  /// Returns true if a flag is compatible if it's enabled in the callee, but
1346  /// disabled in the caller.
1347  static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
1348  return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
1349  }
1350 
1351  // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
1352  // be able to override.
1354  if (DX10Clamp != CalleeMode.DX10Clamp)
1355  return false;
1356  if (IEEE != CalleeMode.IEEE)
1357  return false;
1358 
1359  // Allow inlining denormals enabled into denormals flushed functions.
1364  }
1365 };
1366 
1367 } // end namespace AMDGPU
1368 
1369 raw_ostream &operator<<(raw_ostream &OS,
1371 
1372 } // end namespace llvm
1373 
1374 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:173
llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1613
llvm::AMDGPU::Hwreg::encodeHwreg
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
Definition: AMDGPUBaseInfo.cpp:1437
FP_DENORM_FLUSH_OUT
#define FP_DENORM_FLUSH_OUT
Definition: SIDefines.h:1031
llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:442
llvm::AMDGPU::SIModeRegisterDefaults::fpDenormModeDPValue
uint32_t fpDenormModeDPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.
Definition: AMDGPUBaseInfo.h:1335
llvm::AMDGPU::getMUBUFIsBufferInv
bool getMUBUFIsBufferInv(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:381
llvm::AMDGPU::VOPD::COMPONENTS_NUM
constexpr unsigned COMPONENTS_NUM
Definition: AMDGPUBaseInfo.h:530
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:2025
llvm::AMDGPU::isHsaAbiVersion3
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:126
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::AMDGPUTargetID
AMDGPUTargetID(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:573
llvm::AMDGPU::getMIMGDimInfoByEncoding
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
llvm::AMDGPU::mc2PseudoReg
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
Definition: AMDGPUBaseInfo.cpp:2041
llvm::AMDGPU::VOPD::ComponentLayout::getIndexOfSrcInMCOperands
unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const
Definition: AMDGPUBaseInfo.h:656
llvm::AMDGPU::VOPD::SINGLE
@ SINGLE
Definition: AMDGPUBaseInfo.h:580
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4715
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:196
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
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Definition: AMDGPUBaseInfo.cpp:410
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Definition: AMDGPUBaseInfo.h:323
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Definition: AMDGPUBaseInfo.h:518
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Definition: AMDGPUBaseInfo.h:814
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Definition: AMDGPUBaseInfo.cpp:1950
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Definition: SIDefines.h:168
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Definition: AMDGPUBaseInfo.h:312
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Definition: AMDGPUMetadata.h:258
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Definition: AMDGPUBaseInfo.cpp:1177
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Definition: AMDGPUBaseInfo.h:1273
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Definition: AMDGPUBaseInfo.cpp:1833
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Definition: SIDefines.h:181
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Definition: SIDefines.h:162
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Definition: AMDGPUBaseInfo.cpp:433
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Definition: AMDGPUBaseInfo.cpp:1926
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Definition: AMDGPUBaseInfo.h:1260
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Definition: AMDGPUBaseInfo.h:316
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Definition: AMDGPUBaseInfo.cpp:1922
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Definition: AMDGPUBaseInfo.cpp:396
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Definition: AMDGPUBaseInfo.h:334
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~AMDGPUTargetID()=default
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Definition: X86DisassemblerDecoder.h:462
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Definition: AMDGPUBaseInfo.cpp:1942
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Definition: AMDGPUBaseInfo.cpp:1583
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Definition: AMDGPUBaseInfo.cpp:101
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Definition: SIDefines.h:1032
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Definition: Triple.h:44
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Definition: AMDGPUBaseInfo.cpp:459
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Definition: AMDGPUBaseInfo.cpp:149
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Definition: AMDGPUBaseInfo.cpp:1579
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Definition: AMDGPUBaseInfo.h:526
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Definition: AMDGPUBaseInfo.cpp:1406
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Definition: BasicAliasAnalysis.cpp:1793
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Definition: AMDGPUBaseInfo.cpp:1898
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Definition: AMDGPUBaseInfo.h:533
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Definition: AMDGPUBaseInfo.h:517
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Definition: SIDefines.h:164
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Definition: X86.h:200
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Definition: AMDGPUBaseInfo.cpp:909
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Definition: AMDGPUBaseInfo.cpp:1890
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Definition: AMDGPUBaseInfo.h:583
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Definition: AMDGPUBaseInfo.cpp:976
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Definition: AMDGPUBaseInfo.h:514
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Definition: AMDGPUBaseInfo.cpp:650
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Definition: AMDGPUBaseInfo.h:363
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Definition: AMDGPUBaseInfo.cpp:810
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Definition: AMDGPUBaseInfo.h:1299
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Definition: AMDGPUBaseInfo.h:1268
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Definition: AMDGPUBaseInfo.h:1281
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Definition: AMDGPUBaseInfo.h:528
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Definition: GCNSubtarget.h:31
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Definition: AMDGPUBaseInfo.h:484
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Definition: AMDGPUBaseInfo.cpp:1151
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Definition: AMDGPUBaseInfo.h:1353
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Definition: AMDGPUBaseInfo.cpp:1097
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Definition: AMDGPUBaseInfo.h:335
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Definition: AMDGPUBaseInfo.h:563
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Definition: AMDGPUBaseInfo.cpp:1930
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Returns true if a flag is compatible if it's enabled in the callee, but disabled in the caller.
Definition: AMDGPUBaseInfo.h:1347
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Definition: AMDGPUBaseInfo.cpp:1004
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Definition: AMDGPUBaseInfo.h:325
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Definition: AMDGPUBaseInfo.cpp:1165
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Definition: AMDGPUBaseInfo.cpp:2503
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Definition: AMDGPUBaseInfo.h:337
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Definition: MachineSink.cpp:1628
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Definition: AMDGPUBaseInfo.cpp:326
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Definition: AMDGPUBaseInfo.h:360
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Definition: AMDGPUBaseInfo.cpp:798
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Definition: MD5.cpp:55
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Definition: AMDGPUBaseInfo.cpp:1572
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Definition: AMDGPUBaseInfo.cpp:437
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Definition: AMDGPUBaseInfo.h:485
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Definition: MCRegisterInfo.h:31
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Definition: AMDGPUBaseInfo.h:1067
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Definition: AMDGPUBaseInfo.h:369
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Definition: AMDGPUBaseInfo.h:103
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Definition: AMDGPUBaseInfo.cpp:1448
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Definition: AMDGPUBaseInfo.h:76
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Definition: AMDGPULibCalls.cpp:187
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Definition: MCInstrDesc.h:84
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Definition: AMDGPUBaseInfo.cpp:852
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Definition: AMDGPUBaseInfo.h:709
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Definition: AMDGPUBaseInfo.cpp:1934
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Definition: AMDGPUBaseInfo.h:303
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Optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx) const
Definition: AMDGPUBaseInfo.cpp:511
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@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:157
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Definition: AMDGPUBaseInfo.cpp:1734
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Definition: AMDGPUBaseInfo.h:1305
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Definition: RISCVInsertVSETVLI.cpp:668
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Definition: AMDGPUBaseInfo.h:110
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Definition: AMDGPUBaseInfo.cpp:341
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@ Y
Definition: AMDGPUBaseInfo.h:528
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bool isShader(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1780
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Definition: AMDGPUBaseInfo.cpp:838
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Definition: AMDGPUBaseInfo.h:528
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Definition: AMDGPUBaseInfo.h:667
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@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:169
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Get size of register operand.
Definition: AMDGPUBaseInfo.cpp:2205
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const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:202
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Definition: AMDGPUBaseInfo.h:310
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Definition: AMDGPUBaseInfo.cpp:2289
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MIMGBaseOpcode G
Definition: AMDGPUBaseInfo.h:374
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:186
llvm::AMDGPU::VOPD::InstInfo
Definition: AMDGPUBaseInfo.h:699
llvm::AMDGPU::getMUBUFOpcode
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:356
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Definition: AMDGPUBaseInfo.h:80
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const LLVM_READONLY MIMGOffsetMappingInfo * getMIMGOffsetMappingInfo(unsigned Offset)
llvm::AMDGPU::getSMEMIsBuffer
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Definition: AMDGPUBaseInfo.cpp:386
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uint8_t VAddrOperands
Definition: AMDGPUBaseInfo.h:416
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unsigned getIndexOfDstInParsedOperands() const
Definition: AMDGPUBaseInfo.h:662
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uint8_t Encoding
Definition: AMDGPUBaseInfo.h:340
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bool isGFX940(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1938
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unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
Definition: AMDGPUBaseInfo.cpp:892
llvm::AMDGPU::isSGPR
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Is Reg - scalar register.
Definition: AMDGPUBaseInfo.cpp:1961
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Definition: AMDGPUBaseInfo.cpp:1946
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Definition: SIDefines.h:385
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrAny
bool isXnackOnOrAny() const
Definition: AMDGPUBaseInfo.h:126
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Definition: AMDGPUBaseInfo.h:75
llvm::AMDGPU::decodeExpcnt
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Definition: AMDGPUBaseInfo.cpp:1185
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Definition: AMDGPUBaseInfo.cpp:415
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Definition: AMDGPUBaseInfo.cpp:557
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Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
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Definition: AMDGPUBaseInfo.cpp:1845
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Definition: AMDGPUBaseInfo.h:353
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@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:158
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int getMTBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:321
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Definition: AMDGPUBaseInfo.cpp:1765
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#define FP_DENORM_FLUSH_IN_FLUSH_OUT
Definition: SIDefines.h:1030
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bool getMTBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:346
llvm::AMDGPU::Waitcnt::VsCnt
unsigned VsCnt
Definition: AMDGPUBaseInfo.h:805
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:291
llvm::AMDGPU::decodeWaitcnt
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
Definition: AMDGPUBaseInfo.cpp:1195
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bool dominates(const Waitcnt &Other) const
Definition: AMDGPUBaseInfo.h:828
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:165
llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:829
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TargetIDSetting getSramEccSetting() const
Definition: AMDGPUBaseInfo.h:169
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const LLVM_READONLY MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
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Definition: InstrProf.h:1056
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Definition: AMDGPUBaseInfo.cpp:371
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Definition: AMDGPUBaseInfo.h:324
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Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
Definition: AMDGPUBaseInfo.cpp:2366
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Definition: AMDGPUBaseInfo.cpp:787
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Definition: AMDGPUBaseInfo.h:413
Align
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Definition: ELFObjHandler.cpp:82
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Definition: SIDefines.h:176
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Definition: AMDGPUBaseInfo.h:682
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Definition: AMDGPUBaseInfo.cpp:778
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llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
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int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
Definition: AMDGPUBaseInfo.cpp:195
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Definition: AMDGPUBaseInfo.cpp:1862
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Definition: SIDefines.h:371
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LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
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Definition: AMDGPUBaseInfo.cpp:1894
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Definition: AMDGPUBaseInfo.cpp:1803
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Definition: AMDGPUBaseInfo.cpp:1634
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bool isHsaAbiVersion2(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:120
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Definition: AMDGPUBaseInfo.cpp:1853
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@ TRAP_NUM_SGPRS
Definition: AMDGPUBaseInfo.h:100
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Definition: AMDGPUBaseInfo.h:582
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Definition: AMDGPUBaseInfo.h:520
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Definition: SIDefines.h:160
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Definition: AMDGPUBaseInfo.cpp:2096
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Definition: AMDGPUBaseInfo.cpp:1157
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Definition: AMDGPUBaseInfo.h:706
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Definition: GlobalValue.h:44
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Definition: AMDGPUBaseInfo.cpp:153
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Definition: AMDGPUBaseInfo.cpp:875
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Definition: AMDGPUBaseInfo.h:1193
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Definition: AMDGPUBaseInfo.cpp:1849
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Definition: SIDefines.h:416
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@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:170
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Definition: ELFObjHandler.cpp:83
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Definition: AMDGPUBaseInfo.cpp:406
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@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:172
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Definition: AMDGPUBaseInfo.h:82
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Definition: AMDGPUBaseInfo.h:354
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Definition: AMDGPUBaseInfo.h:1317
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Information about the type of the operand.
Definition: MCInstrDesc.h:96
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Definition: AMDGPUBaseInfo.cpp:1023
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Definition: AMDGPUBaseInfo.h:833
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Definition: AMDGPUBaseInfo.cpp:1111
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Definition: AMDGPUBaseInfo.h:820
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccOnOrOff
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Definition: AMDGPUBaseInfo.h:162
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@ COMPONENT_X
Definition: AMDGPUBaseInfo.h:581
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unsigned BitsPerComp
Definition: AMDGPUBaseInfo.h:73
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#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:1033
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const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2507
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Definition: AMDGPUBaseInfo.h:383
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Definition: AMDGPUBaseInfo.h:358
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Definition: AMDGPUBaseInfo.cpp:769
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bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
Definition: AMDGPUBaseInfo.cpp:2087
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bool isValidHwregOffset(int64_t Offset)
Definition: AMDGPUBaseInfo.cpp:1429
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bool hasMandatoryLiteral() const
Definition: AMDGPUBaseInfo.h:552
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bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:1277
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Definition: AMDGPUBaseInfo.h:483
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
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Definition: AMDGPUBaseInfo.cpp:1210
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Definition: AMDGPUBaseInfo.h:685
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Definition: AMDGPUBaseInfo.h:368
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unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
Definition: AMDGPUBaseInfo.cpp:215
llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
Definition: AMDGPUBaseInfo.h:99
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TargetIDSetting getXnackSetting() const
Definition: AMDGPUBaseInfo.h:140
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:1286
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bool isGFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1874
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@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:184
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:141
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const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::AMDGPU::VOPD::ComponentProps::getMandatoryLiteralCompOperandIndex
unsigned getMandatoryLiteralCompOperandIndex() const
Definition: AMDGPUBaseInfo.h:556
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Definition: SIWholeQuadMode.cpp:264
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
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unsigned Opcode2Addr
Definition: AMDGPUBaseInfo.h:382
llvm::AMDGPU::Waitcnt::LgkmCnt
unsigned LgkmCnt
Definition: AMDGPUBaseInfo.h:804
llvm::AMDGPU::Exp::isSupportedTgtId
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1512
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unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:856
llvm::AMDGPU::VOPD::MAX_OPR_NUM
@ MAX_OPR_NUM
Definition: AMDGPUBaseInfo.h:522
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const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
llvm::AMDGPU::isGFX10Before1030
bool isGFX10Before1030(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1914
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:174
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unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:863
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@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:161
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Definition: AMDGPUBaseInfo.h:690
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Definition: AMDGPUBaseInfo.h:314
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Definition: AMDGPUBaseInfo.cpp:1617
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Definition: AMDGPUBaseInfo.cpp:940
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:187
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::AMDGPU::MIMGInfo::BaseOpcode
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Definition: AMDGPUBaseInfo.h:412
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Definition: AMDGPUBaseInfo.cpp:2255
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@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:156
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const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::AMDGPU::getMIMGMIPMappingInfo
const LLVM_READONLY MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:185
llvm::AMDGPU::isHsaAbiVersion5
bool isHsaAbiVersion5(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:138
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Definition: FileCheck.cpp:357
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Definition: AMDGPUBaseInfo.h:381
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Definition: AMDGPUBaseInfo.cpp:1910
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Definition: AMDGPUBaseInfo.cpp:1661
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Definition: AMDGPUBaseInfo.h:81
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Definition: AMDGPUBaseInfo.cpp:1394
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StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
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Definition: AMDGPUBaseInfo.h:355
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Definition: AMDGPUBaseInfo.h:816
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Definition: AMDGPUBaseInfo.cpp:401
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Definition: AMDGPUBaseInfo.cpp:1820
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
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Definition: AMDGPUBaseInfo.cpp:1799
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Definition: AMDGPUBaseInfo.cpp:964
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const LLVM_READONLY MIMGBiasMappingInfo * getMIMGBiasMappingInfo(unsigned Bias)
llvm::AMDGPU::IsaInfo::getNumVGPRBlocks
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Definition: AMDGPUBaseInfo.cpp:1013
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
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bool Coordinates
Definition: AMDGPUBaseInfo.h:321
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Definition: AMDGPUBaseInfo.cpp:2348
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bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:2051
CC
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Definition: RISCVRedundantCopyElimination.cpp:79
llvm::AMDGPU::Waitcnt::hasWaitVsCnt
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Definition: AMDGPUBaseInfo.h:824
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bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1795
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constexpr bool has_value() const
Definition: Optional.h:285
amd_kernel_code_t
AMD Kernel Code Object (amd_kernel_code_t).
Definition: AMDKernelCodeT.h:526
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackSupported
bool isXnackSupported() const
Definition: AMDGPUBaseInfo.h:121
llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:833
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bool getTgtName(unsigned Id, StringRef &Name, int &Index)
Definition: AMDGPUBaseInfo.cpp:1478
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unsigned VmCnt
Definition: AMDGPUBaseInfo.h:802
llvm::AMDGPU::getMTBUFHasVAddr
bool getMTBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:336
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::AMDGPU::VOPD::ComponentProps::getCompParsedSrcOperandsNum
unsigned getCompParsedSrcOperandsNum() const
Definition: AMDGPUBaseInfo.h:547
llvm::AMDGPU::VOPD::COMPONENTS
constexpr unsigned COMPONENTS[]
Definition: AMDGPUBaseInfo.h:529
llvm::AMDGPU::MIMGBaseOpcodeInfo::BaseOpcode
MIMGBaseOpcode BaseOpcode
Definition: AMDGPUBaseInfo.h:311
llvm::AMDGPU::GcnBufferFormatInfo
Definition: AMDGPUBaseInfo.h:71
llvm::AMDGPU::isGFX8_GFX9_GFX10
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1878
llvm::AMDGPU::GcnBufferFormatInfo::Format
unsigned Format
Definition: AMDGPUBaseInfo.h:72
llvm::AMDGPU::MTBUFFormat::getUnifiedFormat
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1592
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1886
llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:1059
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:1287
llvm::AMDGPU::isGroupSegment
bool isGroupSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:1093
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:201
llvm::AMDGPU::Waitcnt::Waitcnt
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
Definition: AMDGPUBaseInfo.h:808
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setSramEccSetting
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
Definition: AMDGPUBaseInfo.h:174
CallingConv.h
llvm::AMDGPU::encodeWaitcnt
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
Definition: AMDGPUBaseInfo.cpp:1231
llvm::AMDGPU::SendMsg::isValidMsgOp
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1682
llvm::AMDGPU::isSI
bool isSI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1858
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:188
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString
std::string toString() const
Definition: AMDGPUBaseInfo.cpp:662
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:189
Alignment.h
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::AMDGPU::isArgPassedInSGPR
bool isArgPassedInSGPR(const Argument *A)
Definition: AMDGPUBaseInfo.cpp:2313
llvm::AMDGPU::Waitcnt
Represents the counter values to wait for in an s_waitcnt instruction.
Definition: AMDGPUBaseInfo.h:801
llvm::AMDGPU::OPERAND_KIMM32
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:180
llvm::AMDGPU::SendMsg::decodeMsg
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1741
llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults
SIModeRegisterDefaults()
Definition: AMDGPUBaseInfo.h:1289
llvm::AMDGPU::getMUBUFHasVAddr
bool getMUBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:366
llvm::AMDGPU::isInlinableLiteral64
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
Definition: AMDGPUBaseInfo.cpp:2212
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:163
llvm::AMDGPU::VOPD::SRC0
@ SRC0
Definition: AMDGPUBaseInfo.h:516
uint16_t
llvm::AMDGPU::VOPD::MAX_SRC_NUM
@ MAX_SRC_NUM
Definition: AMDGPUBaseInfo.h:521
llvm::AMDGPU::getMUBUFElements
int getMUBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:361
llvm::AMDGPU::SendMsg::getMsgOpId
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1670
SIDefines.h
llvm::AMDGPU::MIMGBaseOpcodeInfo::Atomic
bool Atomic
Definition: AMDGPUBaseInfo.h:313
llvm::FPOpFusion::Strict
@ Strict
Definition: TargetOptions.h:39
llvm::AMDGPU::isFoldableLiteralV216
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2300
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrOff
bool isXnackOnOrOff() const
Definition: AMDGPUBaseInfo.h:133
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:175
llvm::AMDGPU::MIMGInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.h:411
llvm::amdhsa::kernel_descriptor_t
Definition: AMDHSAKernelDescriptor.h:170
llvm::AMDGPU::getVOP1IsSingle
bool getVOP1IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:391
llvm::AMDGPU::getVOPDOpcode
unsigned getVOPDOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:428
llvm::AMDGPU::splitMUBUFOffset
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
Definition: AMDGPUBaseInfo.cpp:2416
llvm::AMDGPU::MIMGInfo
Definition: AMDGPUBaseInfo.h:410
llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
Definition: AMDGPUBaseInfo.cpp:1587
llvm::AMDGPU::Exp::getTgtId
unsigned getTgtId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1489
llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:447
llvm::AMDGPU::getTotalNumVGPRs
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
Definition: AMDGPUBaseInfo.cpp:1954
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:177
llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:987
llvm::AMDGPU::VOPD::DST
@ DST
Definition: AMDGPUBaseInfo.h:515
llvm::AMDGPU::SendMsg::isValidMsgStream
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1708
llvm::AMDGPU::MTBUFFormat::getNfmtName
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1567
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::AMDGPU::getLgkmcntBitMask
unsigned getLgkmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:1161
llvm::AMDGPU::isLegalSMRDImmOffset
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::AMDGPU::VOPD::ComponentLayout::getIndexOfDstInMCOperands
unsigned getIndexOfDstInMCOperands() const
Definition: AMDGPUBaseInfo.h:653
llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs
uint8_t NumExtraArgs
Definition: AMDGPUBaseInfo.h:318
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