LLVM  13.0.0git
AMDGPUBaseInfo.h
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1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 3 or 4,
51 /// false otherwise.
52 bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI);
53 
55  unsigned Format;
56  unsigned BitsPerComp;
57  unsigned NumComponents;
58  unsigned NumFormat;
59  unsigned DataFormat;
60 };
61 
62 #define GET_MIMGBaseOpcode_DECL
63 #define GET_MIMGDim_DECL
64 #define GET_MIMGEncoding_DECL
65 #define GET_MIMGLZMapping_DECL
66 #define GET_MIMGMIPMapping_DECL
67 #include "AMDGPUGenSearchableTables.inc"
68 
69 namespace IsaInfo {
70 
71 enum {
72  // The closed Vulkan driver sets 96, which limits the wave count to 8 but
73  // doesn't spill SGPRs as much as when 80 is set.
76 };
77 
78 enum class TargetIDSetting {
80  Any,
81  Off,
82  On
83 };
84 
86 private:
87  const MCSubtargetInfo &STI;
88  TargetIDSetting XnackSetting;
89  TargetIDSetting SramEccSetting;
90 
91 public:
92  explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
93  ~AMDGPUTargetID() = default;
94 
95  /// \return True if the current xnack setting is not "Unsupported".
96  bool isXnackSupported() const {
97  return XnackSetting != TargetIDSetting::Unsupported;
98  }
99 
100  /// \returns True if the current xnack setting is "On" or "Any".
101  bool isXnackOnOrAny() const {
102  return XnackSetting == TargetIDSetting::On ||
103  XnackSetting == TargetIDSetting::Any;
104  }
105 
106  /// \returns True if current xnack setting is "On" or "Off",
107  /// false otherwise.
108  bool isXnackOnOrOff() const {
109  return getXnackSetting() == TargetIDSetting::On ||
111  }
112 
113  /// \returns The current xnack TargetIDSetting, possible options are
114  /// "Unsupported", "Any", "Off", and "On".
116  return XnackSetting;
117  }
118 
119  /// Sets xnack setting to \p NewXnackSetting.
120  void setXnackSetting(TargetIDSetting NewXnackSetting) {
121  XnackSetting = NewXnackSetting;
122  }
123 
124  /// \return True if the current sramecc setting is not "Unsupported".
125  bool isSramEccSupported() const {
126  return SramEccSetting != TargetIDSetting::Unsupported;
127  }
128 
129  /// \returns True if the current sramecc setting is "On" or "Any".
130  bool isSramEccOnOrAny() const {
131  return SramEccSetting == TargetIDSetting::On ||
132  SramEccSetting == TargetIDSetting::Any;
133  }
134 
135  /// \returns True if current sramecc setting is "On" or "Off",
136  /// false otherwise.
137  bool isSramEccOnOrOff() const {
140  }
141 
142  /// \returns The current sramecc TargetIDSetting, possible options are
143  /// "Unsupported", "Any", "Off", and "On".
145  return SramEccSetting;
146  }
147 
148  /// Sets sramecc setting to \p NewSramEccSetting.
149  void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
150  SramEccSetting = NewSramEccSetting;
151  }
152 
155 
156  /// \returns String representation of an object.
157  std::string toString() const;
158 };
159 
160 /// \returns Wavefront size for given subtarget \p STI.
161 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
162 
163 /// \returns Local memory size in bytes for given subtarget \p STI.
164 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
165 
166 /// \returns Number of execution units per compute unit for given subtarget \p
167 /// STI.
168 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
169 
170 /// \returns Maximum number of work groups per compute unit for given subtarget
171 /// \p STI and limited by given \p FlatWorkGroupSize.
172 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
173  unsigned FlatWorkGroupSize);
174 
175 /// \returns Minimum number of waves per execution unit for given subtarget \p
176 /// STI.
177 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
178 
179 /// \returns Maximum number of waves per execution unit for given subtarget \p
180 /// STI without any kind of limitation.
181 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
182 
183 /// \returns Number of waves per execution unit required to support the given \p
184 /// FlatWorkGroupSize.
185 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
186  unsigned FlatWorkGroupSize);
187 
188 /// \returns Minimum flat work group size for given subtarget \p STI.
189 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
190 
191 /// \returns Maximum flat work group size for given subtarget \p STI.
192 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
193 
194 /// \returns Number of waves per work group for given subtarget \p STI and
195 /// \p FlatWorkGroupSize.
196 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
197  unsigned FlatWorkGroupSize);
198 
199 /// \returns SGPR allocation granularity for given subtarget \p STI.
200 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
201 
202 /// \returns SGPR encoding granularity for given subtarget \p STI.
203 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
204 
205 /// \returns Total number of SGPRs for given subtarget \p STI.
206 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
207 
208 /// \returns Addressable number of SGPRs for given subtarget \p STI.
209 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
210 
211 /// \returns Minimum number of SGPRs that meets the given number of waves per
212 /// execution unit requirement for given subtarget \p STI.
213 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
214 
215 /// \returns Maximum number of SGPRs that meets the given number of waves per
216 /// execution unit requirement for given subtarget \p STI.
217 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
218  bool Addressable);
219 
220 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
221 /// STI when the given special registers are used.
222 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
223  bool FlatScrUsed, bool XNACKUsed);
224 
225 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
226 /// STI when the given special registers are used. XNACK is inferred from
227 /// \p STI.
228 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
229  bool FlatScrUsed);
230 
231 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
232 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
233 /// register counts.
234 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
235 
236 /// \returns VGPR allocation granularity for given subtarget \p STI.
237 ///
238 /// For subtargets which support it, \p EnableWavefrontSize32 should match
239 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
240 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
241  Optional<bool> EnableWavefrontSize32 = None);
242 
243 /// \returns VGPR encoding granularity for given subtarget \p STI.
244 ///
245 /// For subtargets which support it, \p EnableWavefrontSize32 should match
246 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
247 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
248  Optional<bool> EnableWavefrontSize32 = None);
249 
250 /// \returns Total number of VGPRs for given subtarget \p STI.
251 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
252 
253 /// \returns Addressable number of VGPRs for given subtarget \p STI.
254 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
255 
256 /// \returns Minimum number of VGPRs that meets given number of waves per
257 /// execution unit requirement for given subtarget \p STI.
258 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
259 
260 /// \returns Maximum number of VGPRs that meets given number of waves per
261 /// execution unit requirement for given subtarget \p STI.
262 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
263 
264 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
265 /// \p NumVGPRs are used.
266 ///
267 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
268 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
269 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
270  Optional<bool> EnableWavefrontSize32 = None);
271 
272 } // end namespace IsaInfo
273 
275 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
276 
278 int getSOPPWithRelaxation(uint16_t Opcode);
279 
281  MIMGBaseOpcode BaseOpcode;
282  bool Store;
283  bool Atomic;
284  bool AtomicX2;
285  bool Sampler;
286  bool Gather4;
287 
288  uint8_t NumExtraArgs;
289  bool Gradients;
290  bool G16;
293  bool HasD16;
294  bool MSAA;
295 };
296 
298 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
299 
300 struct MIMGDimInfo {
301  MIMGDim Dim;
302  uint8_t NumCoords;
303  uint8_t NumGradients;
304  bool MSAA;
305  bool DA;
306  uint8_t Encoding;
307  const char *AsmSuffix;
308 };
309 
311 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
312 
314 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
315 
318 
320  MIMGBaseOpcode L;
321  MIMGBaseOpcode LZ;
322 };
323 
325  MIMGBaseOpcode MIP;
326  MIMGBaseOpcode NONMIP;
327 };
328 
330  MIMGBaseOpcode G;
331  MIMGBaseOpcode G16;
332 };
333 
335 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
336 
338 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
339 
342 
344 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
345  unsigned VDataDwords, unsigned VAddrDwords);
346 
348 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
349 
350 struct MIMGInfo {
353  uint8_t MIMGEncoding;
354  uint8_t VDataDwords;
355  uint8_t VAddrDwords;
356 };
357 
359 const MIMGInfo *getMIMGInfo(unsigned Opc);
360 
362 int getMTBUFBaseOpcode(unsigned Opc);
363 
365 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
366 
368 int getMTBUFElements(unsigned Opc);
369 
371 bool getMTBUFHasVAddr(unsigned Opc);
372 
374 bool getMTBUFHasSrsrc(unsigned Opc);
375 
377 bool getMTBUFHasSoffset(unsigned Opc);
378 
380 int getMUBUFBaseOpcode(unsigned Opc);
381 
383 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
384 
386 int getMUBUFElements(unsigned Opc);
387 
389 bool getMUBUFHasVAddr(unsigned Opc);
390 
392 bool getMUBUFHasSrsrc(unsigned Opc);
393 
395 bool getMUBUFHasSoffset(unsigned Opc);
396 
398 bool getSMEMIsBuffer(unsigned Opc);
399 
401 bool getVOP1IsSingle(unsigned Opc);
402 
404 bool getVOP2IsSingle(unsigned Opc);
405 
407 bool getVOP3IsSingle(unsigned Opc);
408 
410 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
411  uint8_t NumComponents,
412  uint8_t NumFormat,
413  const MCSubtargetInfo &STI);
415 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
416  const MCSubtargetInfo &STI);
417 
419 int getMCOpcode(uint16_t Opcode, unsigned Gen);
420 
422  const MCSubtargetInfo *STI);
423 
425  const MCSubtargetInfo *STI);
426 
427 bool isGroupSegment(const GlobalValue *GV);
428 bool isGlobalSegment(const GlobalValue *GV);
429 bool isReadOnlySegment(const GlobalValue *GV);
430 
431 /// \returns True if constants should be emitted to .text section for given
432 /// target triple \p TT, false otherwise.
434 
435 /// \returns Integer value requested using \p F's \p Name attribute.
436 ///
437 /// \returns \p Default if attribute is not present.
438 ///
439 /// \returns \p Default and emits error if requested value cannot be converted
440 /// to integer.
441 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
442 
443 /// \returns A pair of integer values requested using \p F's \p Name attribute
444 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
445 /// is false).
446 ///
447 /// \returns \p Default if attribute is not present.
448 ///
449 /// \returns \p Default and emits error if one of the requested values cannot be
450 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
451 /// not present.
452 std::pair<int, int> getIntegerPairAttribute(const Function &F,
453  StringRef Name,
454  std::pair<int, int> Default,
455  bool OnlyFirstRequired = false);
456 
457 /// Represents the counter values to wait for in an s_waitcnt instruction.
458 ///
459 /// Large values (including the maximum possible integer) can be used to
460 /// represent "don't care" waits.
461 struct Waitcnt {
462  unsigned VmCnt = ~0u;
463  unsigned ExpCnt = ~0u;
464  unsigned LgkmCnt = ~0u;
465  unsigned VsCnt = ~0u;
466 
467  Waitcnt() {}
468  Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
470 
471  static Waitcnt allZero(bool HasVscnt) {
472  return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
473  }
474  static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
475 
476  bool hasWait() const {
477  return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
478  }
479 
480  bool dominates(const Waitcnt &Other) const {
481  return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
482  LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
483  }
484 
485  Waitcnt combined(const Waitcnt &Other) const {
486  return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
487  std::min(LgkmCnt, Other.LgkmCnt),
488  std::min(VsCnt, Other.VsCnt));
489  }
490 };
491 
492 /// \returns Vmcnt bit mask for given isa \p Version.
493 unsigned getVmcntBitMask(const IsaVersion &Version);
494 
495 /// \returns Expcnt bit mask for given isa \p Version.
496 unsigned getExpcntBitMask(const IsaVersion &Version);
497 
498 /// \returns Lgkmcnt bit mask for given isa \p Version.
499 unsigned getLgkmcntBitMask(const IsaVersion &Version);
500 
501 /// \returns Waitcnt bit mask for given isa \p Version.
502 unsigned getWaitcntBitMask(const IsaVersion &Version);
503 
504 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
505 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
506 
507 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
508 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
509 
510 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
511 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
512 
513 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
514 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
515 /// \p Lgkmcnt respectively.
516 ///
517 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
518 /// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9 only)
519 /// \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14] (gfx9+ only)
520 /// \p Expcnt = \p Waitcnt[6:4]
521 /// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10 only)
522 /// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10+ only)
523 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
524  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
525 
526 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
527 
528 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
529 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
530  unsigned Vmcnt);
531 
532 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
533 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
534  unsigned Expcnt);
535 
536 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
537 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
538  unsigned Lgkmcnt);
539 
540 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
541 /// \p Version.
542 ///
543 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
544 /// Waitcnt[3:0] = \p Vmcnt (pre-gfx9 only)
545 /// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9+ only)
546 /// Waitcnt[6:4] = \p Expcnt
547 /// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10 only)
548 /// Waitcnt[13:8] = \p Lgkmcnt (gfx10+ only)
549 /// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9+ only)
550 ///
551 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
552 /// isa \p Version.
553 unsigned encodeWaitcnt(const IsaVersion &Version,
554  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
555 
556 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
557 
558 namespace Hwreg {
559 
561 int64_t getHwregId(const StringRef Name);
562 
564 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
565 
567 bool isValidHwreg(int64_t Id);
568 
570 bool isValidHwregOffset(int64_t Offset);
571 
573 bool isValidHwregWidth(int64_t Width);
574 
576 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
577 
579 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
580 
581 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
582 
583 } // namespace Hwreg
584 
585 namespace Exp {
586 
587 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
588 
590 unsigned getTgtId(const StringRef Name);
591 
593 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
594 
595 } // namespace Exp
596 
597 namespace MTBUFFormat {
598 
600 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
601 
602 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
603 
604 int64_t getDfmt(const StringRef Name);
605 
606 StringRef getDfmtName(unsigned Id);
607 
608 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
609 
610 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
611 
612 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
613 
614 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
615 
616 int64_t getUnifiedFormat(const StringRef Name);
617 
618 StringRef getUnifiedFormatName(unsigned Id);
619 
620 bool isValidUnifiedFormat(unsigned Val);
621 
622 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
623 
624 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
625 
626 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
627 
628 } // namespace MTBUFFormat
629 
630 namespace SendMsg {
631 
633 int64_t getMsgId(const StringRef Name);
634 
636 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
637 
639 StringRef getMsgName(int64_t MsgId);
640 
642 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
643 
645 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
646 
648 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
649  bool Strict = true);
650 
652 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
653  const MCSubtargetInfo &STI, bool Strict = true);
654 
656 bool msgRequiresOp(int64_t MsgId);
657 
659 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
660 
661 void decodeMsg(unsigned Val,
662  uint16_t &MsgId,
663  uint16_t &OpId,
664  uint16_t &StreamId);
665 
667 uint64_t encodeMsg(uint64_t MsgId,
668  uint64_t OpId,
669  uint64_t StreamId);
670 
671 } // namespace SendMsg
672 
673 
674 unsigned getInitialPSInputAddr(const Function &F);
675 
677 bool isShader(CallingConv::ID CC);
678 
680 bool isGraphics(CallingConv::ID CC);
681 
683 bool isCompute(CallingConv::ID CC);
684 
687 
688 // These functions are considered entrypoints into the current module, i.e. they
689 // are allowed to be called from outside the current module. This is different
690 // from isEntryFunctionCC, which is only true for functions that are entered by
691 // the hardware. Module entry points include all entry functions but also
692 // include functions that can be called from other functions inside or outside
693 // the current module. Module entry functions are allowed to allocate LDS.
696 
697 // FIXME: Remove this when calling conventions cleaned up
699 inline bool isKernel(CallingConv::ID CC) {
700  switch (CC) {
703  return true;
704  default:
705  return false;
706  }
707 }
708 
709 bool hasXNACK(const MCSubtargetInfo &STI);
710 bool hasSRAMECC(const MCSubtargetInfo &STI);
711 bool hasMIMG_R128(const MCSubtargetInfo &STI);
712 bool hasGFX10A16(const MCSubtargetInfo &STI);
713 bool hasG16(const MCSubtargetInfo &STI);
714 bool hasPackedD16(const MCSubtargetInfo &STI);
715 
716 bool isSI(const MCSubtargetInfo &STI);
717 bool isCI(const MCSubtargetInfo &STI);
718 bool isVI(const MCSubtargetInfo &STI);
719 bool isGFX9(const MCSubtargetInfo &STI);
720 bool isGFX9Plus(const MCSubtargetInfo &STI);
721 bool isGFX10(const MCSubtargetInfo &STI);
722 bool isGFX10Plus(const MCSubtargetInfo &STI);
723 bool isGCN3Encoding(const MCSubtargetInfo &STI);
724 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
725 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
726 bool isGFX90A(const MCSubtargetInfo &STI);
727 
728 /// Is Reg - scalar register
729 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
730 
731 /// Is there any intersection between registers
732 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
733 
734 /// If \p Reg is a pseudo reg, return the correct hardware register given
735 /// \p STI otherwise return \p Reg.
736 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
737 
738 /// Convert hardware register \p Reg to a pseudo register
740 unsigned mc2PseudoReg(unsigned Reg);
741 
742 /// Can this operand also contain immediate values?
743 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
744 
745 /// Is this floating-point operand?
746 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
747 
748 /// Does this opearnd support only inlinable literals?
749 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
750 
751 /// Get the size in bits of a register from the register class \p RC.
752 unsigned getRegBitWidth(unsigned RCID);
753 
754 /// Get the size in bits of a register from the register class \p RC.
755 unsigned getRegBitWidth(const MCRegisterClass &RC);
756 
757 /// Get size of register operand
758 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
759  unsigned OpNo);
760 
762 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
763  switch (OpInfo.OperandType) {
774  return 4;
775 
781  return 8;
782 
795  return 2;
796 
797  default:
798  llvm_unreachable("unhandled operand type");
799  }
800 }
801 
803 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
804  return getOperandSize(Desc.OpInfo[OpNo]);
805 }
806 
807 /// Is this literal inlinable, and not one of the values intended for floating
808 /// point values.
810 inline bool isInlinableIntLiteral(int64_t Literal) {
811  return Literal >= -16 && Literal <= 64;
812 }
813 
814 /// Is this literal inlinable
816 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
817 
819 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
820 
822 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
823 
825 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
826 
828 bool isInlinableIntLiteralV216(int32_t Literal);
829 
831 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
832 
833 bool isArgPassedInSGPR(const Argument *Arg);
834 
837  int64_t EncodedOffset);
838 
841  int64_t EncodedOffset,
842  bool IsBuffer);
843 
844 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
845 /// offsets.
846 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
847 
848 /// \returns The encoding that will be used for \p ByteOffset in the
849 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
850 /// S_LOAD instructions have a signed offset, on other subtargets it is
851 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
853  int64_t ByteOffset, bool IsBuffer);
854 
855 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
856 /// instruction. This is only useful on CI.s
858  int64_t ByteOffset);
859 
860 /// For FLAT segment the offset must be positive;
861 /// MSB is ignored and forced to zero.
862 ///
863 /// \return The number of bits available for the offset field in flat
864 /// instructions.
865 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
866 
867 /// \returns true if this offset is small enough to fit in the SMRD
868 /// offset field. \p ByteOffset should be the offset in bytes and
869 /// not the encoded offset.
870 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
871 
872 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
873  const GCNSubtarget *Subtarget,
874  Align Alignment = Align(4));
875 
877 inline bool isLegal64BitDPPControl(unsigned DC) {
879 }
880 
881 /// \returns true if the intrinsic is divergent
882 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
883 
884 // Track defaults for fields in the MODE registser.
886  /// Floating point opcodes that support exception flag gathering quiet and
887  /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
888  /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
889  /// quieting.
890  bool IEEE : 1;
891 
892  /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
893  /// clamp NaN to zero; otherwise, pass NaN through.
894  bool DX10Clamp : 1;
895 
896  /// If this is set, neither input or output denormals are flushed for most f32
897  /// instructions.
900 
901  /// If this is set, neither input or output denormals are flushed for both f64
902  /// and f16/v2f16 instructions.
905 
907  IEEE(true),
908  DX10Clamp(true),
913 
915 
918  Mode.IEEE = !AMDGPU::isShader(CC);
919  return Mode;
920  }
921 
922  bool operator ==(const SIModeRegisterDefaults Other) const {
923  return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
924  FP32InputDenormals == Other.FP32InputDenormals &&
925  FP32OutputDenormals == Other.FP32OutputDenormals &&
926  FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
927  FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
928  }
929 
930  bool allFP32Denormals() const {
932  }
933 
934  bool allFP64FP16Denormals() const {
936  }
937 
938  /// Get the encoding value for the FP_DENORM bits of the mode register for the
939  /// FP32 denormal mode.
942  return FP_DENORM_FLUSH_NONE;
943  if (FP32InputDenormals)
944  return FP_DENORM_FLUSH_OUT;
946  return FP_DENORM_FLUSH_IN;
948  }
949 
950  /// Get the encoding value for the FP_DENORM bits of the mode register for the
951  /// FP64/FP16 denormal mode.
954  return FP_DENORM_FLUSH_NONE;
956  return FP_DENORM_FLUSH_OUT;
958  return FP_DENORM_FLUSH_IN;
960  }
961 
962  /// Returns true if a flag is compatible if it's enabled in the callee, but
963  /// disabled in the caller.
964  static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
965  return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
966  }
967 
968  // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
969  // be able to override.
971  if (DX10Clamp != CalleeMode.DX10Clamp)
972  return false;
973  if (IEEE != CalleeMode.IEEE)
974  return false;
975 
976  // Allow inlining denormals enabled into denormals flushed functions.
981  }
982 };
983 
984 } // end namespace AMDGPU
985 
986 raw_ostream &operator<<(raw_ostream &OS,
988 
989 } // end namespace llvm
990 
991 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:154
llvm::AMDGPU::Hwreg::encodeHwreg
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
Definition: AMDGPUBaseInfo.cpp:1002
FP_DENORM_FLUSH_OUT
#define FP_DENORM_FLUSH_OUT
Definition: SIDefines.h:890
llvm::AMDGPU::SIModeRegisterDefaults::fpDenormModeDPValue
uint32_t fpDenormModeDPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.
Definition: AMDGPUBaseInfo.h:952
llvm::AMDGPU::SendMsg::getMsgName
StringRef getMsgName(int64_t MsgId)
Definition: AMDGPUBaseInfo.cpp:1216
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1490
llvm::AMDGPU::isHsaAbiVersion3
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:114
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::AMDGPUTargetID
AMDGPUTargetID(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:289
llvm::AMDGPU::getMIMGDimInfoByEncoding
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
llvm::AMDGPU::mc2PseudoReg
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
Definition: AMDGPUBaseInfo.cpp:1502
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4543
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:212
llvm
Definition: AllocatorList.h:23
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unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:557
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bool getMUBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:255
llvm::AMDGPU::MIMGBaseOpcodeInfo::HasD16
bool HasD16
Definition: AMDGPUBaseInfo.h:293
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Definition: MachineSink.cpp:1566
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static Waitcnt allZeroExceptVsCnt()
Definition: AMDGPUBaseInfo.h:474
llvm::AMDGPU::MTBUFFormat::NumFormat
NumFormat
Definition: SIDefines.h:461
llvm::AMDGPU::Hwreg::getHwreg
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1008
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unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1171
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:149
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bool Store
Definition: AMDGPUBaseInfo.h:282
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const char * AsmSuffix
Definition: AMDGPUBaseInfo.h:307
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bool Gradients
Definition: AMDGPUBaseInfo.h:289
llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumSGPRs
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
Definition: AMDGPUMetadata.h:253
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bool LodOrClampOrMip
Definition: AMDGPUBaseInfo.h:292
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StringRef getDfmtName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1095
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uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
Definition: AMDGPUBaseInfo.cpp:1295
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unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:904
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Definition: Function.h:61
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int getMUBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:230
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bool FP32OutputDenormals
Definition: AMDGPUBaseInfo.h:899
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void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
Definition: AMDGPUBaseInfo.h:120
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Optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:1811
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int getMCOpcode(uint16_t Opcode, unsigned Gen)
Definition: AMDGPUBaseInfo.cpp:283
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bool isSramEccOnOrAny() const
Definition: AMDGPUBaseInfo.h:130
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Definition: AMDGPUBaseInfo.cpp:888
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bool hasSRAMECC(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1366
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bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:890
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bool hasXNACK(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1362
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@ Unsupported
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:143
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@ On
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bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1416
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Definition: AMDGPUBaseInfo.h:877
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Definition: AMDGPUBaseInfo.h:286
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Definition: AMDGPUBaseInfo.cpp:270
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Definition: AMDGPUBaseInfo.h:300
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~AMDGPUTargetID()=default
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Definition: AMDGPUBaseInfo.cpp:91
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Definition: SIDefines.h:891
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Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
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@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:145
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Definition: AMDGPUBaseInfo.cpp:1406
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Definition: AMDGPUBaseInfo.cpp:686
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Definition: AMDGPUBaseInfo.cpp:366
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Definition: AMDGPUBaseInfo.cpp:524
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Definition: AMDGPUBaseInfo.h:916
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Definition: AMDGPUBaseInfo.h:885
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If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:898
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@ Any
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Definition: GCNSubtarget.h:38
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Definition: AMDGPUBaseInfo.cpp:858
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Definition: AMDGPUBaseInfo.h:970
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Definition: AMDGPUBaseInfo.h:301
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Definition: AMDGPUBaseInfo.cpp:1420
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static bool oneWayCompatible(bool CallerMode, bool CalleeMode)
Returns true if a flag is compatible if it's enabled in the callee, but disabled in the caller.
Definition: AMDGPUBaseInfo.h:964
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Definition: AMDGPUBaseInfo.cpp:711
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@ FS
Definition: X86.h:183
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Definition: AMDGPUBaseInfo.cpp:875
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Definition: AMDGPUBaseInfo.cpp:1938
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Definition: AMDGPUBaseInfo.cpp:1253
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Definition: AMDGPUBaseInfo.h:303
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Definition: MachineSink.cpp:1567
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Definition: AMDGPUBaseInfo.cpp:205
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Definition: AMDGPUBaseInfo.h:326
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unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:512
F
#define F(x, y, z)
Definition: MD5.cpp:56
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Definition: AMDGPUBaseInfo.cpp:1122
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MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
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LLVM_READNONE bool isKernel(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:699
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Definition: AMDGPUBaseInfo.h:78
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void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
Definition: AMDGPUBaseInfo.cpp:1012
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Definition: AMDGPUBaseInfo.h:59
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
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This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:83
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Definition: AMDGPUBaseInfo.cpp:566
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LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
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bool isGFX90A(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1424
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@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:140
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bool operator==(const SIModeRegisterDefaults Other) const
Definition: AMDGPUBaseInfo.h:922
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Definition: AMDGPUBaseInfo.h:85
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Definition: AMDGPUBaseInfo.cpp:1313
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Definition: AMDGPUBaseInfo.cpp:552
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@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:150
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Get size of register operand.
Definition: AMDGPUBaseInfo.cpp:1641
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Waitcnt()
Definition: AMDGPUBaseInfo.h:467
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@ Literal
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Definition: AMDGPUBaseInfo.h:280
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MIMGBaseOpcode G
Definition: AMDGPUBaseInfo.h:330
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:163
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Definition: AMDGPUBaseInfo.cpp:235
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Definition: AMDGPUBaseInfo.cpp:260
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uint8_t Encoding
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unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
Definition: AMDGPUBaseInfo.cpp:606
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bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
Definition: AMDGPUBaseInfo.cpp:1428
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Id
Definition: SIDefines.h:351
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bool isXnackOnOrAny() const
Definition: AMDGPUBaseInfo.h:101
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unsigned NumFormat
Definition: AMDGPUBaseInfo.h:58
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unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:900
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Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
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bool hasGFX10A16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1374
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Definition: AMDGPUBaseInfo.h:319
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:141
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Definition: AMDGPUBaseInfo.cpp:200
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Definition: SIDefines.h:889
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Definition: AMDGPUBaseInfo.h:465
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raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
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void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
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Definition: AMDGPUBaseInfo.cpp:909
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Definition: AMDGPUBaseInfo.h:480
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@ OPERAND_REG_IMM_V2FP32
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Definition: AMDGPUBaseInfo.h:294
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Definition: AMDGPUBaseInfo.cpp:492
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Definition: Alignment.h:39
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Definition: CallingConv.h:24
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Definition: AMDGPUBaseInfo.cpp:1410
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Definition: AMDGPUBaseInfo.cpp:1167
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Definition: AMDGPUBaseInfo.cpp:1710
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Definition: AMDGPUBaseInfo.cpp:1553
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Definition: AMDGPUBaseInfo.cpp:867
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Definition: GlobalValue.h:44
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Definition: AMDGPUBaseInfo.cpp:120
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Definition: AMDGPUBaseInfo.cpp:589
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Definition: AMDGPUBaseInfo.h:810
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Definition: AMDGPUBaseInfo.cpp:1378
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Definition: SIDefines.h:380
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@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:151
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Definition: ELFObjHandler.cpp:84
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@ ST
Definition: ARMBaseInfo.h:73
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@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:153
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Definition: AMDGPUBaseInfo.h:320
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Definition: AMDGPUBaseInfo.h:934
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Information about the type of the operand.
Definition: MCInstrDesc.h:95
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Definition: AMDGPUBaseInfo.cpp:730
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Definition: AMDGPUBaseInfo.h:485
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@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:147
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Definition: AMDGPUBaseInfo.cpp:818
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Definition: AMDGPUBaseInfo.h:137
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Definition: AMDGPUBaseInfo.h:56
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#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:892
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Definition: AMDGPUBaseInfo.cpp:1942
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Definition: AMDGPUBaseInfo.h:324
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Definition: AMDGPUBaseInfo.cpp:483
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Does this opearnd support only inlinable literals?
Definition: AMDGPUBaseInfo.cpp:1544
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Definition: AMDGPUBaseInfo.cpp:994
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Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:894
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Definition: AMDGPUBaseInfo.cpp:924
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Definition: AMDGPUBaseInfo.cpp:1278
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Definition: AMDGPUBaseInfo.h:115
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Definition: AMDGPUBaseInfo.h:903
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@ OPERAND_REG_INLINE_AC_INT16
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Definition: SIDefines.h:161
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Definition: MCInstrDesc.h:206
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Definition: AMDGPUBaseInfo.cpp:1075
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Definition: AMDGPUBaseInfo.cpp:570
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llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:155
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Definition: AMDGPUBaseInfo.cpp:577
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Definition: AMDGPUBaseInfo.h:284
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Definition: AMDGPUBaseInfo.cpp:653
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:164
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::AMDGPU::MIMGInfo::BaseOpcode
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Definition: AMDGPUBaseInfo.h:352
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Definition: AMDGPUBaseInfo.cpp:1691
llvm::AMDGPU::OPERAND_REG_IMM_INT16
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:139
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const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::AMDGPU::getMIMGMIPMappingInfo
const LLVM_READONLY MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:162
llvm::AMDGPU::SendMsg::msgSupportsStream
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Definition: AMDGPUBaseInfo.cpp:1282
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Definition: FileCheck.cpp:357
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Definition: StringRef.h:57
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MIMGBaseOpcode LZ
Definition: AMDGPUBaseInfo.h:321
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bool hasWait() const
Definition: AMDGPUBaseInfo.h:476
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Definition: AMDGPUBaseInfo.cpp:275
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Definition: AMDGPUBaseInfo.cpp:1353
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#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
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Definition: AMDGPUBaseInfo.cpp:1332
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Definition: AMDGPUBaseInfo.cpp:674
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unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:720
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static ManagedStatic< DebugCounter > DC
Definition: DebugCounter.cpp:55
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
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bool Coordinates
Definition: AMDGPUBaseInfo.h:291
llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset
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Definition: AMDGPUBaseInfo.cpp:1784
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bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:1510
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bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1328
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AMD Kernel Code Object (amd_kernel_code_t).
Definition: AMDKernelCodeT.h:526
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackSupported
bool isXnackSupported() const
Definition: AMDGPUBaseInfo.h:96
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unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:547
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Definition: AMDGPUBaseInfo.cpp:1041
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unsigned VmCnt
Definition: AMDGPUBaseInfo.h:462
llvm::AMDGPU::getMTBUFHasVAddr
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Definition: AMDGPUBaseInfo.cpp:215
llvm::MCRegisterInfo
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Definition: MCRegisterInfo.h:135
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int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt)
Definition: AMDGPUBaseInfo.cpp:1158
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MIMGBaseOpcode BaseOpcode
Definition: AMDGPUBaseInfo.h:281
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Definition: AMDGPUBaseInfo.h:54
llvm::AMDGPU::GcnBufferFormatInfo::Format
unsigned Format
Definition: AMDGPUBaseInfo.h:55
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bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1402
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amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:766
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:904
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Definition: AMDGPUBaseInfo.cpp:800
llvm::AMDGPU::Waitcnt::Waitcnt
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Definition: AMDGPUBaseInfo.h:468
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setSramEccSetting
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
Definition: AMDGPUBaseInfo.h:149
CallingConv.h
llvm::AMDGPU::encodeWaitcnt
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
Definition: AMDGPUBaseInfo.cpp:946
llvm::AMDGPU::SendMsg::isValidMsgOp
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1233
llvm::AMDGPU::isSI
bool isSI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1386
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:165
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString
std::string toString() const
Definition: AMDGPUBaseInfo.cpp:378
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:205
Alignment.h
llvm::AMDGPU::isArgPassedInSGPR
bool isArgPassedInSGPR(const Argument *A)
Definition: AMDGPUBaseInfo.cpp:1749
llvm::AMDGPU::Waitcnt
Represents the counter values to wait for in an s_waitcnt instruction.
Definition: AMDGPUBaseInfo.h:461
llvm::AMDGPU::IsaInfo::TRAP_NUM_SGPRS
@ TRAP_NUM_SGPRS
Definition: AMDGPUBaseInfo.h:75
llvm::GraphProgram::Name
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Definition: GraphWriter.h:52
llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults
SIModeRegisterDefaults()
Definition: AMDGPUBaseInfo.h:906
llvm::AMDGPU::getMUBUFHasVAddr
bool getMUBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:245
llvm::AMDGPU::isInlinableLiteral64
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
Definition: AMDGPUBaseInfo.cpp:1648
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:144
uint16_t
llvm::AMDGPU::getMUBUFElements
int getMUBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:240
llvm::AMDGPU::SendMsg::getMsgOpId
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1221
SIDefines.h
llvm::AMDGPU::MIMGBaseOpcodeInfo::Atomic
bool Atomic
Definition: AMDGPUBaseInfo.h:283
llvm::FPOpFusion::Strict
@ Strict
Definition: TargetOptions.h:39
llvm::AMDGPU::isFoldableLiteralV216
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1736
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrOff
bool isXnackOnOrOff() const
Definition: AMDGPUBaseInfo.h:108
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:156
llvm::AMDGPU::MIMGInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.h:351
llvm::amdhsa::kernel_descriptor_t
Definition: AMDHSAKernelDescriptor.h:165
llvm::AMDGPU::getVOP1IsSingle
bool getVOP1IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:265
llvm::AMDGPU::splitMUBUFOffset
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
Definition: AMDGPUBaseInfo.cpp:1852
llvm::AMDGPU::MIMGInfo
Definition: AMDGPUBaseInfo.h:350
llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
Definition: AMDGPUBaseInfo.cpp:1137
llvm::AMDGPU::Exp::getTgtId
unsigned getTgtId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1052
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:158
llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:694
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void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId)
Definition: AMDGPUBaseInfo.cpp:1286
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bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1258
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StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1117
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::AMDGPU::getLgkmcntBitMask
unsigned getLgkmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:871
llvm::AMDGPU::isLegalSMRDImmOffset
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs
uint8_t NumExtraArgs
Definition: AMDGPUBaseInfo.h:288
llvm::AMDGPU::isInlinableLiteral32
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1665
llvm::AMDGPU::GcnBufferFormatInfo::NumComponents
unsigned NumComponents
Definition: AMDGPUBaseInfo.h:57
llvm::AMDGPU::isSISrcFPOperand
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
Definition: AMDGPUBaseInfo.cpp:1517
llvm::AMDGPU::encodeExpcnt
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
Definition: AMDGPUBaseInfo.cpp:935
llvm::AMDGPU::isRegIntersect
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
Is there any intersection between registers.
Definition: AMDGPUBaseInfo.cpp:1435
llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName
StringRef getUnifiedFormatName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1150
llvm::AMDGPU::isGCN3Encoding
bool isGCN3Encoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1412
llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST
@ ROW_NEWBCAST_FIRST
Definition: SIDefines.h:709
llvm::AMDGPU::MTBUFFormat::getNfmt
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1108
llvm::AMDGPU::getOperandSize
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
Definition: AMDGPUBaseInfo.h:762
llvm::AMDGPU::SIModeRegisterDefaults::fpDenormModeSPValue
uint32_t fpDenormModeSPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode.
Definition: AMDGPUBaseInfo.h:940
llvm::AMDGPU::getNumFlatOffsetBits
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
Definition: AMDGPUBaseInfo.cpp:1837
llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:537
llvm::AMDGPU::MIMGDimInfo::DA
bool DA
Definition: AMDGPUBaseInfo.h:305
llvm::AMDGPU::IsaInfo::getMaxWavesPerEU
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:528
llvm::AMDGPU::IsaInfo::getMinNumVGPRs
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:700
llvm::AMDGPU::Hwreg::getHwregId
int64_t getHwregId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:965
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:137
llvm::AMDGPU::hasMIMG_R128
bool hasMIMG_R128(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1370
llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST
@ ROW_NEWBCAST_LAST
Definition: SIDefines.h:710
llvm::AMDGPU::MIMGBaseOpcodeInfo::G16
bool G16
Definition: AMDGPUBaseInfo.h:290
llvm::AMDGPU::MIMGMIPMappingInfo::MIP
MIMGBaseOpcode MIP
Definition: AMDGPUBaseInfo.h:325
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:152
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromFeaturesString
void setTargetIDFromFeaturesString(StringRef FS)
Definition: AMDGPUBaseInfo.cpp:298
llvm::AMDGPU::isReadOnlySegment
bool isReadOnlySegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:808
llvm::AMDGPU::MIMGDimInfo::MSAA
bool MSAA
Definition: AMDGPUBaseInfo.h:304
llvm::AMDGPU::MIMGG16MappingInfo
Definition: AMDGPUBaseInfo.h:329
llvm::AMDGPU::isLegalSMRDEncodedSignedOffset
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:1790
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:142
llvm::AMDGPU::encodeLgkmcnt
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
Definition: AMDGPUBaseInfo.cpp:940
llvm::AMDGPU::Waitcnt::allZero
static Waitcnt allZero(bool HasVscnt)
Definition: AMDGPUBaseInfo.h:471
llvm::AMDGPU::MIMGInfo::VDataDwords
uint8_t VDataDwords
Definition: AMDGPUBaseInfo.h:354
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:166
llvm::AMDGPU::MTBUFFormat::getDfmt
int64_t getDfmt(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1087
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:221
llvm::AMDGPU::isHsaAbiVersion3Or4
bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:126
llvm::AMDGPU::Waitcnt::ExpCnt
unsigned ExpCnt
Definition: AMDGPUBaseInfo.h:463
llvm::AMDGPU::getIntegerPairAttribute
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
Definition: AMDGPUBaseInfo.cpp:833
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccSupported
bool isSramEccSupported() const
Definition: AMDGPUBaseInfo.h:125
llvm::AMDGPU::getMIMGG16MappingInfo
const LLVM_READONLY MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:211
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1789
llvm::AMDGPU::SendMsg::isValidMsgId
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1193
llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
Definition: AMDGPUBaseInfo.h:74
llvm::AMDGPU::MIMGG16MappingInfo::G16
MIMGBaseOpcode G16
Definition: AMDGPUBaseInfo.h:331
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AMDGPU::SIModeRegisterDefaults::allFP32Denormals
bool allFP32Denormals() const
Definition: AMDGPUBaseInfo.h:930
llvm::AMDGPU::IsaInfo::getVGPRAllocGranule
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:659
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:138
llvm::AMDGPU::getMaskedMIMGOp
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
Definition: AMDGPUBaseInfo.cpp:150
llvm::codeview::PublicSymFlags::Function
@ Function
llvm::AMDGPU::MIMGBaseOpcodeInfo::Sampler
bool Sampler
Definition: AMDGPUBaseInfo.h:285
llvm::AMDGPU::getMTBUFElements
int getMTBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:210
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1167
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:167
llvm::AMDGPU::MIMGDimInfo::NumCoords
uint8_t NumCoords
Definition: AMDGPUBaseInfo.h:302