LLVM 19.0.0git
AMDGPUBaseInfo.h
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1//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11
12#include "SIDefines.h"
13#include "llvm/IR/CallingConv.h"
14#include "llvm/IR/InstrTypes.h"
15#include "llvm/IR/Module.h"
17#include <array>
18#include <functional>
19#include <utility>
20
22
23namespace llvm {
24
25struct Align;
26class Argument;
27class Function;
28class GlobalValue;
29class MCInstrInfo;
30class MCRegisterClass;
31class MCRegisterInfo;
32class MCSubtargetInfo;
33class StringRef;
34class Triple;
35class raw_ostream;
36
37namespace amdhsa {
38struct kernel_descriptor_t;
39}
40
41namespace AMDGPU {
42
43struct IsaVersion;
44
45/// Generic target versions emitted by this version of LLVM.
46///
47/// These numbers are incremented every time a codegen breaking change occurs
48/// within a generic family.
49namespace GenericVersion {
50static constexpr unsigned GFX9 = 1;
51static constexpr unsigned GFX10_1 = 1;
52static constexpr unsigned GFX10_3 = 1;
53static constexpr unsigned GFX11 = 1;
54} // namespace GenericVersion
55
56enum { AMDHSA_COV4 = 4, AMDHSA_COV5 = 5, AMDHSA_COV6 = 6 };
57
58/// \returns True if \p STI is AMDHSA.
59bool isHsaAbi(const MCSubtargetInfo &STI);
60
61/// \returns Code object version from the IR module flag.
62unsigned getAMDHSACodeObjectVersion(const Module &M);
63
64/// \returns Code object version from ELF's e_ident[EI_ABIVERSION].
65unsigned getAMDHSACodeObjectVersion(unsigned ABIVersion);
66
67/// \returns The default HSA code object version. This should only be used when
68/// we lack a more accurate CodeObjectVersion value (e.g. from the IR module
69/// flag or a .amdhsa_code_object_version directive)
71
72/// \returns ABIVersion suitable for use in ELF's e_ident[EI_ABIVERSION]. \param
73/// CodeObjectVersion is a value returned by getAMDHSACodeObjectVersion().
74uint8_t getELFABIVersion(const Triple &OS, unsigned CodeObjectVersion);
75
76/// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
77unsigned getMultigridSyncArgImplicitArgPosition(unsigned COV);
78
79/// \returns The offset of the hostcall pointer argument from implicitarg_ptr
80unsigned getHostcallImplicitArgPosition(unsigned COV);
81
82unsigned getDefaultQueueImplicitArgPosition(unsigned COV);
83unsigned getCompletionActionImplicitArgPosition(unsigned COV);
84
86 unsigned Format;
87 unsigned BitsPerComp;
88 unsigned NumComponents;
89 unsigned NumFormat;
90 unsigned DataFormat;
91};
92
97};
98
99#define GET_MIMGBaseOpcode_DECL
100#define GET_MIMGDim_DECL
101#define GET_MIMGEncoding_DECL
102#define GET_MIMGLZMapping_DECL
103#define GET_MIMGMIPMapping_DECL
104#define GET_MIMGBiASMapping_DECL
105#define GET_MAIInstInfoTable_DECL
106#include "AMDGPUGenSearchableTables.inc"
107
108namespace IsaInfo {
109
110enum {
111 // The closed Vulkan driver sets 96, which limits the wave count to 8 but
112 // doesn't spill SGPRs as much as when 80 is set.
114 TRAP_NUM_SGPRS = 16
116
117enum class TargetIDSetting {
119 Any,
120 Off,
121 On
122};
123
125private:
126 const MCSubtargetInfo &STI;
127 TargetIDSetting XnackSetting;
128 TargetIDSetting SramEccSetting;
129
130public:
131 explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
132 ~AMDGPUTargetID() = default;
133
134 /// \return True if the current xnack setting is not "Unsupported".
135 bool isXnackSupported() const {
136 return XnackSetting != TargetIDSetting::Unsupported;
137 }
138
139 /// \returns True if the current xnack setting is "On" or "Any".
140 bool isXnackOnOrAny() const {
141 return XnackSetting == TargetIDSetting::On ||
142 XnackSetting == TargetIDSetting::Any;
143 }
144
145 /// \returns True if current xnack setting is "On" or "Off",
146 /// false otherwise.
147 bool isXnackOnOrOff() const {
150 }
151
152 /// \returns The current xnack TargetIDSetting, possible options are
153 /// "Unsupported", "Any", "Off", and "On".
155 return XnackSetting;
156 }
157
158 /// Sets xnack setting to \p NewXnackSetting.
159 void setXnackSetting(TargetIDSetting NewXnackSetting) {
160 XnackSetting = NewXnackSetting;
161 }
162
163 /// \return True if the current sramecc setting is not "Unsupported".
164 bool isSramEccSupported() const {
165 return SramEccSetting != TargetIDSetting::Unsupported;
166 }
167
168 /// \returns True if the current sramecc setting is "On" or "Any".
169 bool isSramEccOnOrAny() const {
170 return SramEccSetting == TargetIDSetting::On ||
171 SramEccSetting == TargetIDSetting::Any;
172 }
173
174 /// \returns True if current sramecc setting is "On" or "Off",
175 /// false otherwise.
176 bool isSramEccOnOrOff() const {
179 }
180
181 /// \returns The current sramecc TargetIDSetting, possible options are
182 /// "Unsupported", "Any", "Off", and "On".
184 return SramEccSetting;
185 }
186
187 /// Sets sramecc setting to \p NewSramEccSetting.
188 void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
189 SramEccSetting = NewSramEccSetting;
190 }
191
194
195 /// \returns String representation of an object.
196 std::string toString() const;
197};
198
199/// \returns Wavefront size for given subtarget \p STI.
200unsigned getWavefrontSize(const MCSubtargetInfo *STI);
201
202/// \returns Local memory size in bytes for given subtarget \p STI.
203unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
204
205/// \returns Maximum addressable local memory size in bytes for given subtarget
206/// \p STI.
208
209/// \returns Number of execution units per compute unit for given subtarget \p
210/// STI.
211unsigned getEUsPerCU(const MCSubtargetInfo *STI);
212
213/// \returns Maximum number of work groups per compute unit for given subtarget
214/// \p STI and limited by given \p FlatWorkGroupSize.
215unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
216 unsigned FlatWorkGroupSize);
217
218/// \returns Minimum number of waves per execution unit for given subtarget \p
219/// STI.
220unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
221
222/// \returns Maximum number of waves per execution unit for given subtarget \p
223/// STI without any kind of limitation.
224unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
225
226/// \returns Number of waves per execution unit required to support the given \p
227/// FlatWorkGroupSize.
229 unsigned FlatWorkGroupSize);
230
231/// \returns Minimum flat work group size for given subtarget \p STI.
232unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
233
234/// \returns Maximum flat work group size for given subtarget \p STI.
235unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
236
237/// \returns Number of waves per work group for given subtarget \p STI and
238/// \p FlatWorkGroupSize.
239unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
240 unsigned FlatWorkGroupSize);
241
242/// \returns SGPR allocation granularity for given subtarget \p STI.
243unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
244
245/// \returns SGPR encoding granularity for given subtarget \p STI.
246unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
247
248/// \returns Total number of SGPRs for given subtarget \p STI.
249unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
250
251/// \returns Addressable number of SGPRs for given subtarget \p STI.
252unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
253
254/// \returns Minimum number of SGPRs that meets the given number of waves per
255/// execution unit requirement for given subtarget \p STI.
256unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
257
258/// \returns Maximum number of SGPRs that meets the given number of waves per
259/// execution unit requirement for given subtarget \p STI.
260unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
261 bool Addressable);
262
263/// \returns Number of extra SGPRs implicitly required by given subtarget \p
264/// STI when the given special registers are used.
265unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
266 bool FlatScrUsed, bool XNACKUsed);
267
268/// \returns Number of extra SGPRs implicitly required by given subtarget \p
269/// STI when the given special registers are used. XNACK is inferred from
270/// \p STI.
271unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
272 bool FlatScrUsed);
273
274/// \returns Number of SGPR blocks needed for given subtarget \p STI when
275/// \p NumSGPRs are used. \p NumSGPRs should already include any special
276/// register counts.
277unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
278
279/// \returns VGPR allocation granularity for given subtarget \p STI.
280///
281/// For subtargets which support it, \p EnableWavefrontSize32 should match
282/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
283unsigned
285 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
286
287/// \returns VGPR encoding granularity for given subtarget \p STI.
288///
289/// For subtargets which support it, \p EnableWavefrontSize32 should match
290/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
292 const MCSubtargetInfo *STI,
293 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
294
295/// \returns Total number of VGPRs for given subtarget \p STI.
296unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
297
298/// \returns Addressable number of architectural VGPRs for a given subtarget \p
299/// STI.
301
302/// \returns Addressable number of VGPRs for given subtarget \p STI.
303unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
304
305/// \returns Minimum number of VGPRs that meets given number of waves per
306/// execution unit requirement for given subtarget \p STI.
307unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
308
309/// \returns Maximum number of VGPRs that meets given number of waves per
310/// execution unit requirement for given subtarget \p STI.
311unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
312
313/// \returns Number of waves reachable for a given \p NumVGPRs usage for given
314/// subtarget \p STI.
316 unsigned NumVGPRs);
317
318/// \returns Number of VGPR blocks needed for given subtarget \p STI when
319/// \p NumVGPRs are used.
320///
321/// For subtargets which support it, \p EnableWavefrontSize32 should match the
322/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
323unsigned
324getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
325 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
326
327} // end namespace IsaInfo
328
329// Represents a field in an encoded value.
330template <unsigned HighBit, unsigned LowBit, unsigned D = 0>
332 static_assert(HighBit >= LowBit, "Invalid bit range!");
333 static constexpr unsigned Offset = LowBit;
334 static constexpr unsigned Width = HighBit - LowBit + 1;
335
337 static constexpr ValueType Default = D;
338
341
342 constexpr uint64_t encode() const { return Value; }
343 static ValueType decode(uint64_t Encoded) { return Encoded; }
344};
345
346// A helper for encoding and decoding multiple fields.
347template <typename... Fields> struct EncodingFields {
348 static constexpr uint64_t encode(Fields... Values) {
349 return ((Values.encode() << Values.Offset) | ...);
350 }
351
352 static std::tuple<typename Fields::ValueType...> decode(uint64_t Encoded) {
353 return {Fields::decode((Encoded >> Fields::Offset) &
354 maxUIntN(Fields::Width))...};
355 }
356};
357
359int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
360
362inline bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx) {
363 return getNamedOperandIdx(Opcode, NamedIdx) != -1;
364}
365
368
370 MIMGBaseOpcode BaseOpcode;
371 bool Store;
372 bool Atomic;
376
379 bool G16;
382 bool HasD16;
383 bool MSAA;
384 bool BVH;
385 bool A16;
386};
387
389const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
390
392const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
393
395 MIMGDim Dim;
396 uint8_t NumCoords;
398 bool MSAA;
399 bool DA;
400 uint8_t Encoding;
401 const char *AsmSuffix;
402};
403
405const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
406
409
412
414 MIMGBaseOpcode L;
415 MIMGBaseOpcode LZ;
416};
417
419 MIMGBaseOpcode MIP;
420 MIMGBaseOpcode NONMIP;
421};
422
424 MIMGBaseOpcode Bias;
425 MIMGBaseOpcode NoBias;
426};
427
429 MIMGBaseOpcode Offset;
430 MIMGBaseOpcode NoOffset;
431};
432
434 MIMGBaseOpcode G;
435 MIMGBaseOpcode G16;
436};
437
440
442 unsigned Opcode2Addr;
443 unsigned Opcode3Addr;
444};
445
448
451
454
457
459int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
460 unsigned VDataDwords, unsigned VAddrDwords);
461
463int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
464
466unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
467 const MIMGDimInfo *Dim, bool IsA16,
468 bool IsG16Supported);
469
470struct MIMGInfo {
474 uint8_t VDataDwords;
475 uint8_t VAddrDwords;
477};
478
480const MIMGInfo *getMIMGInfo(unsigned Opc);
481
483int getMTBUFBaseOpcode(unsigned Opc);
484
486int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
487
489int getMTBUFElements(unsigned Opc);
490
492bool getMTBUFHasVAddr(unsigned Opc);
493
495bool getMTBUFHasSrsrc(unsigned Opc);
496
498bool getMTBUFHasSoffset(unsigned Opc);
499
501int getMUBUFBaseOpcode(unsigned Opc);
502
504int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
505
507int getMUBUFElements(unsigned Opc);
508
510bool getMUBUFHasVAddr(unsigned Opc);
511
513bool getMUBUFHasSrsrc(unsigned Opc);
514
516bool getMUBUFHasSoffset(unsigned Opc);
517
519bool getMUBUFIsBufferInv(unsigned Opc);
520
522bool getSMEMIsBuffer(unsigned Opc);
523
525bool getVOP1IsSingle(unsigned Opc);
526
528bool getVOP2IsSingle(unsigned Opc);
529
531bool getVOP3IsSingle(unsigned Opc);
532
534bool isVOPC64DPP(unsigned Opc);
535
537bool isVOPCAsmOnly(unsigned Opc);
538
539/// Returns true if MAI operation is a double precision GEMM.
541bool getMAIIsDGEMM(unsigned Opc);
542
544bool getMAIIsGFX940XDL(unsigned Opc);
545
546struct CanBeVOPD {
547 bool X;
548 bool Y;
549};
550
551/// \returns SIEncodingFamily used for VOPD encoding on a \p ST.
553unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST);
554
556CanBeVOPD getCanBeVOPD(unsigned Opc);
557
559const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
560 uint8_t NumComponents,
561 uint8_t NumFormat,
562 const MCSubtargetInfo &STI);
565 const MCSubtargetInfo &STI);
566
568int getMCOpcode(uint16_t Opcode, unsigned Gen);
569
571unsigned getVOPDOpcode(unsigned Opc);
572
574int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily);
575
577bool isVOPD(unsigned Opc);
578
580bool isMAC(unsigned Opc);
581
583bool isPermlane16(unsigned Opc);
584
586bool isGenericAtomic(unsigned Opc);
587
589bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc);
590
591namespace VOPD {
592
593enum Component : unsigned {
594 DST = 0,
598
603
604// LSB mask for VGPR banks per VOPD component operand.
605// 4 banks result in a mask 3, setting 2 lower bits.
606constexpr unsigned VOPD_VGPR_BANK_MASKS[] = {1, 3, 3, 1};
607
608enum ComponentIndex : unsigned { X = 0, Y = 1 };
610constexpr unsigned COMPONENTS_NUM = 2;
611
612// Properties of VOPD components.
614private:
615 unsigned SrcOperandsNum = 0;
616 unsigned MandatoryLiteralIdx = ~0u;
617 bool HasSrc2Acc = false;
618
619public:
620 ComponentProps() = default;
621 ComponentProps(const MCInstrDesc &OpDesc);
622
623 // Return the total number of src operands this component has.
624 unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }
625
626 // Return the number of src operands of this component visible to the parser.
628 return SrcOperandsNum - HasSrc2Acc;
629 }
630
631 // Return true iif this component has a mandatory literal.
632 bool hasMandatoryLiteral() const { return MandatoryLiteralIdx != ~0u; }
633
634 // If this component has a mandatory literal, return component operand
635 // index of this literal (i.e. either Component::SRC1 or Component::SRC2).
638 return MandatoryLiteralIdx;
639 }
640
641 // Return true iif this component has operand
642 // with component index CompSrcIdx and this operand may be a register.
643 bool hasRegSrcOperand(unsigned CompSrcIdx) const {
644 assert(CompSrcIdx < Component::MAX_SRC_NUM);
645 return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
646 }
647
648 // Return true iif this component has tied src2.
649 bool hasSrc2Acc() const { return HasSrc2Acc; }
650
651private:
652 bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
653 assert(CompSrcIdx < Component::MAX_SRC_NUM);
654 return MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;
655 }
656};
657
658enum ComponentKind : unsigned {
659 SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.
660 COMPONENT_X, // A VOPD instruction, X component.
661 COMPONENT_Y, // A VOPD instruction, Y component.
664
665// Interface functions of this class map VOPD component operand indices
666// to indices of operands in MachineInstr/MCInst or parsed operands array.
667//
668// Note that this class operates with 3 kinds of indices:
669// - VOPD component operand indices (Component::DST, Component::SRC0, etc.);
670// - MC operand indices (they refer operands in a MachineInstr/MCInst);
671// - parsed operand indices (they refer operands in parsed operands array).
672//
673// For SINGLE components mapping between these indices is trivial.
674// But things get more complicated for COMPONENT_X and
675// COMPONENT_Y because these components share the same
676// MachineInstr/MCInst and the same parsed operands array.
677// Below is an example of component operand to parsed operand
678// mapping for the following instruction:
679//
680// v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1
681//
682// PARSED COMPONENT PARSED
683// COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX
684// -------------------------------------------------------------------
685// "v_dual_add_f32" 0
686// v_dual_add_f32 v255 0 (DST) --> 1
687// v4 1 (SRC0) --> 2
688// v5 2 (SRC1) --> 3
689// "::" 4
690// "v_dual_mov_b32" 5
691// v_dual_mov_b32 v6 0 (DST) --> 6
692// v1 1 (SRC0) --> 7
693// -------------------------------------------------------------------
694//
696private:
697 // Regular MachineInstr/MCInst operands are ordered as follows:
698 // dst, src0 [, other src operands]
699 // VOPD MachineInstr/MCInst operands are ordered as follows:
700 // dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
701 // Each ComponentKind has operand indices defined below.
702 static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
703 static constexpr unsigned FIRST_MC_SRC_IDX[] = {1, 2, 2 /* + OpX.MCSrcNum */};
704
705 // Parsed operands of regular instructions are ordered as follows:
706 // Mnemo dst src0 [vsrc1 ...]
707 // Parsed VOPD operands are ordered as follows:
708 // OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'
709 // OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]
710 // Each ComponentKind has operand indices defined below.
711 static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
712 4 /* + OpX.ParsedSrcNum */};
713 static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
714 2, 2, 5 /* + OpX.ParsedSrcNum */};
715
716private:
717 const ComponentKind Kind;
718 const ComponentProps PrevComp;
719
720public:
721 // Create layout for COMPONENT_X or SINGLE component.
722 ComponentLayout(ComponentKind Kind) : Kind(Kind) {
724 }
725
726 // Create layout for COMPONENT_Y which depends on COMPONENT_X layout.
728 : Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps) {}
729
730public:
731 // Return the index of dst operand in MCInst operands.
732 unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }
733
734 // Return the index of the specified src operand in MCInst operands.
735 unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const {
736 assert(CompSrcIdx < Component::MAX_SRC_NUM);
737 return FIRST_MC_SRC_IDX[Kind] + getPrevCompSrcNum() + CompSrcIdx;
738 }
739
740 // Return the index of dst operand in the parsed operands array.
742 return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
743 }
744
745 // Return the index of the specified src operand in the parsed operands array.
746 unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {
747 assert(CompSrcIdx < Component::MAX_SRC_NUM);
748 return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
749 }
750
751private:
752 unsigned getPrevCompSrcNum() const {
753 return PrevComp.getCompSrcOperandsNum();
754 }
755 unsigned getPrevCompParsedSrcNum() const {
756 return PrevComp.getCompParsedSrcOperandsNum();
757 }
758};
759
760// Layout and properties of VOPD components.
762public:
763 // Create ComponentInfo for COMPONENT_X or SINGLE component.
766 : ComponentLayout(Kind), ComponentProps(OpDesc) {}
767
768 // Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.
769 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
770 : ComponentLayout(OpXProps), ComponentProps(OpDesc) {}
771
772 // Map component operand index to parsed operand index.
773 // Return 0 if the specified operand does not exist.
774 unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;
775};
776
777// Properties of VOPD instructions.
778class InstInfo {
779private:
780 const ComponentInfo CompInfo[COMPONENTS_NUM];
781
782public:
783 using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
784
785 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
786 : CompInfo{OpX, OpY} {}
787
788 InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
789 : CompInfo{OprInfoX, OprInfoY} {}
790
791 const ComponentInfo &operator[](size_t ComponentIdx) const {
792 assert(ComponentIdx < COMPONENTS_NUM);
793 return CompInfo[ComponentIdx];
794 }
795
796 // Check VOPD operands constraints.
797 // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
798 // for the specified component and MC operand. The callback must return 0
799 // if the operand is not a register or not a VGPR.
800 // If \p SkipSrc is set to true then constraints for source operands are not
801 // checked.
802 bool hasInvalidOperand(std::function<unsigned(unsigned, unsigned)> GetRegIdx,
803 bool SkipSrc = false) const {
804 return getInvalidCompOperandIndex(GetRegIdx, SkipSrc).has_value();
805 }
806
807 // Check VOPD operands constraints.
808 // Return the index of an invalid component operand, if any.
809 // If \p SkipSrc is set to true then constraints for source operands are not
810 // checked.
811 std::optional<unsigned> getInvalidCompOperandIndex(
812 std::function<unsigned(unsigned, unsigned)> GetRegIdx,
813 bool SkipSrc = false) const;
814
815private:
817 getRegIndices(unsigned ComponentIdx,
818 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
819};
820
821} // namespace VOPD
822
824std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
825
827// Get properties of 2 single VOP1/VOP2 instructions
828// used as components to create a VOPD instruction.
829VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
830
832// Get properties of VOPD X and Y components.
833VOPD::InstInfo
834getVOPDInstInfo(unsigned VOPDOpcode, const MCInstrInfo *InstrInfo);
835
837bool isTrue16Inst(unsigned Opc);
838
840unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
841
843unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
844
846 const MCSubtargetInfo *STI);
847
849 const MCSubtargetInfo *STI);
850
851bool isGroupSegment(const GlobalValue *GV);
852bool isGlobalSegment(const GlobalValue *GV);
853bool isReadOnlySegment(const GlobalValue *GV);
854
855/// \returns True if constants should be emitted to .text section for given
856/// target triple \p TT, false otherwise.
858
859/// \returns A pair of integer values requested using \p F's \p Name attribute
860/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
861/// is false).
862///
863/// \returns \p Default if attribute is not present.
864///
865/// \returns \p Default and emits error if one of the requested values cannot be
866/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
867/// not present.
868std::pair<unsigned, unsigned>
870 std::pair<unsigned, unsigned> Default,
871 bool OnlyFirstRequired = false);
872
873/// Represents the counter values to wait for in an s_waitcnt instruction.
874///
875/// Large values (including the maximum possible integer) can be used to
876/// represent "don't care" waits.
877struct Waitcnt {
878 unsigned LoadCnt = ~0u; // Corresponds to Vmcnt prior to gfx12.
879 unsigned ExpCnt = ~0u;
880 unsigned DsCnt = ~0u; // Corresponds to LGKMcnt prior to gfx12.
881 unsigned StoreCnt = ~0u; // Corresponds to VScnt on gfx10/gfx11.
882 unsigned SampleCnt = ~0u; // gfx12+ only.
883 unsigned BvhCnt = ~0u; // gfx12+ only.
884 unsigned KmCnt = ~0u; // gfx12+ only.
885
886 Waitcnt() = default;
887 // Pre-gfx12 constructor.
888 Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
889 : LoadCnt(VmCnt), ExpCnt(ExpCnt), DsCnt(LgkmCnt), StoreCnt(VsCnt),
890 SampleCnt(~0u), BvhCnt(~0u), KmCnt(~0u) {}
891
892 // gfx12+ constructor.
893 Waitcnt(unsigned LoadCnt, unsigned ExpCnt, unsigned DsCnt, unsigned StoreCnt,
894 unsigned SampleCnt, unsigned BvhCnt, unsigned KmCnt)
897
898 bool hasWait() const { return StoreCnt != ~0u || hasWaitExceptStoreCnt(); }
899
901 return LoadCnt != ~0u || ExpCnt != ~0u || DsCnt != ~0u ||
902 SampleCnt != ~0u || BvhCnt != ~0u || KmCnt != ~0u;
903 }
904
905 bool hasWaitStoreCnt() const { return StoreCnt != ~0u; }
906
908 // Does the right thing provided self and Other are either both pre-gfx12
909 // or both gfx12+.
910 return Waitcnt(
911 std::min(LoadCnt, Other.LoadCnt), std::min(ExpCnt, Other.ExpCnt),
912 std::min(DsCnt, Other.DsCnt), std::min(StoreCnt, Other.StoreCnt),
913 std::min(SampleCnt, Other.SampleCnt), std::min(BvhCnt, Other.BvhCnt),
914 std::min(KmCnt, Other.KmCnt));
915 }
916};
917
918// The following methods are only meaningful on targets that support
919// S_WAITCNT.
920
921/// \returns Vmcnt bit mask for given isa \p Version.
922unsigned getVmcntBitMask(const IsaVersion &Version);
923
924/// \returns Expcnt bit mask for given isa \p Version.
925unsigned getExpcntBitMask(const IsaVersion &Version);
926
927/// \returns Lgkmcnt bit mask for given isa \p Version.
928unsigned getLgkmcntBitMask(const IsaVersion &Version);
929
930/// \returns Waitcnt bit mask for given isa \p Version.
931unsigned getWaitcntBitMask(const IsaVersion &Version);
932
933/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
934unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
935
936/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
937unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
938
939/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
940unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
941
942/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
943/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
944/// \p Lgkmcnt respectively. Should not be used on gfx12+, the instruction
945/// which needs it is deprecated
946///
947/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
948/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
949/// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
950/// \p Vmcnt = \p Waitcnt[15:10] (gfx11)
951/// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
952/// \p Expcnt = \p Waitcnt[2:0] (gfx11)
953/// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
954/// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
955/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11)
956///
957void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
958 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
959
960Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
961
962/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
963unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
964 unsigned Vmcnt);
965
966/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
967unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
968 unsigned Expcnt);
969
970/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
971unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
972 unsigned Lgkmcnt);
973
974/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
975/// \p Version. Should not be used on gfx12+, the instruction which needs
976/// it is deprecated
977///
978/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
979/// Waitcnt[2:0] = \p Expcnt (gfx11+)
980/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
981/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
982/// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
983/// Waitcnt[9:4] = \p Lgkmcnt (gfx11)
984/// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
985/// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
986/// Waitcnt[15:10] = \p Vmcnt (gfx11)
987/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
988///
989/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
990/// isa \p Version.
991///
992unsigned encodeWaitcnt(const IsaVersion &Version,
993 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
994
995unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
996
997// The following methods are only meaningful on targets that support
998// S_WAIT_*CNT, introduced with gfx12.
999
1000/// \returns Loadcnt bit mask for given isa \p Version.
1001/// Returns 0 for versions that do not support LOADcnt
1002unsigned getLoadcntBitMask(const IsaVersion &Version);
1003
1004/// \returns Samplecnt bit mask for given isa \p Version.
1005/// Returns 0 for versions that do not support SAMPLEcnt
1006unsigned getSamplecntBitMask(const IsaVersion &Version);
1007
1008/// \returns Bvhcnt bit mask for given isa \p Version.
1009/// Returns 0 for versions that do not support BVHcnt
1010unsigned getBvhcntBitMask(const IsaVersion &Version);
1011
1012/// \returns Dscnt bit mask for given isa \p Version.
1013/// Returns 0 for versions that do not support DScnt
1014unsigned getDscntBitMask(const IsaVersion &Version);
1015
1016/// \returns Dscnt bit mask for given isa \p Version.
1017/// Returns 0 for versions that do not support KMcnt
1018unsigned getKmcntBitMask(const IsaVersion &Version);
1019
1020/// \return STOREcnt or VScnt bit mask for given isa \p Version.
1021/// returns 0 for versions that do not support STOREcnt or VScnt.
1022/// STOREcnt and VScnt are the same counter, the name used
1023/// depends on the ISA version.
1024unsigned getStorecntBitMask(const IsaVersion &Version);
1025
1026// The following are only meaningful on targets that support
1027// S_WAIT_LOADCNT_DSCNT and S_WAIT_STORECNT_DSCNT.
1028
1029/// \returns Decoded Waitcnt structure from given \p LoadcntDscnt for given
1030/// isa \p Version.
1031Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt);
1032
1033/// \returns Decoded Waitcnt structure from given \p StorecntDscnt for given
1034/// isa \p Version.
1035Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt);
1036
1037/// \returns \p Loadcnt and \p Dscnt components of \p Decoded encoded as an
1038/// immediate that can be used with S_WAIT_LOADCNT_DSCNT for given isa
1039/// \p Version.
1040unsigned encodeLoadcntDscnt(const IsaVersion &Version, const Waitcnt &Decoded);
1041
1042/// \returns \p Storecnt and \p Dscnt components of \p Decoded encoded as an
1043/// immediate that can be used with S_WAIT_STORECNT_DSCNT for given isa
1044/// \p Version.
1045unsigned encodeStorecntDscnt(const IsaVersion &Version, const Waitcnt &Decoded);
1046
1047namespace Hwreg {
1048
1051
1052struct HwregSize : EncodingField<15, 11, 32> {
1054 constexpr uint64_t encode() const { return Value - 1; }
1055 static ValueType decode(uint64_t Encoded) { return Encoded + 1; }
1056};
1057
1059
1061int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
1062
1064StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
1065
1066} // namespace Hwreg
1067
1068namespace DepCtr {
1069
1071int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
1072 const MCSubtargetInfo &STI);
1073bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
1074 const MCSubtargetInfo &STI);
1075bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
1076 bool &IsDefault, const MCSubtargetInfo &STI);
1077
1078/// \returns Decoded VaVdst from given immediate \p Encoded.
1079unsigned decodeFieldVaVdst(unsigned Encoded);
1080
1081/// \returns Decoded VmVsrc from given immediate \p Encoded.
1082unsigned decodeFieldVmVsrc(unsigned Encoded);
1083
1084/// \returns Decoded SaSdst from given immediate \p Encoded.
1085unsigned decodeFieldSaSdst(unsigned Encoded);
1086
1087/// \returns \p VmVsrc as an encoded Depctr immediate.
1088unsigned encodeFieldVmVsrc(unsigned VmVsrc);
1089
1090/// \returns \p Encoded combined with encoded \p VmVsrc.
1091unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc);
1092
1093/// \returns \p VaVdst as an encoded Depctr immediate.
1094unsigned encodeFieldVaVdst(unsigned VaVdst);
1095
1096/// \returns \p Encoded combined with encoded \p VaVdst.
1097unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst);
1098
1099/// \returns \p SaSdst as an encoded Depctr immediate.
1100unsigned encodeFieldSaSdst(unsigned SaSdst);
1101
1102/// \returns \p Encoded combined with encoded \p SaSdst.
1103unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst);
1104
1105} // namespace DepCtr
1106
1107namespace Exp {
1108
1109bool getTgtName(unsigned Id, StringRef &Name, int &Index);
1110
1112unsigned getTgtId(const StringRef Name);
1113
1115bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
1116
1117} // namespace Exp
1118
1119namespace MTBUFFormat {
1120
1122int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
1123
1124void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
1125
1126int64_t getDfmt(const StringRef Name);
1127
1128StringRef getDfmtName(unsigned Id);
1129
1130int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
1131
1132StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
1133
1134bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
1135
1136bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
1137
1138int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
1139
1140StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
1141
1142bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
1143
1144int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
1145 const MCSubtargetInfo &STI);
1146
1147bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
1148
1149unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
1150
1151} // namespace MTBUFFormat
1152
1153namespace SendMsg {
1154
1156int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
1157
1159int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
1160
1162StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
1163
1165StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1166
1168bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
1169
1171bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1172 bool Strict = true);
1173
1175bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1176 const MCSubtargetInfo &STI, bool Strict = true);
1177
1179bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
1180
1182bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1183
1184void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1185 uint16_t &StreamId, const MCSubtargetInfo &STI);
1186
1189 uint64_t OpId,
1191
1192} // namespace SendMsg
1193
1194
1195unsigned getInitialPSInputAddr(const Function &F);
1196
1197bool getHasColorExport(const Function &F);
1198
1199bool getHasDepthExport(const Function &F);
1200
1203
1206
1209
1212
1213// These functions are considered entrypoints into the current module, i.e. they
1214// are allowed to be called from outside the current module. This is different
1215// from isEntryFunctionCC, which is only true for functions that are entered by
1216// the hardware. Module entry points include all entry functions but also
1217// include functions that can be called from other functions inside or outside
1218// the current module. Module entry functions are allowed to allocate LDS.
1221
1224
1225bool isKernelCC(const Function *Func);
1226
1227// FIXME: Remove this when calling conventions cleaned up
1230 switch (CC) {
1233 return true;
1234 default:
1235 return false;
1236 }
1237}
1238
1239bool hasXNACK(const MCSubtargetInfo &STI);
1240bool hasSRAMECC(const MCSubtargetInfo &STI);
1241bool hasMIMG_R128(const MCSubtargetInfo &STI);
1242bool hasA16(const MCSubtargetInfo &STI);
1243bool hasG16(const MCSubtargetInfo &STI);
1244bool hasPackedD16(const MCSubtargetInfo &STI);
1245bool hasGDS(const MCSubtargetInfo &STI);
1246unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler = false);
1247unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI);
1248
1249bool isSI(const MCSubtargetInfo &STI);
1250bool isCI(const MCSubtargetInfo &STI);
1251bool isVI(const MCSubtargetInfo &STI);
1252bool isGFX9(const MCSubtargetInfo &STI);
1253bool isGFX9_GFX10(const MCSubtargetInfo &STI);
1254bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI);
1255bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
1256bool isGFX8Plus(const MCSubtargetInfo &STI);
1257bool isGFX9Plus(const MCSubtargetInfo &STI);
1258bool isGFX10(const MCSubtargetInfo &STI);
1259bool isGFX10_GFX11(const MCSubtargetInfo &STI);
1260bool isGFX10Plus(const MCSubtargetInfo &STI);
1261bool isNotGFX10Plus(const MCSubtargetInfo &STI);
1262bool isGFX10Before1030(const MCSubtargetInfo &STI);
1263bool isGFX11(const MCSubtargetInfo &STI);
1264bool isGFX11Plus(const MCSubtargetInfo &STI);
1265bool isGFX12(const MCSubtargetInfo &STI);
1266bool isGFX12Plus(const MCSubtargetInfo &STI);
1267bool isNotGFX12Plus(const MCSubtargetInfo &STI);
1268bool isNotGFX11Plus(const MCSubtargetInfo &STI);
1269bool isGCN3Encoding(const MCSubtargetInfo &STI);
1270bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
1271bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
1272bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
1273bool isGFX10_3_GFX11(const MCSubtargetInfo &STI);
1274bool isGFX90A(const MCSubtargetInfo &STI);
1275bool isGFX940(const MCSubtargetInfo &STI);
1277bool hasMAIInsts(const MCSubtargetInfo &STI);
1278bool hasVOPD(const MCSubtargetInfo &STI);
1279bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI);
1280int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
1281unsigned hasKernargPreload(const MCSubtargetInfo &STI);
1282
1283/// Is Reg - scalar register
1284bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
1285
1286/// \returns if \p Reg occupies the high 16-bits of a 32-bit register.
1287/// The bit indicating isHi is the LSB of the encoding.
1288bool isHi(unsigned Reg, const MCRegisterInfo &MRI);
1289
1290/// If \p Reg is a pseudo reg, return the correct hardware register given
1291/// \p STI otherwise return \p Reg.
1292unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
1293
1294/// Convert hardware register \p Reg to a pseudo register
1296unsigned mc2PseudoReg(unsigned Reg);
1297
1299bool isInlineValue(unsigned Reg);
1300
1301/// Is this an AMDGPU specific source operand? These include registers,
1302/// inline constants, literals and mandatory literals (KImm).
1303bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1304
1305/// Is this a KImm operand?
1306bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1307
1308/// Is this floating-point operand?
1309bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1310
1311/// Does this operand support only inlinable literals?
1312bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1313
1314/// Get the size in bits of a register from the register class \p RC.
1315unsigned getRegBitWidth(unsigned RCID);
1316
1317/// Get the size in bits of a register from the register class \p RC.
1318unsigned getRegBitWidth(const MCRegisterClass &RC);
1319
1320/// Get size of register operand
1321unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
1322 unsigned OpNo);
1323
1325inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
1326 switch (OpInfo.OperandType) {
1339 case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
1341 return 4;
1342
1348 return 8;
1349
1370 return 2;
1371
1372 default:
1373 llvm_unreachable("unhandled operand type");
1374 }
1375}
1376
1378inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
1379 return getOperandSize(Desc.operands()[OpNo]);
1380}
1381
1382/// Is this literal inlinable, and not one of the values intended for floating
1383/// point values.
1385inline bool isInlinableIntLiteral(int64_t Literal) {
1386 return Literal >= -16 && Literal <= 64;
1387}
1388
1389/// Is this literal inlinable
1391bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
1392
1394bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
1395
1397bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi);
1398
1400bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
1401
1403std::optional<unsigned> getInlineEncodingV2I16(uint32_t Literal);
1404
1406std::optional<unsigned> getInlineEncodingV2BF16(uint32_t Literal);
1407
1409std::optional<unsigned> getInlineEncodingV2F16(uint32_t Literal);
1410
1412bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType);
1413
1416
1419
1422
1424bool isValid32BitLiteral(uint64_t Val, bool IsFP64);
1425
1426bool isArgPassedInSGPR(const Argument *Arg);
1427
1428bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo);
1429
1432 int64_t EncodedOffset);
1433
1436 int64_t EncodedOffset,
1437 bool IsBuffer);
1438
1439/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
1440/// offsets.
1442
1443/// \returns The encoding that will be used for \p ByteOffset in the
1444/// SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10
1445/// S_LOAD instructions have a signed offset, on other subtargets it is
1446/// unsigned. S_BUFFER has an unsigned offset for all subtargets.
1447std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
1448 int64_t ByteOffset, bool IsBuffer);
1449
1450/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
1451/// instruction. This is only useful on CI.s
1452std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
1453 int64_t ByteOffset);
1454
1455/// For pre-GFX12 FLAT instructions the offset must be positive;
1456/// MSB is ignored and forced to zero.
1457///
1458/// \return The number of bits available for the signed offset field in flat
1459/// instructions. Note that some forms of the instruction disallow negative
1460/// offsets.
1461unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);
1462
1463/// \returns true if this offset is small enough to fit in the SMRD
1464/// offset field. \p ByteOffset should be the offset in bytes and
1465/// not the encoded offset.
1466bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
1467
1469inline bool isLegalDPALU_DPPControl(unsigned DC) {
1470 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
1471}
1472
1473/// \returns true if an instruction may have a 64-bit VGPR operand.
1474bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc);
1475
1476/// \returns true if an instruction is a DP ALU DPP.
1477bool isDPALU_DPP(const MCInstrDesc &OpDesc);
1478
1479/// \returns true if the intrinsic is divergent
1480bool isIntrinsicSourceOfDivergence(unsigned IntrID);
1481
1482/// \returns true if the intrinsic is uniform
1483bool isIntrinsicAlwaysUniform(unsigned IntrID);
1484
1485} // end namespace AMDGPU
1486
1487raw_ostream &operator<<(raw_ostream &OS,
1489
1490} // end namespace llvm
1491
1492#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_READNONE
Definition: Compiler.h:220
#define LLVM_READONLY
Definition: Compiler.h:227
uint64_t Align
std::string Name
#define F(x, y, z)
Definition: MD5.cpp:55
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Module.h This file contains the declarations for the Module class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
void setTargetIDFromFeaturesString(StringRef FS)
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
TargetIDSetting getXnackSetting() const
void setTargetIDFromTargetIDStream(StringRef TargetID)
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
TargetIDSetting getSramEccSetting() const
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
ComponentInfo(const MCInstrDesc &OpDesc, ComponentKind Kind=ComponentKind::SINGLE)
ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const
unsigned getIndexOfDstInParsedOperands() const
ComponentLayout(const ComponentProps &OpXProps)
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
bool hasRegSrcOperand(unsigned CompSrcIdx) const
unsigned getMandatoryLiteralCompOperandIndex() const
unsigned getCompParsedSrcOperandsNum() const
InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
bool hasInvalidOperand(std::function< unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc=false) const
const ComponentInfo & operator[](size_t ComponentIdx) const
InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
std::optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc=false) const
std::array< unsigned, Component::MAX_OPR_NUM > RegIndices
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1455
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst)
unsigned decodeFieldSaSdst(unsigned Encoded)
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst)
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
unsigned decodeFieldVaVdst(unsigned Encoded)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
unsigned decodeFieldVmVsrc(unsigned Encoded)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
static constexpr unsigned GFX10_1
static constexpr unsigned GFX10_3
static constexpr unsigned GFX11
static constexpr unsigned GFX9
int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI)
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
StringRef getDfmtName(unsigned Id)
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
int64_t getDfmt(const StringRef Name)
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned VOPD_VGPR_BANK_MASKS[]
constexpr unsigned COMPONENTS_NUM
constexpr unsigned COMPONENTS[]
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
bool isGFX10_GFX11(const MCSubtargetInfo &STI)
bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
LLVM_READONLY const MIMGOffsetMappingInfo * getMIMGOffsetMappingInfo(unsigned Offset)
bool isVOPCAsmOnly(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
LLVM_READNONE bool isLegalDPALU_DPPControl(unsigned DC)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isInlinableLiteralV2I16(uint32_t Literal)
int getMTBUFElements(unsigned Opc)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
bool isInlinableLiteralV2BF16(uint32_t Literal)
unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
bool isGFX12Plus(const MCSubtargetInfo &STI)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler)
CanBeVOPD getCanBeVOPD(unsigned Opc)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getStorecntBitMask(const IsaVersion &Version)
bool isGFX940(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
LLVM_READNONE bool isKernel(CallingConv::ID CC)
bool isInlinableLiteralV2F16(uint32_t Literal)
bool isHsaAbi(const MCSubtargetInfo &STI)
bool isGFX11(const MCSubtargetInfo &STI)
bool getSMEMIsBuffer(unsigned Opc)
bool isGFX10_3_GFX11(const MCSubtargetInfo &STI)
bool isGroupSegment(const GlobalValue *GV)
LLVM_READONLY const MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
bool getMTBUFHasSoffset(unsigned Opc)
bool hasXNACK(const MCSubtargetInfo &STI)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
unsigned getVOPDOpcode(unsigned Opc)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool isCompute(CallingConv::ID cc)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
unsigned getDefaultAMDHSACodeObjectVersion()
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool getVOP1IsSingle(unsigned Opc)
unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isChainCC(CallingConv::ID CC)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getSamplecntBitMask(const IsaVersion &Version)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily)
bool isTrue16Inst(unsigned Opc)
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned getKmcntBitMask(const IsaVersion &Version)
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isKernelCC(const Function *Func)
bool isGenericAtomic(unsigned Opc)
Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
LLVM_READONLY const MIMGBiasMappingInfo * getMIMGBiasMappingInfo(unsigned Bias)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
bool isHi(unsigned Reg, const MCRegisterInfo &MRI)
unsigned getBvhcntBitMask(const IsaVersion &Version)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV2F16(uint32_t Literal)
bool isInlineValue(unsigned Reg)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isShader(CallingConv::ID cc)
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
bool isGlobalSegment(const GlobalValue *GV)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:234
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:201
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:211
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:227
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:223
@ OPERAND_REG_INLINE_C_BF16
Definition: SIDefines.h:220
@ OPERAND_REG_INLINE_C_V2BF16
Definition: SIDefines.h:225
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:212
@ OPERAND_REG_IMM_BF16
Definition: SIDefines.h:205
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:246
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:200
@ OPERAND_REG_IMM_V2BF16
Definition: SIDefines.h:210
@ OPERAND_REG_IMM_BF16_DEFERRED
Definition: SIDefines.h:207
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:206
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:219
@ OPERAND_REG_INLINE_AC_BF16
Definition: SIDefines.h:240
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:217
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:238
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:204
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:226
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:244
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:241
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:239
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:242
@ OPERAND_REG_INLINE_AC_V2BF16
Definition: SIDefines.h:245
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:213
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:203
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:222
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:218
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:224
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:214
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:243
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:221
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:202
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:228
@ OPERAND_INLINE_SPLIT_BARRIER_INT32
Definition: SIDefines.h:231
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:209
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:208
LLVM_READONLY const MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
bool hasGDS(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI)
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt)
std::optional< unsigned > getInlineEncodingV2I16(uint32_t Literal)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
static unsigned encodeStorecntDscnt(const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfo(unsigned DimEnum)
bool getMUBUFIsBufferInv(unsigned Opc)
std::optional< unsigned > getInlineEncodingV2BF16(uint32_t Literal)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
bool isMAC(unsigned Opc)
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
bool getVOP2IsSingle(unsigned Opc)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isModuleEntryFunctionCC(CallingConv::ID CC)
bool isNotGFX12Plus(const MCSubtargetInfo &STI)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
unsigned getLoadcntBitMask(const IsaVersion &Version)
bool hasVOPD(const MCSubtargetInfo &STI)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
bool isGraphics(CallingConv::ID cc)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned getDscntBitMask(const IsaVersion &Version)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:200
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:144
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
@ Other
Any other memory.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:293
@ Default
The result values are uniform if and only if all operands are uniform.
uint64_t maxUIntN(uint64_t N)
Gets the maximum value for a N-bit unsigned integer.
Definition: MathExtras.h:201
AMD Kernel Code Object (amd_kernel_code_t).
static constexpr unsigned Width
constexpr EncodingField(ValueType Value)
static constexpr unsigned Offset
static constexpr ValueType Default
static ValueType decode(uint64_t Encoded)
constexpr uint64_t encode() const
static constexpr uint64_t encode(Fields... Values)
static std::tuple< typename Fields::ValueType... > decode(uint64_t Encoded)
constexpr uint64_t encode() const
static ValueType decode(uint64_t Encoded)
Represents the counter values to wait for in an s_waitcnt instruction.
Waitcnt(unsigned LoadCnt, unsigned ExpCnt, unsigned DsCnt, unsigned StoreCnt, unsigned SampleCnt, unsigned BvhCnt, unsigned KmCnt)
bool hasWaitExceptStoreCnt() const
bool hasWaitStoreCnt() const
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
Waitcnt combined(const Waitcnt &Other) const
Description of the encoding of one expression Op.