LLVM 17.0.0git
AMDGPUBaseInfo.h
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1//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11
12#include "SIDefines.h"
13#include "llvm/IR/CallingConv.h"
14#include "llvm/IR/InstrTypes.h"
15#include "llvm/IR/Module.h"
17#include <array>
18#include <functional>
19#include <utility>
20
22
23namespace llvm {
24
25struct Align;
26class Argument;
27class Function;
28class GlobalValue;
29class MCInstrInfo;
30class MCRegisterClass;
31class MCRegisterInfo;
32class MCSubtargetInfo;
33class StringRef;
34class Triple;
35class raw_ostream;
36
37namespace amdhsa {
38struct kernel_descriptor_t;
39}
40
41namespace AMDGPU {
42
43struct IsaVersion;
44
45enum {
49 AMDHSA_COV5 = 5
50};
51
52/// \returns HSA OS ABI Version identification.
53std::optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
54/// \returns True if HSA OS ABI Version identification is 2,
55/// false otherwise.
56bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
57/// \returns True if HSA OS ABI Version identification is 3,
58/// false otherwise.
59bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
60/// \returns True if HSA OS ABI Version identification is 4,
61/// false otherwise.
62bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
63/// \returns True if HSA OS ABI Version identification is 5,
64/// false otherwise.
65bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
66/// \returns True if HSA OS ABI Version identification is 3 and above,
67/// false otherwise.
69
70/// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
71unsigned getMultigridSyncArgImplicitArgPosition(unsigned COV);
72
73/// \returns The offset of the hostcall pointer argument from implicitarg_ptr
74unsigned getHostcallImplicitArgPosition(unsigned COV);
75
76unsigned getDefaultQueueImplicitArgPosition(unsigned COV);
77unsigned getCompletionActionImplicitArgPosition(unsigned COV);
78
79/// \returns Code object version.
81
82/// \returns Code object version.
83unsigned getCodeObjectVersion(const Module &M);
84
86 unsigned Format;
87 unsigned BitsPerComp;
88 unsigned NumComponents;
89 unsigned NumFormat;
90 unsigned DataFormat;
91};
92
97};
98
99#define GET_MIMGBaseOpcode_DECL
100#define GET_MIMGDim_DECL
101#define GET_MIMGEncoding_DECL
102#define GET_MIMGLZMapping_DECL
103#define GET_MIMGMIPMapping_DECL
104#define GET_MIMGBiASMapping_DECL
105#define GET_MAIInstInfoTable_DECL
106#include "AMDGPUGenSearchableTables.inc"
107
108namespace IsaInfo {
109
110enum {
111 // The closed Vulkan driver sets 96, which limits the wave count to 8 but
112 // doesn't spill SGPRs as much as when 80 is set.
114 TRAP_NUM_SGPRS = 16
116
117enum class TargetIDSetting {
119 Any,
120 Off,
121 On
122};
123
125private:
126 const MCSubtargetInfo &STI;
127 TargetIDSetting XnackSetting;
128 TargetIDSetting SramEccSetting;
129 unsigned CodeObjectVersion;
130
131public:
132 explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
133 ~AMDGPUTargetID() = default;
134
135 /// \return True if the current xnack setting is not "Unsupported".
136 bool isXnackSupported() const {
137 return XnackSetting != TargetIDSetting::Unsupported;
138 }
139
140 /// \returns True if the current xnack setting is "On" or "Any".
141 bool isXnackOnOrAny() const {
142 return XnackSetting == TargetIDSetting::On ||
143 XnackSetting == TargetIDSetting::Any;
144 }
145
146 /// \returns True if current xnack setting is "On" or "Off",
147 /// false otherwise.
148 bool isXnackOnOrOff() const {
151 }
152
153 /// \returns The current xnack TargetIDSetting, possible options are
154 /// "Unsupported", "Any", "Off", and "On".
156 return XnackSetting;
157 }
158
159 void setCodeObjectVersion(unsigned COV) {
160 CodeObjectVersion = COV;
161 }
162
163 /// Sets xnack setting to \p NewXnackSetting.
164 void setXnackSetting(TargetIDSetting NewXnackSetting) {
165 XnackSetting = NewXnackSetting;
166 }
167
168 /// \return True if the current sramecc setting is not "Unsupported".
169 bool isSramEccSupported() const {
170 return SramEccSetting != TargetIDSetting::Unsupported;
171 }
172
173 /// \returns True if the current sramecc setting is "On" or "Any".
174 bool isSramEccOnOrAny() const {
175 return SramEccSetting == TargetIDSetting::On ||
176 SramEccSetting == TargetIDSetting::Any;
177 }
178
179 /// \returns True if current sramecc setting is "On" or "Off",
180 /// false otherwise.
181 bool isSramEccOnOrOff() const {
184 }
185
186 /// \returns The current sramecc TargetIDSetting, possible options are
187 /// "Unsupported", "Any", "Off", and "On".
189 return SramEccSetting;
190 }
191
192 /// Sets sramecc setting to \p NewSramEccSetting.
193 void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
194 SramEccSetting = NewSramEccSetting;
195 }
196
199
200 /// \returns String representation of an object.
201 std::string toString() const;
202};
203
204/// \returns Wavefront size for given subtarget \p STI.
205unsigned getWavefrontSize(const MCSubtargetInfo *STI);
206
207/// \returns Local memory size in bytes for given subtarget \p STI.
208unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
209
210/// \returns Maximum addressable local memory size in bytes for given subtarget
211/// \p STI.
213
214/// \returns Number of execution units per compute unit for given subtarget \p
215/// STI.
216unsigned getEUsPerCU(const MCSubtargetInfo *STI);
217
218/// \returns Maximum number of work groups per compute unit for given subtarget
219/// \p STI and limited by given \p FlatWorkGroupSize.
220unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
221 unsigned FlatWorkGroupSize);
222
223/// \returns Minimum number of waves per execution unit for given subtarget \p
224/// STI.
225unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
226
227/// \returns Maximum number of waves per execution unit for given subtarget \p
228/// STI without any kind of limitation.
229unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
230
231/// \returns Number of waves per execution unit required to support the given \p
232/// FlatWorkGroupSize.
234 unsigned FlatWorkGroupSize);
235
236/// \returns Minimum flat work group size for given subtarget \p STI.
237unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
238
239/// \returns Maximum flat work group size for given subtarget \p STI.
240unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
241
242/// \returns Number of waves per work group for given subtarget \p STI and
243/// \p FlatWorkGroupSize.
244unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
245 unsigned FlatWorkGroupSize);
246
247/// \returns SGPR allocation granularity for given subtarget \p STI.
248unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
249
250/// \returns SGPR encoding granularity for given subtarget \p STI.
251unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
252
253/// \returns Total number of SGPRs for given subtarget \p STI.
254unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
255
256/// \returns Addressable number of SGPRs for given subtarget \p STI.
257unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
258
259/// \returns Minimum number of SGPRs that meets the given number of waves per
260/// execution unit requirement for given subtarget \p STI.
261unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
262
263/// \returns Maximum number of SGPRs that meets the given number of waves per
264/// execution unit requirement for given subtarget \p STI.
265unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
266 bool Addressable);
267
268/// \returns Number of extra SGPRs implicitly required by given subtarget \p
269/// STI when the given special registers are used.
270unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
271 bool FlatScrUsed, bool XNACKUsed);
272
273/// \returns Number of extra SGPRs implicitly required by given subtarget \p
274/// STI when the given special registers are used. XNACK is inferred from
275/// \p STI.
276unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
277 bool FlatScrUsed);
278
279/// \returns Number of SGPR blocks needed for given subtarget \p STI when
280/// \p NumSGPRs are used. \p NumSGPRs should already include any special
281/// register counts.
282unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
283
284/// \returns VGPR allocation granularity for given subtarget \p STI.
285///
286/// For subtargets which support it, \p EnableWavefrontSize32 should match
287/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
288unsigned
290 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
291
292/// \returns VGPR encoding granularity for given subtarget \p STI.
293///
294/// For subtargets which support it, \p EnableWavefrontSize32 should match
295/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
297 const MCSubtargetInfo *STI,
298 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
299
300/// \returns Total number of VGPRs for given subtarget \p STI.
301unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
302
303/// \returns Addressable number of VGPRs for given subtarget \p STI.
304unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
305
306/// \returns Minimum number of VGPRs that meets given number of waves per
307/// execution unit requirement for given subtarget \p STI.
308unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
309
310/// \returns Maximum number of VGPRs that meets given number of waves per
311/// execution unit requirement for given subtarget \p STI.
312unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
313
314/// \returns Number of waves reachable for a given \p NumVGPRs usage for given
315/// subtarget \p STI.
317 unsigned NumVGPRs);
318
319/// \returns Number of VGPR blocks needed for given subtarget \p STI when
320/// \p NumVGPRs are used.
321///
322/// For subtargets which support it, \p EnableWavefrontSize32 should match the
323/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
324unsigned
325getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
326 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
327
328} // end namespace IsaInfo
329
331int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
332
334inline bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx) {
335 return getNamedOperandIdx(Opcode, NamedIdx) != -1;
336}
337
340
342 MIMGBaseOpcode BaseOpcode;
343 bool Store;
344 bool Atomic;
348
351 bool G16;
354 bool HasD16;
355 bool MSAA;
356 bool BVH;
357};
358
360const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
361
363const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
364
366 MIMGDim Dim;
367 uint8_t NumCoords;
369 bool MSAA;
370 bool DA;
371 uint8_t Encoding;
372 const char *AsmSuffix;
373};
374
376const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
377
380
383
385 MIMGBaseOpcode L;
386 MIMGBaseOpcode LZ;
387};
388
390 MIMGBaseOpcode MIP;
391 MIMGBaseOpcode NONMIP;
392};
393
395 MIMGBaseOpcode Bias;
396 MIMGBaseOpcode NoBias;
397};
398
400 MIMGBaseOpcode Offset;
401 MIMGBaseOpcode NoOffset;
402};
403
405 MIMGBaseOpcode G;
406 MIMGBaseOpcode G16;
407};
408
411
413 unsigned Opcode2Addr;
414 unsigned Opcode3Addr;
415};
416
419
422
425
428
430int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
431 unsigned VDataDwords, unsigned VAddrDwords);
432
434int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
435
437unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
438 const MIMGDimInfo *Dim, bool IsA16,
439 bool IsG16Supported);
440
441struct MIMGInfo {
445 uint8_t VDataDwords;
446 uint8_t VAddrDwords;
448};
449
451const MIMGInfo *getMIMGInfo(unsigned Opc);
452
454int getMTBUFBaseOpcode(unsigned Opc);
455
457int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
458
460int getMTBUFElements(unsigned Opc);
461
463bool getMTBUFHasVAddr(unsigned Opc);
464
466bool getMTBUFHasSrsrc(unsigned Opc);
467
469bool getMTBUFHasSoffset(unsigned Opc);
470
472int getMUBUFBaseOpcode(unsigned Opc);
473
475int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
476
478int getMUBUFElements(unsigned Opc);
479
481bool getMUBUFHasVAddr(unsigned Opc);
482
484bool getMUBUFHasSrsrc(unsigned Opc);
485
487bool getMUBUFHasSoffset(unsigned Opc);
488
490bool getMUBUFIsBufferInv(unsigned Opc);
491
493bool getSMEMIsBuffer(unsigned Opc);
494
496bool getVOP1IsSingle(unsigned Opc);
497
499bool getVOP2IsSingle(unsigned Opc);
500
502bool getVOP3IsSingle(unsigned Opc);
503
505bool isVOPC64DPP(unsigned Opc);
506
507/// Returns true if MAI operation is a double precision GEMM.
509bool getMAIIsDGEMM(unsigned Opc);
510
512bool getMAIIsGFX940XDL(unsigned Opc);
513
514struct CanBeVOPD {
515 bool X;
516 bool Y;
517};
518
520CanBeVOPD getCanBeVOPD(unsigned Opc);
521
523const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
524 uint8_t NumComponents,
525 uint8_t NumFormat,
526 const MCSubtargetInfo &STI);
529 const MCSubtargetInfo &STI);
530
532int getMCOpcode(uint16_t Opcode, unsigned Gen);
533
535unsigned getVOPDOpcode(unsigned Opc);
536
538int getVOPDFull(unsigned OpX, unsigned OpY);
539
541bool isVOPD(unsigned Opc);
542
544bool isMAC(unsigned Opc);
545
547bool isPermlane16(unsigned Opc);
548
549namespace VOPD {
550
551enum Component : unsigned {
552 DST = 0,
556
561
562// Number of VGPR banks per VOPD component operand.
563constexpr unsigned BANKS_NUM[] = {2, 4, 4, 2};
564
565enum ComponentIndex : unsigned { X = 0, Y = 1 };
567constexpr unsigned COMPONENTS_NUM = 2;
568
569// Properties of VOPD components.
571private:
572 unsigned SrcOperandsNum = 0;
573 std::optional<unsigned> MandatoryLiteralIdx;
574 bool HasSrc2Acc = false;
575
576public:
577 ComponentProps() = default;
578 ComponentProps(const MCInstrDesc &OpDesc);
579
580 // Return the total number of src operands this component has.
581 unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }
582
583 // Return the number of src operands of this component visible to the parser.
585 return SrcOperandsNum - HasSrc2Acc;
586 }
587
588 // Return true iif this component has a mandatory literal.
589 bool hasMandatoryLiteral() const { return MandatoryLiteralIdx.has_value(); }
590
591 // If this component has a mandatory literal, return component operand
592 // index of this literal (i.e. either Component::SRC1 or Component::SRC2).
595 return *MandatoryLiteralIdx;
596 }
597
598 // Return true iif this component has operand
599 // with component index CompSrcIdx and this operand may be a register.
600 bool hasRegSrcOperand(unsigned CompSrcIdx) const {
601 assert(CompSrcIdx < Component::MAX_SRC_NUM);
602 return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
603 }
604
605 // Return true iif this component has tied src2.
606 bool hasSrc2Acc() const { return HasSrc2Acc; }
607
608private:
609 bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
610 assert(CompSrcIdx < Component::MAX_SRC_NUM);
611 return hasMandatoryLiteral() &&
612 *MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;
613 }
614};
615
616enum ComponentKind : unsigned {
617 SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.
618 COMPONENT_X, // A VOPD instruction, X component.
619 COMPONENT_Y, // A VOPD instruction, Y component.
622
623// Interface functions of this class map VOPD component operand indices
624// to indices of operands in MachineInstr/MCInst or parsed operands array.
625//
626// Note that this class operates with 3 kinds of indices:
627// - VOPD component operand indices (Component::DST, Component::SRC0, etc.);
628// - MC operand indices (they refer operands in a MachineInstr/MCInst);
629// - parsed operand indices (they refer operands in parsed operands array).
630//
631// For SINGLE components mapping between these indices is trivial.
632// But things get more complicated for COMPONENT_X and
633// COMPONENT_Y because these components share the same
634// MachineInstr/MCInst and the same parsed operands array.
635// Below is an example of component operand to parsed operand
636// mapping for the following instruction:
637//
638// v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1
639//
640// PARSED COMPONENT PARSED
641// COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX
642// -------------------------------------------------------------------
643// "v_dual_add_f32" 0
644// v_dual_add_f32 v255 0 (DST) --> 1
645// v4 1 (SRC0) --> 2
646// v5 2 (SRC1) --> 3
647// "::" 4
648// "v_dual_mov_b32" 5
649// v_dual_mov_b32 v6 0 (DST) --> 6
650// v1 1 (SRC0) --> 7
651// -------------------------------------------------------------------
652//
654private:
655 // Regular MachineInstr/MCInst operands are ordered as follows:
656 // dst, src0 [, other src operands]
657 // VOPD MachineInstr/MCInst operands are ordered as follows:
658 // dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
659 // Each ComponentKind has operand indices defined below.
660 static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
661 static constexpr unsigned FIRST_MC_SRC_IDX[] = {1, 2, 2 /* + OpX.MCSrcNum */};
662
663 // Parsed operands of regular instructions are ordered as follows:
664 // Mnemo dst src0 [vsrc1 ...]
665 // Parsed VOPD operands are ordered as follows:
666 // OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'
667 // OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]
668 // Each ComponentKind has operand indices defined below.
669 static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
670 4 /* + OpX.ParsedSrcNum */};
671 static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
672 2, 2, 5 /* + OpX.ParsedSrcNum */};
673
674private:
675 const ComponentKind Kind;
676 const ComponentProps PrevComp;
677
678public:
679 // Create layout for COMPONENT_X or SINGLE component.
680 ComponentLayout(ComponentKind Kind) : Kind(Kind) {
682 }
683
684 // Create layout for COMPONENT_Y which depends on COMPONENT_X layout.
686 : Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps) {}
687
688public:
689 // Return the index of dst operand in MCInst operands.
690 unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }
691
692 // Return the index of the specified src operand in MCInst operands.
693 unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const {
694 assert(CompSrcIdx < Component::MAX_SRC_NUM);
695 return FIRST_MC_SRC_IDX[Kind] + getPrevCompSrcNum() + CompSrcIdx;
696 }
697
698 // Return the index of dst operand in the parsed operands array.
700 return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
701 }
702
703 // Return the index of the specified src operand in the parsed operands array.
704 unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {
705 assert(CompSrcIdx < Component::MAX_SRC_NUM);
706 return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
707 }
708
709private:
710 unsigned getPrevCompSrcNum() const {
711 return PrevComp.getCompSrcOperandsNum();
712 }
713 unsigned getPrevCompParsedSrcNum() const {
714 return PrevComp.getCompParsedSrcOperandsNum();
715 }
716};
717
718// Layout and properties of VOPD components.
720public:
721 // Create ComponentInfo for COMPONENT_X or SINGLE component.
724 : ComponentLayout(Kind), ComponentProps(OpDesc) {}
725
726 // Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.
727 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
728 : ComponentLayout(OpXProps), ComponentProps(OpDesc) {}
729
730 // Map component operand index to parsed operand index.
731 // Return 0 if the specified operand does not exist.
732 unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;
733};
734
735// Properties of VOPD instructions.
736class InstInfo {
737private:
738 const ComponentInfo CompInfo[COMPONENTS_NUM];
739
740public:
741 using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
742
743 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
744 : CompInfo{OpX, OpY} {}
745
746 InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
747 : CompInfo{OprInfoX, OprInfoY} {}
748
749 const ComponentInfo &operator[](size_t ComponentIdx) const {
750 assert(ComponentIdx < COMPONENTS_NUM);
751 return CompInfo[ComponentIdx];
752 }
753
754 // Check VOPD operands constraints.
755 // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
756 // for the specified component and MC operand. The callback must return 0
757 // if the operand is not a register or not a VGPR.
759 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const {
760 return getInvalidCompOperandIndex(GetRegIdx).has_value();
761 }
762
763 // Check VOPD operands constraints.
764 // Return the index of an invalid component operand, if any.
765 std::optional<unsigned> getInvalidCompOperandIndex(
766 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
767
768private:
770 getRegIndices(unsigned ComponentIdx,
771 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
772};
773
774} // namespace VOPD
775
777std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
778
780// Get properties of 2 single VOP1/VOP2 instructions
781// used as components to create a VOPD instruction.
782VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
783
785// Get properties of VOPD X and Y components.
786VOPD::InstInfo
787getVOPDInstInfo(unsigned VOPDOpcode, const MCInstrInfo *InstrInfo);
788
790bool isTrue16Inst(unsigned Opc);
791
793unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
794
796unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
797
799 const MCSubtargetInfo *STI);
800
802 const MCSubtargetInfo *STI);
803
804bool isGroupSegment(const GlobalValue *GV);
805bool isGlobalSegment(const GlobalValue *GV);
806bool isReadOnlySegment(const GlobalValue *GV);
807
808/// \returns True if constants should be emitted to .text section for given
809/// target triple \p TT, false otherwise.
811
812/// \returns Integer value requested using \p F's \p Name attribute.
813///
814/// \returns \p Default if attribute is not present.
815///
816/// \returns \p Default and emits error if requested value cannot be converted
817/// to integer.
819
820/// \returns A pair of integer values requested using \p F's \p Name attribute
821/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
822/// is false).
823///
824/// \returns \p Default if attribute is not present.
825///
826/// \returns \p Default and emits error if one of the requested values cannot be
827/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
828/// not present.
829std::pair<int, int> getIntegerPairAttribute(const Function &F,
831 std::pair<int, int> Default,
832 bool OnlyFirstRequired = false);
833
834/// Represents the counter values to wait for in an s_waitcnt instruction.
835///
836/// Large values (including the maximum possible integer) can be used to
837/// represent "don't care" waits.
838struct Waitcnt {
839 unsigned VmCnt = ~0u;
840 unsigned ExpCnt = ~0u;
841 unsigned LgkmCnt = ~0u;
842 unsigned VsCnt = ~0u;
843
844 Waitcnt() = default;
845 Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
847
848 static Waitcnt allZero(bool HasVscnt) {
849 return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
850 }
851 static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
852
853 bool hasWait() const {
854 return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
855 }
856
857 bool hasWaitExceptVsCnt() const {
858 return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
859 }
860
861 bool hasWaitVsCnt() const {
862 return VsCnt != ~0u;
863 }
864
865 bool dominates(const Waitcnt &Other) const {
866 return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
867 LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
868 }
869
871 return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
872 std::min(LgkmCnt, Other.LgkmCnt),
873 std::min(VsCnt, Other.VsCnt));
874 }
875};
876
877/// \returns Vmcnt bit mask for given isa \p Version.
878unsigned getVmcntBitMask(const IsaVersion &Version);
879
880/// \returns Expcnt bit mask for given isa \p Version.
881unsigned getExpcntBitMask(const IsaVersion &Version);
882
883/// \returns Lgkmcnt bit mask for given isa \p Version.
884unsigned getLgkmcntBitMask(const IsaVersion &Version);
885
886/// \returns Waitcnt bit mask for given isa \p Version.
887unsigned getWaitcntBitMask(const IsaVersion &Version);
888
889/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
890unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
891
892/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
893unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
894
895/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
896unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
897
898/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
899/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
900/// \p Lgkmcnt respectively.
901///
902/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
903/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
904/// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
905/// \p Vmcnt = \p Waitcnt[15:10] (gfx11+)
906/// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
907/// \p Expcnt = \p Waitcnt[2:0] (gfx11+)
908/// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
909/// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
910/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11+)
911void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
912 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
913
914Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
915
916/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
917unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
918 unsigned Vmcnt);
919
920/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
921unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
922 unsigned Expcnt);
923
924/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
925unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
926 unsigned Lgkmcnt);
927
928/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
929/// \p Version.
930///
931/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
932/// Waitcnt[2:0] = \p Expcnt (gfx11+)
933/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
934/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
935/// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
936/// Waitcnt[9:4] = \p Lgkmcnt (gfx11+)
937/// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
938/// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
939/// Waitcnt[15:10] = \p Vmcnt (gfx11+)
940/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
941///
942/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
943/// isa \p Version.
944unsigned encodeWaitcnt(const IsaVersion &Version,
945 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
946
947unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
948
949namespace Hwreg {
950
952int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
953
955bool isValidHwreg(int64_t Id);
956
958bool isValidHwregOffset(int64_t Offset);
959
961bool isValidHwregWidth(int64_t Width);
962
965
967StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
968
969void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
970
971} // namespace Hwreg
972
973namespace DepCtr {
974
975int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
976int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
977 const MCSubtargetInfo &STI);
978bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
979 const MCSubtargetInfo &STI);
980bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
981 bool &IsDefault, const MCSubtargetInfo &STI);
982
983} // namespace DepCtr
984
985namespace Exp {
986
987bool getTgtName(unsigned Id, StringRef &Name, int &Index);
988
990unsigned getTgtId(const StringRef Name);
991
993bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
994
995} // namespace Exp
996
997namespace MTBUFFormat {
998
1000int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
1001
1002void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
1003
1004int64_t getDfmt(const StringRef Name);
1005
1006StringRef getDfmtName(unsigned Id);
1007
1008int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
1009
1010StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
1011
1012bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
1013
1014bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
1015
1016int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
1017
1018StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
1019
1020bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
1021
1022int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
1023 const MCSubtargetInfo &STI);
1024
1025bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
1026
1027unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
1028
1029} // namespace MTBUFFormat
1030
1031namespace SendMsg {
1032
1034int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
1035
1037int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
1038
1040StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
1041
1043StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1044
1046bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
1047
1049bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1050 bool Strict = true);
1051
1053bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1054 const MCSubtargetInfo &STI, bool Strict = true);
1055
1057bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
1058
1060bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1061
1062void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1063 uint16_t &StreamId, const MCSubtargetInfo &STI);
1064
1067 uint64_t OpId,
1069
1070} // namespace SendMsg
1071
1072
1073unsigned getInitialPSInputAddr(const Function &F);
1074
1075bool getHasColorExport(const Function &F);
1076
1077bool getHasDepthExport(const Function &F);
1078
1081
1084
1087
1090
1091// These functions are considered entrypoints into the current module, i.e. they
1092// are allowed to be called from outside the current module. This is different
1093// from isEntryFunctionCC, which is only true for functions that are entered by
1094// the hardware. Module entry points include all entry functions but also
1095// include functions that can be called from other functions inside or outside
1096// the current module. Module entry functions are allowed to allocate LDS.
1099
1100bool isKernelCC(const Function *Func);
1101
1102// FIXME: Remove this when calling conventions cleaned up
1105 switch (CC) {
1108 return true;
1109 default:
1110 return false;
1111 }
1112}
1113
1114bool hasXNACK(const MCSubtargetInfo &STI);
1115bool hasSRAMECC(const MCSubtargetInfo &STI);
1116bool hasMIMG_R128(const MCSubtargetInfo &STI);
1117bool hasA16(const MCSubtargetInfo &STI);
1118bool hasG16(const MCSubtargetInfo &STI);
1119bool hasPackedD16(const MCSubtargetInfo &STI);
1120unsigned getNSAMaxSize(const MCSubtargetInfo &STI);
1121
1122bool isSI(const MCSubtargetInfo &STI);
1123bool isCI(const MCSubtargetInfo &STI);
1124bool isVI(const MCSubtargetInfo &STI);
1125bool isGFX9(const MCSubtargetInfo &STI);
1126bool isGFX9_GFX10(const MCSubtargetInfo &STI);
1127bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
1128bool isGFX8Plus(const MCSubtargetInfo &STI);
1129bool isGFX9Plus(const MCSubtargetInfo &STI);
1130bool isGFX10(const MCSubtargetInfo &STI);
1131bool isGFX10Plus(const MCSubtargetInfo &STI);
1132bool isNotGFX10Plus(const MCSubtargetInfo &STI);
1133bool isGFX10Before1030(const MCSubtargetInfo &STI);
1134bool isGFX11(const MCSubtargetInfo &STI);
1135bool isGFX11Plus(const MCSubtargetInfo &STI);
1136bool isNotGFX11Plus(const MCSubtargetInfo &STI);
1137bool isGCN3Encoding(const MCSubtargetInfo &STI);
1138bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
1139bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
1140bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
1141bool isGFX90A(const MCSubtargetInfo &STI);
1142bool isGFX940(const MCSubtargetInfo &STI);
1144bool hasMAIInsts(const MCSubtargetInfo &STI);
1145bool hasVOPD(const MCSubtargetInfo &STI);
1146int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
1147
1148/// Is Reg - scalar register
1149bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
1150
1151/// If \p Reg is a pseudo reg, return the correct hardware register given
1152/// \p STI otherwise return \p Reg.
1153unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
1154
1155/// Convert hardware register \p Reg to a pseudo register
1157unsigned mc2PseudoReg(unsigned Reg);
1158
1160bool isInlineValue(unsigned Reg);
1161
1162/// Is this an AMDGPU specific source operand? These include registers,
1163/// inline constants, literals and mandatory literals (KImm).
1164bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1165
1166/// Is this a KImm operand?
1167bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1168
1169/// Is this floating-point operand?
1170bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1171
1172/// Does this operand support only inlinable literals?
1173bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1174
1175/// Get the size in bits of a register from the register class \p RC.
1176unsigned getRegBitWidth(unsigned RCID);
1177
1178/// Get the size in bits of a register from the register class \p RC.
1179unsigned getRegBitWidth(const MCRegisterClass &RC);
1180
1181/// Get size of register operand
1182unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
1183 unsigned OpNo);
1184
1186inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
1187 switch (OpInfo.OperandType) {
1200 case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
1201 return 4;
1202
1208 return 8;
1209
1223 return 2;
1224
1225 default:
1226 llvm_unreachable("unhandled operand type");
1227 }
1228}
1229
1231inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
1232 return getOperandSize(Desc.operands()[OpNo]);
1233}
1234
1235/// Is this literal inlinable, and not one of the values intended for floating
1236/// point values.
1238inline bool isInlinableIntLiteral(int64_t Literal) {
1239 return Literal >= -16 && Literal <= 64;
1240}
1241
1242/// Is this literal inlinable
1244bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
1245
1247bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
1248
1250bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
1251
1253bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
1254
1257
1259bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
1260
1261bool isArgPassedInSGPR(const Argument *Arg);
1262
1263bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo);
1264
1267 int64_t EncodedOffset);
1268
1271 int64_t EncodedOffset,
1272 bool IsBuffer);
1273
1274/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
1275/// offsets.
1277
1278/// \returns The encoding that will be used for \p ByteOffset in the
1279/// SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10
1280/// S_LOAD instructions have a signed offset, on other subtargets it is
1281/// unsigned. S_BUFFER has an unsigned offset for all subtargets.
1282std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
1283 int64_t ByteOffset, bool IsBuffer);
1284
1285/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
1286/// instruction. This is only useful on CI.s
1287std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
1288 int64_t ByteOffset);
1289
1290/// For FLAT segment the offset must be positive;
1291/// MSB is ignored and forced to zero.
1292///
1293/// \return The number of bits available for the signed offset field in flat
1294/// instructions. Note that some forms of the instruction disallow negative
1295/// offsets.
1296unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);
1297
1298/// \returns true if this offset is small enough to fit in the SMRD
1299/// offset field. \p ByteOffset should be the offset in bytes and
1300/// not the encoded offset.
1301bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
1302
1304inline bool isLegal64BitDPPControl(unsigned DC) {
1305 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
1306}
1307
1308/// \returns true if the intrinsic is divergent
1309bool isIntrinsicSourceOfDivergence(unsigned IntrID);
1310
1311/// \returns true if the intrinsic is uniform
1312bool isIntrinsicAlwaysUniform(unsigned IntrID);
1313
1314} // end namespace AMDGPU
1315
1316raw_ostream &operator<<(raw_ostream &OS,
1318
1319} // end namespace llvm
1320
1321#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
unsigned const MachineRegisterInfo * MRI
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
#define LLVM_READNONE
Definition: Compiler.h:189
#define LLVM_READONLY
Definition: Compiler.h:196
uint64_t Align
std::string Name
#define F(x, y, z)
Definition: MD5.cpp:55
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Module.h This file contains the declarations for the Module class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
void setTargetIDFromFeaturesString(StringRef FS)
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
TargetIDSetting getXnackSetting() const
void setTargetIDFromTargetIDStream(StringRef TargetID)
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
TargetIDSetting getSramEccSetting() const
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
ComponentInfo(const MCInstrDesc &OpDesc, ComponentKind Kind=ComponentKind::SINGLE)
ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const
unsigned getIndexOfDstInParsedOperands() const
ComponentLayout(const ComponentProps &OpXProps)
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
bool hasRegSrcOperand(unsigned CompSrcIdx) const
unsigned getMandatoryLiteralCompOperandIndex() const
unsigned getCompParsedSrcOperandsNum() const
InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
const ComponentInfo & operator[](size_t ComponentIdx) const
bool hasInvalidOperand(std::function< unsigned(unsigned, unsigned)> GetRegIdx) const
InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
std::optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx) const
std::array< unsigned, Component::MAX_OPR_NUM > RegIndices
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1186
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
bool isValidHwreg(int64_t Id)
bool isValidHwregOffset(int64_t Offset)
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
bool isValidHwregWidth(int64_t Width)
int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI)
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
StringRef getDfmtName(unsigned Id)
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
int64_t getDfmt(const StringRef Name)
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned COMPONENTS_NUM
constexpr unsigned COMPONENTS[]
constexpr unsigned BANKS_NUM[]
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI)
int getVOPDFull(unsigned OpX, unsigned OpY)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
LLVM_READNONE bool isLegal64BitDPPControl(unsigned DC)
LLVM_READONLY const MIMGOffsetMappingInfo * getMIMGOffsetMappingInfo(unsigned Offset)
bool isHsaAbiVersion2(const MCSubtargetInfo *STI)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool isHsaAbiVersion5(const MCSubtargetInfo *STI)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isInlinableIntLiteralV216(int32_t Literal)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
bool isHsaAbiVersion4(const MCSubtargetInfo *STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
int getMTBUFElements(unsigned Opc)
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
CanBeVOPD getCanBeVOPD(unsigned Opc)
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getCodeObjectVersion(const Module &M)
bool isGFX940(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
LLVM_READNONE bool isKernel(CallingConv::ID CC)
bool isGFX11(const MCSubtargetInfo &STI)
bool getSMEMIsBuffer(unsigned Opc)
bool isGroupSegment(const GlobalValue *GV)
LLVM_READONLY const MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
bool getMTBUFHasSoffset(unsigned Opc)
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
bool hasXNACK(const MCSubtargetInfo &STI)
unsigned getVOPDOpcode(unsigned Opc)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool isCompute(CallingConv::ID cc)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool getVOP1IsSingle(unsigned Opc)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
bool isTrue16Inst(unsigned Opc)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
unsigned getAmdhsaCodeObjectVersion()
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isKernelCC(const Function *Func)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
LLVM_READONLY const MIMGBiasMappingInfo * getMIMGBiasMappingInfo(unsigned Bias)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
bool isInlineValue(unsigned Reg)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isShader(CallingConv::ID cc)
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
bool isGlobalSegment(const GlobalValue *GV)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:186
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:161
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:168
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:182
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:179
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:169
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:196
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:160
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:165
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:176
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:174
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:190
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:164
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:181
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:195
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:192
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:191
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:193
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:170
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:163
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:178
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:175
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:180
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:171
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:194
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:177
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:162
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:183
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:167
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:166
LLVM_READONLY const MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
std::optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfo(unsigned DimEnum)
bool getMUBUFIsBufferInv(unsigned Opc)
bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI)
bool isMAC(unsigned Opc)
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
bool getVOP2IsSingle(unsigned Opc)
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isModuleEntryFunctionCC(CallingConv::ID CC)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
bool hasVOPD(const MCSubtargetInfo &STI)
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
bool isGraphics(CallingConv::ID cc)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:197
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:141
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:292
@ Default
The result values are uniform if and only if all operands are uniform.
AMD Kernel Code Object (amd_kernel_code_t).
Represents the counter values to wait for in an s_waitcnt instruction.
bool hasWaitExceptVsCnt() const
static Waitcnt allZero(bool HasVscnt)
static Waitcnt allZeroExceptVsCnt()
bool dominates(const Waitcnt &Other) const
bool hasWaitVsCnt() const
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
Waitcnt combined(const Waitcnt &Other) const