LLVM 18.0.0git
AMDGPUBaseInfo.h
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1//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11
12#include "SIDefines.h"
13#include "llvm/IR/CallingConv.h"
14#include "llvm/IR/InstrTypes.h"
15#include "llvm/IR/Module.h"
17#include <array>
18#include <functional>
19#include <utility>
20
22
23namespace llvm {
24
25struct Align;
26class Argument;
27class Function;
28class GlobalValue;
29class MCInstrInfo;
30class MCRegisterClass;
31class MCRegisterInfo;
32class MCSubtargetInfo;
33class StringRef;
34class Triple;
35class raw_ostream;
36
37namespace amdhsa {
38struct kernel_descriptor_t;
39}
40
41namespace AMDGPU {
42
43struct IsaVersion;
44
45enum {
48 AMDHSA_COV5 = 5
49};
50
51/// \returns True if \p STI is AMDHSA.
52bool isHsaAbi(const MCSubtargetInfo &STI);
53/// \returns HSA OS ABI Version identification.
54std::optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
55/// \returns True if HSA OS ABI Version identification is 3,
56/// false otherwise.
57bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
58/// \returns True if HSA OS ABI Version identification is 4,
59/// false otherwise.
60bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
61/// \returns True if HSA OS ABI Version identification is 5,
62/// false otherwise.
63bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
64
65/// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
66unsigned getMultigridSyncArgImplicitArgPosition(unsigned COV);
67
68/// \returns The offset of the hostcall pointer argument from implicitarg_ptr
69unsigned getHostcallImplicitArgPosition(unsigned COV);
70
71unsigned getDefaultQueueImplicitArgPosition(unsigned COV);
72unsigned getCompletionActionImplicitArgPosition(unsigned COV);
73
74/// \returns Code object version.
76
77/// \returns Code object version.
78unsigned getCodeObjectVersion(const Module &M);
79
81 unsigned Format;
82 unsigned BitsPerComp;
83 unsigned NumComponents;
84 unsigned NumFormat;
85 unsigned DataFormat;
86};
87
92};
93
94#define GET_MIMGBaseOpcode_DECL
95#define GET_MIMGDim_DECL
96#define GET_MIMGEncoding_DECL
97#define GET_MIMGLZMapping_DECL
98#define GET_MIMGMIPMapping_DECL
99#define GET_MIMGBiASMapping_DECL
100#define GET_MAIInstInfoTable_DECL
101#include "AMDGPUGenSearchableTables.inc"
102
103namespace IsaInfo {
104
105enum {
106 // The closed Vulkan driver sets 96, which limits the wave count to 8 but
107 // doesn't spill SGPRs as much as when 80 is set.
109 TRAP_NUM_SGPRS = 16
111
112enum class TargetIDSetting {
114 Any,
115 Off,
116 On
117};
118
120private:
121 const MCSubtargetInfo &STI;
122 TargetIDSetting XnackSetting;
123 TargetIDSetting SramEccSetting;
124 unsigned CodeObjectVersion;
125
126public:
127 explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
128 ~AMDGPUTargetID() = default;
129
130 /// \return True if the current xnack setting is not "Unsupported".
131 bool isXnackSupported() const {
132 return XnackSetting != TargetIDSetting::Unsupported;
133 }
134
135 /// \returns True if the current xnack setting is "On" or "Any".
136 bool isXnackOnOrAny() const {
137 return XnackSetting == TargetIDSetting::On ||
138 XnackSetting == TargetIDSetting::Any;
139 }
140
141 /// \returns True if current xnack setting is "On" or "Off",
142 /// false otherwise.
143 bool isXnackOnOrOff() const {
146 }
147
148 /// \returns The current xnack TargetIDSetting, possible options are
149 /// "Unsupported", "Any", "Off", and "On".
151 return XnackSetting;
152 }
153
154 void setCodeObjectVersion(unsigned COV) {
155 CodeObjectVersion = COV;
156 }
157
158 /// Sets xnack setting to \p NewXnackSetting.
159 void setXnackSetting(TargetIDSetting NewXnackSetting) {
160 XnackSetting = NewXnackSetting;
161 }
162
163 /// \return True if the current sramecc setting is not "Unsupported".
164 bool isSramEccSupported() const {
165 return SramEccSetting != TargetIDSetting::Unsupported;
166 }
167
168 /// \returns True if the current sramecc setting is "On" or "Any".
169 bool isSramEccOnOrAny() const {
170 return SramEccSetting == TargetIDSetting::On ||
171 SramEccSetting == TargetIDSetting::Any;
172 }
173
174 /// \returns True if current sramecc setting is "On" or "Off",
175 /// false otherwise.
176 bool isSramEccOnOrOff() const {
179 }
180
181 /// \returns The current sramecc TargetIDSetting, possible options are
182 /// "Unsupported", "Any", "Off", and "On".
184 return SramEccSetting;
185 }
186
187 /// Sets sramecc setting to \p NewSramEccSetting.
188 void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
189 SramEccSetting = NewSramEccSetting;
190 }
191
194
195 /// \returns String representation of an object.
196 std::string toString() const;
197};
198
199/// \returns Wavefront size for given subtarget \p STI.
200unsigned getWavefrontSize(const MCSubtargetInfo *STI);
201
202/// \returns Local memory size in bytes for given subtarget \p STI.
203unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
204
205/// \returns Maximum addressable local memory size in bytes for given subtarget
206/// \p STI.
208
209/// \returns Number of execution units per compute unit for given subtarget \p
210/// STI.
211unsigned getEUsPerCU(const MCSubtargetInfo *STI);
212
213/// \returns Maximum number of work groups per compute unit for given subtarget
214/// \p STI and limited by given \p FlatWorkGroupSize.
215unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
216 unsigned FlatWorkGroupSize);
217
218/// \returns Minimum number of waves per execution unit for given subtarget \p
219/// STI.
220unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
221
222/// \returns Maximum number of waves per execution unit for given subtarget \p
223/// STI without any kind of limitation.
224unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
225
226/// \returns Number of waves per execution unit required to support the given \p
227/// FlatWorkGroupSize.
229 unsigned FlatWorkGroupSize);
230
231/// \returns Minimum flat work group size for given subtarget \p STI.
232unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
233
234/// \returns Maximum flat work group size for given subtarget \p STI.
235unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
236
237/// \returns Number of waves per work group for given subtarget \p STI and
238/// \p FlatWorkGroupSize.
239unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
240 unsigned FlatWorkGroupSize);
241
242/// \returns SGPR allocation granularity for given subtarget \p STI.
243unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
244
245/// \returns SGPR encoding granularity for given subtarget \p STI.
246unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
247
248/// \returns Total number of SGPRs for given subtarget \p STI.
249unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
250
251/// \returns Addressable number of SGPRs for given subtarget \p STI.
252unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
253
254/// \returns Minimum number of SGPRs that meets the given number of waves per
255/// execution unit requirement for given subtarget \p STI.
256unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
257
258/// \returns Maximum number of SGPRs that meets the given number of waves per
259/// execution unit requirement for given subtarget \p STI.
260unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
261 bool Addressable);
262
263/// \returns Number of extra SGPRs implicitly required by given subtarget \p
264/// STI when the given special registers are used.
265unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
266 bool FlatScrUsed, bool XNACKUsed);
267
268/// \returns Number of extra SGPRs implicitly required by given subtarget \p
269/// STI when the given special registers are used. XNACK is inferred from
270/// \p STI.
271unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
272 bool FlatScrUsed);
273
274/// \returns Number of SGPR blocks needed for given subtarget \p STI when
275/// \p NumSGPRs are used. \p NumSGPRs should already include any special
276/// register counts.
277unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
278
279/// \returns VGPR allocation granularity for given subtarget \p STI.
280///
281/// For subtargets which support it, \p EnableWavefrontSize32 should match
282/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
283unsigned
285 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
286
287/// \returns VGPR encoding granularity for given subtarget \p STI.
288///
289/// For subtargets which support it, \p EnableWavefrontSize32 should match
290/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
292 const MCSubtargetInfo *STI,
293 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
294
295/// \returns Total number of VGPRs for given subtarget \p STI.
296unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
297
298/// \returns Addressable number of VGPRs for given subtarget \p STI.
299unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
300
301/// \returns Minimum number of VGPRs that meets given number of waves per
302/// execution unit requirement for given subtarget \p STI.
303unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
304
305/// \returns Maximum number of VGPRs that meets given number of waves per
306/// execution unit requirement for given subtarget \p STI.
307unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
308
309/// \returns Number of waves reachable for a given \p NumVGPRs usage for given
310/// subtarget \p STI.
312 unsigned NumVGPRs);
313
314/// \returns Number of VGPR blocks needed for given subtarget \p STI when
315/// \p NumVGPRs are used.
316///
317/// For subtargets which support it, \p EnableWavefrontSize32 should match the
318/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
319unsigned
320getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
321 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
322
323} // end namespace IsaInfo
324
326int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
327
329inline bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx) {
330 return getNamedOperandIdx(Opcode, NamedIdx) != -1;
331}
332
335
337 MIMGBaseOpcode BaseOpcode;
338 bool Store;
339 bool Atomic;
343
346 bool G16;
349 bool HasD16;
350 bool MSAA;
351 bool BVH;
352 bool A16;
353};
354
356const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
357
359const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
360
362 MIMGDim Dim;
363 uint8_t NumCoords;
365 bool MSAA;
366 bool DA;
367 uint8_t Encoding;
368 const char *AsmSuffix;
369};
370
372const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
373
376
379
381 MIMGBaseOpcode L;
382 MIMGBaseOpcode LZ;
383};
384
386 MIMGBaseOpcode MIP;
387 MIMGBaseOpcode NONMIP;
388};
389
391 MIMGBaseOpcode Bias;
392 MIMGBaseOpcode NoBias;
393};
394
396 MIMGBaseOpcode Offset;
397 MIMGBaseOpcode NoOffset;
398};
399
401 MIMGBaseOpcode G;
402 MIMGBaseOpcode G16;
403};
404
407
409 unsigned Opcode2Addr;
410 unsigned Opcode3Addr;
411};
412
415
418
421
424
426int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
427 unsigned VDataDwords, unsigned VAddrDwords);
428
430int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
431
433unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
434 const MIMGDimInfo *Dim, bool IsA16,
435 bool IsG16Supported);
436
437struct MIMGInfo {
441 uint8_t VDataDwords;
442 uint8_t VAddrDwords;
444};
445
447const MIMGInfo *getMIMGInfo(unsigned Opc);
448
450int getMTBUFBaseOpcode(unsigned Opc);
451
453int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
454
456int getMTBUFElements(unsigned Opc);
457
459bool getMTBUFHasVAddr(unsigned Opc);
460
462bool getMTBUFHasSrsrc(unsigned Opc);
463
465bool getMTBUFHasSoffset(unsigned Opc);
466
468int getMUBUFBaseOpcode(unsigned Opc);
469
471int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
472
474int getMUBUFElements(unsigned Opc);
475
477bool getMUBUFHasVAddr(unsigned Opc);
478
480bool getMUBUFHasSrsrc(unsigned Opc);
481
483bool getMUBUFHasSoffset(unsigned Opc);
484
486bool getMUBUFIsBufferInv(unsigned Opc);
487
489bool getSMEMIsBuffer(unsigned Opc);
490
492bool getVOP1IsSingle(unsigned Opc);
493
495bool getVOP2IsSingle(unsigned Opc);
496
498bool getVOP3IsSingle(unsigned Opc);
499
501bool isVOPC64DPP(unsigned Opc);
502
503/// Returns true if MAI operation is a double precision GEMM.
505bool getMAIIsDGEMM(unsigned Opc);
506
508bool getMAIIsGFX940XDL(unsigned Opc);
509
510struct CanBeVOPD {
511 bool X;
512 bool Y;
513};
514
516CanBeVOPD getCanBeVOPD(unsigned Opc);
517
519const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
520 uint8_t NumComponents,
521 uint8_t NumFormat,
522 const MCSubtargetInfo &STI);
525 const MCSubtargetInfo &STI);
526
528int getMCOpcode(uint16_t Opcode, unsigned Gen);
529
531unsigned getVOPDOpcode(unsigned Opc);
532
534int getVOPDFull(unsigned OpX, unsigned OpY);
535
537bool isVOPD(unsigned Opc);
538
540bool isMAC(unsigned Opc);
541
543bool isPermlane16(unsigned Opc);
544
546bool isGenericAtomic(unsigned Opc);
547
548namespace VOPD {
549
550enum Component : unsigned {
551 DST = 0,
555
560
561// LSB mask for VGPR banks per VOPD component operand.
562// 4 banks result in a mask 3, setting 2 lower bits.
563constexpr unsigned VOPD_VGPR_BANK_MASKS[] = {1, 3, 3, 1};
564
565enum ComponentIndex : unsigned { X = 0, Y = 1 };
567constexpr unsigned COMPONENTS_NUM = 2;
568
569// Properties of VOPD components.
571private:
572 unsigned SrcOperandsNum = 0;
573 unsigned MandatoryLiteralIdx = ~0u;
574 bool HasSrc2Acc = false;
575
576public:
577 ComponentProps() = default;
578 ComponentProps(const MCInstrDesc &OpDesc);
579
580 // Return the total number of src operands this component has.
581 unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }
582
583 // Return the number of src operands of this component visible to the parser.
585 return SrcOperandsNum - HasSrc2Acc;
586 }
587
588 // Return true iif this component has a mandatory literal.
589 bool hasMandatoryLiteral() const { return MandatoryLiteralIdx != ~0u; }
590
591 // If this component has a mandatory literal, return component operand
592 // index of this literal (i.e. either Component::SRC1 or Component::SRC2).
595 return MandatoryLiteralIdx;
596 }
597
598 // Return true iif this component has operand
599 // with component index CompSrcIdx and this operand may be a register.
600 bool hasRegSrcOperand(unsigned CompSrcIdx) const {
601 assert(CompSrcIdx < Component::MAX_SRC_NUM);
602 return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
603 }
604
605 // Return true iif this component has tied src2.
606 bool hasSrc2Acc() const { return HasSrc2Acc; }
607
608private:
609 bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
610 assert(CompSrcIdx < Component::MAX_SRC_NUM);
611 return MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;
612 }
613};
614
615enum ComponentKind : unsigned {
616 SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.
617 COMPONENT_X, // A VOPD instruction, X component.
618 COMPONENT_Y, // A VOPD instruction, Y component.
621
622// Interface functions of this class map VOPD component operand indices
623// to indices of operands in MachineInstr/MCInst or parsed operands array.
624//
625// Note that this class operates with 3 kinds of indices:
626// - VOPD component operand indices (Component::DST, Component::SRC0, etc.);
627// - MC operand indices (they refer operands in a MachineInstr/MCInst);
628// - parsed operand indices (they refer operands in parsed operands array).
629//
630// For SINGLE components mapping between these indices is trivial.
631// But things get more complicated for COMPONENT_X and
632// COMPONENT_Y because these components share the same
633// MachineInstr/MCInst and the same parsed operands array.
634// Below is an example of component operand to parsed operand
635// mapping for the following instruction:
636//
637// v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1
638//
639// PARSED COMPONENT PARSED
640// COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX
641// -------------------------------------------------------------------
642// "v_dual_add_f32" 0
643// v_dual_add_f32 v255 0 (DST) --> 1
644// v4 1 (SRC0) --> 2
645// v5 2 (SRC1) --> 3
646// "::" 4
647// "v_dual_mov_b32" 5
648// v_dual_mov_b32 v6 0 (DST) --> 6
649// v1 1 (SRC0) --> 7
650// -------------------------------------------------------------------
651//
653private:
654 // Regular MachineInstr/MCInst operands are ordered as follows:
655 // dst, src0 [, other src operands]
656 // VOPD MachineInstr/MCInst operands are ordered as follows:
657 // dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
658 // Each ComponentKind has operand indices defined below.
659 static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
660 static constexpr unsigned FIRST_MC_SRC_IDX[] = {1, 2, 2 /* + OpX.MCSrcNum */};
661
662 // Parsed operands of regular instructions are ordered as follows:
663 // Mnemo dst src0 [vsrc1 ...]
664 // Parsed VOPD operands are ordered as follows:
665 // OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'
666 // OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]
667 // Each ComponentKind has operand indices defined below.
668 static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
669 4 /* + OpX.ParsedSrcNum */};
670 static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
671 2, 2, 5 /* + OpX.ParsedSrcNum */};
672
673private:
674 const ComponentKind Kind;
675 const ComponentProps PrevComp;
676
677public:
678 // Create layout for COMPONENT_X or SINGLE component.
679 ComponentLayout(ComponentKind Kind) : Kind(Kind) {
681 }
682
683 // Create layout for COMPONENT_Y which depends on COMPONENT_X layout.
685 : Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps) {}
686
687public:
688 // Return the index of dst operand in MCInst operands.
689 unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }
690
691 // Return the index of the specified src operand in MCInst operands.
692 unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const {
693 assert(CompSrcIdx < Component::MAX_SRC_NUM);
694 return FIRST_MC_SRC_IDX[Kind] + getPrevCompSrcNum() + CompSrcIdx;
695 }
696
697 // Return the index of dst operand in the parsed operands array.
699 return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
700 }
701
702 // Return the index of the specified src operand in the parsed operands array.
703 unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {
704 assert(CompSrcIdx < Component::MAX_SRC_NUM);
705 return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
706 }
707
708private:
709 unsigned getPrevCompSrcNum() const {
710 return PrevComp.getCompSrcOperandsNum();
711 }
712 unsigned getPrevCompParsedSrcNum() const {
713 return PrevComp.getCompParsedSrcOperandsNum();
714 }
715};
716
717// Layout and properties of VOPD components.
719public:
720 // Create ComponentInfo for COMPONENT_X or SINGLE component.
723 : ComponentLayout(Kind), ComponentProps(OpDesc) {}
724
725 // Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.
726 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
727 : ComponentLayout(OpXProps), ComponentProps(OpDesc) {}
728
729 // Map component operand index to parsed operand index.
730 // Return 0 if the specified operand does not exist.
731 unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;
732};
733
734// Properties of VOPD instructions.
735class InstInfo {
736private:
737 const ComponentInfo CompInfo[COMPONENTS_NUM];
738
739public:
740 using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
741
742 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
743 : CompInfo{OpX, OpY} {}
744
745 InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
746 : CompInfo{OprInfoX, OprInfoY} {}
747
748 const ComponentInfo &operator[](size_t ComponentIdx) const {
749 assert(ComponentIdx < COMPONENTS_NUM);
750 return CompInfo[ComponentIdx];
751 }
752
753 // Check VOPD operands constraints.
754 // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
755 // for the specified component and MC operand. The callback must return 0
756 // if the operand is not a register or not a VGPR.
758 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const {
759 return getInvalidCompOperandIndex(GetRegIdx).has_value();
760 }
761
762 // Check VOPD operands constraints.
763 // Return the index of an invalid component operand, if any.
764 std::optional<unsigned> getInvalidCompOperandIndex(
765 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
766
767private:
769 getRegIndices(unsigned ComponentIdx,
770 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
771};
772
773} // namespace VOPD
774
776std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
777
779// Get properties of 2 single VOP1/VOP2 instructions
780// used as components to create a VOPD instruction.
781VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
782
784// Get properties of VOPD X and Y components.
785VOPD::InstInfo
786getVOPDInstInfo(unsigned VOPDOpcode, const MCInstrInfo *InstrInfo);
787
789bool isTrue16Inst(unsigned Opc);
790
792unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
793
795unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
796
798 const MCSubtargetInfo *STI);
799
801 const MCSubtargetInfo *STI);
802
803bool isGroupSegment(const GlobalValue *GV);
804bool isGlobalSegment(const GlobalValue *GV);
805bool isReadOnlySegment(const GlobalValue *GV);
806
807/// \returns True if constants should be emitted to .text section for given
808/// target triple \p TT, false otherwise.
810
811/// \returns Integer value requested using \p F's \p Name attribute.
812///
813/// \returns \p Default if attribute is not present.
814///
815/// \returns \p Default and emits error if requested value cannot be converted
816/// to integer.
818
819/// \returns A pair of integer values requested using \p F's \p Name attribute
820/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
821/// is false).
822///
823/// \returns \p Default if attribute is not present.
824///
825/// \returns \p Default and emits error if one of the requested values cannot be
826/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
827/// not present.
828std::pair<unsigned, unsigned>
830 std::pair<unsigned, unsigned> Default,
831 bool OnlyFirstRequired = false);
832
833/// Represents the counter values to wait for in an s_waitcnt instruction.
834///
835/// Large values (including the maximum possible integer) can be used to
836/// represent "don't care" waits.
837struct Waitcnt {
838 unsigned VmCnt = ~0u;
839 unsigned ExpCnt = ~0u;
840 unsigned LgkmCnt = ~0u;
841 unsigned VsCnt = ~0u;
842
843 Waitcnt() = default;
844 Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
846
847 static Waitcnt allZero(bool HasVscnt) {
848 return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
849 }
850 static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
851
852 bool hasWait() const {
853 return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
854 }
855
856 bool hasWaitExceptVsCnt() const {
857 return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
858 }
859
860 bool hasWaitVsCnt() const {
861 return VsCnt != ~0u;
862 }
863
865 return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
866 std::min(LgkmCnt, Other.LgkmCnt),
867 std::min(VsCnt, Other.VsCnt));
868 }
869};
870
871/// \returns Vmcnt bit mask for given isa \p Version.
872unsigned getVmcntBitMask(const IsaVersion &Version);
873
874/// \returns Expcnt bit mask for given isa \p Version.
875unsigned getExpcntBitMask(const IsaVersion &Version);
876
877/// \returns Lgkmcnt bit mask for given isa \p Version.
878unsigned getLgkmcntBitMask(const IsaVersion &Version);
879
880/// \returns Waitcnt bit mask for given isa \p Version.
881unsigned getWaitcntBitMask(const IsaVersion &Version);
882
883/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
884unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
885
886/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
887unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
888
889/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
890unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
891
892/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
893/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
894/// \p Lgkmcnt respectively.
895///
896/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
897/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
898/// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
899/// \p Vmcnt = \p Waitcnt[15:10] (gfx11+)
900/// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
901/// \p Expcnt = \p Waitcnt[2:0] (gfx11+)
902/// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
903/// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
904/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11+)
905void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
906 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
907
908Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
909
910/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
911unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
912 unsigned Vmcnt);
913
914/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
915unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
916 unsigned Expcnt);
917
918/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
919unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
920 unsigned Lgkmcnt);
921
922/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
923/// \p Version.
924///
925/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
926/// Waitcnt[2:0] = \p Expcnt (gfx11+)
927/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
928/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
929/// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
930/// Waitcnt[9:4] = \p Lgkmcnt (gfx11+)
931/// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
932/// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
933/// Waitcnt[15:10] = \p Vmcnt (gfx11+)
934/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
935///
936/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
937/// isa \p Version.
938unsigned encodeWaitcnt(const IsaVersion &Version,
939 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
940
941unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
942
943namespace Hwreg {
944
946int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
947
949bool isValidHwreg(int64_t Id);
950
952bool isValidHwregOffset(int64_t Offset);
953
955bool isValidHwregWidth(int64_t Width);
956
959
961StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
962
963void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
964
965} // namespace Hwreg
966
967namespace DepCtr {
968
969int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
970int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
971 const MCSubtargetInfo &STI);
972bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
973 const MCSubtargetInfo &STI);
974bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
975 bool &IsDefault, const MCSubtargetInfo &STI);
976
977/// \returns Decoded VaVdst from given immediate \p Encoded.
978unsigned decodeFieldVaVdst(unsigned Encoded);
979
980/// \returns Decoded VmVsrc from given immediate \p Encoded.
981unsigned decodeFieldVmVsrc(unsigned Encoded);
982
983/// \returns Decoded SaSdst from given immediate \p Encoded.
984unsigned decodeFieldSaSdst(unsigned Encoded);
985
986/// \returns \p VmVsrc as an encoded Depctr immediate.
987unsigned encodeFieldVmVsrc(unsigned VmVsrc);
988
989/// \returns \p Encoded combined with encoded \p VmVsrc.
990unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc);
991
992/// \returns \p VaVdst as an encoded Depctr immediate.
993unsigned encodeFieldVaVdst(unsigned VaVdst);
994
995/// \returns \p Encoded combined with encoded \p VaVdst.
996unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst);
997
998/// \returns \p SaSdst as an encoded Depctr immediate.
999unsigned encodeFieldSaSdst(unsigned SaSdst);
1000
1001/// \returns \p Encoded combined with encoded \p SaSdst.
1002unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst);
1003
1004} // namespace DepCtr
1005
1006namespace Exp {
1007
1008bool getTgtName(unsigned Id, StringRef &Name, int &Index);
1009
1011unsigned getTgtId(const StringRef Name);
1012
1014bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
1015
1016} // namespace Exp
1017
1018namespace MTBUFFormat {
1019
1021int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
1022
1023void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
1024
1025int64_t getDfmt(const StringRef Name);
1026
1027StringRef getDfmtName(unsigned Id);
1028
1029int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
1030
1031StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
1032
1033bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
1034
1035bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
1036
1037int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
1038
1039StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
1040
1041bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
1042
1043int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
1044 const MCSubtargetInfo &STI);
1045
1046bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
1047
1048unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
1049
1050} // namespace MTBUFFormat
1051
1052namespace SendMsg {
1053
1055int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
1056
1058int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
1059
1061StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
1062
1064StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1065
1067bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
1068
1070bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1071 bool Strict = true);
1072
1074bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1075 const MCSubtargetInfo &STI, bool Strict = true);
1076
1078bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
1079
1081bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1082
1083void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1084 uint16_t &StreamId, const MCSubtargetInfo &STI);
1085
1088 uint64_t OpId,
1090
1091} // namespace SendMsg
1092
1093
1094unsigned getInitialPSInputAddr(const Function &F);
1095
1096bool getHasColorExport(const Function &F);
1097
1098bool getHasDepthExport(const Function &F);
1099
1102
1105
1108
1111
1112// These functions are considered entrypoints into the current module, i.e. they
1113// are allowed to be called from outside the current module. This is different
1114// from isEntryFunctionCC, which is only true for functions that are entered by
1115// the hardware. Module entry points include all entry functions but also
1116// include functions that can be called from other functions inside or outside
1117// the current module. Module entry functions are allowed to allocate LDS.
1120
1123
1124bool isKernelCC(const Function *Func);
1125
1126// FIXME: Remove this when calling conventions cleaned up
1129 switch (CC) {
1132 return true;
1133 default:
1134 return false;
1135 }
1136}
1137
1138bool hasXNACK(const MCSubtargetInfo &STI);
1139bool hasSRAMECC(const MCSubtargetInfo &STI);
1140bool hasMIMG_R128(const MCSubtargetInfo &STI);
1141bool hasA16(const MCSubtargetInfo &STI);
1142bool hasG16(const MCSubtargetInfo &STI);
1143bool hasPackedD16(const MCSubtargetInfo &STI);
1144bool hasGDS(const MCSubtargetInfo &STI);
1145unsigned getNSAMaxSize(const MCSubtargetInfo &STI);
1146unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI);
1147
1148bool isSI(const MCSubtargetInfo &STI);
1149bool isCI(const MCSubtargetInfo &STI);
1150bool isVI(const MCSubtargetInfo &STI);
1151bool isGFX9(const MCSubtargetInfo &STI);
1152bool isGFX9_GFX10(const MCSubtargetInfo &STI);
1153bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
1154bool isGFX8Plus(const MCSubtargetInfo &STI);
1155bool isGFX9Plus(const MCSubtargetInfo &STI);
1156bool isGFX10(const MCSubtargetInfo &STI);
1157bool isGFX10Plus(const MCSubtargetInfo &STI);
1158bool isNotGFX10Plus(const MCSubtargetInfo &STI);
1159bool isGFX10Before1030(const MCSubtargetInfo &STI);
1160bool isGFX11(const MCSubtargetInfo &STI);
1161bool isGFX11Plus(const MCSubtargetInfo &STI);
1162bool isNotGFX11Plus(const MCSubtargetInfo &STI);
1163bool isGCN3Encoding(const MCSubtargetInfo &STI);
1164bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
1165bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
1166bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
1167bool isGFX90A(const MCSubtargetInfo &STI);
1168bool isGFX940(const MCSubtargetInfo &STI);
1170bool hasMAIInsts(const MCSubtargetInfo &STI);
1171bool hasVOPD(const MCSubtargetInfo &STI);
1172int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
1173unsigned hasKernargPreload(const MCSubtargetInfo &STI);
1174
1175/// Is Reg - scalar register
1176bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
1177
1178/// If \p Reg is a pseudo reg, return the correct hardware register given
1179/// \p STI otherwise return \p Reg.
1180unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
1181
1182/// Convert hardware register \p Reg to a pseudo register
1184unsigned mc2PseudoReg(unsigned Reg);
1185
1187bool isInlineValue(unsigned Reg);
1188
1189/// Is this an AMDGPU specific source operand? These include registers,
1190/// inline constants, literals and mandatory literals (KImm).
1191bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1192
1193/// Is this a KImm operand?
1194bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1195
1196/// Is this floating-point operand?
1197bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1198
1199/// Does this operand support only inlinable literals?
1200bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1201
1202/// Get the size in bits of a register from the register class \p RC.
1203unsigned getRegBitWidth(unsigned RCID);
1204
1205/// Get the size in bits of a register from the register class \p RC.
1206unsigned getRegBitWidth(const MCRegisterClass &RC);
1207
1208/// Get size of register operand
1209unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
1210 unsigned OpNo);
1211
1213inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
1214 switch (OpInfo.OperandType) {
1227 case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
1228 return 4;
1229
1235 return 8;
1236
1250 return 2;
1251
1252 default:
1253 llvm_unreachable("unhandled operand type");
1254 }
1255}
1256
1258inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
1259 return getOperandSize(Desc.operands()[OpNo]);
1260}
1261
1262/// Is this literal inlinable, and not one of the values intended for floating
1263/// point values.
1265inline bool isInlinableIntLiteral(int64_t Literal) {
1266 return Literal >= -16 && Literal <= 64;
1267}
1268
1269/// Is this literal inlinable
1271bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
1272
1274bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
1275
1277bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
1278
1280bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
1281
1284
1286bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
1287
1288bool isArgPassedInSGPR(const Argument *Arg);
1289
1290bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo);
1291
1294 int64_t EncodedOffset);
1295
1298 int64_t EncodedOffset,
1299 bool IsBuffer);
1300
1301/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
1302/// offsets.
1304
1305/// \returns The encoding that will be used for \p ByteOffset in the
1306/// SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10
1307/// S_LOAD instructions have a signed offset, on other subtargets it is
1308/// unsigned. S_BUFFER has an unsigned offset for all subtargets.
1309std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
1310 int64_t ByteOffset, bool IsBuffer);
1311
1312/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
1313/// instruction. This is only useful on CI.s
1314std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
1315 int64_t ByteOffset);
1316
1317/// For FLAT segment the offset must be positive;
1318/// MSB is ignored and forced to zero.
1319///
1320/// \return The number of bits available for the signed offset field in flat
1321/// instructions. Note that some forms of the instruction disallow negative
1322/// offsets.
1323unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);
1324
1325/// \returns true if this offset is small enough to fit in the SMRD
1326/// offset field. \p ByteOffset should be the offset in bytes and
1327/// not the encoded offset.
1328bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
1329
1331inline bool isLegalDPALU_DPPControl(unsigned DC) {
1332 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
1333}
1334
1335/// \returns true if an instruction may have a 64-bit VGPR operand.
1336bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc);
1337
1338/// \returns true if an instruction is a DP ALU DPP.
1339bool isDPALU_DPP(const MCInstrDesc &OpDesc);
1340
1341/// \returns true if the intrinsic is divergent
1342bool isIntrinsicSourceOfDivergence(unsigned IntrID);
1343
1344/// \returns true if the intrinsic is uniform
1345bool isIntrinsicAlwaysUniform(unsigned IntrID);
1346
1347} // end namespace AMDGPU
1348
1349raw_ostream &operator<<(raw_ostream &OS,
1351
1352} // end namespace llvm
1353
1354#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
unsigned const MachineRegisterInfo * MRI
#define LLVM_READNONE
Definition: Compiler.h:201
#define LLVM_READONLY
Definition: Compiler.h:208
uint64_t Align
std::string Name
#define F(x, y, z)
Definition: MD5.cpp:55
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Module.h This file contains the declarations for the Module class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
void setTargetIDFromFeaturesString(StringRef FS)
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
TargetIDSetting getXnackSetting() const
void setTargetIDFromTargetIDStream(StringRef TargetID)
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
TargetIDSetting getSramEccSetting() const
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
ComponentInfo(const MCInstrDesc &OpDesc, ComponentKind Kind=ComponentKind::SINGLE)
ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const
unsigned getIndexOfDstInParsedOperands() const
ComponentLayout(const ComponentProps &OpXProps)
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
bool hasRegSrcOperand(unsigned CompSrcIdx) const
unsigned getMandatoryLiteralCompOperandIndex() const
unsigned getCompParsedSrcOperandsNum() const
InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
const ComponentInfo & operator[](size_t ComponentIdx) const
bool hasInvalidOperand(std::function< unsigned(unsigned, unsigned)> GetRegIdx) const
InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
std::optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx) const
std::array< unsigned, Component::MAX_OPR_NUM > RegIndices
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1190
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst)
unsigned decodeFieldSaSdst(unsigned Encoded)
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst)
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
unsigned decodeFieldVaVdst(unsigned Encoded)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
unsigned decodeFieldVmVsrc(unsigned Encoded)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
bool isValidHwreg(int64_t Id)
bool isValidHwregOffset(int64_t Offset)
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
bool isValidHwregWidth(int64_t Width)
int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI)
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
StringRef getDfmtName(unsigned Id)
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
int64_t getDfmt(const StringRef Name)
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned VOPD_VGPR_BANK_MASKS[]
constexpr unsigned COMPONENTS_NUM
constexpr unsigned COMPONENTS[]
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI)
int getVOPDFull(unsigned OpX, unsigned OpY)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
LLVM_READONLY const MIMGOffsetMappingInfo * getMIMGOffsetMappingInfo(unsigned Offset)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool isHsaAbiVersion5(const MCSubtargetInfo *STI)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isInlinableIntLiteralV216(int32_t Literal)
LLVM_READNONE bool isLegalDPALU_DPPControl(unsigned DC)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
bool isHsaAbiVersion4(const MCSubtargetInfo *STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
int getMTBUFElements(unsigned Opc)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
CanBeVOPD getCanBeVOPD(unsigned Opc)
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getCodeObjectVersion(const Module &M)
bool isGFX940(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
LLVM_READNONE bool isKernel(CallingConv::ID CC)
bool isHsaAbi(const MCSubtargetInfo &STI)
bool isGFX11(const MCSubtargetInfo &STI)
bool getSMEMIsBuffer(unsigned Opc)
bool isGroupSegment(const GlobalValue *GV)
LLVM_READONLY const MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
bool getMTBUFHasSoffset(unsigned Opc)
bool hasXNACK(const MCSubtargetInfo &STI)
unsigned getVOPDOpcode(unsigned Opc)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool isCompute(CallingConv::ID cc)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool getVOP1IsSingle(unsigned Opc)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isChainCC(CallingConv::ID CC)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
bool isTrue16Inst(unsigned Opc)
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
unsigned getAmdhsaCodeObjectVersion()
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isKernelCC(const Function *Func)
bool isGenericAtomic(unsigned Opc)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
LLVM_READONLY const MIMGBiasMappingInfo * getMIMGBiasMappingInfo(unsigned Bias)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
bool isInlineValue(unsigned Reg)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isShader(CallingConv::ID cc)
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
bool isGlobalSegment(const GlobalValue *GV)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:214
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:189
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:196
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:210
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:207
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:197
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:224
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:188
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:193
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:204
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:202
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:218
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:192
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:209
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:223
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:220
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:219
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:221
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:198
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:191
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:206
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:203
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:208
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:199
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:222
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:205
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:190
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:211
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:195
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:194
LLVM_READONLY const MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
bool hasGDS(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
std::optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfo(unsigned DimEnum)
bool getMUBUFIsBufferInv(unsigned Opc)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
bool isMAC(unsigned Opc)
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
bool getVOP2IsSingle(unsigned Opc)
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isModuleEntryFunctionCC(CallingConv::ID CC)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
bool hasVOPD(const MCSubtargetInfo &STI)
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
bool isGraphics(CallingConv::ID cc)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:197
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:141
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
@ Other
Any other memory.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:292
@ Default
The result values are uniform if and only if all operands are uniform.
AMD Kernel Code Object (amd_kernel_code_t).
Represents the counter values to wait for in an s_waitcnt instruction.
bool hasWaitExceptVsCnt() const
static Waitcnt allZero(bool HasVscnt)
static Waitcnt allZeroExceptVsCnt()
bool hasWaitVsCnt() const
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
Waitcnt combined(const Waitcnt &Other) const
Description of the encoding of one expression Op.